diff options
Diffstat (limited to 'llvm/lib/Target/Lanai')
25 files changed, 108 insertions, 114 deletions
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp index 8b8504978c755..639ab24b08179 100644 --- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -47,7 +47,7 @@ struct LanaiOperand; class LanaiAsmParser : public MCTargetAsmParser { // Parse operands - std::unique_ptr<LanaiOperand> parseRegister(); + std::unique_ptr<LanaiOperand> parseRegister(bool RestoreOnFailure = false); std::unique_ptr<LanaiOperand> parseImmediate(); @@ -67,6 +67,8 @@ class LanaiAsmParser : public MCTargetAsmParser { SMLoc NameLoc, OperandVector &Operands) override; bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -657,7 +659,7 @@ bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { case Match_Success: - Out.EmitInstruction(Inst, SubtargetInfo); + Out.emitInstruction(Inst, SubtargetInfo); Opcode = Inst.getOpcode(); return false; case Match_MissingFeature: @@ -687,21 +689,30 @@ bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, // backwards compatible with GCC and the different ways inline assembly is // handled. // TODO: see if there isn't a better way to do this. -std::unique_ptr<LanaiOperand> LanaiAsmParser::parseRegister() { +std::unique_ptr<LanaiOperand> +LanaiAsmParser::parseRegister(bool RestoreOnFailure) { SMLoc Start = Parser.getTok().getLoc(); SMLoc End = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Optional<AsmToken> PercentTok; unsigned RegNum; // Eat the '%'. - if (Lexer.getKind() == AsmToken::Percent) + if (Lexer.getKind() == AsmToken::Percent) { + PercentTok = Parser.getTok(); Parser.Lex(); + } if (Lexer.getKind() == AsmToken::Identifier) { RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); - if (RegNum == 0) + if (RegNum == 0) { + if (PercentTok.hasValue() && RestoreOnFailure) + Lexer.UnLex(PercentTok.getValue()); return nullptr; + } Parser.Lex(); // Eat identifier token return LanaiOperand::createReg(RegNum, Start, End); } + if (PercentTok.hasValue() && RestoreOnFailure) + Lexer.UnLex(PercentTok.getValue()); return nullptr; } @@ -710,12 +721,25 @@ bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, const AsmToken &Tok = getParser().getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); - std::unique_ptr<LanaiOperand> Op = parseRegister(); + std::unique_ptr<LanaiOperand> Op = parseRegister(/*RestoreOnFailure=*/false); if (Op != nullptr) RegNum = Op->getReg(); return (Op == nullptr); } +OperandMatchResultTy LanaiAsmParser::tryParseRegister(unsigned &RegNum, + SMLoc &StartLoc, + SMLoc &EndLoc) { + const AsmToken &Tok = getParser().getTok(); + StartLoc = Tok.getLoc(); + EndLoc = Tok.getEndLoc(); + std::unique_ptr<LanaiOperand> Op = parseRegister(/*RestoreOnFailure=*/true); + if (Op == nullptr) + return MatchOperand_NoMatch; + RegNum = Op->getReg(); + return MatchOperand_Success; +} + std::unique_ptr<LanaiOperand> LanaiAsmParser::parseIdentifier() { SMLoc Start = Parser.getTok().getLoc(); SMLoc End = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); diff --git a/llvm/lib/Target/Lanai/Lanai.h b/llvm/lib/Target/Lanai/Lanai.h index 2f06ea91ab03c..2bd266b1b96ee 100644 --- a/llvm/lib/Target/Lanai/Lanai.h +++ b/llvm/lib/Target/Lanai/Lanai.h @@ -19,9 +19,6 @@ namespace llvm { class FunctionPass; class LanaiTargetMachine; -class MachineFunctionPass; -class TargetMachine; -class formatted_raw_ostream; // createLanaiISelDag - This pass converts a legalized DAG into a // Lanai-specific DAG, ready for instruction scheduling. diff --git a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp index c13ee08e1213e..6bac7c75853de 100644 --- a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp +++ b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp @@ -51,7 +51,7 @@ public: void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; bool isBlockOnlyReachableByFallthrough( const MachineBasicBlock *MBB) const override; @@ -155,7 +155,7 @@ void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) { // Insert save rca instruction immediately before the call. // TODO: We should generate a pc-relative mov instruction here instead // of pc + 16 (should be mov .+16 %rca). - OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_I_LO) + OutStreamer->emitInstruction(MCInstBuilder(Lanai::ADD_I_LO) .addReg(Lanai::RCA) .addReg(Lanai::PC) .addImm(16), @@ -163,7 +163,7 @@ void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) { // Push rca onto the stack. // st %rca, [--%sp] - OutStreamer->EmitInstruction(MCInstBuilder(Lanai::SW_RI) + OutStreamer->emitInstruction(MCInstBuilder(Lanai::SW_RI) .addReg(Lanai::RCA) .addReg(Lanai::SP) .addImm(-4) @@ -175,9 +175,9 @@ void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) { MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); TmpInst.setOpcode(Lanai::BT); - OutStreamer->EmitInstruction(TmpInst, STI); + OutStreamer->emitInstruction(TmpInst, STI); } else { - OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_R) + OutStreamer->emitInstruction(MCInstBuilder(Lanai::ADD_R) .addReg(Lanai::PC) .addReg(MI->getOperand(0).getReg()) .addReg(Lanai::R0) @@ -191,10 +191,10 @@ void LanaiAsmPrinter::customEmitInstruction(const MachineInstr *MI) { MCSubtargetInfo STI = getSubtargetInfo(); MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); - OutStreamer->EmitInstruction(TmpInst, STI); + OutStreamer->emitInstruction(TmpInst, STI); } -void LanaiAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void LanaiAsmPrinter::emitInstruction(const MachineInstr *MI) { MachineBasicBlock::const_instr_iterator I = MI->getIterator(); MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); @@ -211,7 +211,7 @@ void LanaiAsmPrinter::EmitInstruction(const MachineInstr *MI) { // isBlockOnlyReachableByFallthough - Return true if the basic block has // exactly one predecessor and the control transfer mechanism between // the predecessor and this block is a fall-through. -// FIXME: could the overridden cases be handled in AnalyzeBranch? +// FIXME: could the overridden cases be handled in analyzeBranch? bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough( const MachineBasicBlock *MBB) const { // The predecessor has to be immediately before this block. diff --git a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp index eddc2b8e61f7d..3c84ed057fd19 100644 --- a/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiFrameLowering.cpp @@ -32,8 +32,8 @@ void LanaiFrameLowering::determineFrameLayout(MachineFunction &MF) const { unsigned FrameSize = MFI.getStackSize(); // Get the alignment. - unsigned StackAlign = LRI->needsStackRealignment(MF) ? MFI.getMaxAlignment() - : getStackAlignment(); + Align StackAlign = + LRI->needsStackRealignment(MF) ? MFI.getMaxAlign() : getStackAlign(); // Get the maximum call frame size of all the calls. unsigned MaxCallFrameSize = MFI.getMaxCallFrameSize(); diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index 6fa0c93d4a05a..32ccf71725943 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -388,7 +388,7 @@ static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, } // VarArgs get passed on stack - unsigned Offset = State.AllocateStack(4, 4); + unsigned Offset = State.AllocateStack(4, Align(4)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); return false; } @@ -633,13 +633,13 @@ SDValue LanaiTargetLowering::LowerCCCCallTo( SDValue Arg = OutVals[I]; unsigned Size = Flags.getByValSize(); - unsigned Align = Flags.getByValAlign(); + Align Alignment = Flags.getNonZeroByValAlign(); - int FI = MFI.CreateStackObject(Size, Align, false); + int FI = MFI.CreateStackObject(Size, Alignment, false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32); - Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align, + Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, /*IsVolatile=*/false, /*AlwaysInline=*/false, /*isTailCall=*/false, MachinePointerInfo(), @@ -1136,7 +1136,7 @@ SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op, if (getTargetMachine().getCodeModel() == CodeModel::Small || TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) { SDValue Small = DAG.getTargetConstantPool( - C, MVT::i32, N->getAlignment(), N->getOffset(), LanaiII::MO_NO_FLAG); + C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG); return DAG.getNode(ISD::OR, DL, MVT::i32, DAG.getRegister(Lanai::R0, MVT::i32), DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small)); @@ -1144,9 +1144,9 @@ SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op, uint8_t OpFlagHi = LanaiII::MO_ABS_HI; uint8_t OpFlagLo = LanaiII::MO_ABS_LO; - SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), + SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(), N->getOffset(), OpFlagHi); - SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), + SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(), N->getOffset(), OpFlagLo); Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi); Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo); diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index 4ce72f9621ad6..c821429703570 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -48,7 +48,7 @@ void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void LanaiInstrInfo::storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, - unsigned SourceRegister, bool IsKill, int FrameIndex, + Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo * /*RegisterInfo*/) const { DebugLoc DL; @@ -68,7 +68,7 @@ void LanaiInstrInfo::storeRegToStackSlot( void LanaiInstrInfo::loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, - unsigned DestinationRegister, int FrameIndex, + Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo * /*RegisterInfo*/) const { DebugLoc DL; @@ -174,8 +174,8 @@ LanaiInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { return makeArrayRef(TargetFlags); } -bool LanaiInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, - unsigned &SrcReg2, int &CmpMask, +bool LanaiInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int &CmpMask, int &CmpValue) const { switch (MI.getOpcode()) { default: @@ -183,7 +183,7 @@ bool LanaiInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, case Lanai::SFSUB_F_RI_LO: case Lanai::SFSUB_F_RI_HI: SrcReg = MI.getOperand(0).getReg(); - SrcReg2 = 0; + SrcReg2 = Register(); CmpMask = ~0; CmpValue = MI.getOperand(1).getImm(); return true; @@ -281,7 +281,7 @@ inline static unsigned flagSettingOpcodeVariant(unsigned OldOpcode) { } bool LanaiInstrInfo::optimizeCompareInstr( - MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, + MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, int CmpValue, const MachineRegisterInfo *MRI) const { // Get the unique definition of SrcReg. MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); @@ -454,9 +454,9 @@ bool LanaiInstrInfo::analyzeSelect(const MachineInstr &MI, // Identify instructions that can be folded into a SELECT instruction, and // return the defining instruction. -static MachineInstr *canFoldIntoSelect(unsigned Reg, +static MachineInstr *canFoldIntoSelect(Register Reg, const MachineRegisterInfo &MRI) { - if (!Register::isVirtualRegister(Reg)) + if (!Reg.isVirtual()) return nullptr; if (!MRI.hasOneNonDBGUse(Reg)) return nullptr; @@ -795,10 +795,10 @@ bool LanaiInstrInfo::getMemOperandWithOffsetWidth( return true; } -bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, - const MachineOperand *&BaseOp, - int64_t &Offset, - const TargetRegisterInfo *TRI) const { +bool LanaiInstrInfo::getMemOperandsWithOffsetWidth( + const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, + int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, + const TargetRegisterInfo *TRI) const { switch (LdSt.getOpcode()) { default: return false; @@ -811,7 +811,11 @@ bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, case Lanai::STH_RI: case Lanai::LDBs_RI: case Lanai::LDBz_RI: - unsigned Width; - return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); + const MachineOperand *BaseOp; + OffsetIsScalable = false; + if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) + return false; + BaseOps.push_back(BaseOp); + return true; } } diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h index c7741dd7437f8..44c1e629a8e66 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -54,23 +54,24 @@ public: void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, - unsigned SourceRegister, bool IsKill, int FrameIndex, + Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, - unsigned DestinationRegister, int FrameIndex, + Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; - bool getMemOperandWithOffset(const MachineInstr &LdSt, - const MachineOperand *&BaseOp, - int64_t &Offset, - const TargetRegisterInfo *TRI) const override; + bool getMemOperandsWithOffsetWidth( + const MachineInstr &LdSt, + SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, + bool &OffsetIsScalable, unsigned &Width, + const TargetRegisterInfo *TRI) const override; bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, @@ -94,15 +95,15 @@ public: // For a comparison instruction, return the source registers in SrcReg and // SrcReg2 if having two register operands, and the value it compares against // in CmpValue. Return true if the comparison instruction can be analyzed. - bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, - unsigned &SrcReg2, int &CmpMask, + bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int &CmpMask, int &CmpValue) const override; // See if the comparison instruction can be converted into something more // efficient. E.g., on Lanai register-register instructions can set the flag // register, obviating the need for a separate compare. - bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, - unsigned SrcReg2, int CmpMask, int CmpValue, + bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, + Register SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override; // Analyze the given select instruction, returning true if it cannot be diff --git a/llvm/lib/Target/Lanai/LanaiMCInstLower.h b/llvm/lib/Target/Lanai/LanaiMCInstLower.h index 00d3ebb050455..6323319fae437 100644 --- a/llvm/lib/Target/Lanai/LanaiMCInstLower.h +++ b/llvm/lib/Target/Lanai/LanaiMCInstLower.h @@ -18,9 +18,7 @@ class MCInst; class MCOperand; class MCSymbol; class MachineInstr; -class MachineModuleInfoMachO; class MachineOperand; -class Mangler; // LanaiMCInstLower - This class is used to lower an MachineInstr // into an MCInst. diff --git a/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp b/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp index 7b4e0750ba08a..eeef1d919925e 100644 --- a/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp @@ -11,12 +11,3 @@ using namespace llvm; void LanaiMachineFunctionInfo::anchor() {} - -unsigned LanaiMachineFunctionInfo::getGlobalBaseReg() { - // Return if it has already been initialized. - if (GlobalBaseReg) - return GlobalBaseReg; - - return GlobalBaseReg = - MF.getRegInfo().createVirtualRegister(&Lanai::GPRRegClass); -} diff --git a/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h b/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h index 2c97c619c2462..de712637b5a47 100644 --- a/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h +++ b/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h @@ -24,29 +24,25 @@ namespace llvm { class LanaiMachineFunctionInfo : public MachineFunctionInfo { virtual void anchor(); - MachineFunction &MF; - // SRetReturnReg - Lanai ABI require that sret lowering includes // returning the value of the returned struct in a register. This field // holds the virtual register into which the sret argument is passed. - unsigned SRetReturnReg; + Register SRetReturnReg; // GlobalBaseReg - keeps track of the virtual register initialized for // use as the global base register. This is used for PIC in some PIC // relocation models. - unsigned GlobalBaseReg; + Register GlobalBaseReg; // VarArgsFrameIndex - FrameIndex for start of varargs area. int VarArgsFrameIndex; public: explicit LanaiMachineFunctionInfo(MachineFunction &MF) - : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0) {} - - unsigned getSRetReturnReg() const { return SRetReturnReg; } - void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } + : VarArgsFrameIndex(0) {} - unsigned getGlobalBaseReg(); + Register getSRetReturnReg() const { return SRetReturnReg; } + void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; } int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } diff --git a/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp b/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp index 7c28debb94dd4..64f87ae5f9630 100644 --- a/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp @@ -66,11 +66,6 @@ bool LanaiRegisterInfo::requiresRegisterScavenging( return true; } -bool LanaiRegisterInfo::trackLivenessAfterRegAlloc( - const MachineFunction & /*MF*/) const { - return true; -} - static bool isALUArithLoOpcode(unsigned Opcode) { switch (Opcode) { case Lanai::ADD_I_LO: diff --git a/llvm/lib/Target/Lanai/LanaiRegisterInfo.h b/llvm/lib/Target/Lanai/LanaiRegisterInfo.h index 4e4da619d366c..cbc95b273e1df 100644 --- a/llvm/lib/Target/Lanai/LanaiRegisterInfo.h +++ b/llvm/lib/Target/Lanai/LanaiRegisterInfo.h @@ -34,8 +34,6 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo { bool requiresRegisterScavenging(const MachineFunction &MF) const override; - bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; - void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; diff --git a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp index dff87a3e264d9..307619c044818 100644 --- a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp @@ -20,7 +20,7 @@ namespace llvm { SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy( SelectionDAG & /*DAG*/, const SDLoc & /*dl*/, SDValue /*Chain*/, - SDValue /*Dst*/, SDValue /*Src*/, SDValue Size, unsigned /*Align*/, + SDValue /*Dst*/, SDValue /*Src*/, SDValue Size, Align /*Alignment*/, bool /*isVolatile*/, bool /*AlwaysInline*/, MachinePointerInfo /*DstPtrInfo*/, MachinePointerInfo /*SrcPtrInfo*/) const { diff --git a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h index c5650a7c1f53b..8355168a7396f 100644 --- a/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h +++ b/llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h @@ -24,8 +24,8 @@ public: SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVolatile, - bool AlwaysInline, + SDValue Size, Align Alignment, + bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const override; }; diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp index 9a872c789bcc6..ebf91e08fbc8e 100644 --- a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp +++ b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp @@ -23,7 +23,7 @@ using namespace llvm; void LanaiSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { - std::string CPUName = CPU; + std::string CPUName = std::string(CPU); if (CPUName.empty()) CPUName = "generic"; diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h index d2ac40007e24d..fb2bc0644fe84 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -22,7 +22,6 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class formatted_raw_ostream; class LanaiTargetMachine : public LLVMTargetMachine { LanaiSubtarget Subtarget; diff --git a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp index b0f7c090bb8ec..a421f3156153f 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.cpp @@ -28,7 +28,6 @@ static cl::opt<unsigned> SSThreshold( void LanaiTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { TargetLoweringObjectFileELF::Initialize(Ctx, TM); - InitializeELF(TM.Options.UseInitArray); SmallDataSection = getContext().getELFSection( ".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); @@ -117,13 +116,13 @@ bool LanaiTargetObjectFile::isConstantInSmallSection(const DataLayout &DL, return isInSmallSection(DL.getTypeAllocSize(CN->getType())); } -MCSection *LanaiTargetObjectFile::getSectionForConstant(const DataLayout &DL, - SectionKind Kind, - const Constant *C, - unsigned &Align) const { +MCSection *LanaiTargetObjectFile::getSectionForConstant( + const DataLayout &DL, SectionKind Kind, const Constant *C, + Align &Alignment) const { if (isConstantInSmallSection(DL, C)) return SmallDataSection; // Otherwise, we work the same as ELF. - return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Align); + return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, + Alignment); } diff --git a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h index 938a1e675b6a4..404349465dbcb 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h +++ b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h @@ -12,7 +12,6 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" namespace llvm { -class LanaiTargetMachine; class LanaiTargetObjectFile : public TargetLoweringObjectFileELF { MCSection *SmallDataSection; MCSection *SmallBSSSection; @@ -38,7 +37,7 @@ public: MCSection *getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, - unsigned &Align) const override; + Align &Alignment) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h index a22d3a34f98c9..7366d5059c9ff 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h +++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h @@ -49,7 +49,7 @@ public: return TTI::PSK_Software; } - int getIntImmCost(const APInt &Imm, Type *Ty) { + int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) { assert(Ty->isIntegerTy()); if (Imm == 0) return TTI::TCC_Free; @@ -66,17 +66,19 @@ public: return 4 * TTI::TCC_Basic; } - int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) { - return getIntImmCost(Imm, Ty); + int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, + TTI::TargetCostKind CostKind) { + return getIntImmCost(Imm, Ty, CostKind); } int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, - Type *Ty) { - return getIntImmCost(Imm, Ty); + Type *Ty, TTI::TargetCostKind CostKind) { + return getIntImmCost(Imm, Ty, CostKind); } unsigned getArithmeticInstrCost( unsigned Opcode, Type *Ty, + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, @@ -87,7 +89,8 @@ public: switch (ISD) { default: - return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, + return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, + Opd2Info, Opd1PropInfo, Opd2PropInfo); case ISD::MUL: case ISD::SDIV: @@ -98,7 +101,8 @@ public: // instruction cost was arbitrarily chosen to reduce the desirability // of emitting arithmetic instructions that are emulated in software. // TODO: Investigate the performance impact given specialized lowerings. - return 64 * BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, + return 64 * BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, + Opd2Info, Opd1PropInfo, Opd2PropInfo); } } diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp index a6ce3d5eb4ff0..0fb27a926003f 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp @@ -74,10 +74,6 @@ public: return false; } - void relaxInstruction(const MCInst & /*Inst*/, - const MCSubtargetInfo & /*STI*/, - MCInst & /*Res*/) const override {} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; }; diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp index ccc4139959175..7027d18126bb1 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp @@ -141,7 +141,7 @@ void LanaiInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annotation, const MCSubtargetInfo & /*STI*/, raw_ostream &OS) { - if (!printAlias(MI, OS) && !printAliasInstr(MI, OS)) + if (!printAlias(MI, OS) && !printAliasInstr(MI, Address, OS)) printInstruction(MI, Address, OS); printAnnotation(OS, Annotation); } diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h index a71a9497c691d..ce6df2969d734 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h @@ -44,9 +44,10 @@ public: // Autogenerated by tblgen. void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); + bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS); + void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, + raw_ostream &O); static const char *getRegisterName(unsigned RegNo); void printRegName(raw_ostream &OS, unsigned RegNo) const override; diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp index f1c174897047f..d8c7bd15aacb5 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp @@ -28,9 +28,6 @@ LanaiMCAsmInfo::LanaiMCAsmInfo(const Triple & /*TheTriple*/, // Lanai assembly requires ".section" before ".bss" UsesELFSectionDirectiveForBSS = true; - // Use the integrated assembler instead of system one. - UseIntegratedAssembler = true; - // Use '!' as comment string to correspond with old toolchain. CommentString = "!"; diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp index 9de15bf61c8ca..2ff893273c927 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp @@ -52,7 +52,7 @@ static MCRegisterInfo *createLanaiMCRegisterInfo(const Triple & /*TT*/) { static MCSubtargetInfo * createLanaiMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - std::string CPUName = CPU; + std::string CPUName = std::string(CPU); if (CPUName.empty()) CPUName = "generic"; diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h index cf66d32266597..651ed36cdc249 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h @@ -22,14 +22,9 @@ class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCInstrInfo; -class MCInstrAnalysis; class MCObjectTargetWriter; -class MCRelocationInfo; class MCSubtargetInfo; class Target; -class Triple; -class StringRef; -class raw_pwrite_stream; MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, |