diff options
Diffstat (limited to 'llvm/lib/Target/MSP430')
22 files changed, 117 insertions, 117 deletions
diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp index 0995e80a0a097..9529b5e802d58 100644 --- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp +++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp @@ -46,6 +46,8 @@ class MSP430AsmParser : public MCTargetAsmParser { bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -154,12 +156,12 @@ public: addExprOperand(Inst, Mem.Offset); } - bool isReg() const { return Kind == k_Reg; } - bool isImm() const { return Kind == k_Imm; } - bool isToken() const { return Kind == k_Tok; } - bool isMem() const { return Kind == k_Mem; } - bool isIndReg() const { return Kind == k_IndReg; } - bool isPostIndReg() const { return Kind == k_PostIndReg; } + bool isReg() const override { return Kind == k_Reg; } + bool isImm() const override { return Kind == k_Imm; } + bool isToken() const override { return Kind == k_Tok; } + bool isMem() const override { return Kind == k_Mem; } + bool isIndReg() const { return Kind == k_IndReg; } + bool isPostIndReg() const { return Kind == k_PostIndReg; } bool isCGImm() const { if (Kind != k_Imm) @@ -180,7 +182,7 @@ public: return Tok; } - unsigned getReg() const { + unsigned getReg() const override { assert(Kind == k_Reg && "Invalid access!"); return Reg; } @@ -220,10 +222,10 @@ public: return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E); } - SMLoc getStartLoc() const { return Start; } - SMLoc getEndLoc() const { return End; } + SMLoc getStartLoc() const override { return Start; } + SMLoc getEndLoc() const override { return End; } - virtual void print(raw_ostream &O) const { + void print(raw_ostream &O) const override { switch (Kind) { case k_Tok: O << "Token " << Tok; @@ -261,7 +263,7 @@ bool MSP430AsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode, switch (MatchResult) { case Match_Success: Inst.setLoc(Loc); - Out.EmitInstruction(Inst, STI); + Out.emitInstruction(Inst, STI); return false; case Match_MnemonicFail: return Error(Loc, "invalid instruction mnemonic"); @@ -288,13 +290,28 @@ static unsigned MatchRegisterAltName(StringRef Name); bool MSP430AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + switch (tryParseRegister(RegNo, StartLoc, EndLoc)) { + case MatchOperand_ParseFail: + return Error(StartLoc, "invalid register name"); + case MatchOperand_Success: + return false; + case MatchOperand_NoMatch: + return true; + } + + llvm_unreachable("unknown match result type"); +} + +OperandMatchResultTy MSP430AsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { if (getLexer().getKind() == AsmToken::Identifier) { auto Name = getLexer().getTok().getIdentifier().lower(); RegNo = MatchRegisterName(Name); if (RegNo == MSP430::NoRegister) { RegNo = MatchRegisterAltName(Name); if (RegNo == MSP430::NoRegister) - return true; + return MatchOperand_NoMatch; } AsmToken const &T = getParser().getTok(); @@ -302,10 +319,10 @@ bool MSP430AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, EndLoc = T.getEndLoc(); getLexer().Lex(); // eat register token - return false; + return MatchOperand_Success; } - return Error(StartLoc, "invalid register name"); + return MatchOperand_ParseFail; } bool MSP430AsmParser::parseJccInstruction(ParseInstructionInfo &Info, @@ -414,7 +431,7 @@ bool MSP430AsmParser::ParseDirectiveRefSym(AsmToken DirectiveID) { return TokError("expected identifier in directive"); MCSymbol *Sym = getContext().getOrCreateSymbol(Name); - getStreamer().EmitSymbolAttribute(Sym, MCSA_Global); + getStreamer().emitSymbolAttribute(Sym, MCSA_Global); return false; } @@ -523,7 +540,7 @@ bool MSP430AsmParser::ParseLiteralValues(unsigned Size, SMLoc L) { const MCExpr *Value; if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().EmitValue(Value, Size, L); + getParser().getStreamer().emitValue(Value, Size, L); return false; }; return (parseMany(parseOne)); @@ -545,7 +562,7 @@ static unsigned convertGR16ToGR8(unsigned Reg) { case MSP430::SP: return MSP430::SPB; case MSP430::SR: return MSP430::SRB; case MSP430::CG: return MSP430::CGB; - case MSP430::FP: return MSP430::FPB; + case MSP430::R4: return MSP430::R4B; case MSP430::R5: return MSP430::R5B; case MSP430::R6: return MSP430::R6B; case MSP430::R7: return MSP430::R7B; diff --git a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp index 6aa76156bf140..d2902189ec403 100644 --- a/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp +++ b/llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp @@ -65,7 +65,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Disassembler() { static const unsigned GR8DecoderTable[] = { MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB, - MSP430::FPB, MSP430::R5B, MSP430::R6B, MSP430::R7B, + MSP430::R4B, MSP430::R5B, MSP430::R6B, MSP430::R7B, MSP430::R8B, MSP430::R9B, MSP430::R10B, MSP430::R11B, MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B }; @@ -83,7 +83,7 @@ static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo, static const unsigned GR16DecoderTable[] = { MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG, - MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 }; diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp index 365e5da74de06..958212dc77c9c 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp @@ -95,9 +95,6 @@ public: return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; }; diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp index 4e054f85ccc39..87ee312424c8c 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp @@ -43,26 +43,26 @@ MSP430TargetELFStreamer::MSP430TargetELFStreamer(MCStreamer &S, Streamer.SwitchSection(AttributeSection); // Format version. - Streamer.EmitIntValue(0x41, 1); + Streamer.emitInt8(0x41); // Subsection length. - Streamer.EmitIntValue(22, 4); + Streamer.emitInt32(22); // Vendor name string, zero-terminated. - Streamer.EmitBytes("mspabi"); - Streamer.EmitIntValue(0, 1); + Streamer.emitBytes("mspabi"); + Streamer.emitInt8(0); // Attribute vector scope tag. 1 stands for the entire file. - Streamer.EmitIntValue(1, 1); + Streamer.emitInt8(1); // Attribute vector length. - Streamer.EmitIntValue(11, 4); + Streamer.emitInt32(11); // OFBA_MSPABI_Tag_ISA(4) = 1, MSP430 - Streamer.EmitIntValue(4, 1); - Streamer.EmitIntValue(1, 1); + Streamer.emitInt8(4); + Streamer.emitInt8(1); // OFBA_MSPABI_Tag_Code_Model(6) = 1, Small - Streamer.EmitIntValue(6, 1); - Streamer.EmitIntValue(1, 1); + Streamer.emitInt8(6); + Streamer.emitInt8(1); // OFBA_MSPABI_Tag_Data_Model(8) = 1, Small - Streamer.EmitIntValue(8, 1); - Streamer.EmitIntValue(1, 1); + Streamer.emitInt8(8); + Streamer.emitInt8(1); } MCELFStreamer &MSP430TargetELFStreamer::getStreamer() { diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp index 0c6da5a35c685..420893f65d5b9 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp @@ -29,7 +29,7 @@ using namespace llvm; void MSP430InstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) { - if (!printAliasInstr(MI, O)) + if (!printAliasInstr(MI, Address, O)) printInstruction(MI, Address, O); printAnnotation(O, Annot); } diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h index 200dc0e6db601..6a6b07f2eba01 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h @@ -27,9 +27,10 @@ namespace llvm { // Autogenerated by tblgen. void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, raw_ostream &O); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); + bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &O); + void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, + raw_ostream &O); static const char *getRegisterName(unsigned RegNo); private: diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp index cfdc44ada771e..de07b47096d34 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp @@ -24,5 +24,6 @@ MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT, AlignmentIsInBytes = false; UsesELFSectionDirectiveForBSS = true; - UseIntegratedAssembler = true; + + SupportsDebugInformation = true; } diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h index 67f35b8034d99..34f0a37bced90 100644 --- a/llvm/lib/Target/MSP430/MSP430.h +++ b/llvm/lib/Target/MSP430/MSP430.h @@ -36,7 +36,6 @@ namespace MSP430CC { namespace llvm { class MSP430TargetMachine; class FunctionPass; - class formatted_raw_ostream; FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel); diff --git a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp index 2f871b959a710..459188434f2cb 100644 --- a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp +++ b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -57,7 +57,7 @@ namespace { const char *ExtraCode, raw_ostream &O) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void EmitInterruptVectorSection(MachineFunction &ISR); }; @@ -148,7 +148,7 @@ bool MSP430AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, } //===----------------------------------------------------------------------===// -void MSP430AsmPrinter::EmitInstruction(const MachineInstr *MI) { +void MSP430AsmPrinter::emitInstruction(const MachineInstr *MI) { MSP430MCInstLower MCInstLowering(OutContext, *this); MCInst TmpInst; @@ -169,7 +169,7 @@ void MSP430AsmPrinter::EmitInterruptVectorSection(MachineFunction &ISR) { OutStreamer->SwitchSection(IV); const MCSymbol *FunctionSymbol = getSymbol(F); - OutStreamer->EmitSymbolValue(FunctionSymbol, TM.getProgramPointerSize()); + OutStreamer->emitSymbolValue(FunctionSymbol, TM.getProgramPointerSize()); OutStreamer->SwitchSection(Cur); } @@ -180,7 +180,7 @@ bool MSP430AsmPrinter::runOnMachineFunction(MachineFunction &MF) { } SetupMachineFunction(MF); - EmitFunctionBody(); + emitFunctionBody(); return false; } diff --git a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp index de60ad9bd7e6f..4be8d0760e689 100644 --- a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp @@ -64,16 +64,16 @@ void MSP430FrameLowering::emitPrologue(MachineFunction &MF, // Save FP into the appropriate stack slot... BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) - .addReg(MSP430::FP, RegState::Kill); + .addReg(MSP430::R4, RegState::Kill); // Update FP with the new base value... - BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) + BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) .addReg(MSP430::SP); // Mark the FramePtr as live-in in every block except the entry. for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end(); I != E; ++I) - I->addLiveIn(MSP430::FP); + I->addLiveIn(MSP430::R4); } else NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize(); @@ -132,7 +132,7 @@ void MSP430FrameLowering::emitEpilogue(MachineFunction &MF, NumBytes = FrameSize - CSSize; // pop FP. - BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); + BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4); } else NumBytes = StackSize - CSSize; @@ -154,7 +154,7 @@ void MSP430FrameLowering::emitEpilogue(MachineFunction &MF, if (MFI.hasVarSizedObjects()) { BuildMI(MBB, MBBI, DL, - TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); + TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::R4); if (CSSize) { MachineInstr *MI = BuildMI(MBB, MBBI, DL, @@ -176,11 +176,9 @@ void MSP430FrameLowering::emitEpilogue(MachineFunction &MF, } // FIXME: Can we eleminate these in favour of generic code? -bool -MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { +bool MSP430FrameLowering::spillCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { if (CSI.empty()) return false; @@ -202,11 +200,9 @@ MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, return true; } -bool -MSP430FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { +bool MSP430FrameLowering::restoreCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { if (CSI.empty()) return false; @@ -227,8 +223,6 @@ MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr( MachineBasicBlock::iterator I) const { const MSP430InstrInfo &TII = *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo()); - unsigned StackAlign = getStackAlignment(); - if (!hasReservedCallFrame(MF)) { // If the stack pointer can be changed after prologue, turn the // adjcallstackup instruction into a 'sub SP, <amt>' and the @@ -240,7 +234,7 @@ MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr( // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; + Amount = alignTo(Amount, getStackAlign()); MachineInstr *New = nullptr; if (Old.getOpcode() == TII.getCallFrameSetupOpcode()) { diff --git a/llvm/lib/Target/MSP430/MSP430FrameLowering.h b/llvm/lib/Target/MSP430/MSP430FrameLowering.h index 70e2840530211..f6995edf4b0ad 100644 --- a/llvm/lib/Target/MSP430/MSP430FrameLowering.h +++ b/llvm/lib/Target/MSP430/MSP430FrameLowering.h @@ -36,12 +36,13 @@ public: bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, + ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const override; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const override; + bool + restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + MutableArrayRef<CalleeSavedInfo> CSI, + const TargetRegisterInfo *TRI) const override; bool hasFP(const MachineFunction &MF) const override; bool hasReservedCallFrame(const MachineFunction &MF) const override; diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 8550230155c87..7dabb9b4abaeb 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -50,7 +50,7 @@ namespace { const BlockAddress *BlockAddr = nullptr; const char *ES = nullptr; int JT = -1; - unsigned Align = 0; // CP alignment. + Align Alignment; // CP alignment. MSP430ISelAddressMode() = default; @@ -74,12 +74,12 @@ namespace { } else if (CP) { errs() << " CP "; CP->dump(); - errs() << " Align" << Align << '\n'; + errs() << " Align" << Alignment.value() << '\n'; } else if (ES) { errs() << "ES "; errs() << ES << '\n'; } else if (JT != -1) - errs() << " JT" << JT << " Align" << Align << '\n'; + errs() << " JT" << JT << " Align" << Alignment.value() << '\n'; } #endif }; @@ -146,7 +146,7 @@ bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { //AM.SymbolFlags = G->getTargetFlags(); } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { AM.CP = CP->getConstVal(); - AM.Align = CP->getAlignment(); + AM.Alignment = CP->getAlign(); AM.Disp += CP->getOffset(); //AM.SymbolFlags = CP->getTargetFlags(); } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { @@ -263,8 +263,8 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue N, MVT::i16, AM.Disp, 0/*AM.SymbolFlags*/); else if (AM.CP) - Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, - AM.Align, AM.Disp, 0/*AM.SymbolFlags*/); + Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, AM.Alignment, AM.Disp, + 0 /*AM.SymbolFlags*/); else if (AM.ES) Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/); else if (AM.JT != -1) diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp index 37e6ea24d0884..821339f503551 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -514,7 +514,7 @@ static void AnalyzeArguments(CCState &State, // Handle byval arguments if (ArgFlags.isByVal()) { - State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags); + State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, Align(2), ArgFlags); continue; } @@ -863,13 +863,11 @@ SDValue MSP430TargetLowering::LowerCCCCallTo( if (Flags.isByVal()) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16); - MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, - Flags.getByValAlign(), - /*isVolatile*/false, - /*AlwaysInline=*/true, - /*isTailCall=*/false, - MachinePointerInfo(), - MachinePointerInfo()); + MemOp = DAG.getMemcpy( + Chain, dl, PtrOff, Arg, SizeNode, Flags.getNonZeroByValAlign(), + /*isVolatile*/ false, + /*AlwaysInline=*/true, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); } else { MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()); } @@ -1302,7 +1300,7 @@ SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, SDLoc dl(Op); // FIXME probably not meaningful unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, - MSP430::FP, VT); + MSP430::R4, VT); while (Depth--) FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, MachinePointerInfo()); diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.h b/llvm/lib/Target/MSP430/MSP430ISelLowering.h index 650f9a7040628..f23042a369fd6 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.h +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.h @@ -79,6 +79,10 @@ namespace llvm { return MVT::i8; } + MVT::SimpleValueType getCmpLibcallReturnType() const override { + return MVT::i16; + } + /// LowerOperation - Provide custom lowering hooks for some operations. SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index 9e03334d6b62d..130211878be17 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -35,7 +35,7 @@ MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI) void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIdx, + Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; @@ -46,7 +46,7 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FrameIdx), MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx), - MFI.getObjectAlignment(FrameIdx)); + MFI.getObjectAlign(FrameIdx)); if (RC == &MSP430::GR16RegClass) BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) @@ -62,7 +62,7 @@ void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, + Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const{ DebugLoc DL; @@ -73,7 +73,7 @@ void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FrameIdx), MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx), - MFI.getObjectAlignment(FrameIdx)); + MFI.getObjectAlign(FrameIdx)); if (RC == &MSP430::GR16RegClass) BuildMI(MBB, MI, DL, get(MSP430::MOV16rm)) @@ -160,18 +160,6 @@ reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { return false; } -bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const { - if (!MI.isTerminator()) - return false; - - // Conditional branch is a special case. - if (MI.isBranch() && !MI.isBarrier()) - return true; - if (!MI.isPredicable()) - return true; - return !isPredicated(MI); -} - bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h index e3838772c0610..710913b2d36f6 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -41,13 +41,13 @@ public: void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, + Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; @@ -56,7 +56,6 @@ public: // Branch folding goodness bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; - bool isUnpredicatedTerminator(const MachineInstr &MI) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, diff --git a/llvm/lib/Target/MSP430/MSP430MCInstLower.h b/llvm/lib/Target/MSP430/MSP430MCInstLower.h index 910ad4bb12d54..4d0197d9e2b1e 100644 --- a/llvm/lib/Target/MSP430/MSP430MCInstLower.h +++ b/llvm/lib/Target/MSP430/MSP430MCInstLower.h @@ -18,7 +18,6 @@ namespace llvm { class MCOperand; class MCSymbol; class MachineInstr; - class MachineModuleInfoMachO; class MachineOperand; /// MSP430MCInstLower - This class is used to lower an MachineInstr diff --git a/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h b/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h index 712519cfe38aa..261db9e288f57 100644 --- a/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h +++ b/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h @@ -35,7 +35,7 @@ class MSP430MachineFunctionInfo : public MachineFunctionInfo { /// SRetReturnReg - Some subtargets require that sret lowering includes /// returning the value of the returned struct in a register. This field /// holds the virtual register into which the sret argument is passed. - unsigned SRetReturnReg = 0; + Register SRetReturnReg; public: MSP430MachineFunctionInfo() = default; @@ -46,8 +46,8 @@ public: unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; } void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; } - unsigned getSRetReturnReg() const { return SRetReturnReg; } - void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } + Register getSRetReturnReg() const { return SRetReturnReg; } + void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; } int getRAIndex() const { return ReturnAddrIndex; } void setRAIndex(int Index) { ReturnAddrIndex = Index; } diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp index bec357a1548d6..5583ebee2f311 100644 --- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -39,7 +39,7 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { const MSP430FrameLowering *TFI = getFrameLowering(*MF); const Function* F = &MF->getFunction(); static const MCPhysReg CalleeSavedRegs[] = { - MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, MSP430::R8, MSP430::R9, MSP430::R10, 0 }; @@ -49,7 +49,7 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 0 }; static const MCPhysReg CalleeSavedRegsIntr[] = { - MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, 0 @@ -86,8 +86,8 @@ BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { // Mark frame pointer as reserved if needed. if (TFI->hasFP(MF)) { - Reserved.set(MSP430::FPB); - Reserved.set(MSP430::FP); + Reserved.set(MSP430::R4B); + Reserved.set(MSP430::R4); } return Reserved; @@ -112,7 +112,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, DebugLoc dl = MI.getDebugLoc(); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); - unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP); + unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP); int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex); // Skip the saved PC @@ -156,5 +156,5 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { const MSP430FrameLowering *TFI = getFrameLowering(MF); - return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP; + return TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP; } diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td index 11003dba383f4..61cc72d494b5b 100644 --- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td @@ -15,6 +15,7 @@ class MSP430Reg<bits<4> num, string n, list<string> alt = []> : Register<n> { let Namespace = "MSP430"; let HWEncoding{3-0} = num; let AltNames = alt; + let DwarfNumbers = [num]; } class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs, @@ -24,6 +25,7 @@ class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs, let Namespace = "MSP430"; let HWEncoding{3-0} = num; let AltNames = alt; + let DwarfNumbers = [num]; } //===----------------------------------------------------------------------===// @@ -34,7 +36,7 @@ def PCB : MSP430Reg<0, "r0", ["pc"]>; def SPB : MSP430Reg<1, "r1", ["sp"]>; def SRB : MSP430Reg<2, "r2", ["sr"]>; def CGB : MSP430Reg<3, "r3", ["cg"]>; -def FPB : MSP430Reg<4, "r4", ["fp"]>; +def R4B : MSP430Reg<4, "r4", ["fp"]>; def R5B : MSP430Reg<5, "r5">; def R6B : MSP430Reg<6, "r6">; def R7B : MSP430Reg<7, "r7">; @@ -54,7 +56,7 @@ def PC : MSP430RegWithSubregs<0, "r0", [PCB], ["pc"]>; def SP : MSP430RegWithSubregs<1, "r1", [SPB], ["sp"]>; def SR : MSP430RegWithSubregs<2, "r2", [SRB], ["sr"]>; def CG : MSP430RegWithSubregs<3, "r3", [CGB], ["cg"]>; -def FP : MSP430RegWithSubregs<4, "r4", [FPB], ["fp"]>; +def R4 : MSP430RegWithSubregs<4, "r4", [R4B], ["fp"]>; def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>; def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>; def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>; @@ -72,7 +74,7 @@ def GR8 : RegisterClass<"MSP430", [i8], 8, // Volatile registers (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, // Frame pointer, sometimes allocable - FPB, + R4B, // Volatile, but not allocable PCB, SPB, SRB, CGB)>; @@ -80,6 +82,6 @@ def GR16 : RegisterClass<"MSP430", [i16], 16, // Volatile registers (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, // Frame pointer, sometimes allocable - FP, + R4, // Volatile, but not allocable PC, SP, SR, CG)>; diff --git a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp index 20168773cd533..1f3c1d34f76f4 100644 --- a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp +++ b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp @@ -43,7 +43,7 @@ MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { ExtendedInsts = false; HWMultMode = NoHWMult; - std::string CPUName = CPU; + StringRef CPUName = CPU; if (CPUName.empty()) CPUName = "msp430"; diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index 81851427c0edf..827f24daad167 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -47,7 +47,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique<TargetLoweringObjectFileELF>()), - Subtarget(TT, CPU, FS, *this) { + Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); } |