diff options
Diffstat (limited to 'llvm/lib/Target/Mips/MCTargetDesc')
15 files changed, 148 insertions, 168 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp index fca1149453c9e..c5a1a3e6286ed 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp @@ -57,17 +57,17 @@ namespace llvm { MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) { // Write out a Elf_Internal_ABIFlags_v0 struct - OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2); // version - OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level - OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev - OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size - OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size - OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size - OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi - OS.EmitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext - OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases - OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1 - OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2 + OS.emitIntValue(ABIFlagsSection.getVersionValue(), 2); // version + OS.emitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level + OS.emitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev + OS.emitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size + OS.emitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size + OS.emitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size + OS.emitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi + OS.emitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext + OS.emitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases + OS.emitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1 + OS.emitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2 return OS; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h index 534e6573b63c5..046cc686b3118 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -18,7 +18,6 @@ namespace llvm { template <typename T> class ArrayRef; class MCTargetOptions; class StringRef; -class TargetRegisterClass; class MipsABIInfo { public: diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index cca75dfc45c28..1126b871cb114 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -22,9 +22,7 @@ namespace llvm { class MCAssembler; struct MCFixupKindInfo; -class MCObjectWriter; class MCRegisterInfo; -class MCSymbolELF; class Target; class MipsAsmBackend : public MCAsmBackend { @@ -74,17 +72,6 @@ public: return false; } - /// RelaxInstruction - Relax the instruction in the given fragment - /// to the next wider instruction. - /// - /// \param Inst - The instruction to relax, which may be the same - /// as the output. - /// \param [out] Res On return, the relaxed instruction. - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - - /// @} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index cc3168790b981..9c317e3f8840f 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -234,14 +234,15 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, case Mips::fixup_Mips_32: case FK_Data_4: return IsPCRel ? ELF::R_MIPS_PC32 : ELF::R_MIPS_32; + case Mips::fixup_Mips_64: + case FK_Data_8: + return IsPCRel + ? setRTypes(ELF::R_MIPS_PC32, ELF::R_MIPS_64, ELF::R_MIPS_NONE) + : (unsigned)ELF::R_MIPS_64; } if (IsPCRel) { switch (Kind) { - case FK_Data_8: - Ctx.reportError(Fixup.getLoc(), - "MIPS does not support 64-bit PC-relative relocations"); - return ELF::R_MIPS_NONE; case Mips::fixup_Mips_Branch_PCRel: case Mips::fixup_Mips_PC16: return ELF::R_MIPS_PC16; @@ -277,9 +278,6 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, } switch (Kind) { - case Mips::fixup_Mips_64: - case FK_Data_8: - return ELF::R_MIPS_64; case FK_DTPRel_4: return ELF::R_MIPS_TLS_DTPREL32; case FK_DTPRel_8: @@ -289,14 +287,9 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, case FK_TPRel_8: return ELF::R_MIPS_TLS_TPREL64; case FK_GPRel_4: - if (is64Bit()) { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MIPS_GPREL32, Type); - Type = setRType2((unsigned)ELF::R_MIPS_64, Type); - Type = setRType3((unsigned)ELF::R_MIPS_NONE, Type); - return Type; - } - return ELF::R_MIPS_GPREL32; + return setRTypes(ELF::R_MIPS_GPREL32, + is64Bit() ? ELF::R_MIPS_64 : ELF::R_MIPS_NONE, + ELF::R_MIPS_NONE); case Mips::fixup_Mips_GPREL16: return ELF::R_MIPS_GPREL16; case Mips::fixup_Mips_26: @@ -329,34 +322,16 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, return ELF::R_MIPS_GOT_OFST; case Mips::fixup_Mips_GOT_DISP: return ELF::R_MIPS_GOT_DISP; - case Mips::fixup_Mips_GPOFF_HI: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MIPS_HI16, Type); - return Type; - } - case Mips::fixup_MICROMIPS_GPOFF_HI: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MICROMIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MICROMIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MICROMIPS_HI16, Type); - return Type; - } - case Mips::fixup_Mips_GPOFF_LO: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MIPS_LO16, Type); - return Type; - } - case Mips::fixup_MICROMIPS_GPOFF_LO: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MICROMIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MICROMIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MICROMIPS_LO16, Type); - return Type; - } + case Mips::fixup_Mips_GPOFF_HI: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_HI16); + case Mips::fixup_MICROMIPS_GPOFF_HI: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, + ELF::R_MICROMIPS_HI16); + case Mips::fixup_Mips_GPOFF_LO: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_LO16); + case Mips::fixup_MICROMIPS_GPOFF_LO: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, + ELF::R_MICROMIPS_LO16); case Mips::fixup_Mips_HIGHER: return ELF::R_MIPS_HIGHER; case Mips::fixup_Mips_HIGHEST: diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp index 1b83e9445fb5c..e6e32ec7f27cd 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp @@ -33,9 +33,9 @@ MipsELFStreamer::MipsELFStreamer(MCContext &Context, std::unique_ptr<MipsRegInfoRecord>(RegInfoRecord)); } -void MipsELFStreamer::EmitInstruction(const MCInst &Inst, +void MipsELFStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); MCContext &Context = getContext(); const MCRegisterInfo *MCRegInfo = Context.getRegisterInfo(); @@ -53,20 +53,20 @@ void MipsELFStreamer::EmitInstruction(const MCInst &Inst, createPendingLabelRelocs(); } -void MipsELFStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { +void MipsELFStreamer::emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { Frame.Begin = getContext().createTempSymbol(); - MCELFStreamer::EmitLabel(Frame.Begin); + MCELFStreamer::emitLabel(Frame.Begin); } -MCSymbol *MipsELFStreamer::EmitCFILabel() { +MCSymbol *MipsELFStreamer::emitCFILabel() { MCSymbol *Label = getContext().createTempSymbol("cfi", true); - MCELFStreamer::EmitLabel(Label); + MCELFStreamer::emitLabel(Label); return Label; } -void MipsELFStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { +void MipsELFStreamer::emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { Frame.End = getContext().createTempSymbol(); - MCELFStreamer::EmitLabel(Frame.End); + MCELFStreamer::emitLabel(Frame.End); } void MipsELFStreamer::createPendingLabelRelocs() { @@ -85,8 +85,8 @@ void MipsELFStreamer::createPendingLabelRelocs() { Labels.clear(); } -void MipsELFStreamer::EmitLabel(MCSymbol *Symbol, SMLoc Loc) { - MCELFStreamer::EmitLabel(Symbol); +void MipsELFStreamer::emitLabel(MCSymbol *Symbol, SMLoc Loc) { + MCELFStreamer::emitLabel(Symbol); Labels.push_back(Symbol); } @@ -96,14 +96,14 @@ void MipsELFStreamer::SwitchSection(MCSection *Section, Labels.clear(); } -void MipsELFStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, +void MipsELFStreamer::emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) { - MCELFStreamer::EmitValueImpl(Value, Size, Loc); + MCELFStreamer::emitValueImpl(Value, Size, Loc); Labels.clear(); } -void MipsELFStreamer::EmitIntValue(uint64_t Value, unsigned Size) { - MCELFStreamer::EmitIntValue(Value, Size); +void MipsELFStreamer::emitIntValue(uint64_t Value, unsigned Size) { + MCELFStreamer::emitIntValue(Value, Size); Labels.clear(); } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h index 2febfbc69b6fe..f6a2c039c0c37 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h @@ -41,12 +41,12 @@ public: /// \p Inst is actually emitted. For example, we can inspect the operands and /// gather sufficient information that allows us to reason about the register /// usage for the translation unit. - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; /// Overriding this function allows us to record all labels that should be /// marked as microMIPS. Based on this data marking is done in /// EmitInstruction. - void EmitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; + void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; /// Overriding this function allows us to dismiss all labels that are /// candidates for marking as microMIPS when .section directive is processed. @@ -56,14 +56,14 @@ public: /// Overriding these functions allows us to dismiss all labels that are /// candidates for marking as microMIPS when .word/.long/.4byte etc /// directives are emitted. - void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override; - void EmitIntValue(uint64_t Value, unsigned Size) override; + void emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override; + void emitIntValue(uint64_t Value, unsigned Size) override; // Overriding these functions allows us to avoid recording of these labels // in EmitLabel and later marking them as microMIPS. - void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; - void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; - MCSymbol *EmitCFILabel() override; + void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + MCSymbol *emitCFILabel() override; /// Emits all the option records stored up until the point it's called. void EmitMipsOptionRecords(); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp index 649ba20324bf0..3700d6309e1a0 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp @@ -109,7 +109,7 @@ void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, } // Try to print any aliases first. - if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) + if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O)) printInstruction(MI, Address, O); printAnnotation(O, Annot); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h index 0b1ee800e4401..3f534a2f18435 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h @@ -86,12 +86,17 @@ public: void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); + bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS); + void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, + raw_ostream &O); private: void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum, + raw_ostream &O) { + printOperand(MI, OpNum, O); + } template <unsigned Bits, unsigned Offset = 0> void printUImm(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index 5182205edaeac..9c85a39bc348a 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -50,5 +50,4 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple, ExceptionsType = ExceptionHandling::DwarfCFI; DwarfRegNumForCFI = true; HasMipsExpressions = true; - UseIntegratedAssembler = true; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 846f508005f58..9de34cc0e7878 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -129,7 +129,7 @@ void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; } -void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, +void MipsMCCodeEmitter::emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const { // Output the instruction encoding in little endian byte order. @@ -137,8 +137,8 @@ void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, // mips32r2: 4 | 3 | 2 | 1 // microMIPS: 2 | 1 | 4 | 3 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { - EmitInstruction(Val >> 16, 2, STI, OS); - EmitInstruction(Val, 2, STI, OS); + emitInstruction(Val >> 16, 2, STI, OS); + emitInstruction(Val, 2, STI, OS); } else { for (unsigned i = 0; i < Size; ++i) { unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; @@ -226,7 +226,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS, if (!Size) llvm_unreachable("Desc.getSize() returns 0"); - EmitInstruction(Binary, Size, STI, OS); + emitInstruction(Binary, Size, STI, OS); } /// getBranchTargetOpValue - Return binary encoding of the branch @@ -723,21 +723,8 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, return 0; } - if (Kind == MCExpr::SymbolRef) { - Mips::Fixups FixupKind = Mips::Fixups(0); - - switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { - default: llvm_unreachable("Unknown fixup kind!"); - break; - case MCSymbolRefExpr::VK_None: - // FIXME: This is ok for O32/N32 but not N64. - FixupKind = Mips::fixup_Mips_32; - break; - } // switch - - Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); - return 0; - } + if (Kind == MCExpr::SymbolRef) + Ctx.reportError(Expr->getLoc(), "expected an immediate"); return 0; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h index ff6e1d62b05f6..16e94c723b347 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -44,7 +44,7 @@ public: void EmitByte(unsigned char C, raw_ostream &OS) const; - void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, + void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const; void encodeInstruction(const MCInst &MI, raw_ostream &OS, diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index 809be99ff3f40..b7ecb0fdca5e7 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -29,8 +29,6 @@ class MCTargetOptions; class StringRef; class Target; class Triple; -class raw_ostream; -class raw_pwrite_stream; MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp index 0544758f8a253..eade2d9bd7450 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp @@ -105,7 +105,7 @@ private: MaskInst.addOperand(MCOperand::createReg(AddrReg)); MaskInst.addOperand(MCOperand::createReg(AddrReg)); MaskInst.addOperand(MCOperand::createReg(MaskReg)); - MipsELFStreamer::EmitInstruction(MaskInst, STI); + MipsELFStreamer::emitInstruction(MaskInst, STI); } // Sandbox indirect branch or return instruction by inserting mask operation @@ -113,10 +113,10 @@ private: void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) { unsigned AddrReg = MI.getOperand(0).getReg(); - EmitBundleLock(false); + emitBundleLock(false); emitMask(AddrReg, IndirectBranchMaskReg, STI); - MipsELFStreamer::EmitInstruction(MI, STI); - EmitBundleUnlock(); + MipsELFStreamer::emitInstruction(MI, STI); + emitBundleUnlock(); } // Sandbox memory access or SP change. Insert mask operation before and/or @@ -124,26 +124,26 @@ private: void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, const MCSubtargetInfo &STI, bool MaskBefore, bool MaskAfter) { - EmitBundleLock(false); + emitBundleLock(false); if (MaskBefore) { // Sandbox memory access. unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); emitMask(BaseReg, LoadStoreStackMaskReg, STI); } - MipsELFStreamer::EmitInstruction(MI, STI); + MipsELFStreamer::emitInstruction(MI, STI); if (MaskAfter) { // Sandbox SP change. unsigned SPReg = MI.getOperand(0).getReg(); assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); emitMask(SPReg, LoadStoreStackMaskReg, STI); } - EmitBundleUnlock(); + emitBundleUnlock(); } public: /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to mask dangerous instructions. - void EmitInstruction(const MCInst &Inst, + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override { // Sandbox indirect jumps. if (isIndirectJump(Inst)) { @@ -181,25 +181,25 @@ public: report_fatal_error("Dangerous instruction in branch delay slot!"); // Start the sandboxing sequence by emitting call. - EmitBundleLock(true); + emitBundleLock(true); if (IsIndirectCall) { unsigned TargetReg = Inst.getOperand(1).getReg(); emitMask(TargetReg, IndirectBranchMaskReg, STI); } - MipsELFStreamer::EmitInstruction(Inst, STI); + MipsELFStreamer::emitInstruction(Inst, STI); PendingCall = true; return; } if (PendingCall) { // Finish the sandboxing sequence by emitting branch delay. - MipsELFStreamer::EmitInstruction(Inst, STI); - EmitBundleUnlock(); + MipsELFStreamer::emitInstruction(Inst, STI); + emitBundleUnlock(); PendingCall = false; return; } // None of the sandboxing applies, just emit the instruction. - MipsELFStreamer::EmitInstruction(Inst, STI); + MipsELFStreamer::emitInstruction(Inst, STI); } }; @@ -270,7 +270,7 @@ MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, S->getAssembler().setRelaxAll(true); // Set bundle-alignment as required by the NaCl ABI for the target. - S->EmitBundleAlignMode(Log2(MIPS_NACL_BUNDLE_ALIGN)); + S->emitBundleAlignMode(Log2(MIPS_NACL_BUNDLE_ALIGN)); return S; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp index bdfb70aa98131..a4a953bcd7c38 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp @@ -40,17 +40,17 @@ void MipsRegInfoRecord::EmitMipsOptionRecord() { Sec->setAlignment(Align(8)); Streamer->SwitchSection(Sec); - Streamer->EmitIntValue(ELF::ODK_REGINFO, 1); // kind - Streamer->EmitIntValue(40, 1); // size - Streamer->EmitIntValue(0, 2); // section - Streamer->EmitIntValue(0, 4); // info - Streamer->EmitIntValue(ri_gprmask, 4); - Streamer->EmitIntValue(0, 4); // pad - Streamer->EmitIntValue(ri_cprmask[0], 4); - Streamer->EmitIntValue(ri_cprmask[1], 4); - Streamer->EmitIntValue(ri_cprmask[2], 4); - Streamer->EmitIntValue(ri_cprmask[3], 4); - Streamer->EmitIntValue(ri_gp_value, 8); + Streamer->emitInt8(ELF::ODK_REGINFO); // kind + Streamer->emitInt8(40); // size + Streamer->emitInt16(0); // section + Streamer->emitInt32(0); // info + Streamer->emitInt32(ri_gprmask); + Streamer->emitInt32(0); // pad + Streamer->emitInt32(ri_cprmask[0]); + Streamer->emitInt32(ri_cprmask[1]); + Streamer->emitInt32(ri_cprmask[2]); + Streamer->emitInt32(ri_cprmask[3]); + Streamer->emitIntValue(ri_gp_value, 8); } else { MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC, 24, ""); @@ -58,13 +58,13 @@ void MipsRegInfoRecord::EmitMipsOptionRecord() { Sec->setAlignment(MTS->getABI().IsN32() ? Align(8) : Align(4)); Streamer->SwitchSection(Sec); - Streamer->EmitIntValue(ri_gprmask, 4); - Streamer->EmitIntValue(ri_cprmask[0], 4); - Streamer->EmitIntValue(ri_cprmask[1], 4); - Streamer->EmitIntValue(ri_cprmask[2], 4); - Streamer->EmitIntValue(ri_cprmask[3], 4); + Streamer->emitInt32(ri_gprmask); + Streamer->emitInt32(ri_cprmask[0]); + Streamer->emitInt32(ri_cprmask[1]); + Streamer->emitInt32(ri_cprmask[2]); + Streamer->emitInt32(ri_cprmask[3]); assert((ri_gp_value & 0xffffffff) == ri_gp_value); - Streamer->EmitIntValue(ri_gp_value, 4); + Streamer->emitInt32(ri_gp_value); } Streamer->PopSection(); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index 054dc79f4aa91..6ec8fe8059680 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -109,6 +109,9 @@ void MipsTargetStreamer::emitDirectiveSetHardFloat() { void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveCpAdd(unsigned RegNo) {} void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {} void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) { // .cplocal $reg @@ -169,7 +172,7 @@ void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, TmpInst.setOpcode(Opcode); TmpInst.addOperand(MCOperand::createReg(Reg0)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, @@ -179,7 +182,7 @@ void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, TmpInst.addOperand(MCOperand::createReg(Reg0)); TmpInst.addOperand(Op1); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, @@ -199,7 +202,7 @@ void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, TmpInst.addOperand(MCOperand::createImm(Imm1)); TmpInst.addOperand(MCOperand::createImm(Imm2)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -211,7 +214,7 @@ void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, TmpInst.addOperand(MCOperand::createReg(Reg1)); TmpInst.addOperand(Op2); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -230,7 +233,7 @@ void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, TmpInst.addOperand(MCOperand::createReg(Reg2)); TmpInst.addOperand(Op3); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -251,7 +254,7 @@ void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, TmpInst.addOperand(MCOperand::createImm(Imm1)); TmpInst.addOperand(MCOperand::createImm(Imm2)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg, @@ -609,6 +612,16 @@ void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() { MipsTargetStreamer::emitDirectiveSetNoDsp(); } +void MipsTargetAsmStreamer::emitDirectiveSetMips3D() { + OS << "\t.set\tmips3d\n"; + MipsTargetStreamer::emitDirectiveSetMips3D(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetNoMips3D() { + OS << "\t.set\tnomips3d\n"; + MipsTargetStreamer::emitDirectiveSetNoMips3D(); +} + void MipsTargetAsmStreamer::emitDirectiveSetPop() { OS << "\t.set\tpop\n"; MipsTargetStreamer::emitDirectiveSetPop(); @@ -650,6 +663,12 @@ void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask, OS << "," << FPUTopSavedRegOff << '\n'; } +void MipsTargetAsmStreamer::emitDirectiveCpAdd(unsigned RegNo) { + OS << "\t.cpadd\t$" + << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; + forbidModuleDirective(); +} + void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) { OS << "\t.cpload\t$" << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; @@ -883,9 +902,9 @@ void MipsTargetELFStreamer::finish() { if (Alignment) { OS.SwitchSection(&Section); if (Section.UseCodeAlign()) - OS.EmitCodeAlignment(Alignment, Alignment); + OS.emitCodeAlignment(Alignment, Alignment); else - OS.EmitValueToAlignment(Alignment, 0, 1, Alignment); + OS.emitValueToAlignment(Alignment, 0, 1, Alignment); } } } @@ -997,17 +1016,17 @@ void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) { OS.SwitchSection(Sec); - OS.EmitValueImpl(ExprRef, 4); + OS.emitValueImpl(ExprRef, 4); - OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask - OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset + OS.emitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask + OS.emitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset - OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask - OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset + OS.emitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask + OS.emitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset - OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset - OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg - OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg + OS.emitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset + OS.emitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg + OS.emitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg // The .end directive marks the end of a procedure. Invalidate // the information gathered up until this point. @@ -1017,7 +1036,7 @@ void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) { // .end also implicitly sets the size. MCSymbol *CurPCSym = Context.createTempSymbol(); - OS.EmitLabel(CurPCSym); + OS.emitLabel(CurPCSym); const MCExpr *Size = MCBinaryExpr::createSub( MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context), ExprRef, Context); @@ -1108,6 +1127,17 @@ void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask, FPROffset = FPUTopSavedRegOff; } +void MipsTargetELFStreamer::emitDirectiveCpAdd(unsigned RegNo) { + // .cpadd $reg + // This directive inserts code to add $gp to the argument's register + // when support for position independent code is enabled. + if (!Pic) + return; + + emitAddu(RegNo, RegNo, GPReg, getABI().IsN64(), &STI); + forbidModuleDirective(); +} + void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { // .cpload $reg // This directive expands to: @@ -1139,7 +1169,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { MCA.getContext()), MCA.getContext()); TmpInst.addOperand(MCOperand::createExpr(HiSym)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); TmpInst.clear(); @@ -1152,7 +1182,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { MCA.getContext()), MCA.getContext()); TmpInst.addOperand(MCOperand::createExpr(LoSym)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); TmpInst.clear(); @@ -1160,7 +1190,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { TmpInst.addOperand(MCOperand::createReg(GPReg)); TmpInst.addOperand(MCOperand::createReg(GPReg)); TmpInst.addOperand(MCOperand::createReg(RegNo)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); forbidModuleDirective(); } @@ -1269,7 +1299,7 @@ void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation, Inst.addOperand(MCOperand::createReg(Mips::SP)); Inst.addOperand(MCOperand::createImm(SaveLocation)); } - getStreamer().EmitInstruction(Inst, STI); + getStreamer().emitInstruction(Inst, STI); forbidModuleDirective(); } |