diff options
Diffstat (limited to 'llvm/lib/Target/XCore')
23 files changed, 117 insertions, 138 deletions
diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp index ae19e2a78eec9..4c1c87cc1e689 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp @@ -28,5 +28,7 @@ XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) { // Debug ExceptionsType = ExceptionHandling::DwarfCFI; DwarfRegNumForCFI = true; + + UseIntegratedAssembler = false; } diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index 46ebccee521e5..4de252548961d 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -60,7 +60,7 @@ static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); // Initial state of the frame pointer is SP. - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, XCore::SP, 0); MAI->addInitialFrameState(Inst); return MAI; diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h index 3e56302f4adde..096b22415a22c 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h @@ -13,12 +13,6 @@ #ifndef LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCTARGETDESC_H #define LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREMCTARGETDESC_H -namespace llvm { - -class Target; - -} // end namespace llvm - // Defines symbolic names for XCore registers. This defines a mapping from // register name to register number. // diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h index b7b86be9ab511..d31c34910ef62 100644 --- a/llvm/lib/Target/XCore/XCore.h +++ b/llvm/lib/Target/XCore/XCore.h @@ -22,7 +22,6 @@ namespace llvm { class ModulePass; class TargetMachine; class XCoreTargetMachine; - class formatted_raw_ostream; void initializeXCoreLowerThreadLocalPass(PassRegistry &p); diff --git a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp index 35dc56e904195..4ea775305e127 100644 --- a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -72,12 +72,12 @@ namespace { const char *ExtraCode, raw_ostream &O) override; void emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV); - void EmitGlobalVariable(const GlobalVariable *GV) override; + void emitGlobalVariable(const GlobalVariable *GV) override; - void EmitFunctionEntryLabel() override; - void EmitInstruction(const MachineInstr *MI) override; - void EmitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; + void emitFunctionEntryLabel() override; + void emitInstruction(const MachineInstr *MI) override; + void emitFunctionBodyStart() override; + void emitFunctionBodyEnd() override; }; } // end of anonymous namespace @@ -93,21 +93,20 @@ void XCoreAsmPrinter::emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV) { MCSymbol *SymGlob = OutContext.getOrCreateSymbol( Twine(Sym->getName() + StringRef(".globound"))); - OutStreamer->EmitSymbolAttribute(SymGlob, MCSA_Global); - OutStreamer->EmitAssignment(SymGlob, + OutStreamer->emitSymbolAttribute(SymGlob, MCSA_Global); + OutStreamer->emitAssignment(SymGlob, MCConstantExpr::create(ATy->getNumElements(), OutContext)); if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || GV->hasCommonLinkage()) { - OutStreamer->EmitSymbolAttribute(SymGlob, MCSA_Weak); + OutStreamer->emitSymbolAttribute(SymGlob, MCSA_Weak); } } } -void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { +void XCoreAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { // Check to see if this is a special global used by LLVM, if so, emit it. - if (!GV->hasInitializer() || - EmitSpecialLLVMGlobal(GV)) + if (!GV->hasInitializer() || emitSpecialLLVMGlobal(GV)) return; const DataLayout &DL = getDataLayout(); @@ -130,11 +129,11 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { case GlobalValue::ExternalLinkage: case GlobalValue::CommonLinkage: emitArrayBound(GVSym, GV); - OutStreamer->EmitSymbolAttribute(GVSym, MCSA_Global); + OutStreamer->emitSymbolAttribute(GVSym, MCSA_Global); if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || GV->hasCommonLinkage()) - OutStreamer->EmitSymbolAttribute(GVSym, MCSA_Weak); + OutStreamer->emitSymbolAttribute(GVSym, MCSA_Weak); LLVM_FALLTHROUGH; case GlobalValue::InternalLinkage: case GlobalValue::PrivateLinkage: @@ -143,43 +142,43 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { llvm_unreachable("Unknown linkage type!"); } - EmitAlignment(std::max(Alignment, Align(4)), GV); + emitAlignment(std::max(Alignment, Align(4)), GV); if (GV->isThreadLocal()) { report_fatal_error("TLS is not supported by this target!"); } unsigned Size = DL.getTypeAllocSize(C->getType()); if (MAI->hasDotTypeDotSizeDirective()) { - OutStreamer->EmitSymbolAttribute(GVSym, MCSA_ELF_TypeObject); + OutStreamer->emitSymbolAttribute(GVSym, MCSA_ELF_TypeObject); OutStreamer->emitELFSize(GVSym, MCConstantExpr::create(Size, OutContext)); } - OutStreamer->EmitLabel(GVSym); + OutStreamer->emitLabel(GVSym); - EmitGlobalConstant(DL, C); + emitGlobalConstant(DL, C); // The ABI requires that unsigned scalar types smaller than 32 bits // are padded to 32 bits. if (Size < 4) - OutStreamer->EmitZeros(4 - Size); + OutStreamer->emitZeros(4 - Size); // Mark the end of the global getTargetStreamer().emitCCBottomData(GVSym->getName()); } -void XCoreAsmPrinter::EmitFunctionBodyStart() { +void XCoreAsmPrinter::emitFunctionBodyStart() { MCInstLowering.Initialize(&MF->getContext()); } /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. -void XCoreAsmPrinter::EmitFunctionBodyEnd() { +void XCoreAsmPrinter::emitFunctionBodyEnd() { // Emit function end directives getTargetStreamer().emitCCBottomFunction(CurrentFnSym->getName()); } -void XCoreAsmPrinter::EmitFunctionEntryLabel() { +void XCoreAsmPrinter::emitFunctionEntryLabel() { // Mark the start of the function getTargetStreamer().emitCCTopFunction(CurrentFnSym->getName()); - OutStreamer->EmitLabel(CurrentFnSym); + OutStreamer->emitLabel(CurrentFnSym); } void XCoreAsmPrinter:: @@ -256,7 +255,7 @@ bool XCoreAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return false; } -void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void XCoreAsmPrinter::emitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream O(Str); @@ -268,7 +267,7 @@ void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { O << "\tmov " << XCoreInstPrinter::getRegisterName(MI->getOperand(0).getReg()) << ", " << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg()); - OutStreamer->EmitRawText(O.str()); + OutStreamer->emitRawText(O.str()); return; } break; @@ -281,7 +280,7 @@ void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { else printInlineJT32(MI, 0, O); O << '\n'; - OutStreamer->EmitRawText(O.str()); + OutStreamer->emitRawText(O.str()); return; } diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index fd8b37e26e471..27ac6a4d1439b 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -73,7 +73,7 @@ static void EmitDefCfaOffset(MachineBasicBlock &MBB, int Offset) { MachineFunction &MF = *MBB.getParent(); unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset)); + MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -179,7 +179,7 @@ static MachineMemOperand *getFrameIndexMMO(MachineBasicBlock &MBB, const MachineFrameInfo &MFI = MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FrameIndex), flags, - MFI.getObjectSize(FrameIndex), MFI.getObjectAlignment(FrameIndex)); + MFI.getObjectSize(FrameIndex), MFI.getObjectAlign(FrameIndex)); return MMO; } @@ -233,9 +233,9 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF, // to determine the end of the prologue. DebugLoc dl; - if (MFI.getMaxAlignment() > getStackAlignment()) - report_fatal_error("emitPrologue unsupported alignment: " - + Twine(MFI.getMaxAlignment())); + if (MFI.getMaxAlign() > getStackAlign()) + report_fatal_error("emitPrologue unsupported alignment: " + + Twine(MFI.getMaxAlign().value())); const AttributeList &PAL = MF.getFunction().getAttributes(); if (PAL.hasAttrSomewhere(Attribute::Nest)) @@ -412,11 +412,9 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, } // else Don't erase the return instruction. } -bool XCoreFrameLowering:: -spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { +bool XCoreFrameLowering::spillCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { if (CSI.empty()) return true; @@ -429,8 +427,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, if (MI != MBB.end() && !MI->isDebugInstr()) DL = MI->getDebugLoc(); - for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); - it != CSI.end(); ++it) { + for (auto it = CSI.begin(); it != CSI.end(); ++it) { unsigned Reg = it->getReg(); assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && "LR & FP are always handled in emitPrologue"); @@ -448,25 +445,22 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, return true; } -bool XCoreFrameLowering:: -restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const{ +bool XCoreFrameLowering::restoreCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); bool AtStart = MI == MBB.begin(); MachineBasicBlock::iterator BeforeI = MI; if (!AtStart) --BeforeI; - for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); - it != CSI.end(); ++it) { - unsigned Reg = it->getReg(); + for (const CalleeSavedInfo &CSR : CSI) { + unsigned Reg = CSR.getReg(); assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && "LR & FP are always handled in emitEpilogue"); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI); + TII.loadRegFromStackSlot(MBB, MI, Reg, CSR.getFrameIdx(), RC, TRI); assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); // Insert in reverse order. loadRegFromStackSlot can insert multiple @@ -496,8 +490,7 @@ MachineBasicBlock::iterator XCoreFrameLowering::eliminateCallFramePseudoInstr( // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - unsigned Align = getStackAlignment(); - Amount = (Amount+Align-1)/Align*Align; + Amount = alignTo(Amount, getStackAlign()); assert(Amount%4 == 0); Amount /= 4; @@ -582,9 +575,9 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF, // When using SP for large frames, we may need 2 scratch registers. // When using FP, for large or small frames, we may need 1 scratch register. unsigned Size = TRI.getSpillSize(RC); - unsigned Align = TRI.getSpillAlignment(RC); + Align Alignment = TRI.getSpillAlign(RC); if (XFI->isLargeFrame(MF) || hasFP(MF)) - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false)); + RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); if (XFI->isLargeFrame(MF) && !hasFP(MF)) - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false)); + RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); } diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.h b/llvm/lib/Target/XCore/XCoreFrameLowering.h index 95c3a2973033d..a914d82e19894 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.h +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.h @@ -31,14 +31,16 @@ namespace llvm { void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const override; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const override; + bool + spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + ArrayRef<CalleeSavedInfo> CSI, + const TargetRegisterInfo *TRI) const override; + bool + restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + MutableArrayRef<CalleeSavedInfo> CSI, + const TargetRegisterInfo *TRI) const override; MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp index b1f9717fbddc0..b300697cc5ae5 100644 --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -152,7 +152,7 @@ void XCoreDAGToDAGISel::Select(SDNode *N) { CurDAG->getEntryNode()); MachineMemOperand *MemOp = MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF), - MachineMemOperand::MOLoad, 4, 4); + MachineMemOperand::MOLoad, 4, Align(4)); CurDAG->setNodeMemRefs(cast<MachineSDNode>(node), {MemOp}); ReplaceNode(N, node); return; diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index 70770f4c8e7cd..c32653137a10b 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -107,6 +107,7 @@ XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM, setOperationAction(ISD::CTPOP, MVT::i32, Expand); setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::BITREVERSE , MVT::i32, Legal); setOperationAction(ISD::TRAP, MVT::Other, Legal); @@ -328,10 +329,10 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const SDValue Res; if (CP->isMachineConstantPoolEntry()) { Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, - CP->getAlignment(), CP->getOffset()); + CP->getAlign(), CP->getOffset()); } else { - Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, - CP->getAlignment(), CP->getOffset()); + Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(), + CP->getOffset()); } return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); } @@ -434,7 +435,7 @@ SDValue XCoreTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { Offset, DAG); } if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) && - MinAlign(GV->getAlignment(), 4) == 4) { + GV->getPointerAlignment(DAG.getDataLayout()) >= 4) { SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL, BasePtr->getValueType(0)); return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, @@ -996,7 +997,7 @@ LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const { } MachineMemOperand::Flags -XCoreTargetLowering::getMMOFlags(const Instruction &I) const { +XCoreTargetLowering::getTargetMMOFlags(const Instruction &I) const { // Because of how we convert atomic_load and atomic_store to normal loads and // stores in the DAG, we need to ensure that the MMOs are marked volatile // since DAGCombine hasn't been updated to account for atomic, but non @@ -1118,7 +1119,7 @@ SDValue XCoreTargetLowering::LowerCCCCallTo( // The ABI dictates there should be one stack slot available to the callee // on function entry (for saving lr). - CCInfo.AllocateStack(4, 4); + CCInfo.AllocateStack(4, Align(4)); CCInfo.AnalyzeCallOperands(Outs, CC_XCore); @@ -1126,7 +1127,7 @@ SDValue XCoreTargetLowering::LowerCCCCallTo( // Analyze return values to determine the number of bytes of stack required. CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext()); - RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4); + RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), Align(4)); RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore); // Get a count of how many bytes are to be pushed on the stack. @@ -1391,16 +1392,16 @@ SDValue XCoreTargetLowering::LowerCCCArguments( ArgDI != ArgDE; ++ArgDI) { if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) { unsigned Size = ArgDI->Flags.getByValSize(); - unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign()); + Align Alignment = + std::max(Align(StackSlotSize), ArgDI->Flags.getNonZeroByValAlign()); // Create a new object on the stack and copy the pointee into it. - int FI = MFI.CreateStackObject(Size, Align, false); + int FI = MFI.CreateStackObject(Size, Alignment, false); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); InVals.push_back(FIN); - MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, - DAG.getConstant(Size, dl, MVT::i32), - Align, false, false, false, - MachinePointerInfo(), - MachinePointerInfo())); + MemOps.push_back(DAG.getMemcpy( + Chain, dl, FIN, ArgDI->SDV, DAG.getConstant(Size, dl, MVT::i32), + Alignment, false, false, false, MachinePointerInfo(), + MachinePointerInfo())); } else { InVals.push_back(ArgDI->SDV); } @@ -1454,7 +1455,7 @@ XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, // Analyze return values. if (!isVarArg) - CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4); + CCInfo.AllocateStack(XFI->getReturnStackOffset(), Align(4)); CCInfo.AnalyzeReturn(Outs, RetCC_XCore); @@ -1800,11 +1801,10 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, !LD->isVolatile() && !LD->isIndexed() && Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { bool isTail = isInTailCallPosition(DAG, ST, Chain); - return DAG.getMemmove(Chain, dl, ST->getBasePtr(), - LD->getBasePtr(), - DAG.getConstant(StoreBits/8, dl, MVT::i32), - Alignment, false, isTail, ST->getPointerInfo(), - LD->getPointerInfo()); + return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(), + DAG.getConstant(StoreBits / 8, dl, MVT::i32), + Align(Alignment), false, isTail, + ST->getPointerInfo(), LD->getPointerInfo()); } } break; diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h index b4f25feda7fe9..45c21fbf2b749 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.h +++ b/llvm/lib/Target/XCore/XCoreISelLowering.h @@ -22,7 +22,6 @@ namespace llvm { // Forward delcarations class XCoreSubtarget; - class XCoreTargetMachine; namespace XCoreISD { enum NodeType : unsigned { @@ -127,14 +126,14 @@ namespace llvm { /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. - unsigned + Register getExceptionPointerRegister(const Constant *PersonalityFn) const override { return XCore::R0; } /// If a physical register, this returns the register that receives the /// exception typeid on entry to a landing pad. - unsigned + Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override { return XCore::R1; } @@ -188,7 +187,8 @@ namespace llvm { SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; - MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override; + MachineMemOperand::Flags getTargetMMOFlags( + const Instruction &I) const override; // Inline asm support std::pair<unsigned, const TargetRegisterClass *> diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index db44a56be5389..1b21e1ce195b2 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -163,7 +163,7 @@ static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) } } -/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning +/// analyzeBranch - Analyze the branching code at the end of MBB, returning /// true if it cannot be understood (e.g. it's a switch dispatch or isn't /// implemented for a target). Upon success, this returns false and returns /// with the following information in various cases: @@ -357,7 +357,7 @@ void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const @@ -370,7 +370,7 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FrameIndex), MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex), - MFI.getObjectAlignment(FrameIndex)); + MFI.getObjectAlign(FrameIndex)); BuildMI(MBB, I, DL, get(XCore::STWFI)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex) @@ -380,7 +380,7 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { @@ -392,7 +392,7 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FrameIndex), MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), - MFI.getObjectAlignment(FrameIndex)); + MFI.getObjectAlign(FrameIndex)); BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) .addFrameIndex(FrameIndex) .addImm(0) @@ -443,7 +443,7 @@ MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate( MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool(); const Constant *C = ConstantInt::get( Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), Value); - unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); + unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4)); return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg) .addConstantPoolIndex(Idx) .getInstr(); diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index 057fb763efbf4..1fbb293bde602 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -68,13 +68,13 @@ public: void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index 18f02e1d80f0f..aa3739d0335ec 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -535,7 +535,7 @@ let hasSideEffects = 0, isReMaterializable = 1 in def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), "ldaw $a, dp[$b]", []>; -let isReMaterializable = 1 in +let isReMaterializable = 1 in def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), "ldaw $a, dp[$b]", [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; @@ -974,17 +974,17 @@ def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; let hasSideEffects=0 in def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; -let hasCtrlDep = 1 in +let hasCtrlDep = 1 in def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), "ecallt $a", []>; -let hasCtrlDep = 1 in +let hasCtrlDep = 1 in def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), "ecallf $a", []>; -let isCall=1, +let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), @@ -1141,7 +1141,7 @@ def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; - + def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), @@ -1154,6 +1154,9 @@ def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), def : Pat<(store GRRegs:$val, GRRegs:$addr), (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; +/// bitrev +def : Pat<(bitreverse GRRegs:$src), (BITREV_l2r GRRegs:$src)>; + /// cttz def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; diff --git a/llvm/lib/Target/XCore/XCoreMCInstLower.h b/llvm/lib/Target/XCore/XCoreMCInstLower.h index 0eaa84ef736b1..efb359cc57e11 100644 --- a/llvm/lib/Target/XCore/XCoreMCInstLower.h +++ b/llvm/lib/Target/XCore/XCoreMCInstLower.h @@ -8,6 +8,7 @@ #ifndef LLVM_LIB_TARGET_XCORE_XCOREMCINSTLOWER_H #define LLVM_LIB_TARGET_XCORE_XCOREMCINSTLOWER_H + #include "llvm/CodeGen/MachineOperand.h" #include "llvm/Support/Compiler.h" @@ -16,8 +17,6 @@ namespace llvm { class MCInst; class MCOperand; class MachineInstr; - class MachineFunction; - class Mangler; class AsmPrinter; /// This class is used to lower an MachineInstr into an MCInst. diff --git a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp index 0b4fcffbc6559..ec44d2899dd5c 100644 --- a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp @@ -43,7 +43,7 @@ int XCoreFunctionInfo::createLRSpillSlot(MachineFunction &MF) { LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); } else { LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), - TRI.getSpillAlignment(RC), true); + TRI.getSpillAlign(RC), true); } LRSpillSlotSet = true; return LRSpillSlot; @@ -56,8 +56,8 @@ int XCoreFunctionInfo::createFPSpillSlot(MachineFunction &MF) { const TargetRegisterClass &RC = XCore::GRRegsRegClass; const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); - FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), - TRI.getSpillAlignment(RC), true); + FPSpillSlot = + MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); FPSpillSlotSet = true; return FPSpillSlot; } @@ -70,9 +70,9 @@ const int* XCoreFunctionInfo::createEHSpillSlot(MachineFunction &MF) { const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); unsigned Size = TRI.getSpillSize(RC); - unsigned Align = TRI.getSpillAlignment(RC); - EHSpillSlot[0] = MFI.CreateStackObject(Size, Align, true); - EHSpillSlot[1] = MFI.CreateStackObject(Size, Align, true); + Align Alignment = TRI.getSpillAlign(RC); + EHSpillSlot[0] = MFI.CreateStackObject(Size, Alignment, true); + EHSpillSlot[1] = MFI.CreateStackObject(Size, Alignment, true); EHSpillSlotSet = true; return EHSpillSlot; } diff --git a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp index 56fed26ebd7bf..6799823f6fcb7 100644 --- a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -246,11 +246,6 @@ XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { } bool -XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { - return true; -} - -bool XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { return false; } diff --git a/llvm/lib/Target/XCore/XCoreRegisterInfo.h b/llvm/lib/Target/XCore/XCoreRegisterInfo.h index 35a42e1a14577..f1eec7bc87b43 100644 --- a/llvm/lib/Target/XCore/XCoreRegisterInfo.h +++ b/llvm/lib/Target/XCore/XCoreRegisterInfo.h @@ -20,8 +20,6 @@ namespace llvm { -class TargetInstrInfo; - struct XCoreRegisterInfo : public XCoreGenRegisterInfo { public: XCoreRegisterInfo(); @@ -34,8 +32,6 @@ public: bool requiresRegisterScavenging(const MachineFunction &MF) const override; - bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; - bool useFPForScavengingIndex(const MachineFunction &MF) const override; void eliminateFrameIndex(MachineBasicBlock::iterator II, diff --git a/llvm/lib/Target/XCore/XCoreRegisterInfo.td b/llvm/lib/Target/XCore/XCoreRegisterInfo.td index d9502939bae37..82f61d5865ab4 100644 --- a/llvm/lib/Target/XCore/XCoreRegisterInfo.td +++ b/llvm/lib/Target/XCore/XCoreRegisterInfo.td @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Declarations that describe the XCore register file +// Declarations that describe the XCore register file //===----------------------------------------------------------------------===// class XCoreReg<string n> : Register<n> { @@ -24,17 +24,17 @@ class Ri<bits<4> num, string n> : XCoreReg<n> { // CPU registers def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; -def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; +def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>; -def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>; +def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>; def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>; def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>; def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>; -def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>; +def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>; def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; def R11 : Ri<11, "r11">, DwarfRegNum<[11]>; -def CP : Ri<12, "cp">, DwarfRegNum<[12]>; +def CP : Ri<12, "cp">, DwarfRegNum<[12]>; def DP : Ri<13, "dp">, DwarfRegNum<[13]>; def SP : Ri<14, "sp">, DwarfRegNum<[14]>; def LR : Ri<15, "lr">, DwarfRegNum<[15]>; diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp index c86756e345a94..0d097076348ca 100644 --- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp @@ -17,11 +17,11 @@ using namespace llvm; SDValue XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, + SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { unsigned SizeBitWidth = Size.getValueSizeInBits(); // Call __memcpy_4 if the src, dst and size are all 4 byte aligned. - if (!AlwaysInline && (Align & 3) == 0 && + if (!AlwaysInline && Alignment >= Align(4) && DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering(); TargetLowering::ArgListTy Args; diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h index 5dcef08391c90..2abf526779785 100644 --- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h +++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h @@ -17,13 +17,11 @@ namespace llvm { -class XCoreTargetMachine; - class XCoreSelectionDAGInfo : public SelectionDAGTargetInfo { public: SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, - SDValue Op3, unsigned Align, bool isVolatile, + SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const override; diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index 736bc4148a197..1eea1e37c2538 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -54,7 +54,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT, TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveXCoreCodeModel(CM), OL), TLOF(std::make_unique<XCoreTargetObjectFile>()), - Subtarget(TT, CPU, FS, *this) { + Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); } diff --git a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp index fe743b28b4b49..9fec74a372fbe 100644 --- a/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetObjectFile.cpp @@ -140,10 +140,9 @@ MCSection *XCoreTargetObjectFile::SelectSectionForGlobal( report_fatal_error("Target does not support TLS or Common sections"); } -MCSection *XCoreTargetObjectFile::getSectionForConstant(const DataLayout &DL, - SectionKind Kind, - const Constant *C, - unsigned &Align) const { +MCSection *XCoreTargetObjectFile::getSectionForConstant( + const DataLayout &DL, SectionKind Kind, const Constant *C, + Align &Alignment) const { if (Kind.isMergeableConst4()) return MergeableConst4Section; if (Kind.isMergeableConst8()) return MergeableConst8Section; if (Kind.isMergeableConst16()) return MergeableConst16Section; diff --git a/llvm/lib/Target/XCore/XCoreTargetObjectFile.h b/llvm/lib/Target/XCore/XCoreTargetObjectFile.h index fd172c55919fa..73cc6686d7755 100644 --- a/llvm/lib/Target/XCore/XCoreTargetObjectFile.h +++ b/llvm/lib/Target/XCore/XCoreTargetObjectFile.h @@ -32,7 +32,7 @@ static const unsigned CodeModelLargeSize = 256; MCSection *getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, - unsigned &Align) const override; + Align &Alignment) const override; }; } // end namespace llvm |