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-rw-r--r--source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp2
-rw-r--r--source/Plugins/Instruction/ARM/EmulationStateARM.cpp3
-rw-r--r--source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp7
-rw-r--r--source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp7
-rw-r--r--source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp82
5 files changed, 66 insertions, 35 deletions
diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
index d0ef688f07735..262a7914d249d 100644
--- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
+++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
@@ -12,12 +12,12 @@
#include "EmulateInstructionARM.h"
#include "EmulationStateARM.h"
#include "lldb/Core/Address.h"
-#include "lldb/Core/ArchSpec.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Host/PosixApi.h"
#include "lldb/Interpreter/OptionValueArray.h"
#include "lldb/Interpreter/OptionValueDictionary.h"
#include "lldb/Symbol/UnwindPlan.h"
+#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/ConstString.h"
#include "lldb/Utility/Stream.h"
diff --git a/source/Plugins/Instruction/ARM/EmulationStateARM.cpp b/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
index 5e90965c18812..d1032f56f31cf 100644
--- a/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
+++ b/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
@@ -203,7 +203,8 @@ size_t EmulationStateARM::WritePseudoMemory(
uint32_t value1;
uint32_t value2;
memcpy (&value1, dst, sizeof (uint32_t));
- memcpy (&value2, (uint8_t *) dst + sizeof (uint32_t), sizeof (uint32_t));
+ memcpy(&value2, static_cast<const uint8_t *>(dst) + sizeof(uint32_t),
+ sizeof(uint32_t));
if (endian::InlHostByteOrder() == lldb::eByteOrderBig) {
value1 = llvm::ByteSwap_32(value1);
value2 = llvm::ByteSwap_32(value2);
diff --git a/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp b/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
index 54dd237eb4b73..d882108c25f41 100644
--- a/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
+++ b/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
@@ -12,10 +12,10 @@
#include <stdlib.h>
#include "lldb/Core/Address.h"
-#include "lldb/Core/ArchSpec.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Core/RegisterValue.h"
#include "lldb/Symbol/UnwindPlan.h"
+#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/ConstString.h"
#include "lldb/Utility/Stream.h"
@@ -167,10 +167,7 @@ EmulateInstructionARM64::CreateInstance(const ArchSpec &arch,
if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic(
inst_type)) {
if (arch.GetTriple().getArch() == llvm::Triple::aarch64) {
- std::auto_ptr<EmulateInstructionARM64> emulate_insn_ap(
- new EmulateInstructionARM64(arch));
- if (emulate_insn_ap.get())
- return emulate_insn_ap.release();
+ return new EmulateInstructionARM64(arch);
}
}
diff --git a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
index 4d1d89abb1d0f..db3d8fc1b8ca2 100644
--- a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+++ b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
@@ -12,12 +12,12 @@
#include <stdlib.h>
#include "lldb/Core/Address.h"
-#include "lldb/Core/ArchSpec.h"
#include "lldb/Core/Opcode.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Core/RegisterValue.h"
#include "lldb/Symbol/UnwindPlan.h"
#include "lldb/Target/Target.h"
+#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/ConstString.h"
#include "lldb/Utility/DataExtractor.h"
#include "lldb/Utility/Stream.h"
@@ -212,10 +212,7 @@ EmulateInstructionMIPS::CreateInstance(const ArchSpec &arch,
inst_type)) {
if (arch.GetTriple().getArch() == llvm::Triple::mips ||
arch.GetTriple().getArch() == llvm::Triple::mipsel) {
- std::auto_ptr<EmulateInstructionMIPS> emulate_insn_ap(
- new EmulateInstructionMIPS(arch));
- if (emulate_insn_ap.get())
- return emulate_insn_ap.release();
+ return new EmulateInstructionMIPS(arch);
}
}
diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
index 1e6d98756958b..d298589afdd9e 100644
--- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -12,12 +12,12 @@
#include <stdlib.h>
#include "lldb/Core/Address.h"
-#include "lldb/Core/ArchSpec.h"
#include "lldb/Core/Opcode.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Core/RegisterValue.h"
#include "lldb/Host/PosixApi.h"
#include "lldb/Symbol/UnwindPlan.h"
+#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/ConstString.h"
#include "lldb/Utility/DataExtractor.h"
#include "lldb/Utility/Stream.h"
@@ -199,10 +199,7 @@ EmulateInstructionMIPS64::CreateInstance(const ArchSpec &arch,
inst_type)) {
if (arch.GetTriple().getArch() == llvm::Triple::mips64 ||
arch.GetTriple().getArch() == llvm::Triple::mips64el) {
- std::auto_ptr<EmulateInstructionMIPS64> emulate_insn_ap(
- new EmulateInstructionMIPS64(arch));
- if (emulate_insn_ap.get())
- return emulate_insn_ap.release();
+ return new EmulateInstructionMIPS64(arch);
}
}
@@ -801,7 +798,9 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction(const char *op_name) {
// Branch instructions
//----------------------------------------------------------------------
{"BEQ", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
+ {"BEQ64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
{"BNE", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"},
+ {"BNE64", &EmulateInstructionMIPS64::Emulate_BXX_3ops, "BNE rs,rt,offset"},
{"BEQL", &EmulateInstructionMIPS64::Emulate_BXX_3ops,
"BEQL rs,rt,offset"},
{"BNEL", &EmulateInstructionMIPS64::Emulate_BXX_3ops,
@@ -814,6 +813,7 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction(const char *op_name) {
{"BALC", &EmulateInstructionMIPS64::Emulate_BALC, "BALC offset"},
{"BC", &EmulateInstructionMIPS64::Emulate_BC, "BC offset"},
{"BGEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"},
+ {"BGEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZ rs,offset"},
{"BLEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
"BLEZALC rs,offset"},
{"BGEZALC", &EmulateInstructionMIPS64::Emulate_Bcond_Link_C,
@@ -828,34 +828,61 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction(const char *op_name) {
"BNEZALC rs,offset"},
{"BEQC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
"BEQC rs,rt,offset"},
+ {"BEQC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
+ "BEQC rs,rt,offset"},
{"BNEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
"BNEC rs,rt,offset"},
+ {"BNEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
+ "BNEC rs,rt,offset"},
{"BLTC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
"BLTC rs,rt,offset"},
+ {"BLTC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
+ "BLTC rs,rt,offset"},
{"BGEC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
"BGEC rs,rt,offset"},
+ {"BGEC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
+ "BGEC rs,rt,offset"},
{"BLTUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
"BLTUC rs,rt,offset"},
+ {"BLTUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
+ "BLTUC rs,rt,offset"},
{"BGEUC", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
"BGEUC rs,rt,offset"},
+ {"BGEUC64", &EmulateInstructionMIPS64::Emulate_BXX_3ops_C,
+ "BGEUC rs,rt,offset"},
{"BLTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
"BLTZC rt,offset"},
+ {"BLTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
+ "BLTZC rt,offset"},
{"BLEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
"BLEZC rt,offset"},
+ {"BLEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
+ "BLEZC rt,offset"},
{"BGEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
"BGEZC rt,offset"},
+ {"BGEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
+ "BGEZC rt,offset"},
{"BGTZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
"BGTZC rt,offset"},
+ {"BGTZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
+ "BGTZC rt,offset"},
{"BEQZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
"BEQZC rt,offset"},
+ {"BEQZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
+ "BEQZC rt,offset"},
{"BNEZC", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
"BNEZC rt,offset"},
+ {"BNEZC64", &EmulateInstructionMIPS64::Emulate_BXX_2ops_C,
+ "BNEZC rt,offset"},
{"BGEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGEZL rt,offset"},
{"BGTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"},
+ {"BGTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZ rt,offset"},
{"BGTZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BGTZL rt,offset"},
{"BLEZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"},
+ {"BLEZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZ rt,offset"},
{"BLEZL", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLEZL rt,offset"},
{"BLTZ", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"},
+ {"BLTZ64", &EmulateInstructionMIPS64::Emulate_BXX_2ops, "BLTZ rt,offset"},
{"BLTZAL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
"BLTZAL rt,offset"},
{"BLTZALL", &EmulateInstructionMIPS64::Emulate_Bcond_Link,
@@ -872,8 +899,11 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction(const char *op_name) {
{"JALR64", &EmulateInstructionMIPS64::Emulate_JALR, "JALR target"},
{"JALR_HB", &EmulateInstructionMIPS64::Emulate_JALR, "JALR.HB target"},
{"JIALC", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"},
+ {"JIALC64", &EmulateInstructionMIPS64::Emulate_JIALC, "JIALC rt,offset"},
{"JIC", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"},
+ {"JIC64", &EmulateInstructionMIPS64::Emulate_JIC, "JIC rt,offset"},
{"JR", &EmulateInstructionMIPS64::Emulate_JR, "JR target"},
+ {"JR64", &EmulateInstructionMIPS64::Emulate_JR, "JR target"},
{"JR_HB", &EmulateInstructionMIPS64::Emulate_JR, "JR.HB target"},
{"BC1F", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1F cc, offset"},
{"BC1T", &EmulateInstructionMIPS64::Emulate_FP_branch, "BC1T cc, offset"},
@@ -1338,12 +1368,14 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) {
if (!success)
return false;
- if (!strcasecmp(op_name, "BEQ") || !strcasecmp(op_name, "BEQL")) {
+ if (!strcasecmp(op_name, "BEQ") || !strcasecmp(op_name, "BEQL")
+ || !strcasecmp(op_name, "BEQ64") ) {
if (rs_val == rt_val)
target = pc + offset;
else
target = pc + 8;
- } else if (!strcasecmp(op_name, "BNE") || !strcasecmp(op_name, "BNEL")) {
+ } else if (!strcasecmp(op_name, "BNE") || !strcasecmp(op_name, "BNEL")
+ || !strcasecmp(op_name, "BNE64")) {
if (rs_val != rt_val)
target = pc + offset;
else
@@ -1563,22 +1595,26 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) {
if (!success)
return false;
- if (!strcasecmp(op_name, "BLTZL") || !strcasecmp(op_name, "BLTZ")) {
+ if (!strcasecmp(op_name, "BLTZL") || !strcasecmp(op_name, "BLTZ")
+ || !strcasecmp(op_name, "BLTZ64")) {
if (rs_val < 0)
target = pc + offset;
else
target = pc + 8;
- } else if (!strcasecmp(op_name, "BGEZL") || !strcasecmp(op_name, "BGEZ")) {
+ } else if (!strcasecmp(op_name, "BGEZL") || !strcasecmp(op_name, "BGEZ")
+ || !strcasecmp(op_name, "BGEZ64")) {
if (rs_val >= 0)
target = pc + offset;
else
target = pc + 8;
- } else if (!strcasecmp(op_name, "BGTZL") || !strcasecmp(op_name, "BGTZ")) {
+ } else if (!strcasecmp(op_name, "BGTZL") || !strcasecmp(op_name, "BGTZ")
+ || !strcasecmp(op_name, "BGTZ64")) {
if (rs_val > 0)
target = pc + offset;
else
target = pc + 8;
- } else if (!strcasecmp(op_name, "BLEZL") || !strcasecmp(op_name, "BLEZ")) {
+ } else if (!strcasecmp(op_name, "BLEZL") || !strcasecmp(op_name, "BLEZ")
+ || !strcasecmp(op_name, "BLEZ64")) {
if (rs_val <= 0)
target = pc + offset;
else
@@ -1657,32 +1693,32 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
if (!success)
return false;
- if (!strcasecmp(op_name, "BEQC")) {
+ if (!strcasecmp(op_name, "BEQC") || !strcasecmp(op_name, "BEQC64")) {
if (rs_val == rt_val)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BNEC")) {
+ } else if (!strcasecmp(op_name, "BNEC") || !strcasecmp(op_name, "BNEC64")) {
if (rs_val != rt_val)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BLTC")) {
+ } else if (!strcasecmp(op_name, "BLTC") || !strcasecmp(op_name, "BLTC64")) {
if (rs_val < rt_val)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BGEC")) {
+ } else if (!strcasecmp(op_name, "BGEC64") || !strcasecmp(op_name, "BGEC")) {
if (rs_val >= rt_val)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BLTUC")) {
+ } else if (!strcasecmp(op_name, "BLTUC") || !strcasecmp(op_name, "BLTUC64")) {
if (rs_val < rt_val)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BGEUC")) {
+ } else if (!strcasecmp(op_name, "BGEUC") || !strcasecmp(op_name, "BGEUC64")) {
if ((uint32_t)rs_val >= (uint32_t)rt_val)
target = pc + offset;
else
@@ -1734,32 +1770,32 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
if (!success)
return false;
- if (!strcasecmp(op_name, "BLTZC")) {
+ if (!strcasecmp(op_name, "BLTZC") || !strcasecmp(op_name, "BLTZC64")) {
if (rs_val < 0)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BLEZC")) {
+ } else if (!strcasecmp(op_name, "BLEZC") || !strcasecmp(op_name, "BLEZC64")) {
if (rs_val <= 0)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BGEZC")) {
+ } else if (!strcasecmp(op_name, "BGEZC") || !strcasecmp(op_name, "BGEZC64")) {
if (rs_val >= 0)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BGTZC")) {
+ } else if (!strcasecmp(op_name, "BGTZC") || !strcasecmp(op_name, "BGTZC64")) {
if (rs_val > 0)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BEQZC")) {
+ } else if (!strcasecmp(op_name, "BEQZC") || !strcasecmp(op_name, "BEQZC64")) {
if (rs_val == 0)
target = pc + offset;
else
target = pc + 4;
- } else if (!strcasecmp(op_name, "BNEZC")) {
+ } else if (!strcasecmp(op_name, "BNEZC") || !strcasecmp(op_name, "BNEZC64")) {
if (rs_val != 0)
target = pc + offset;
else
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-02 08:39:34 +0000