diff options
Diffstat (limited to 'src/arc')
| -rw-r--r-- | src/arc/axc003.dtsi | 8 | ||||
| -rw-r--r-- | src/arc/axc003_idu.dtsi | 8 | ||||
| -rw-r--r-- | src/arc/axs10x_mb.dtsi | 8 | ||||
| -rw-r--r-- | src/arc/hsdk.dts | 8 |
4 files changed, 32 insertions, 0 deletions
diff --git a/src/arc/axc003.dtsi b/src/arc/axc003.dtsi index 4e6e9f57e790a..dc91c663bcc02 100644 --- a/src/arc/axc003.dtsi +++ b/src/arc/axc003.dtsi @@ -35,6 +35,14 @@ reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 90MHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <90000000>; }; core_intc: archs-intc@cpu { diff --git a/src/arc/axc003_idu.dtsi b/src/arc/axc003_idu.dtsi index 63954a8b0100e..69ff4895f2ba4 100644 --- a/src/arc/axc003_idu.dtsi +++ b/src/arc/axc003_idu.dtsi @@ -35,6 +35,14 @@ reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 100MHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <100000000>; }; core_intc: archs-intc@cpu { diff --git a/src/arc/axs10x_mb.dtsi b/src/arc/axs10x_mb.dtsi index e114000a84f56..74d070cd3c13a 100644 --- a/src/arc/axs10x_mb.dtsi +++ b/src/arc/axs10x_mb.dtsi @@ -16,6 +16,12 @@ ranges = <0x00000000 0x0 0xe0000000 0x10000000>; interrupt-parent = <&mb_intc>; + creg_rst: reset-controller@11220 { + compatible = "snps,axs10x-reset"; + #reset-cells = <1>; + reg = <0x11220 0x4>; + }; + i2sclk: i2sclk@100a0 { compatible = "snps,axs10x-i2s-pll-clock"; reg = <0x100a0 0x10>; @@ -73,6 +79,8 @@ clocks = <&apbclk>; clock-names = "stmmaceth"; max-speed = <100>; + resets = <&creg_rst 5>; + reset-names = "stmmaceth"; }; ehci@0x40000 { diff --git a/src/arc/hsdk.dts b/src/arc/hsdk.dts index 8f627c200d609..006aa3de5348f 100644 --- a/src/arc/hsdk.dts +++ b/src/arc/hsdk.dts @@ -114,6 +114,14 @@ reg = <0x00 0x10>, <0x14B8 0x4>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 1GHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <1000000000>; }; serial: serial@5000 { |