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-rw-r--r--test/Analysis/BlockFrequencyInfo/irreducible.ll11
-rw-r--r--test/Analysis/CallGraph/do-nothing-intrinsic.ll4
-rw-r--r--test/Analysis/CallGraph/non-leaf-intrinsics.ll32
-rw-r--r--test/Analysis/CostModel/X86/sitofp.ll428
-rw-r--r--test/Analysis/CostModel/X86/testshiftashr.ll24
-rw-r--r--test/Analysis/CostModel/X86/testshiftlshr.ll24
-rw-r--r--test/Analysis/CostModel/X86/testshiftshl.ll24
-rw-r--r--test/Analysis/CostModel/X86/uitofp.ll455
-rw-r--r--test/Analysis/Dominators/invoke.ll4
-rw-r--r--test/Analysis/LazyCallGraph/basic.ll4
-rw-r--r--test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll10
-rw-r--r--test/Analysis/Lint/cppeh-catch-intrinsics.ll26
-rw-r--r--test/Analysis/ValueTracking/assume.ll14
-rw-r--r--test/Analysis/ValueTracking/dom-cond.ll18
14 files changed, 884 insertions, 194 deletions
diff --git a/test/Analysis/BlockFrequencyInfo/irreducible.ll b/test/Analysis/BlockFrequencyInfo/irreducible.ll
index b275aae62792d..c1b1c2a7a23c1 100644
--- a/test/Analysis/BlockFrequencyInfo/irreducible.ll
+++ b/test/Analysis/BlockFrequencyInfo/irreducible.ll
@@ -130,9 +130,6 @@ exit:
; At the first step, c1 and c2 each get 1/3 of the entry. At each subsequent
; step, c1 and c2 each get 1/3 of what's left in c1 and c2 combined. This
; infinite series sums to 1.
-;
-; Since the currently algorithm *always* assumes entry blocks are equal,
-; -block-freq gets the right answers here.
define void @crossloops(i2 %x) {
; CHECK-LABEL: Printing analysis {{.*}} for function 'crossloops':
; CHECK-NEXT: block-frequency-info: crossloops
@@ -386,7 +383,7 @@ exit:
;
; This testcases uses non-trivial branch weights. The CHECK statements here
; will start to fail if we change -block-freq to be more accurate. Currently,
-; we expect left, right and top to be treated as equal headers.
+; loop headers are affected by the weight of their corresponding back edges.
define void @nonentry_header(i1 %x, i2 %y) {
; CHECK-LABEL: Printing analysis {{.*}} for function 'nonentry_header':
; CHECK-NEXT: block-frequency-info: nonentry_header
@@ -395,15 +392,15 @@ entry:
br i1 %x, label %left, label %right, !prof !21
left:
-; CHECK-NEXT: left: float = 3.0,
+; CHECK-NEXT: left: float = 0.14
br i1 %x, label %top, label %bottom, !prof !22
right:
-; CHECK-NEXT: right: float = 3.0,
+; CHECK-NEXT: right: float = 0.42
br i1 %x, label %top, label %bottom, !prof !22
top:
-; CHECK-NEXT: top: float = 3.0,
+; CHECK-NEXT: top: float = 8.43
switch i2 %y, label %exit [ i2 0, label %left
i2 1, label %right
i2 2, label %bottom ], !prof !23
diff --git a/test/Analysis/CallGraph/do-nothing-intrinsic.ll b/test/Analysis/CallGraph/do-nothing-intrinsic.ll
index f28ad10f57c8a..5462371708368 100644
--- a/test/Analysis/CallGraph/do-nothing-intrinsic.ll
+++ b/test/Analysis/CallGraph/do-nothing-intrinsic.ll
@@ -1,11 +1,11 @@
; RUN: opt < %s -basiccg
; PR13903
-define void @main() {
+define void @main() personality i8 0 {
invoke void @llvm.donothing()
to label %ret unwind label %unw
unw:
- %tmp = landingpad i8 personality i8 0 cleanup
+ %tmp = landingpad i8 cleanup
br label %ret
ret:
ret void
diff --git a/test/Analysis/CallGraph/non-leaf-intrinsics.ll b/test/Analysis/CallGraph/non-leaf-intrinsics.ll
new file mode 100644
index 0000000000000..11bed6abce601
--- /dev/null
+++ b/test/Analysis/CallGraph/non-leaf-intrinsics.ll
@@ -0,0 +1,32 @@
+; RUN: opt -S -print-callgraph -disable-output < %s 2>&1 | FileCheck %s
+
+declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
+declare i32 @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)
+
+define private void @f() {
+ ret void
+}
+
+define void @calls_statepoint(i8 addrspace(1)* %arg) gc "statepoint-example" {
+entry:
+ %cast = bitcast i8 addrspace(1)* %arg to i64 addrspace(1)*
+ %safepoint_token = call i32 (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @f, i32 0, i32 0, i32 0, i32 5, i32 0, i32 0, i32 0, i32 10, i32 0, i8 addrspace(1)* %arg, i64 addrspace(1)* %cast, i8 addrspace(1)* %arg, i8 addrspace(1)* %arg)
+ ret void
+}
+
+define void @calls_patchpoint() {
+entry:
+ %c = bitcast void()* @f to i8*
+ tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %c, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
+ ret void
+}
+
+
+; CHECK: Call graph node <<null function>>
+; CHECK: CS<0x0> calls function 'f'
+
+; CHECK: Call graph node for function: 'calls_patchpoint'
+; CHECK-NEXT: CS<[[addr_1:[^>]+]]> calls external node
+
+; CHECK: Call graph node for function: 'calls_statepoint'
+; CHECK-NEXT: CS<[[addr_0:[^>]+]]> calls external node
diff --git a/test/Analysis/CostModel/X86/sitofp.ll b/test/Analysis/CostModel/X86/sitofp.ll
index edc937ecf9467..dcd0088d0df70 100644
--- a/test/Analysis/CostModel/X86/sitofp.ll
+++ b/test/Analysis/CostModel/X86/sitofp.ll
@@ -1,9 +1,20 @@
-; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s
-; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=knl -cost-model -analyze < %s | FileCheck --check-prefix=AVX512F %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE --check-prefix=SSE2 %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+avx -cost-model -analyze < %s | FileCheck --check-prefix=AVX --check-prefix=AVX1 %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+avx2 -cost-model -analyze < %s | FileCheck --check-prefix=AVX --check-prefix=AVX2 %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+avx512f -cost-model -analyze < %s | FileCheck --check-prefix=AVX512F %s
define <2 x double> @sitofpv2i8v2double(<2 x i8> %a) {
; SSE2: sitofpv2i8v2double
; SSE2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i8v2double
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i8v2double
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i8v2double
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i8> %a to <2 x double>
ret <2 x double> %1
}
@@ -11,6 +22,15 @@ define <2 x double> @sitofpv2i8v2double(<2 x i8> %a) {
define <4 x double> @sitofpv4i8v4double(<4 x i8> %a) {
; SSE2: sitofpv4i8v4double
; SSE2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i8v4double
+ ; AVX1: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i8v4double
+ ; AVX2: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i8v4double
+ ; AVX512F: cost of 3 {{.*}} sitofp
%1 = sitofp <4 x i8> %a to <4 x double>
ret <4 x double> %1
}
@@ -18,13 +38,31 @@ define <4 x double> @sitofpv4i8v4double(<4 x i8> %a) {
define <8 x double> @sitofpv8i8v8double(<8 x i8> %a) {
; SSE2: sitofpv8i8v8double
; SSE2: cost of 80 {{.*}} sitofp
-%1 = sitofp <8 x i8> %a to <8 x double>
+ ;
+ ; AVX1: sitofpv8i8v8double
+ ; AVX1: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i8v8double
+ ; AVX2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i8v8double
+ ; AVX512F: cost of 2 {{.*}} sitofp
+ %1 = sitofp <8 x i8> %a to <8 x double>
ret <8 x double> %1
}
define <16 x double> @sitofpv16i8v16double(<16 x i8> %a) {
; SSE2: sitofpv16i8v16double
; SSE2: cost of 160 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i8v16double
+ ; AVX1: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i8v16double
+ ; AVX2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i8v16double
+ ; AVX512F: cost of 44 {{.*}} sitofp
%1 = sitofp <16 x i8> %a to <16 x double>
ret <16 x double> %1
}
@@ -32,6 +70,15 @@ define <16 x double> @sitofpv16i8v16double(<16 x i8> %a) {
define <32 x double> @sitofpv32i8v32double(<32 x i8> %a) {
; SSE2: sitofpv32i8v32double
; SSE2: cost of 320 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i8v32double
+ ; AVX1: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i8v32double
+ ; AVX2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i8v32double
+ ; AVX512F: cost of 88 {{.*}} sitofp
%1 = sitofp <32 x i8> %a to <32 x double>
ret <32 x double> %1
}
@@ -39,6 +86,15 @@ define <32 x double> @sitofpv32i8v32double(<32 x i8> %a) {
define <2 x double> @sitofpv2i16v2double(<2 x i16> %a) {
; SSE2: sitofpv2i16v2double
; SSE2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i16v2double
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i16v2double
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i16v2double
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i16> %a to <2 x double>
ret <2 x double> %1
}
@@ -46,6 +102,15 @@ define <2 x double> @sitofpv2i16v2double(<2 x i16> %a) {
define <4 x double> @sitofpv4i16v4double(<4 x i16> %a) {
; SSE2: sitofpv4i16v4double
; SSE2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i16v4double
+ ; AVX1: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i16v4double
+ ; AVX2: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i16v4double
+ ; AVX512F: cost of 3 {{.*}} sitofp
%1 = sitofp <4 x i16> %a to <4 x double>
ret <4 x double> %1
}
@@ -53,6 +118,15 @@ define <4 x double> @sitofpv4i16v4double(<4 x i16> %a) {
define <8 x double> @sitofpv8i16v8double(<8 x i16> %a) {
; SSE2: sitofpv8i16v8double
; SSE2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i16v8double
+ ; AVX1: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i16v8double
+ ; AVX2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i16v8double
+ ; AVX512F: cost of 2 {{.*}} sitofp
%1 = sitofp <8 x i16> %a to <8 x double>
ret <8 x double> %1
}
@@ -60,6 +134,15 @@ define <8 x double> @sitofpv8i16v8double(<8 x i16> %a) {
define <16 x double> @sitofpv16i16v16double(<16 x i16> %a) {
; SSE2: sitofpv16i16v16double
; SSE2: cost of 160 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i16v16double
+ ; AVX1: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i16v16double
+ ; AVX2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i16v16double
+ ; AVX512F: cost of 44 {{.*}} sitofp
%1 = sitofp <16 x i16> %a to <16 x double>
ret <16 x double> %1
}
@@ -67,6 +150,15 @@ define <16 x double> @sitofpv16i16v16double(<16 x i16> %a) {
define <32 x double> @sitofpv32i16v32double(<32 x i16> %a) {
; SSE2: sitofpv32i16v32double
; SSE2: cost of 320 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i16v32double
+ ; AVX1: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i16v32double
+ ; AVX2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i16v32double
+ ; AVX512F: cost of 88 {{.*}} sitofp
%1 = sitofp <32 x i16> %a to <32 x double>
ret <32 x double> %1
}
@@ -74,6 +166,15 @@ define <32 x double> @sitofpv32i16v32double(<32 x i16> %a) {
define <2 x double> @sitofpv2i32v2double(<2 x i32> %a) {
; SSE2: sitofpv2i32v2double
; SSE2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i32v2double
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i32v2double
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i32v2double
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i32> %a to <2 x double>
ret <2 x double> %1
}
@@ -81,6 +182,15 @@ define <2 x double> @sitofpv2i32v2double(<2 x i32> %a) {
define <4 x double> @sitofpv4i32v4double(<4 x i32> %a) {
; SSE2: sitofpv4i32v4double
; SSE2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i32v4double
+ ; AVX1: cost of 1 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i32v4double
+ ; AVX2: cost of 1 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i32v4double
+ ; AVX512F: cost of 1 {{.*}} sitofp
%1 = sitofp <4 x i32> %a to <4 x double>
ret <4 x double> %1
}
@@ -88,6 +198,15 @@ define <4 x double> @sitofpv4i32v4double(<4 x i32> %a) {
define <8 x double> @sitofpv8i32v8double(<8 x i32> %a) {
; SSE2: sitofpv8i32v8double
; SSE2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i32v8double
+ ; AVX1: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i32v8double
+ ; AVX2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i32v8double
+ ; AVX512F: cost of 1 {{.*}} sitofp
%1 = sitofp <8 x i32> %a to <8 x double>
ret <8 x double> %1
}
@@ -95,6 +214,15 @@ define <8 x double> @sitofpv8i32v8double(<8 x i32> %a) {
define <16 x double> @sitofpv16i32v16double(<16 x i32> %a) {
; SSE2: sitofpv16i32v16double
; SSE2: cost of 160 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i32v16double
+ ; AVX1: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i32v16double
+ ; AVX2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i32v16double
+ ; AVX512F: cost of 44 {{.*}} sitofp
%1 = sitofp <16 x i32> %a to <16 x double>
ret <16 x double> %1
}
@@ -102,6 +230,15 @@ define <16 x double> @sitofpv16i32v16double(<16 x i32> %a) {
define <32 x double> @sitofpv32i32v32double(<32 x i32> %a) {
; SSE2: sitofpv32i32v32double
; SSE2: cost of 320 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i32v32double
+ ; AVX1: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i32v32double
+ ; AVX2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i32v32double
+ ; AVX512F: cost of 88 {{.*}} sitofp
%1 = sitofp <32 x i32> %a to <32 x double>
ret <32 x double> %1
}
@@ -109,6 +246,15 @@ define <32 x double> @sitofpv32i32v32double(<32 x i32> %a) {
define <2 x double> @sitofpv2i64v2double(<2 x i64> %a) {
; SSE2: sitofpv2i64v2double
; SSE2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i64v2double
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i64v2double
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i64v2double
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i64> %a to <2 x double>
ret <2 x double> %1
}
@@ -116,20 +262,47 @@ define <2 x double> @sitofpv2i64v2double(<2 x i64> %a) {
define <4 x double> @sitofpv4i64v4double(<4 x i64> %a) {
; SSE2: sitofpv4i64v4double
; SSE2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i64v4double
+ ; AVX1: cost of 10 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i64v4double
+ ; AVX2: cost of 10 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i64v4double
+ ; AVX512F: cost of 10 {{.*}} sitofp
%1 = sitofp <4 x i64> %a to <4 x double>
ret <4 x double> %1
}
define <8 x double> @sitofpv8i64v8double(<8 x i64> %a) {
- %1 = sitofp <8 x i64> %a to <8 x double>
; SSE2: sitofpv8i64v8double
; SSE2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i64v8double
+ ; AVX1: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i64v8double
+ ; AVX2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i64v8double
+ ; AVX512F: cost of 22 {{.*}} sitofp
+ %1 = sitofp <8 x i64> %a to <8 x double>
ret <8 x double> %1
}
define <16 x double> @sitofpv16i64v16double(<16 x i64> %a) {
; SSE2: sitofpv16i64v16double
; SSE2: cost of 160 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i64v16double
+ ; AVX1: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i64v16double
+ ; AVX2: cost of 40 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i64v16double
+ ; AVX512F: cost of 44 {{.*}} sitofp
%1 = sitofp <16 x i64> %a to <16 x double>
ret <16 x double> %1
}
@@ -137,6 +310,15 @@ define <16 x double> @sitofpv16i64v16double(<16 x i64> %a) {
define <32 x double> @sitofpv32i64v32double(<32 x i64> %a) {
; SSE2: sitofpv32i64v32double
; SSE2: cost of 320 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i64v32double
+ ; AVX1: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i64v32double
+ ; AVX2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i64v32double
+ ; AVX512F: cost of 88 {{.*}} sitofp
%1 = sitofp <32 x i64> %a to <32 x double>
ret <32 x double> %1
}
@@ -144,6 +326,15 @@ define <32 x double> @sitofpv32i64v32double(<32 x i64> %a) {
define <2 x float> @sitofpv2i8v2float(<2 x i8> %a) {
; SSE2: sitofpv2i8v2float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i8v2float
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i8v2float
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i8v2float
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i8> %a to <2 x float>
ret <2 x float> %1
}
@@ -151,6 +342,15 @@ define <2 x float> @sitofpv2i8v2float(<2 x i8> %a) {
define <4 x float> @sitofpv4i8v4float(<4 x i8> %a) {
; SSE2: sitofpv4i8v4float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i8v4float
+ ; AVX1: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i8v4float
+ ; AVX2: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i8v4float
+ ; AVX512F: cost of 3 {{.*}} sitofp
%1 = sitofp <4 x i8> %a to <4 x float>
ret <4 x float> %1
}
@@ -158,6 +358,15 @@ define <4 x float> @sitofpv4i8v4float(<4 x i8> %a) {
define <8 x float> @sitofpv8i8v8float(<8 x i8> %a) {
; SSE2: sitofpv8i8v8float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i8v8float
+ ; AVX1: cost of 8 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i8v8float
+ ; AVX2: cost of 8 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i8v8float
+ ; AVX512F: cost of 8 {{.*}} sitofp
%1 = sitofp <8 x i8> %a to <8 x float>
ret <8 x float> %1
}
@@ -165,6 +374,15 @@ define <8 x float> @sitofpv8i8v8float(<8 x i8> %a) {
define <16 x float> @sitofpv16i8v16float(<16 x i8> %a) {
; SSE2: sitofpv16i8v16float
; SSE2: cost of 8 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i8v16float
+ ; AVX1: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i8v16float
+ ; AVX2: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i8v16float
+ ; AVX512F: cost of 2 {{.*}} sitofp
%1 = sitofp <16 x i8> %a to <16 x float>
ret <16 x float> %1
}
@@ -172,6 +390,15 @@ define <16 x float> @sitofpv16i8v16float(<16 x i8> %a) {
define <32 x float> @sitofpv32i8v32float(<32 x i8> %a) {
; SSE2: sitofpv32i8v32float
; SSE2: cost of 16 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i8v32float
+ ; AVX1: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i8v32float
+ ; AVX2: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i8v32float
+ ; AVX512F: cost of 92 {{.*}} sitofp
%1 = sitofp <32 x i8> %a to <32 x float>
ret <32 x float> %1
}
@@ -179,6 +406,15 @@ define <32 x float> @sitofpv32i8v32float(<32 x i8> %a) {
define <2 x float> @sitofpv2i16v2float(<2 x i16> %a) {
; SSE2: sitofpv2i16v2float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i16v2float
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i16v2float
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i16v2float
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i16> %a to <2 x float>
ret <2 x float> %1
}
@@ -186,6 +422,15 @@ define <2 x float> @sitofpv2i16v2float(<2 x i16> %a) {
define <4 x float> @sitofpv4i16v4float(<4 x i16> %a) {
; SSE2: sitofpv4i16v4float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i16v4float
+ ; AVX1: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i16v4float
+ ; AVX2: cost of 3 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i16v4float
+ ; AVX512F: cost of 3 {{.*}} sitofp
%1 = sitofp <4 x i16> %a to <4 x float>
ret <4 x float> %1
}
@@ -193,6 +438,15 @@ define <4 x float> @sitofpv4i16v4float(<4 x i16> %a) {
define <8 x float> @sitofpv8i16v8float(<8 x i16> %a) {
; SSE2: sitofpv8i16v8float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i16v8float
+ ; AVX1: cost of 5 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i16v8float
+ ; AVX2: cost of 5 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i16v8float
+ ; AVX512F: cost of 5 {{.*}} sitofp
%1 = sitofp <8 x i16> %a to <8 x float>
ret <8 x float> %1
}
@@ -200,6 +454,15 @@ define <8 x float> @sitofpv8i16v8float(<8 x i16> %a) {
define <16 x float> @sitofpv16i16v16float(<16 x i16> %a) {
; SSE2: sitofpv16i16v16float
; SSE2: cost of 30 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i16v16float
+ ; AVX1: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i16v16float
+ ; AVX2: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i16v16float
+ ; AVX512F: cost of 2 {{.*}} sitofp
%1 = sitofp <16 x i16> %a to <16 x float>
ret <16 x float> %1
}
@@ -207,6 +470,15 @@ define <16 x float> @sitofpv16i16v16float(<16 x i16> %a) {
define <32 x float> @sitofpv32i16v32float(<32 x i16> %a) {
; SSE2: sitofpv32i16v32float
; SSE2: cost of 60 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i16v32float
+ ; AVX1: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i16v32float
+ ; AVX2: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i16v32float
+ ; AVX512F: cost of 2 {{.*}} sitofp
%1 = sitofp <32 x i16> %a to <32 x float>
ret <32 x float> %1
}
@@ -214,6 +486,15 @@ define <32 x float> @sitofpv32i16v32float(<32 x i16> %a) {
define <2 x float> @sitofpv2i32v2float(<2 x i32> %a) {
; SSE2: sitofpv2i32v2float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i32v2float
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i32v2float
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i32v2float
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i32> %a to <2 x float>
ret <2 x float> %1
}
@@ -221,6 +502,15 @@ define <2 x float> @sitofpv2i32v2float(<2 x i32> %a) {
define <4 x float> @sitofpv4i32v4float(<4 x i32> %a) {
; SSE2: sitofpv4i32v4float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i32v4float
+ ; AVX1: cost of 1 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i32v4float
+ ; AVX2: cost of 1 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i32v4float
+ ; AVX512F: cost of 1 {{.*}} sitofp
%1 = sitofp <4 x i32> %a to <4 x float>
ret <4 x float> %1
}
@@ -228,6 +518,15 @@ define <4 x float> @sitofpv4i32v4float(<4 x i32> %a) {
define <8 x float> @sitofpv8i32v8float(<8 x i32> %a) {
; SSE2: sitofpv8i32v8float
; SSE2: cost of 30 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i32v8float
+ ; AVX1: cost of 1 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i32v8float
+ ; AVX2: cost of 1 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i32v8float
+ ; AVX512F: cost of 1 {{.*}} sitofp
%1 = sitofp <8 x i32> %a to <8 x float>
ret <8 x float> %1
}
@@ -235,6 +534,15 @@ define <8 x float> @sitofpv8i32v8float(<8 x i32> %a) {
define <16 x float> @sitofpv16i32v16float(<16 x i32> %a) {
; SSE2: sitofpv16i32v16float
; SSE2: cost of 60 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i32v16float
+ ; AVX1: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i32v16float
+ ; AVX2: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i32v16float
+ ; AVX512F: cost of 1 {{.*}} sitofp
%1 = sitofp <16 x i32> %a to <16 x float>
ret <16 x float> %1
}
@@ -242,6 +550,15 @@ define <16 x float> @sitofpv16i32v16float(<16 x i32> %a) {
define <32 x float> @sitofpv32i32v32float(<32 x i32> %a) {
; SSE2: sitofpv32i32v32float
; SSE2: cost of 120 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i32v32float
+ ; AVX1: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i32v32float
+ ; AVX2: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i32v32float
+ ; AVX512F: cost of 1 {{.*}} sitofp
%1 = sitofp <32 x i32> %a to <32 x float>
ret <32 x float> %1
}
@@ -249,6 +566,15 @@ define <32 x float> @sitofpv32i32v32float(<32 x i32> %a) {
define <2 x float> @sitofpv2i64v2float(<2 x i64> %a) {
; SSE2: sitofpv2i64v2float
; SSE2: cost of 15 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv2i64v2float
+ ; AVX1: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv2i64v2float
+ ; AVX2: cost of 4 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv2i64v2float
+ ; AVX512F: cost of 4 {{.*}} sitofp
%1 = sitofp <2 x i64> %a to <2 x float>
ret <2 x float> %1
}
@@ -256,6 +582,15 @@ define <2 x float> @sitofpv2i64v2float(<2 x i64> %a) {
define <4 x float> @sitofpv4i64v4float(<4 x i64> %a) {
; SSE2: sitofpv4i64v4float
; SSE2: cost of 30 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv4i64v4float
+ ; AVX1: cost of 10 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv4i64v4float
+ ; AVX2: cost of 10 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv4i64v4float
+ ; AVX512F: cost of 10 {{.*}} sitofp
%1 = sitofp <4 x i64> %a to <4 x float>
ret <4 x float> %1
}
@@ -263,6 +598,15 @@ define <4 x float> @sitofpv4i64v4float(<4 x i64> %a) {
define <8 x float> @sitofpv8i64v8float(<8 x i64> %a) {
; SSE2: sitofpv8i64v8float
; SSE2: cost of 60 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i64v8float
+ ; AVX1: cost of 22 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i64v8float
+ ; AVX2: cost of 22 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i64v8float
+ ; AVX512F: cost of 22 {{.*}} sitofp
%1 = sitofp <8 x i64> %a to <8 x float>
ret <8 x float> %1
}
@@ -270,6 +614,15 @@ define <8 x float> @sitofpv8i64v8float(<8 x i64> %a) {
define <16 x float> @sitofpv16i64v16float(<16 x i64> %a) {
; SSE2: sitofpv16i64v16float
; SSE2: cost of 120 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i64v16float
+ ; AVX1: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i64v16float
+ ; AVX2: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i64v16float
+ ; AVX512F: cost of 46 {{.*}} sitofp
%1 = sitofp <16 x i64> %a to <16 x float>
ret <16 x float> %1
}
@@ -277,49 +630,48 @@ define <16 x float> @sitofpv16i64v16float(<16 x i64> %a) {
define <32 x float> @sitofpv32i64v32float(<32 x i64> %a) {
; SSE2: sitofpv32i64v32float
; SSE2: cost of 240 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv32i64v32float
+ ; AVX1: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv32i64v32float
+ ; AVX2: cost of 88 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv32i64v32float
+ ; AVX512F: cost of 92 {{.*}} sitofp
%1 = sitofp <32 x i64> %a to <32 x float>
ret <32 x float> %1
}
-; AVX512F-LABEL: sitofp_16i8_float
-; AVX512F: cost of 2 {{.*}} sitofp
-define <16 x float> @sitofp_16i8_float(<16 x i8> %a) {
- %1 = sitofp <16 x i8> %a to <16 x float>
- ret <16 x float> %1
-}
-
-define <16 x float> @sitofp_16i16_float(<16 x i16> %a) {
- ; AVX512F-LABEL: sitofp_16i16_float
- ; AVX512F: cost of 2 {{.*}} sitofp
- %1 = sitofp <16 x i16> %a to <16 x float>
- ret <16 x float> %1
-}
-
-; AVX512F-LABEL: sitofp_8i8_double
-; AVX512F: cost of 2 {{.*}} sitofp
-define <8 x double> @sitofp_8i8_double(<8 x i8> %a) {
- %1 = sitofp <8 x i8> %a to <8 x double>
- ret <8 x double> %1
-}
-
-; AVX512F-LABEL: sitofp_8i16_double
-; AVX512F: cost of 2 {{.*}} sitofp
-define <8 x double> @sitofp_8i16_double(<8 x i16> %a) {
- %1 = sitofp <8 x i16> %a to <8 x double>
- ret <8 x double> %1
-}
-
-; AVX512F-LABEL: sitofp_8i1_double
-; AVX512F: cost of 4 {{.*}} sitofp
-define <8 x double> @sitofp_8i1_double(<8 x double> %a) {
+define <8 x double> @sitofpv8i1v8double(<8 x double> %a) {
+ ; SSE2: sitofpv8i1v8double
+ ; SSE2: cost of 80 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv8i1v8double
+ ; AVX1: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv8i1v8double
+ ; AVX2: cost of 20 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv8i1v8double
+ ; AVX512F: cost of 4 {{.*}} sitofp
%cmpres = fcmp ogt <8 x double> %a, zeroinitializer
%1 = sitofp <8 x i1> %cmpres to <8 x double>
ret <8 x double> %1
}
-; AVX512F-LABEL: sitofp_16i1_float
-; AVX512F: cost of 3 {{.*}} sitofp
-define <16 x float> @sitofp_16i1_float(<16 x float> %a) {
+define <16 x float> @sitofpv16i1v16float(<16 x float> %a) {
+ ; SSE2: sitofpv16i1v16float
+ ; SSE2: cost of 8 {{.*}} sitofp
+ ;
+ ; AVX1: sitofpv16i1v16float
+ ; AVX1: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX2: sitofpv16i1v16float
+ ; AVX2: cost of 44 {{.*}} sitofp
+ ;
+ ; AVX512F: sitofpv16i1v16float
+ ; AVX512F: cost of 3 {{.*}} sitofp
%cmpres = fcmp ogt <16 x float> %a, zeroinitializer
%1 = sitofp <16 x i1> %cmpres to <16 x float>
ret <16 x float> %1
diff --git a/test/Analysis/CostModel/X86/testshiftashr.ll b/test/Analysis/CostModel/X86/testshiftashr.ll
index d96a92fe2a8a2..ced2ffed45520 100644
--- a/test/Analysis/CostModel/X86/testshiftashr.ll
+++ b/test/Analysis/CostModel/X86/testshiftashr.ll
@@ -29,9 +29,9 @@ entry:
define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) {
entry:
; SSE2: shift8i16
- ; SSE2: cost of 80 {{.*}} ashr
+ ; SSE2: cost of 32 {{.*}} ashr
; SSE2-CODEGEN: shift8i16
- ; SSE2-CODEGEN: sarw %cl
+ ; SSE2-CODEGEN: psraw
%0 = ashr %shifttype8i16 %a , %b
ret %shifttype8i16 %0
@@ -41,9 +41,9 @@ entry:
define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) {
entry:
; SSE2: shift16i16
- ; SSE2: cost of 160 {{.*}} ashr
+ ; SSE2: cost of 64 {{.*}} ashr
; SSE2-CODEGEN: shift16i16
- ; SSE2-CODEGEN: sarw %cl
+ ; SSE2-CODEGEN: psraw
%0 = ashr %shifttype16i16 %a , %b
ret %shifttype16i16 %0
@@ -53,9 +53,9 @@ entry:
define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) {
entry:
; SSE2: shift32i16
- ; SSE2: cost of 320 {{.*}} ashr
+ ; SSE2: cost of 128 {{.*}} ashr
; SSE2-CODEGEN: shift32i16
- ; SSE2-CODEGEN: sarw %cl
+ ; SSE2-CODEGEN: psraw
%0 = ashr %shifttype32i16 %a , %b
ret %shifttype32i16 %0
@@ -209,9 +209,9 @@ entry:
define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) {
entry:
; SSE2: shift8i8
- ; SSE2: cost of 80 {{.*}} ashr
+ ; SSE2: cost of 32 {{.*}} ashr
; SSE2-CODEGEN: shift8i8
- ; SSE2-CODEGEN: sarw %cl
+ ; SSE2-CODEGEN: psraw
%0 = ashr %shifttype8i8 %a , %b
ret %shifttype8i8 %0
@@ -221,9 +221,9 @@ entry:
define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) {
entry:
; SSE2: shift16i8
- ; SSE2: cost of 160 {{.*}} ashr
+ ; SSE2: cost of 54 {{.*}} ashr
; SSE2-CODEGEN: shift16i8
- ; SSE2-CODEGEN: sarb %cl
+ ; SSE2-CODEGEN: psraw
%0 = ashr %shifttype16i8 %a , %b
ret %shifttype16i8 %0
@@ -233,9 +233,9 @@ entry:
define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) {
entry:
; SSE2: shift32i8
- ; SSE2: cost of 320 {{.*}} ashr
+ ; SSE2: cost of 108 {{.*}} ashr
; SSE2-CODEGEN: shift32i8
- ; SSE2-CODEGEN: sarb %cl
+ ; SSE2-CODEGEN: psraw
%0 = ashr %shifttype32i8 %a , %b
ret %shifttype32i8 %0
diff --git a/test/Analysis/CostModel/X86/testshiftlshr.ll b/test/Analysis/CostModel/X86/testshiftlshr.ll
index 78bf0a6083070..0bc60eacac9ac 100644
--- a/test/Analysis/CostModel/X86/testshiftlshr.ll
+++ b/test/Analysis/CostModel/X86/testshiftlshr.ll
@@ -29,9 +29,9 @@ entry:
define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) {
entry:
; SSE2: shift8i16
- ; SSE2: cost of 80 {{.*}} lshr
+ ; SSE2: cost of 32 {{.*}} lshr
; SSE2-CODEGEN: shift8i16
- ; SSE2-CODEGEN: shrl %cl
+ ; SSE2-CODEGEN: psrlw
%0 = lshr %shifttype8i16 %a , %b
ret %shifttype8i16 %0
@@ -41,9 +41,9 @@ entry:
define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) {
entry:
; SSE2: shift16i16
- ; SSE2: cost of 160 {{.*}} lshr
+ ; SSE2: cost of 64 {{.*}} lshr
; SSE2-CODEGEN: shift16i16
- ; SSE2-CODEGEN: shrl %cl
+ ; SSE2-CODEGEN: psrlw
%0 = lshr %shifttype16i16 %a , %b
ret %shifttype16i16 %0
@@ -53,9 +53,9 @@ entry:
define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) {
entry:
; SSE2: shift32i16
- ; SSE2: cost of 320 {{.*}} lshr
+ ; SSE2: cost of 128 {{.*}} lshr
; SSE2-CODEGEN: shift32i16
- ; SSE2-CODEGEN: shrl %cl
+ ; SSE2-CODEGEN: psrlw
%0 = lshr %shifttype32i16 %a , %b
ret %shifttype32i16 %0
@@ -209,9 +209,9 @@ entry:
define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) {
entry:
; SSE2: shift8i8
- ; SSE2: cost of 80 {{.*}} lshr
+ ; SSE2: cost of 32 {{.*}} lshr
; SSE2-CODEGEN: shift8i8
- ; SSE2-CODEGEN: shrl %cl
+ ; SSE2-CODEGEN: psrlw
%0 = lshr %shifttype8i8 %a , %b
ret %shifttype8i8 %0
@@ -221,9 +221,9 @@ entry:
define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) {
entry:
; SSE2: shift16i8
- ; SSE2: cost of 160 {{.*}} lshr
+ ; SSE2: cost of 26 {{.*}} lshr
; SSE2-CODEGEN: shift16i8
- ; SSE2-CODEGEN: shrb %cl
+ ; SSE2-CODEGEN: psrlw
%0 = lshr %shifttype16i8 %a , %b
ret %shifttype16i8 %0
@@ -233,9 +233,9 @@ entry:
define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) {
entry:
; SSE2: shift32i8
- ; SSE2: cost of 320 {{.*}} lshr
+ ; SSE2: cost of 52 {{.*}} lshr
; SSE2-CODEGEN: shift32i8
- ; SSE2-CODEGEN: shrb %cl
+ ; SSE2-CODEGEN: psrlw
%0 = lshr %shifttype32i8 %a , %b
ret %shifttype32i8 %0
diff --git a/test/Analysis/CostModel/X86/testshiftshl.ll b/test/Analysis/CostModel/X86/testshiftshl.ll
index c36e0f5dfdfea..d4e33818932bd 100644
--- a/test/Analysis/CostModel/X86/testshiftshl.ll
+++ b/test/Analysis/CostModel/X86/testshiftshl.ll
@@ -29,9 +29,9 @@ entry:
define %shifttype8i16 @shift8i16(%shifttype8i16 %a, %shifttype8i16 %b) {
entry:
; SSE2: shift8i16
- ; SSE2: cost of 80 {{.*}} shl
+ ; SSE2: cost of 32 {{.*}} shl
; SSE2-CODEGEN: shift8i16
- ; SSE2-CODEGEN: shll %cl
+ ; SSE2-CODEGEN: psllw
%0 = shl %shifttype8i16 %a , %b
ret %shifttype8i16 %0
@@ -41,9 +41,9 @@ entry:
define %shifttype16i16 @shift16i16(%shifttype16i16 %a, %shifttype16i16 %b) {
entry:
; SSE2: shift16i16
- ; SSE2: cost of 160 {{.*}} shl
+ ; SSE2: cost of 64 {{.*}} shl
; SSE2-CODEGEN: shift16i16
- ; SSE2-CODEGEN: shll %cl
+ ; SSE2-CODEGEN: psllw
%0 = shl %shifttype16i16 %a , %b
ret %shifttype16i16 %0
@@ -53,9 +53,9 @@ entry:
define %shifttype32i16 @shift32i16(%shifttype32i16 %a, %shifttype32i16 %b) {
entry:
; SSE2: shift32i16
- ; SSE2: cost of 320 {{.*}} shl
+ ; SSE2: cost of 128 {{.*}} shl
; SSE2-CODEGEN: shift32i16
- ; SSE2-CODEGEN: shll %cl
+ ; SSE2-CODEGEN: psllw
%0 = shl %shifttype32i16 %a , %b
ret %shifttype32i16 %0
@@ -209,9 +209,9 @@ entry:
define %shifttype8i8 @shift8i8(%shifttype8i8 %a, %shifttype8i8 %b) {
entry:
; SSE2: shift8i8
- ; SSE2: cost of 80 {{.*}} shl
+ ; SSE2: cost of 32 {{.*}} shl
; SSE2-CODEGEN: shift8i8
- ; SSE2-CODEGEN: shll
+ ; SSE2-CODEGEN: psllw
%0 = shl %shifttype8i8 %a , %b
ret %shifttype8i8 %0
@@ -221,9 +221,9 @@ entry:
define %shifttype16i8 @shift16i8(%shifttype16i8 %a, %shifttype16i8 %b) {
entry:
; SSE2: shift16i8
- ; SSE2: cost of 30 {{.*}} shl
+ ; SSE2: cost of 26 {{.*}} shl
; SSE2-CODEGEN: shift16i8
- ; SSE2-CODEGEN: cmpeqb
+ ; SSE2-CODEGEN: psllw
%0 = shl %shifttype16i8 %a , %b
ret %shifttype16i8 %0
@@ -233,9 +233,9 @@ entry:
define %shifttype32i8 @shift32i8(%shifttype32i8 %a, %shifttype32i8 %b) {
entry:
; SSE2: shift32i8
- ; SSE2: cost of 60 {{.*}} shl
+ ; SSE2: cost of 52 {{.*}} shl
; SSE2-CODEGEN: shift32i8
- ; SSE2-CODEGEN: cmpeqb
+ ; SSE2-CODEGEN: psllw
%0 = shl %shifttype32i8 %a , %b
ret %shifttype32i8 %0
diff --git a/test/Analysis/CostModel/X86/uitofp.ll b/test/Analysis/CostModel/X86/uitofp.ll
index 27ec268b42a88..9ffc483e3f5a2 100644
--- a/test/Analysis/CostModel/X86/uitofp.ll
+++ b/test/Analysis/CostModel/X86/uitofp.ll
@@ -1,18 +1,20 @@
-; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s
-; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s
-
-; In X86TargetTransformInfo::getCastInstrCost we have code that depends on
-; getSimpleVT on a value type. On AVX2 we execute this code. Make sure we exit
-; early if the type is not a simple value type before we call this function.
-; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -cost-model -analyze < %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE --check-prefix=SSE2 %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+avx -cost-model -analyze < %s | FileCheck --check-prefix=AVX --check-prefix=AVX1 %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+avx2 -cost-model -analyze < %s | FileCheck --check-prefix=AVX --check-prefix=AVX2 %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+avx512f -cost-model -analyze < %s | FileCheck --check-prefix=AVX512F %s
define <2 x double> @uitofpv2i8v2double(<2 x i8> %a) {
; SSE2: uitofpv2i8v2double
; SSE2: cost of 20 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv2i8v2double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv2i8v2double
+ ; AVX1: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i8v2double
+ ; AVX2: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i8v2double
+ ; AVX512F: cost of 4 {{.*}} uitofp
%1 = uitofp <2 x i8> %a to <2 x double>
ret <2 x double> %1
}
@@ -20,10 +22,15 @@ define <2 x double> @uitofpv2i8v2double(<2 x i8> %a) {
define <4 x double> @uitofpv4i8v4double(<4 x i8> %a) {
; SSE2: uitofpv4i8v4double
; SSE2: cost of 40 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv4i8v4double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv4i8v4double
+ ; AVX1: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i8v4double
+ ; AVX2: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i8v4double
+ ; AVX512F: cost of 2 {{.*}} uitofp
%1 = uitofp <4 x i8> %a to <4 x double>
ret <4 x double> %1
}
@@ -31,21 +38,31 @@ define <4 x double> @uitofpv4i8v4double(<4 x i8> %a) {
define <8 x double> @uitofpv8i8v8double(<8 x i8> %a) {
; SSE2: uitofpv8i8v8double
; SSE2: cost of 80 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv8i8v8double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
-%1 = uitofp <8 x i8> %a to <8 x double>
+ ;
+ ; AVX1: uitofpv8i8v8double
+ ; AVX1: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i8v8double
+ ; AVX2: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i8v8double
+ ; AVX512F: cost of 22 {{.*}} uitofp
+ %1 = uitofp <8 x i8> %a to <8 x double>
ret <8 x double> %1
}
define <16 x double> @uitofpv16i8v16double(<16 x i8> %a) {
; SSE2: uitofpv16i8v16double
; SSE2: cost of 160 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv16i8v16double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv16i8v16double
+ ; AVX1: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i8v16double
+ ; AVX2: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i8v16double
+ ; AVX512F: cost of 44 {{.*}} uitofp
%1 = uitofp <16 x i8> %a to <16 x double>
ret <16 x double> %1
}
@@ -53,10 +70,15 @@ define <16 x double> @uitofpv16i8v16double(<16 x i8> %a) {
define <32 x double> @uitofpv32i8v32double(<32 x i8> %a) {
; SSE2: uitofpv32i8v32double
; SSE2: cost of 320 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv32i8v32double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv32i8v32double
+ ; AVX1: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i8v32double
+ ; AVX2: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i8v32double
+ ; AVX512F: cost of 88 {{.*}} uitofp
%1 = uitofp <32 x i8> %a to <32 x double>
ret <32 x double> %1
}
@@ -64,10 +86,15 @@ define <32 x double> @uitofpv32i8v32double(<32 x i8> %a) {
define <2 x double> @uitofpv2i16v2double(<2 x i16> %a) {
; SSE2: uitofpv2i16v2double
; SSE2: cost of 20 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv2i16v2double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv2i16v2double
+ ; AVX1: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i16v2double
+ ; AVX2: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i16v2double
+ ; AVX512F: cost of 4 {{.*}} uitofp
%1 = uitofp <2 x i16> %a to <2 x double>
ret <2 x double> %1
}
@@ -75,10 +102,15 @@ define <2 x double> @uitofpv2i16v2double(<2 x i16> %a) {
define <4 x double> @uitofpv4i16v4double(<4 x i16> %a) {
; SSE2: uitofpv4i16v4double
; SSE2: cost of 40 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv4i16v4double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv4i16v4double
+ ; AVX1: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i16v4double
+ ; AVX2: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i16v4double
+ ; AVX512F: cost of 2 {{.*}} uitofp
%1 = uitofp <4 x i16> %a to <4 x double>
ret <4 x double> %1
}
@@ -86,10 +118,15 @@ define <4 x double> @uitofpv4i16v4double(<4 x i16> %a) {
define <8 x double> @uitofpv8i16v8double(<8 x i16> %a) {
; SSE2: uitofpv8i16v8double
; SSE2: cost of 80 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv8i16v8double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv8i16v8double
+ ; AVX1: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i16v8double
+ ; AVX2: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i16v8double
+ ; AVX512F: cost of 22 {{.*}} uitofp
%1 = uitofp <8 x i16> %a to <8 x double>
ret <8 x double> %1
}
@@ -97,10 +134,15 @@ define <8 x double> @uitofpv8i16v8double(<8 x i16> %a) {
define <16 x double> @uitofpv16i16v16double(<16 x i16> %a) {
; SSE2: uitofpv16i16v16double
; SSE2: cost of 160 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv16i16v16double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv16i16v16double
+ ; AVX1: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i16v16double
+ ; AVX2: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i16v16double
+ ; AVX512F: cost of 44 {{.*}} uitofp
%1 = uitofp <16 x i16> %a to <16 x double>
ret <16 x double> %1
}
@@ -108,10 +150,15 @@ define <16 x double> @uitofpv16i16v16double(<16 x i16> %a) {
define <32 x double> @uitofpv32i16v32double(<32 x i16> %a) {
; SSE2: uitofpv32i16v32double
; SSE2: cost of 320 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv32i16v32double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv32i16v32double
+ ; AVX1: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i16v32double
+ ; AVX2: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i16v32double
+ ; AVX512F: cost of 88 {{.*}} uitofp
%1 = uitofp <32 x i16> %a to <32 x double>
ret <32 x double> %1
}
@@ -119,10 +166,15 @@ define <32 x double> @uitofpv32i16v32double(<32 x i16> %a) {
define <2 x double> @uitofpv2i32v2double(<2 x i32> %a) {
; SSE2: uitofpv2i32v2double
; SSE2: cost of 20 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv2i32v2double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv2i32v2double
+ ; AVX1: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i32v2double
+ ; AVX2: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i32v2double
+ ; AVX512F: cost of 4 {{.*}} uitofp
%1 = uitofp <2 x i32> %a to <2 x double>
ret <2 x double> %1
}
@@ -130,10 +182,15 @@ define <2 x double> @uitofpv2i32v2double(<2 x i32> %a) {
define <4 x double> @uitofpv4i32v4double(<4 x i32> %a) {
; SSE2: uitofpv4i32v4double
; SSE2: cost of 40 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv4i32v4double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv4i32v4double
+ ; AVX1: cost of 6 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i32v4double
+ ; AVX2: cost of 6 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i32v4double
+ ; AVX512F: cost of 6 {{.*}} uitofp
%1 = uitofp <4 x i32> %a to <4 x double>
ret <4 x double> %1
}
@@ -141,10 +198,15 @@ define <4 x double> @uitofpv4i32v4double(<4 x i32> %a) {
define <8 x double> @uitofpv8i32v8double(<8 x i32> %a) {
; SSE2: uitofpv8i32v8double
; SSE2: cost of 80 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv8i32v8double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv8i32v8double
+ ; AVX1: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i32v8double
+ ; AVX2: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i32v8double
+ ; AVX512F: cost of 22 {{.*}} uitofp
%1 = uitofp <8 x i32> %a to <8 x double>
ret <8 x double> %1
}
@@ -152,10 +214,15 @@ define <8 x double> @uitofpv8i32v8double(<8 x i32> %a) {
define <16 x double> @uitofpv16i32v16double(<16 x i32> %a) {
; SSE2: uitofpv16i32v16double
; SSE2: cost of 160 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv16i32v16double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv16i32v16double
+ ; AVX1: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i32v16double
+ ; AVX2: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i32v16double
+ ; AVX512F: cost of 44 {{.*}} uitofp
%1 = uitofp <16 x i32> %a to <16 x double>
ret <16 x double> %1
}
@@ -163,10 +230,15 @@ define <16 x double> @uitofpv16i32v16double(<16 x i32> %a) {
define <32 x double> @uitofpv32i32v32double(<32 x i32> %a) {
; SSE2: uitofpv32i32v32double
; SSE2: cost of 320 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv32i32v32double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv32i32v32double
+ ; AVX1: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i32v32double
+ ; AVX2: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i32v32double
+ ; AVX512F: cost of 88 {{.*}} uitofp
%1 = uitofp <32 x i32> %a to <32 x double>
ret <32 x double> %1
}
@@ -174,10 +246,15 @@ define <32 x double> @uitofpv32i32v32double(<32 x i32> %a) {
define <2 x double> @uitofpv2i64v2double(<2 x i64> %a) {
; SSE2: uitofpv2i64v2double
; SSE2: cost of 20 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv2i64v2double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv2i64v2double
+ ; AVX1: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i64v2double
+ ; AVX2: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i64v2double
+ ; AVX512F: cost of 20 {{.*}} uitofp
%1 = uitofp <2 x i64> %a to <2 x double>
ret <2 x double> %1
}
@@ -185,32 +262,47 @@ define <2 x double> @uitofpv2i64v2double(<2 x i64> %a) {
define <4 x double> @uitofpv4i64v4double(<4 x i64> %a) {
; SSE2: uitofpv4i64v4double
; SSE2: cost of 40 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv4i64v4double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv4i64v4double
+ ; AVX1: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i64v4double
+ ; AVX2: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i64v4double
+ ; AVX512F: cost of 40 {{.*}} uitofp
%1 = uitofp <4 x i64> %a to <4 x double>
ret <4 x double> %1
}
define <8 x double> @uitofpv8i64v8double(<8 x i64> %a) {
- %1 = uitofp <8 x i64> %a to <8 x double>
; SSE2: uitofpv8i64v8double
; SSE2: cost of 80 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv8i64v8double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv8i64v8double
+ ; AVX1: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i64v8double
+ ; AVX2: cost of 20 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i64v8double
+ ; AVX512F: cost of 22 {{.*}} uitofp
+ %1 = uitofp <8 x i64> %a to <8 x double>
ret <8 x double> %1
}
define <16 x double> @uitofpv16i64v16double(<16 x i64> %a) {
; SSE2: uitofpv16i64v16double
; SSE2: cost of 160 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv16i64v16double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv16i64v16double
+ ; AVX1: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i64v16double
+ ; AVX2: cost of 40 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i64v16double
+ ; AVX512F: cost of 44 {{.*}} uitofp
%1 = uitofp <16 x i64> %a to <16 x double>
ret <16 x double> %1
}
@@ -218,10 +310,15 @@ define <16 x double> @uitofpv16i64v16double(<16 x i64> %a) {
define <32 x double> @uitofpv32i64v32double(<32 x i64> %a) {
; SSE2: uitofpv32i64v32double
; SSE2: cost of 320 {{.*}} uitofp
- ; SSE2-CODEGEN: uitofpv32i64v32double
- ; SSE2-CODEGEN: movapd LCPI
- ; SSE2-CODEGEN: subpd
- ; SSE2-CODEGEN: addpd
+ ;
+ ; AVX1: uitofpv32i64v32double
+ ; AVX1: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i64v32double
+ ; AVX2: cost of 80 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i64v32double
+ ; AVX512F: cost of 88 {{.*}} uitofp
%1 = uitofp <32 x i64> %a to <32 x double>
ret <32 x double> %1
}
@@ -229,6 +326,15 @@ define <32 x double> @uitofpv32i64v32double(<32 x i64> %a) {
define <2 x float> @uitofpv2i8v2float(<2 x i8> %a) {
; SSE2: uitofpv2i8v2float
; SSE2: cost of 15 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv2i8v2float
+ ; AVX1: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i8v2float
+ ; AVX2: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i8v2float
+ ; AVX512F: cost of 4 {{.*}} uitofp
%1 = uitofp <2 x i8> %a to <2 x float>
ret <2 x float> %1
}
@@ -236,6 +342,15 @@ define <2 x float> @uitofpv2i8v2float(<2 x i8> %a) {
define <4 x float> @uitofpv4i8v4float(<4 x i8> %a) {
; SSE2: uitofpv4i8v4float
; SSE2: cost of 8 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv4i8v4float
+ ; AVX1: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i8v4float
+ ; AVX2: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i8v4float
+ ; AVX512F: cost of 2 {{.*}} uitofp
%1 = uitofp <4 x i8> %a to <4 x float>
ret <4 x float> %1
}
@@ -243,6 +358,15 @@ define <4 x float> @uitofpv4i8v4float(<4 x i8> %a) {
define <8 x float> @uitofpv8i8v8float(<8 x i8> %a) {
; SSE2: uitofpv8i8v8float
; SSE2: cost of 15 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv8i8v8float
+ ; AVX1: cost of 5 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i8v8float
+ ; AVX2: cost of 5 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i8v8float
+ ; AVX512F: cost of 5 {{.*}} uitofp
%1 = uitofp <8 x i8> %a to <8 x float>
ret <8 x float> %1
}
@@ -250,6 +374,15 @@ define <8 x float> @uitofpv8i8v8float(<8 x i8> %a) {
define <16 x float> @uitofpv16i8v16float(<16 x i8> %a) {
; SSE2: uitofpv16i8v16float
; SSE2: cost of 8 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv16i8v16float
+ ; AVX1: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i8v16float
+ ; AVX2: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i8v16float
+ ; AVX512F: cost of 46 {{.*}} uitofp
%1 = uitofp <16 x i8> %a to <16 x float>
ret <16 x float> %1
}
@@ -257,6 +390,15 @@ define <16 x float> @uitofpv16i8v16float(<16 x i8> %a) {
define <32 x float> @uitofpv32i8v32float(<32 x i8> %a) {
; SSE2: uitofpv32i8v32float
; SSE2: cost of 16 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv32i8v32float
+ ; AVX1: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i8v32float
+ ; AVX2: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i8v32float
+ ; AVX512F: cost of 92 {{.*}} uitofp
%1 = uitofp <32 x i8> %a to <32 x float>
ret <32 x float> %1
}
@@ -264,6 +406,15 @@ define <32 x float> @uitofpv32i8v32float(<32 x i8> %a) {
define <2 x float> @uitofpv2i16v2float(<2 x i16> %a) {
; SSE2: uitofpv2i16v2float
; SSE2: cost of 15 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv2i16v2float
+ ; AVX1: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i16v2float
+ ; AVX2: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i16v2float
+ ; AVX512F: cost of 4 {{.*}} uitofp
%1 = uitofp <2 x i16> %a to <2 x float>
ret <2 x float> %1
}
@@ -271,6 +422,15 @@ define <2 x float> @uitofpv2i16v2float(<2 x i16> %a) {
define <4 x float> @uitofpv4i16v4float(<4 x i16> %a) {
; SSE2: uitofpv4i16v4float
; SSE2: cost of 8 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv4i16v4float
+ ; AVX1: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i16v4float
+ ; AVX2: cost of 2 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i16v4float
+ ; AVX512F: cost of 2 {{.*}} uitofp
%1 = uitofp <4 x i16> %a to <4 x float>
ret <4 x float> %1
}
@@ -278,6 +438,15 @@ define <4 x float> @uitofpv4i16v4float(<4 x i16> %a) {
define <8 x float> @uitofpv8i16v8float(<8 x i16> %a) {
; SSE2: uitofpv8i16v8float
; SSE2: cost of 15 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv8i16v8float
+ ; AVX1: cost of 5 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i16v8float
+ ; AVX2: cost of 5 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i16v8float
+ ; AVX512F: cost of 5 {{.*}} uitofp
%1 = uitofp <8 x i16> %a to <8 x float>
ret <8 x float> %1
}
@@ -285,6 +454,15 @@ define <8 x float> @uitofpv8i16v8float(<8 x i16> %a) {
define <16 x float> @uitofpv16i16v16float(<16 x i16> %a) {
; SSE2: uitofpv16i16v16float
; SSE2: cost of 30 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv16i16v16float
+ ; AVX1: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i16v16float
+ ; AVX2: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i16v16float
+ ; AVX512F: cost of 46 {{.*}} uitofp
%1 = uitofp <16 x i16> %a to <16 x float>
ret <16 x float> %1
}
@@ -292,6 +470,15 @@ define <16 x float> @uitofpv16i16v16float(<16 x i16> %a) {
define <32 x float> @uitofpv32i16v32float(<32 x i16> %a) {
; SSE2: uitofpv32i16v32float
; SSE2: cost of 60 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv32i16v32float
+ ; AVX1: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i16v32float
+ ; AVX2: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i16v32float
+ ; AVX512F: cost of 92 {{.*}} uitofp
%1 = uitofp <32 x i16> %a to <32 x float>
ret <32 x float> %1
}
@@ -299,6 +486,15 @@ define <32 x float> @uitofpv32i16v32float(<32 x i16> %a) {
define <2 x float> @uitofpv2i32v2float(<2 x i32> %a) {
; SSE2: uitofpv2i32v2float
; SSE2: cost of 15 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv2i32v2float
+ ; AVX1: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i32v2float
+ ; AVX2: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i32v2float
+ ; AVX512F: cost of 4 {{.*}} uitofp
%1 = uitofp <2 x i32> %a to <2 x float>
ret <2 x float> %1
}
@@ -306,6 +502,15 @@ define <2 x float> @uitofpv2i32v2float(<2 x i32> %a) {
define <4 x float> @uitofpv4i32v4float(<4 x i32> %a) {
; SSE2: uitofpv4i32v4float
; SSE2: cost of 8 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv4i32v4float
+ ; AVX1: cost of 6 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i32v4float
+ ; AVX2: cost of 6 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i32v4float
+ ; AVX512F: cost of 6 {{.*}} uitofp
%1 = uitofp <4 x i32> %a to <4 x float>
ret <4 x float> %1
}
@@ -313,6 +518,15 @@ define <4 x float> @uitofpv4i32v4float(<4 x i32> %a) {
define <8 x float> @uitofpv8i32v8float(<8 x i32> %a) {
; SSE2: uitofpv8i32v8float
; SSE2: cost of 16 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv8i32v8float
+ ; AVX1: cost of 9 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i32v8float
+ ; AVX2: cost of 8 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i32v8float
+ ; AVX512F: cost of 8 {{.*}} uitofp
%1 = uitofp <8 x i32> %a to <8 x float>
ret <8 x float> %1
}
@@ -320,6 +534,15 @@ define <8 x float> @uitofpv8i32v8float(<8 x i32> %a) {
define <16 x float> @uitofpv16i32v16float(<16 x i32> %a) {
; SSE2: uitofpv16i32v16float
; SSE2: cost of 32 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv16i32v16float
+ ; AVX1: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i32v16float
+ ; AVX2: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i32v16float
+ ; AVX512F: cost of 46 {{.*}} uitofp
%1 = uitofp <16 x i32> %a to <16 x float>
ret <16 x float> %1
}
@@ -327,6 +550,15 @@ define <16 x float> @uitofpv16i32v16float(<16 x i32> %a) {
define <32 x float> @uitofpv32i32v32float(<32 x i32> %a) {
; SSE2: uitofpv32i32v32float
; SSE2: cost of 64 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv32i32v32float
+ ; AVX1: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i32v32float
+ ; AVX2: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i32v32float
+ ; AVX512F: cost of 92 {{.*}} uitofp
%1 = uitofp <32 x i32> %a to <32 x float>
ret <32 x float> %1
}
@@ -334,6 +566,15 @@ define <32 x float> @uitofpv32i32v32float(<32 x i32> %a) {
define <2 x float> @uitofpv2i64v2float(<2 x i64> %a) {
; SSE2: uitofpv2i64v2float
; SSE2: cost of 15 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv2i64v2float
+ ; AVX1: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv2i64v2float
+ ; AVX2: cost of 4 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv2i64v2float
+ ; AVX512F: cost of 4 {{.*}} uitofp
%1 = uitofp <2 x i64> %a to <2 x float>
ret <2 x float> %1
}
@@ -341,6 +582,15 @@ define <2 x float> @uitofpv2i64v2float(<2 x i64> %a) {
define <4 x float> @uitofpv4i64v4float(<4 x i64> %a) {
; SSE2: uitofpv4i64v4float
; SSE2: cost of 30 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv4i64v4float
+ ; AVX1: cost of 10 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv4i64v4float
+ ; AVX2: cost of 10 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv4i64v4float
+ ; AVX512F: cost of 10 {{.*}} uitofp
%1 = uitofp <4 x i64> %a to <4 x float>
ret <4 x float> %1
}
@@ -348,6 +598,15 @@ define <4 x float> @uitofpv4i64v4float(<4 x i64> %a) {
define <8 x float> @uitofpv8i64v8float(<8 x i64> %a) {
; SSE2: uitofpv8i64v8float
; SSE2: cost of 60 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv8i64v8float
+ ; AVX1: cost of 22 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv8i64v8float
+ ; AVX2: cost of 22 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv8i64v8float
+ ; AVX512F: cost of 22 {{.*}} uitofp
%1 = uitofp <8 x i64> %a to <8 x float>
ret <8 x float> %1
}
@@ -355,6 +614,15 @@ define <8 x float> @uitofpv8i64v8float(<8 x i64> %a) {
define <16 x float> @uitofpv16i64v16float(<16 x i64> %a) {
; SSE2: uitofpv16i64v16float
; SSE2: cost of 120 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv16i64v16float
+ ; AVX1: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv16i64v16float
+ ; AVX2: cost of 44 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv16i64v16float
+ ; AVX512F: cost of 46 {{.*}} uitofp
%1 = uitofp <16 x i64> %a to <16 x float>
ret <16 x float> %1
}
@@ -362,6 +630,15 @@ define <16 x float> @uitofpv16i64v16float(<16 x i64> %a) {
define <32 x float> @uitofpv32i64v32float(<32 x i64> %a) {
; SSE2: uitofpv32i64v32float
; SSE2: cost of 240 {{.*}} uitofp
+ ;
+ ; AVX1: uitofpv32i64v32float
+ ; AVX1: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX2: uitofpv32i64v32float
+ ; AVX2: cost of 88 {{.*}} uitofp
+ ;
+ ; AVX512F: uitofpv32i64v32float
+ ; AVX512F: cost of 92 {{.*}} uitofp
%1 = uitofp <32 x i64> %a to <32 x float>
ret <32 x float> %1
}
diff --git a/test/Analysis/Dominators/invoke.ll b/test/Analysis/Dominators/invoke.ll
index ce5f992d8f4ea..ab0afd4354a76 100644
--- a/test/Analysis/Dominators/invoke.ll
+++ b/test/Analysis/Dominators/invoke.ll
@@ -1,7 +1,7 @@
; RUN: opt -verify -disable-output < %s
; This tests that we handle unreachable blocks correctly
-define void @f() {
+define void @f() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
%v1 = invoke i32* @g()
to label %bb1 unwind label %bb2
invoke void @__dynamic_cast()
@@ -10,7 +10,7 @@ bb1:
%Hidden = getelementptr inbounds i32, i32* %v1, i64 1
ret void
bb2:
- %lpad.loopexit80 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+ %lpad.loopexit80 = landingpad { i8*, i32 }
cleanup
ret void
}
diff --git a/test/Analysis/LazyCallGraph/basic.ll b/test/Analysis/LazyCallGraph/basic.ll
index 7c13d2bef390c..fce453bc15de7 100644
--- a/test/Analysis/LazyCallGraph/basic.ll
+++ b/test/Analysis/LazyCallGraph/basic.ll
@@ -63,7 +63,7 @@ entry:
ret void
}
-define void ()* @test1(void ()** %x) {
+define void ()* @test1(void ()** %x) personality i32 (...)* @__gxx_personality_v0 {
; CHECK-LABEL: Call edges in function: test1
; CHECK-NEXT: -> f12
; CHECK-NEXT: -> f11
@@ -97,7 +97,7 @@ exit:
ret void ()* @f11
unwind:
- %res = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
+ %res = landingpad { i8*, i32 }
cleanup
resume { i8*, i32 } { i8* bitcast (void ()* @f12 to i8*), i32 42 }
}
diff --git a/test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll b/test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll
index 8cd44c86a72ab..743ebace700ee 100644
--- a/test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll
+++ b/test/Analysis/Lint/cppeh-catch-intrinsics-clean.ll
@@ -12,13 +12,13 @@ declare void @llvm.eh.endcatch()
@_ZTIi = external constant i8*
; Function Attrs: uwtable
-define void @test_ref_clean() {
+define void @test_ref_clean() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
entry:
invoke void @_Z9may_throwv()
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -43,7 +43,7 @@ eh.resume: ; preds = %catch.dispatch
}
; Function Attrs: uwtable
-define void @test_ref_clean_multibranch() {
+define void @test_ref_clean_multibranch() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
entry:
invoke void @_Z9may_throwv()
to label %invoke.cont unwind label %lpad
@@ -53,7 +53,7 @@ invoke.cont:
to label %invoke.cont unwind label %lpad1
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -65,7 +65,7 @@ lpad: ; preds = %entry
to label %try.cont unwind label %lpad
lpad1: ; preds = %entry
- %l1.0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %l1.0 = landingpad { i8*, i32 }
cleanup
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn1 = extractvalue { i8*, i32 } %l1.0, 0
diff --git a/test/Analysis/Lint/cppeh-catch-intrinsics.ll b/test/Analysis/Lint/cppeh-catch-intrinsics.ll
index 3a0c487c290b2..19480a2f60fe0 100644
--- a/test/Analysis/Lint/cppeh-catch-intrinsics.ll
+++ b/test/Analysis/Lint/cppeh-catch-intrinsics.ll
@@ -13,7 +13,7 @@ declare void @llvm.eh.endcatch()
@_ZTIi = external constant i8*
; Function Attrs: uwtable
-define void @test_missing_endcatch() {
+define void @test_missing_endcatch() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
; CHECK: Some paths from llvm.eh.begincatch may not reach llvm.eh.endcatch
; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn, i8* null)
entry:
@@ -21,7 +21,7 @@ entry:
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -45,7 +45,7 @@ eh.resume: ; preds = %catch.dispatch
}
; Function Attrs: uwtable
-define void @test_missing_begincatch() {
+define void @test_missing_begincatch() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
; CHECK: llvm.eh.endcatch may be reachable without passing llvm.eh.begincatch
; CHECK-NEXT: call void @llvm.eh.endcatch()
entry:
@@ -53,7 +53,7 @@ entry:
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -77,7 +77,7 @@ eh.resume: ; preds = %catch.dispatch
}
; Function Attrs: uwtable
-define void @test_multiple_begin() {
+define void @test_multiple_begin() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
; CHECK: llvm.eh.begincatch may be called a second time before llvm.eh.endcatch
; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn, i8* null)
; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn, i8* null)
@@ -86,7 +86,7 @@ entry:
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -112,7 +112,7 @@ eh.resume: ; preds = %catch.dispatch
}
; Function Attrs: uwtable
-define void @test_multiple_end() {
+define void @test_multiple_end() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
; CHECK: llvm.eh.endcatch may be called a second time after llvm.eh.begincatch
; CHECK-NEXT: call void @llvm.eh.endcatch()
; CHECK-NEXT: call void @llvm.eh.endcatch()
@@ -121,7 +121,7 @@ entry:
to label %try.cont unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -166,7 +166,7 @@ try.cont: ; preds = %invoke.cont2, %entr
}
; Function Attrs: uwtable
-define void @test_branch_to_begincatch_with_no_lpad(i32 %fake.sel) {
+define void @test_branch_to_begincatch_with_no_lpad(i32 %fake.sel) personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
; CHECK: llvm.eh.begincatch may be reachable without passing a landingpad
; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn2, i8* null)
entry:
@@ -175,7 +175,7 @@ entry:
to label %catch unwind label %lpad
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -211,7 +211,7 @@ eh.resume: ; preds = %catch.dispatch
}
; Function Attrs: uwtable
-define void @test_branch_missing_endcatch() {
+define void @test_branch_missing_endcatch() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {
; CHECK: Some paths from llvm.eh.begincatch may not reach llvm.eh.endcatch
; CHECK-NEXT: call void @llvm.eh.begincatch(i8* %exn2, i8* null)
entry:
@@ -223,7 +223,7 @@ invoke.cont:
to label %invoke.cont unwind label %lpad1
lpad: ; preds = %entry
- %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %0 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn = extractvalue { i8*, i32 } %0, 0
%sel = extractvalue { i8*, i32 } %0, 1
@@ -235,7 +235,7 @@ lpad: ; preds = %entry
to label %try.cont unwind label %lpad
lpad1: ; preds = %entry
- %l1.0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*)
+ %l1.0 = landingpad { i8*, i32 }
cleanup
catch i8* bitcast (i8** @_ZTIi to i8*)
%exn1 = extractvalue { i8*, i32 } %l1.0, 0
diff --git a/test/Analysis/ValueTracking/assume.ll b/test/Analysis/ValueTracking/assume.ll
new file mode 100644
index 0000000000000..4bffe8ef79096
--- /dev/null
+++ b/test/Analysis/ValueTracking/assume.ll
@@ -0,0 +1,14 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @assume_add(i32 %a, i32 %b) {
+; CHECK-LABEL: @assume_add(
+ %1 = add i32 %a, %b
+ %last_two_digits = and i32 %1, 3
+ %2 = icmp eq i32 %last_two_digits, 0
+ call void @llvm.assume(i1 %2)
+ %3 = add i32 %1, 3
+; CHECK: %3 = or i32 %1, 3
+ ret i32 %3
+}
+
+declare void @llvm.assume(i1)
diff --git a/test/Analysis/ValueTracking/dom-cond.ll b/test/Analysis/ValueTracking/dom-cond.ll
new file mode 100644
index 0000000000000..c0cafdd0ade08
--- /dev/null
+++ b/test/Analysis/ValueTracking/dom-cond.ll
@@ -0,0 +1,18 @@
+; RUN: opt < %s -instcombine -value-tracking-dom-conditions -S | FileCheck %s
+
+define i32 @dom_cond(i32 %a, i32 %b) {
+; CHECK-LABEL: @dom_cond(
+entry:
+ %v = add i32 %a, %b
+ %cond = icmp ule i32 %v, 7
+ br i1 %cond, label %then, label %exit
+
+then:
+ %v2 = add i32 %v, 8
+; CHECK: or i32 %v, 8
+ br label %exit
+
+exit:
+ %v3 = phi i32 [ %v, %entry ], [ %v2, %then ]
+ ret i32 %v3
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-08 07:34:49 +0000