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-rw-r--r--test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll60
-rw-r--r--test/CodeGen/AArch64/arm64-nvcast.ll29
-rw-r--r--test/CodeGen/AArch64/arm64-shrink-wrapping.ll39
-rw-r--r--test/CodeGen/AArch64/nest-register.ll23
-rw-r--r--test/CodeGen/AArch64/xbfiz.ll33
5 files changed, 179 insertions, 5 deletions
diff --git a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
index a31c66bad4be5..739570236da92 100644
--- a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
+++ b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
@@ -255,7 +255,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15
-; CHECK: and x9, x9, #0xfffffffffffffff0
+; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]]
@@ -302,7 +302,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15
-; CHECK: and x9, x9, #0xfffffffffffffff0
+; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]]
@@ -364,7 +364,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15
-; CHECK: and x9, x9, #0xfffffffffffffff0
+; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]]
@@ -417,7 +417,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15
-; CHECK: and x9, x9, #0xfffffffffffffff0
+; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]]
@@ -468,7 +468,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15
-; CHECK: and x9, x9, #0xfffffffffffffff0
+; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]]
@@ -482,6 +482,56 @@ entry:
; CHECK: ldp x20, x19, [sp], #32
; CHECK: ret
+
+define void @realign_conditional(i1 %b) {
+entry:
+ br i1 %b, label %bb0, label %bb1
+
+bb0:
+ %MyAlloca = alloca i8, i64 64, align 32
+ br label %bb1
+
+bb1:
+ ret void
+}
+
+; CHECK-LABEL: realign_conditional
+; No realignment in the prologue.
+; CHECK-NOT: and
+; CHECK-NOT: 0xffffffffffffffe0
+; CHECK: tbz {{.*}} .[[LABEL:.*]]
+; Stack is realigned in a non-entry BB.
+; CHECK: sub [[REG:x[01-9]+]], sp, #64
+; CHECK: and sp, [[REG]], #0xffffffffffffffe0
+; CHECK: .[[LABEL]]:
+; CHECK: ret
+
+
+define void @realign_conditional2(i1 %b) {
+entry:
+ %tmp = alloca i8, i32 4
+ br i1 %b, label %bb0, label %bb1
+
+bb0:
+ %MyAlloca = alloca i8, i64 64, align 32
+ br label %bb1
+
+bb1:
+ ret void
+}
+
+; CHECK-LABEL: realign_conditional2
+; Extra realignment in the prologue (performance issue).
+; CHECK: sub x9, sp, #32 // =32
+; CHECK: and sp, x9, #0xffffffffffffffe0
+; CHECK: mov x19, sp
+; CHECK: tbz {{.*}} .[[LABEL:.*]]
+; Stack is realigned in a non-entry BB.
+; CHECK: sub [[REG:x[01-9]+]], sp, #64
+; CHECK: and sp, [[REG]], #0xffffffffffffffe0
+; CHECK: .[[LABEL]]:
+; CHECK: ret
+
attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/AArch64/arm64-nvcast.ll b/test/CodeGen/AArch64/arm64-nvcast.ll
new file mode 100644
index 0000000000000..3cb1bf25fc344
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-nvcast.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
+
+; CHECK-LABEL: _test:
+; CHECK: fmov.2d v0, #2.00000000
+; CHECK: str q0, [sp]
+; CHECK: mov x8, sp
+; CHECK: ldr s0, [x8, w1, sxtw #2]
+; CHECK: str s0, [x0]
+
+define void @test(float * %p1, i32 %v1) {
+entry:
+ %v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1
+ store float %v2, float* %p1, align 4
+ ret void
+}
+
+; CHECK-LABEL: _test2
+; CHECK: movi.16b v0, #0x3f
+; CHECK: str q0, [sp]
+; CHECK: mov x8, sp
+; CHECK: ldr s0, [x8, w1, sxtw #2]
+; CHECK: str s0, [x0]
+
+define void @test2(float * %p1, i32 %v1) {
+entry:
+ %v2 = extractelement <3 x float> <float 0.7470588088035583, float 0.7470588088035583, float 0.7470588088035583>, i32 %v1
+ store float %v2, float* %p1, align 4
+ ret void
+}
diff --git a/test/CodeGen/AArch64/arm64-shrink-wrapping.ll b/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
index c1777513fa045..599712be401c6 100644
--- a/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
+++ b/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
@@ -500,3 +500,42 @@ if.end: ; preds = %if.else, %if.then
}
declare i32 @someVariadicFunc(i32, ...)
+
+; Make sure we do not insert unreachable code after noreturn function.
+; Although this is not incorrect to insert such code, it is useless
+; and it hurts the binary size.
+;
+; CHECK-LABEL: noreturn:
+; DISABLE: stp
+;
+; CHECK: and [[TEST:w[0-9]+]], w0, #0xff
+; CHECK-NEXT: cbnz [[TEST]], [[ABORT:LBB[0-9_]+]]
+;
+; CHECK: movz w0, #0x2a
+;
+; DISABLE-NEXT: ldp
+;
+; CHECK-NEXT: ret
+;
+; CHECK: [[ABORT]]: ; %if.abort
+;
+; ENABLE: stp
+;
+; CHECK: bl _abort
+; ENABLE-NOT: ldp
+define i32 @noreturn(i8 signext %bad_thing) {
+entry:
+ %tobool = icmp eq i8 %bad_thing, 0
+ br i1 %tobool, label %if.end, label %if.abort
+
+if.abort:
+ tail call void @abort() #0
+ unreachable
+
+if.end:
+ ret i32 42
+}
+
+declare void @abort() #0
+
+attributes #0 = { noreturn nounwind }
diff --git a/test/CodeGen/AArch64/nest-register.ll b/test/CodeGen/AArch64/nest-register.ll
new file mode 100644
index 0000000000000..9c659fb74ec44
--- /dev/null
+++ b/test/CodeGen/AArch64/nest-register.ll
@@ -0,0 +1,23 @@
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+; Tests that the 'nest' parameter attribute causes the relevant parameter to be
+; passed in the right register.
+
+define i8* @nest_receiver(i8* nest %arg) nounwind {
+; CHECK-LABEL: nest_receiver:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: mov x0, x18
+; CHECK-NEXT: ret
+
+ ret i8* %arg
+}
+
+define i8* @nest_caller(i8* %arg) nounwind {
+; CHECK-LABEL: nest_caller:
+; CHECK: mov x18, x0
+; CHECK-NEXT: bl nest_receiver
+; CHECK: ret
+
+ %result = call i8* @nest_receiver(i8* nest %arg)
+ ret i8* %result
+}
diff --git a/test/CodeGen/AArch64/xbfiz.ll b/test/CodeGen/AArch64/xbfiz.ll
new file mode 100644
index 0000000000000..f763400d7f6a7
--- /dev/null
+++ b/test/CodeGen/AArch64/xbfiz.ll
@@ -0,0 +1,33 @@
+; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
+
+define i64 @sbfiz64(i64 %v) {
+; CHECK-LABEL: sbfiz64:
+; CHECK: sbfiz x0, x0, #1, #16
+ %shl = shl i64 %v, 48
+ %shr = ashr i64 %shl, 47
+ ret i64 %shr
+}
+
+define i32 @sbfiz32(i32 %v) {
+; CHECK-LABEL: sbfiz32:
+; CHECK: sbfiz w0, w0, #1, #14
+ %shl = shl i32 %v, 18
+ %shr = ashr i32 %shl, 17
+ ret i32 %shr
+}
+
+define i64 @ubfiz64(i64 %v) {
+; CHECK-LABEL: ubfiz64:
+; CHECK: ubfiz x0, x0, #36, #11
+ %shl = shl i64 %v, 53
+ %shr = lshr i64 %shl, 17
+ ret i64 %shr
+}
+
+define i32 @ubfiz32(i32 %v) {
+; CHECK-LABEL: ubfiz32:
+; CHECK: ubfiz w0, w0, #6, #24
+ %shl = shl i32 %v, 8
+ %shr = lshr i32 %shl, 2
+ ret i32 %shr
+}
generated by cgit v1.3 (git 2.53.0) at 2026-09-04 02:16:18 +0000