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-rw-r--r--test/CodeGen/AMDGPU/fmin.ll8
1 files changed, 3 insertions, 5 deletions
diff --git a/test/CodeGen/AMDGPU/fmin.ll b/test/CodeGen/AMDGPU/fmin.ll
index defa8c09638aa..d044a7a0542c9 100644
--- a/test/CodeGen/AMDGPU/fmin.ll
+++ b/test/CodeGen/AMDGPU/fmin.ll
@@ -2,16 +2,14 @@
;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @test(<4 x float> inreg %reg0) #0 {
+define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fcmp uge float %r0, %r1
%r3 = select i1 %r2, float %r1, float %r0
%vec = insertelement <4 x float> undef, float %r3, i32 0
- call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
+ call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="0" } \ No newline at end of file
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)