diff options
Diffstat (limited to 'test/CodeGen/AMDGPU/shared-op-cycle.ll')
| -rw-r--r-- | test/CodeGen/AMDGPU/shared-op-cycle.ll | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/test/CodeGen/AMDGPU/shared-op-cycle.ll b/test/CodeGen/AMDGPU/shared-op-cycle.ll index f52a9baf4d187..f9a72b47cc996 100644 --- a/test/CodeGen/AMDGPU/shared-op-cycle.ll +++ b/test/CodeGen/AMDGPU/shared-op-cycle.ll @@ -4,7 +4,7 @@ ; CHECK: MULADD_IEEE * ; CHECK-NOT: MULADD_IEEE * -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) { %w0 = extractelement <4 x float> %reg0, i32 3 %w1 = extractelement <4 x float> %reg1, i32 3 %w2 = extractelement <4 x float> %reg2, i32 3 @@ -17,16 +17,15 @@ define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> %v0 = insertelement <4 x float> undef, float %r0, i32 0 %v1 = insertelement <4 x float> %v0, float %r1, i32 1 %v2 = insertelement <4 x float> %v1, float %r2, i32 2 - %res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2) + %res = call float @llvm.r600.dot4(<4 x float> %v2, <4 x float> %v2) %vecres = insertelement <4 x float> undef, float %res, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) ret void } ; Function Attrs: readnone -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } -attributes #1 = { readnone }
\ No newline at end of file +attributes #1 = { readnone } |