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Diffstat (limited to 'test/CodeGen/ARM/atomic-op.ll')
-rw-r--r--test/CodeGen/ARM/atomic-op.ll111
1 files changed, 47 insertions, 64 deletions
diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll
index 7913894566192..17324d64153d2 100644
--- a/test/CodeGen/ARM/atomic-op.ll
+++ b/test/CodeGen/ARM/atomic-op.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix CHECK-ARMV7
; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T2
; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
-; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
+; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-T1
; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -29,8 +29,7 @@ entry:
; CHECK: ldrex
; CHECK: add
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_add_4
- ; CHECK-M0: bl ___sync_fetch_and_add_4
+ ; CHECK-T1: bl ___sync_fetch_and_add_4
; CHECK-BAREMETAL: add
; CHECK-BAREMETAL-NOT: __sync
%0 = atomicrmw add i32* %val1, i32 %tmp monotonic
@@ -38,8 +37,7 @@ entry:
; CHECK: ldrex
; CHECK: sub
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_sub_4
- ; CHECK-M0: bl ___sync_fetch_and_sub_4
+ ; CHECK-T1: bl ___sync_fetch_and_sub_4
; CHECK-BAREMETAL: sub
; CHECK-BAREMETAL-NOT: __sync
%1 = atomicrmw sub i32* %val2, i32 30 monotonic
@@ -47,8 +45,7 @@ entry:
; CHECK: ldrex
; CHECK: add
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_add_4
- ; CHECK-M0: bl ___sync_fetch_and_add_4
+ ; CHECK-T1: bl ___sync_fetch_and_add_4
; CHECK-BAREMETAL: add
; CHECK-BAREMETAL-NOT: __sync
%2 = atomicrmw add i32* %val2, i32 1 monotonic
@@ -56,8 +53,7 @@ entry:
; CHECK: ldrex
; CHECK: sub
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_sub_4
- ; CHECK-M0: bl ___sync_fetch_and_sub_4
+ ; CHECK-T1: bl ___sync_fetch_and_sub_4
; CHECK-BAREMETAL: sub
; CHECK-BAREMETAL-NOT: __sync
%3 = atomicrmw sub i32* %val2, i32 1 monotonic
@@ -65,8 +61,7 @@ entry:
; CHECK: ldrex
; CHECK: and
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_and_4
- ; CHECK-M0: bl ___sync_fetch_and_and_4
+ ; CHECK-T1: bl ___sync_fetch_and_and_4
; CHECK-BAREMETAL: and
; CHECK-BAREMETAL-NOT: __sync
%4 = atomicrmw and i32* %andt, i32 4080 monotonic
@@ -74,8 +69,7 @@ entry:
; CHECK: ldrex
; CHECK: or
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_or_4
- ; CHECK-M0: bl ___sync_fetch_and_or_4
+ ; CHECK-T1: bl ___sync_fetch_and_or_4
; CHECK-BAREMETAL: or
; CHECK-BAREMETAL-NOT: __sync
%5 = atomicrmw or i32* %ort, i32 4080 monotonic
@@ -83,8 +77,7 @@ entry:
; CHECK: ldrex
; CHECK: eor
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_xor_4
- ; CHECK-M0: bl ___sync_fetch_and_xor_4
+ ; CHECK-T1: bl ___sync_fetch_and_xor_4
; CHECK-BAREMETAL: eor
; CHECK-BAREMETAL-NOT: __sync
%6 = atomicrmw xor i32* %xort, i32 4080 monotonic
@@ -92,8 +85,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_min_4
- ; CHECK-M0: bl ___sync_fetch_and_min_4
+ ; CHECK-T1: bl ___sync_fetch_and_min_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%7 = atomicrmw min i32* %val2, i32 16 monotonic
@@ -102,8 +94,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_min_4
- ; CHECK-M0: bl ___sync_fetch_and_min_4
+ ; CHECK-T1: bl ___sync_fetch_and_min_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%8 = atomicrmw min i32* %val2, i32 %neg monotonic
@@ -111,8 +102,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_max_4
- ; CHECK-M0: bl ___sync_fetch_and_max_4
+ ; CHECK-T1: bl ___sync_fetch_and_max_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%9 = atomicrmw max i32* %val2, i32 1 monotonic
@@ -120,8 +110,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_max_4
- ; CHECK-M0: bl ___sync_fetch_and_max_4
+ ; CHECK-T1: bl ___sync_fetch_and_max_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%10 = atomicrmw max i32* %val2, i32 0 monotonic
@@ -129,8 +118,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umin_4
- ; CHECK-M0: bl ___sync_fetch_and_umin_4
+ ; CHECK-T1: bl ___sync_fetch_and_umin_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%11 = atomicrmw umin i32* %val2, i32 16 monotonic
@@ -139,8 +127,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umin_4
- ; CHECK-M0: bl ___sync_fetch_and_umin_4
+ ; CHECK-T1: bl ___sync_fetch_and_umin_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
@@ -148,8 +135,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umax_4
- ; CHECK-M0: bl ___sync_fetch_and_umax_4
+ ; CHECK-T1: bl ___sync_fetch_and_umax_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%13 = atomicrmw umax i32* %val2, i32 1 monotonic
@@ -157,8 +143,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umax_4
- ; CHECK-M0: bl ___sync_fetch_and_umax_4
+ ; CHECK-T1: bl ___sync_fetch_and_umax_4
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%14 = atomicrmw umax i32* %val2, i32 0 monotonic
@@ -175,8 +160,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umin_2
- ; CHECK-M0: bl ___sync_fetch_and_umin_2
+ ; CHECK-T1: bl ___sync_fetch_and_umin_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%0 = atomicrmw umin i16* %val, i16 16 monotonic
@@ -185,8 +169,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umin_2
- ; CHECK-M0: bl ___sync_fetch_and_umin_2
+ ; CHECK-T1: bl ___sync_fetch_and_umin_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%1 = atomicrmw umin i16* %val, i16 %uneg monotonic
@@ -194,8 +177,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umax_2
- ; CHECK-M0: bl ___sync_fetch_and_umax_2
+ ; CHECK-T1: bl ___sync_fetch_and_umax_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%2 = atomicrmw umax i16* %val, i16 1 monotonic
@@ -203,8 +185,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umax_2
- ; CHECK-M0: bl ___sync_fetch_and_umax_2
+ ; CHECK-T1: bl ___sync_fetch_and_umax_2
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%3 = atomicrmw umax i16* %val, i16 0 monotonic
@@ -220,8 +201,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umin_1
- ; CHECK-M0: bl ___sync_fetch_and_umin_1
+ ; CHECK-T1: bl ___sync_fetch_and_umin_1
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%0 = atomicrmw umin i8* %val, i8 16 monotonic
@@ -229,8 +209,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umin_1
- ; CHECK-M0: bl ___sync_fetch_and_umin_1
+ ; CHECK-T1: bl ___sync_fetch_and_umin_1
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%uneg = sub i8 0, 1
@@ -239,8 +218,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umax_1
- ; CHECK-M0: bl ___sync_fetch_and_umax_1
+ ; CHECK-T1: bl ___sync_fetch_and_umax_1
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%2 = atomicrmw umax i8* %val, i8 1 monotonic
@@ -248,8 +226,7 @@ entry:
; CHECK: ldrex
; CHECK: cmp
; CHECK: strex
- ; CHECK-T1: blx ___sync_fetch_and_umax_1
- ; CHECK-M0: bl ___sync_fetch_and_umax_1
+ ; CHECK-T1: bl ___sync_fetch_and_umax_1
; CHECK-BAREMETAL: cmp
; CHECK-BAREMETAL-NOT: __sync
%3 = atomicrmw umax i8* %val, i8 0 monotonic
@@ -272,31 +249,37 @@ define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
%oldval = extractvalue { i32, i1 } %pair, 0
-; CHECK-ARMV7: dmb ish
-; CHECK-ARMV7: [[LOOP_BB:\.?LBB[0-9]+_1]]:
; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
; CHECK-ARMV7: cmp [[OLDVAL]], r1
; CHECK-ARMV7: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]]
+; CHECK-ARMV7: dmb ish
+; CHECK-ARMV7: [[LOOP_BB:\.?LBB.*]]:
; CHECK-ARMV7: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
; CHECK-ARMV7: cmp [[SUCCESS]], #0
-; CHECK-ARMV7: bne [[LOOP_BB]]
-; CHECK-ARMV7: dmb ish
-; CHECK-ARMV7: bx lr
+; CHECK-ARMV7: beq [[SUCCESS_BB:\.?LBB.*]]
+; CHECK-ARMV7: ldrex [[OLDVAL]], [r[[ADDR]]]
+; CHECK-ARMV7: cmp [[OLDVAL]], r1
+; CHECK-ARMV7: beq [[LOOP_BB]]
; CHECK-ARMV7: [[FAIL_BB]]:
; CHECK-ARMV7: clrex
; CHECK-ARMV7: bx lr
+; CHECK-ARMV7: [[SUCCESS_BB]]:
+; CHECK-ARMV7: dmb ish
+; CHECK-ARMV7: bx lr
-; CHECK-T2: dmb ish
-; CHECK-T2: [[LOOP_BB:\.?LBB[0-9]+_1]]:
; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
; CHECK-T2: cmp [[OLDVAL]], r1
-; CHECK-T2: clrexne
-; CHECK-T2: bxne lr
+; CHECK-T2: bne [[FAIL_BB:\.?LBB.*]]
+; CHECK-T2: dmb ish
+; CHECK-T2: [[LOOP_BB:\.?LBB.*]]:
; CHECK-T2: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]]
; CHECK-T2: cmp [[SUCCESS]], #0
; CHECK-T2: dmbeq ish
; CHECK-T2: bxeq lr
-; CHECK-T2: b [[LOOP_BB]]
+; CHECK-T2: ldrex [[OLDVAL]], [r[[ADDR]]]
+; CHECK-T2: cmp [[OLDVAL]], r1
+; CHECK-T2: beq [[LOOP_BB]]
+; CHECK-T2: clrex
ret i32 %oldval
}
@@ -336,8 +319,8 @@ define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
; CHECK: dmb
; CHECK: add r0,
-; CHECK-M0: ___sync_val_compare_and_swap_4
-; CHECK-M0: ___sync_val_compare_and_swap_4
+; CHECK-T1: ___sync_val_compare_and_swap_4
+; CHECK-T1: ___sync_val_compare_and_swap_4
; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r0]
; CHECK-BAREMETAL-NOT: dmb
@@ -358,8 +341,8 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
; CHECK: dmb
; CHECK: str r3, [r2]
-; CHECK-M0: ___sync_lock_test_and_set
-; CHECK-M0: ___sync_lock_test_and_set
+; CHECK-T1: ___sync_lock_test_and_set
+; CHECK-T1: ___sync_lock_test_and_set
; CHECK-BAREMETAL-NOT: dmb
; CHECK-BAREMTEAL: str r1, [r0]
@@ -379,9 +362,9 @@ define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) {
; CHECK: dmb
; CHECK: str [[R0]], [r1]
-; CHECK-M0: ldr [[R0:r[0-9]]], [r0]
-; CHECK-M0: dmb
-; CHECK-M0: str [[R0]], [r1]
+; CHECK-T1: ldr [[R0:r[0-9]]], [{{r[0-9]+}}]
+; CHECK-T1: {{dmb|bl ___sync_synchronize}}
+; CHECK-T1: str [[R0]], [{{r[0-9]+}}]
; CHECK-BAREMETAL: ldr [[R0:r[0-9]]], [r0]
; CHECK-BAREMETAL-NOT: dmb
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-16 06:08:59 +0000