diff options
Diffstat (limited to 'test/CodeGen/ARM/fp16-v3.ll')
| -rw-r--r-- | test/CodeGen/ARM/fp16-v3.ll | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/fp16-v3.ll b/test/CodeGen/ARM/fp16-v3.ll index 6ed9c9d22c9d2..e26455e61e7f0 100644 --- a/test/CodeGen/ARM/fp16-v3.ll +++ b/test/CodeGen/ARM/fp16-v3.ll @@ -1,14 +1,16 @@ -; RUN: llc -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mattr=+fp16 < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv7a--none-eabi" ; CHECK-LABEL: test_vec3: -; CHECK: vcvtb.f32.f16 -; CHECK: vcvt.f32.s32 -; CHECK: vadd.f32 -; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}} -; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]] +; CHECK-DAG: vcvtb.f32.f16 [[SREG1:s[0-9]+]], +; CHECK-DAG: vcvt.f32.s32 [[SREG2:s[0-9]+]], +; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]] +; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]] +; CHECK: vadd.f32 [[SREG5:s[0-9]+]], [[SREG4]], [[SREG1]] +; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]] +; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG6]] ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]] ; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16 ; CHECK-DAG: strh [[RREG1]], [r0, #4] @@ -25,4 +27,16 @@ define void @test_vec3(<3 x half>* %arr, i32 %i) #0 { ret void } +; CHECK-LABEL: test_bitcast: +; CHECK: vcvtb.f16.f32 +; CHECK: vcvtb.f16.f32 +; CHECK: vcvtb.f16.f32 +; CHECK: pkhbt +; CHECK: uxth +define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 { + %bc = bitcast <3 x half> %inp to <3 x i16> + store <3 x i16> %bc, <3 x i16>* %arr, align 8 + ret void +} + attributes #0 = { nounwind } |