diff options
Diffstat (limited to 'test/CodeGen/ARM/vcgt.ll')
| -rw-r--r-- | test/CodeGen/ARM/vcgt.ll | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll index 2243bac91fb16..056866fe994b3 100644 --- a/test/CodeGen/ARM/vcgt.ll +++ b/test/CodeGen/ARM/vcgt.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vcgts8: +;CHECK-LABEL: vcgts8: ;CHECK: vcgt.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -12,7 +12,7 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcgts16: +;CHECK-LABEL: vcgts16: ;CHECK: vcgt.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -22,7 +22,7 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vcgts32: +;CHECK-LABEL: vcgts32: ;CHECK: vcgt.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -32,7 +32,7 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vcgtu8: +;CHECK-LABEL: vcgtu8: ;CHECK: vcgt.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -42,7 +42,7 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcgtu16: +;CHECK-LABEL: vcgtu16: ;CHECK: vcgt.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -52,7 +52,7 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vcgtu32: +;CHECK-LABEL: vcgtu32: ;CHECK: vcgt.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -62,7 +62,7 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcgtf32: +;CHECK-LABEL: vcgtf32: ;CHECK: vcgt.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -72,7 +72,7 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcgtQs8: +;CHECK-LABEL: vcgtQs8: ;CHECK: vcgt.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -82,7 +82,7 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vcgtQs16: +;CHECK-LABEL: vcgtQs16: ;CHECK: vcgt.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -92,7 +92,7 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcgtQs32: +;CHECK-LABEL: vcgtQs32: ;CHECK: vcgt.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -102,7 +102,7 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcgtQu8: +;CHECK-LABEL: vcgtQu8: ;CHECK: vcgt.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -112,7 +112,7 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vcgtQu16: +;CHECK-LABEL: vcgtQu16: ;CHECK: vcgt.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -122,7 +122,7 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcgtQu32: +;CHECK-LABEL: vcgtQu32: ;CHECK: vcgt.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -132,7 +132,7 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vcgtQf32: +;CHECK-LABEL: vcgtQf32: ;CHECK: vcgt.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -142,7 +142,7 @@ define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vacgtf32: +;CHECK-LABEL: vacgtf32: ;CHECK: vacgt.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -151,7 +151,7 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vacgtQf32: +;CHECK-LABEL: vacgtQf32: ;CHECK: vacgt.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -161,7 +161,7 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ; rdar://7923010 define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vcgt_zext: +;CHECK-LABEL: vcgt_zext: ;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1 ;CHECK: vcgt.f32 [[Q1:q[0-9]+]] ;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]] @@ -176,7 +176,7 @@ declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readn declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { -;CHECK: vcgti8Z: +;CHECK-LABEL: vcgti8Z: ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vcgt.s8 @@ -187,7 +187,7 @@ define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { } define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind { -;CHECK: vclti8Z: +;CHECK-LABEL: vclti8Z: ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vclt.s8 |