diff options
Diffstat (limited to 'test/CodeGen/ARM/vld3.ll')
| -rw-r--r-- | test/CodeGen/ARM/vld3.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index c3e8ee8691fd7..0eaad0f900354 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -15,7 +15,7 @@ define <8 x i8> @vld3i8(i8* %A) nounwind { ;CHECK-LABEL: vld3i8: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld3.8 {d16, d17, d18}, [r0:64] +;CHECK: vld3.8 {d16, d17, d18}, [{{r[0-9]+|lr}}:64] %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2 @@ -37,7 +37,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { ;Check for a post-increment updating load with register increment. define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind { ;CHECK-LABEL: vld3i16_update: -;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}} +;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+|lr}}], {{r[0-9]+|lr}} %A = load i16*, i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1) @@ -74,7 +74,7 @@ define <2 x float> @vld3f(float* %A) nounwind { define <1 x i64> @vld3i64(i64* %A) nounwind { ;CHECK-LABEL: vld3i64: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld1.64 {d16, d17, d18}, [r0:64] +;CHECK: vld1.64 {d16, d17, d18}, [{{r[0-9]+|lr}}:64] %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8* %tmp0, i32 16) %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 @@ -85,7 +85,7 @@ define <1 x i64> @vld3i64(i64* %A) nounwind { define <1 x i64> @vld3i64_update(i64** %ptr, i64* %A) nounwind { ;CHECK-LABEL: vld3i64_update: -;CHECK: vld1.64 {d16, d17, d18}, [r1:64]! +;CHECK: vld1.64 {d16, d17, d18}, [{{r[0-9]+|lr}}:64]! %tmp0 = bitcast i64* %A to i8* %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64.p0i8(i8* %tmp0, i32 16) %tmp5 = getelementptr i64, i64* %A, i32 3 @@ -99,8 +99,8 @@ define <1 x i64> @vld3i64_update(i64** %ptr, i64* %A) nounwind { define <16 x i8> @vld3Qi8(i8* %A) nounwind { ;CHECK-LABEL: vld3Qi8: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld3.8 {d16, d18, d20}, [r0:64]! -;CHECK: vld3.8 {d17, d19, d21}, [r0:64] +;CHECK: vld3.8 {d16, d18, d20}, [{{r[0-9]+|lr}}:64]! +;CHECK: vld3.8 {d17, d19, d21}, [{{r[0-9]+|lr}}:64] %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8.p0i8(i8* %A, i32 32) %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2 @@ -135,8 +135,8 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind { ;Check for a post-increment updating load. define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { ;CHECK-LABEL: vld3Qi32_update: -;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]! -;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]! +;CHECK: vld3.32 {d16, d18, d20}, {{\[}}[[R:r[0-9]+|lr]]]! +;CHECK: vld3.32 {d17, d19, d21}, {{\[}}[[R]]]! %A = load i32*, i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32.p0i8(i8* %tmp0, i32 1) |