diff options
Diffstat (limited to 'test/CodeGen/ARM')
25 files changed, 342 insertions, 79 deletions
diff --git a/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll new file mode 100644 index 0000000000000..465368b0ba8dc --- /dev/null +++ b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll @@ -0,0 +1,63 @@ +; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s +; PR5367 + +define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(i8* nocapture %pBuffer, i32 %numItems) nounwind { +entry: + br i1 undef, label %return, label %bb + +bb: ; preds = %bb, %entry + %0 = load float* undef, align 4 ; <float> [#uses=1] + %1 = load float* null, align 4 ; <float> [#uses=1] + %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1] + %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2] + %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] + %5 = insertelement <4 x float> %4, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=4] + %6 = fsub <4 x float> zeroinitializer, %3 ; <<4 x float>> [#uses=1] + %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=2] + %8 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1] + %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=2] + %10 = fmul <4 x float> %7, %9 ; <<4 x float>> [#uses=1] + %11 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %12 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=2] + %13 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %14 = fmul <4 x float> %11, %13 ; <<4 x float>> [#uses=1] + %15 = fadd <4 x float> %10, %14 ; <<4 x float>> [#uses=1] + %16 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1] + %17 = fadd <4 x float> %15, zeroinitializer ; <<4 x float>> [#uses=1] + %18 = shufflevector <4 x float> %17, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] + %19 = fmul <4 x float> %7, %16 ; <<4 x float>> [#uses=1] + %20 = fadd <4 x float> %19, zeroinitializer ; <<4 x float>> [#uses=1] + %21 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] + %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %23 = fmul <4 x float> %22, %9 ; <<4 x float>> [#uses=1] + %24 = fadd <4 x float> %20, %23 ; <<4 x float>> [#uses=1] + %25 = shufflevector <4 x float> %18, <4 x float> %24, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> ; <<4 x float>> [#uses=1] + %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1] + %27 = fmul <4 x float> %26, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1] + %28 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %5 ; <<4 x float>> [#uses=1] + %29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1] + %30 = fmul <4 x float> zeroinitializer, %29 ; <<4 x float>> [#uses=1] + %31 = fmul <4 x float> %30, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1] + %32 = shufflevector <4 x float> %27, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %33 = shufflevector <4 x float> %28, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1] + %34 = shufflevector <2 x float> %33, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1] + %35 = fmul <4 x float> %32, %34 ; <<4 x float>> [#uses=1] + %36 = fadd <4 x float> %35, zeroinitializer ; <<4 x float>> [#uses=1] + %37 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] + %38 = shufflevector <4 x float> %37, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %39 = fmul <4 x float> zeroinitializer, %38 ; <<4 x float>> [#uses=1] + %40 = fadd <4 x float> %36, %39 ; <<4 x float>> [#uses=1] + %41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1] + %42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1] + %43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1] + store float undef, float* undef, align 4 + store float 0.000000e+00, float* null, align 4 + %44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1] + store float %44, float* undef, align 4 + br i1 undef, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} + +declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll new file mode 100644 index 0000000000000..a4e76859d16de --- /dev/null +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s + +@.str = private constant [1 x i8] zeroinitializer, align 1 + +define arm_aapcscc void @g() { +entry: +;CHECK: [sp, #+8] +;CHECK: [sp, #+12] +;CHECK: [sp] + tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + ret void +} + +declare arm_aapcscc void @f(i8*, ...) diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll new file mode 100644 index 0000000000000..82563869bd968 --- /dev/null +++ b/test/CodeGen/ARM/2009-10-30.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; This test checks that the address of the varg arguments is correctly +; computed when there are 5 or more regular arguments. + +define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) { +entry: +;CHECK: sub sp, sp, #4 +;CHECK: add r0, sp, #8 +;CHECK: str r0, [sp], #+4 +;CHECK: bx lr + %ap = alloca i8*, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret void +} + +declare void @llvm.va_start(i8*) nounwind diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll new file mode 100644 index 0000000000000..c260b973b5a0b --- /dev/null +++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -0,0 +1,37 @@ +; RUN: llc -mcpu=cortex-a8 < %s | grep vmov | count 1 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv7-eabi" + +%foo = type { <4 x float> } + +define arm_aapcs_vfpcc void @bar(%foo* noalias sret %agg.result, <4 x float> %quat.0) nounwind { +entry: + %quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2] + %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] + store <4 x float> %quat.0, <4 x float>* %0 + %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3] + %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2] + %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1] + %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1] + %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2] + %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2] + %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2] + %8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses=3] + %9 = fmul <4 x float> %8, %8 ; <<4 x float>> [#uses=1] + %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1] + %11 = fmul <4 x float> %10, %8 ; <<4 x float>> [#uses=1] + %12 = fmul <4 x float> %11, %1 ; <<4 x float>> [#uses=1] + %13 = call arm_aapcs_vfpcc %foo* @baz(%foo* %agg.result, <4 x float> %12) nounwind ; <%foo*> [#uses=0] + ret void +} + +declare arm_aapcs_vfpcc %foo* @baz(%foo*, <4 x float>) nounwind + +declare arm_aapcs_vfpcc <4 x float> @quux(%foo* nocapture) nounwind readonly + +declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll new file mode 100644 index 0000000000000..f2288c3710e16 --- /dev/null +++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -0,0 +1,20 @@ +; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.32 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv7-eabi" + +define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind { +entry: + br i1 undef, label %return, label %bb + +bb: ; preds = %bb, %entry + %0 = load float* undef, align 4 ; <float> [#uses=1] + %1 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] + %2 = insertelement <4 x float> %1, float undef, i32 3 ; <<4 x float>> [#uses=1] + %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1] + %4 = extractelement <4 x float> %3, i32 1 ; <float> [#uses=1] + store float %4, float* undef, align 4 + br i1 undef, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/ARM/alloca.ll b/test/CodeGen/ARM/alloca.ll index 15cf67734cb2d..82a8c98599c21 100644 --- a/test/CodeGen/ARM/alloca.ll +++ b/test/CodeGen/ARM/alloca.ll @@ -1,13 +1,12 @@ -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \ -; RUN: grep {mov r11, sp} -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \ -; RUN: grep {mov sp, r11} +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s define void @f(i32 %a) { entry: +; CHECK: mov r11, sp %tmp = alloca i8, i32 %a ; <i8*> [#uses=1] call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 ) ret void +; CHECK: mov sp, r11 } declare void @g(i8*, i32, i32, i32, i32) diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll index ad5b2d69fab92..cc718399ea96e 100644 --- a/test/CodeGen/ARM/arguments.ll +++ b/test/CodeGen/ARM/arguments.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | \ -; RUN: grep {mov r0, r2} | count 1 -; RUN: llc < %s -mtriple=arm-apple-darwin | \ -; RUN: grep {mov r0, r1} | count 1 +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN define i32 @f(i32 %a, i64 %b) { +; ELF: mov r0, r2 +; DARWIN: mov r0, r1 %tmp = call i32 @g(i64 %b) ret i32 %tmp } diff --git a/test/CodeGen/ARM/arguments_f64_backfill.ll b/test/CodeGen/ARM/arguments_f64_backfill.ll index 690f488d8483d..d8019a07fabf1 100644 --- a/test/CodeGen/ARM/arguments_f64_backfill.ll +++ b/test/CodeGen/ARM/arguments_f64_backfill.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 -float-abi=hard | grep {fcpys s0, s1} +; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 -float-abi=hard | FileCheck %s define float @f(float %z, double %a, float %b) { +; CHECK: fcpys s0, s1 %tmp = call float @g(float %b) ret float %tmp } diff --git a/test/CodeGen/ARM/arm-negative-stride.ll b/test/CodeGen/ARM/arm-negative-stride.ll index c4b4ec613ee55..72ec8efcc4459 100644 --- a/test/CodeGen/ARM/arm-negative-stride.ll +++ b/test/CodeGen/ARM/arm-negative-stride.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=arm | grep {str r1, \\\[r.*, -r.*, lsl #2\} +; RUN: llc < %s -march=arm | FileCheck %s define void @test(i32* %P, i32 %A, i32 %i) nounwind { entry: +; CHECK: str r1, [{{r.*}}, -{{r.*}}, lsl #2] icmp eq i32 %i, 0 ; <i1>:0 [#uses=1] br i1 %0, label %return, label %bb diff --git a/test/CodeGen/ARM/bfc.ll b/test/CodeGen/ARM/bfc.ll index 53392de73fcf8..c4a44b4472d1e 100644 --- a/test/CodeGen/ARM/bfc.ll +++ b/test/CodeGen/ARM/bfc.ll @@ -1,19 +1,25 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | grep "bfc " | count 3 +; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s ; 4278190095 = 0xff00000f define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: bfc %tmp = and i32 %a, 4278190095 ret i32 %tmp } ; 4286578688 = 0xff800000 define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: bfc %tmp = and i32 %a, 4286578688 ret i32 %tmp } ; 4095 = 0x00000fff define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: bfc %tmp = and i32 %a, 4095 ret i32 %tmp } diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index 52246c3f0cd77..3dd66ae71df86 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -1,13 +1,16 @@ -; RUN: llc < %s -march=arm | grep {mov lr, pc} -; RUN: llc < %s -march=arm -mattr=+v5t | grep blx +; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ -; RUN: -relocation-model=pic | grep {PLT} +; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF @t = weak global i32 ()* null ; <i32 ()**> [#uses=1] declare void @g(i32, i32, i32, i32) define void @f() { +; CHECKV4: mov lr, pc +; CHECKV5: blx +; CHECKELF: PLT call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll index 294de5ff72780..a6a7ed6af1840 100644 --- a/test/CodeGen/ARM/carry.ll +++ b/test/CodeGen/ARM/carry.ll @@ -1,14 +1,19 @@ -; RUN: llc < %s -march=arm | grep "subs r" | count 2 -; RUN: llc < %s -march=arm | grep "adc r" -; RUN: llc < %s -march=arm | grep "sbc r" | count 2 +; RUN: llc < %s -march=arm | FileCheck %s define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: subs r +; CHECK: sbc r entry: %tmp = sub i64 %a, %b ret i64 %tmp } define i64 @f2(i64 %a, i64 %b) { +; CHECK: f2: +; CHECK: adc r +; CHECK: subs r +; CHECK: sbc r entry: %tmp1 = shl i64 %a, 1 %tmp2 = sub i64 %tmp1, %b diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll index e2d8ddc63fcf4..ce919361619a0 100644 --- a/test/CodeGen/ARM/constants.ll +++ b/test/CodeGen/ARM/constants.ll @@ -1,39 +1,44 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep {mov r0, #0} | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep {mov r0, #255$} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | \ -; RUN: grep {mov r0.*256} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | grep {orr.*256} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | grep {mov r0, .*-1073741761} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | grep {mov r0, .*1008} | count 1 -; RUN: llc < %s -march=arm | grep {cmp r0, #1, 16} | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1() { +; CHECK: f1 +; CHECK: mov r0, #0 ret i32 0 } define i32 @f2() { +; CHECK: f2 +; CHECK: mov r0, #255 ret i32 255 } define i32 @f3() { +; CHECK: f3 +; CHECK: mov r0{{.*}}256 ret i32 256 } define i32 @f4() { +; CHECK: f4 +; CHECK: orr{{.*}}256 ret i32 257 } define i32 @f5() { +; CHECK: f5 +; CHECK: mov r0, {{.*}}-1073741761 ret i32 -1073741761 } define i32 @f6() { +; CHECK: f6 +; CHECK: mov r0, {{.*}}1008 ret i32 1008 } define void @f7(i32 %a) { +; CHECK: f7 +; CHECK: cmp r0, #1, 16 %b = icmp ugt i32 %a, 65536 ; <i1> [#uses=1] br i1 %b, label %r, label %r diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index 1a1cd0747b498..5c31ea641de49 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 ; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 define float @test(float %acc, float %a, float %b) { diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll index e57bbbba3b384..8fc13e78bc30c 100644 --- a/test/CodeGen/ARM/fnmacs.ll +++ b/test/CodeGen/ARM/fnmacs.ll @@ -1,11 +1,18 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEONFP define float @test(float %acc, float %a, float %b) { entry: +; VFP2: fnmacs +; NEON: fnmacs + +; NEONFP-NOT: vmls +; NEONFP-NOT: fcpys +; NEONFP: vmul.f32 +; NEONFP: vsub.f32 +; NEONFP: fmrs + %0 = fmul float %a, %b %1 = fsub float %acc, %0 ret float %1 diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll new file mode 100644 index 0000000000000..4de18bc3b456e --- /dev/null +++ b/test/CodeGen/ARM/fpconsts.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s + +define arm_apcscc float @t1(float %x) nounwind readnone optsize { +entry: +; CHECK: t1: +; CHECK: fconsts s1, #16 + %0 = fadd float %x, 4.000000e+00 + ret float %0 +} + +define arm_apcscc double @t2(double %x) nounwind readnone optsize { +entry: +; CHECK: t2: +; CHECK: fconstd d1, #8 + %0 = fadd double %x, 3.000000e+00 + ret double %0 +} + +define arm_apcscc double @t3(double %x) nounwind readnone optsize { +entry: +; CHECK: t3: +; CHECK: fconstd d1, #170 + %0 = fmul double %x, -1.300000e+01 + ret double %0 +} + +define arm_apcscc float @t4(float %x) nounwind readnone optsize { +entry: +; CHECK: t4: +; CHECK: fconsts s1, #184 + %0 = fmul float %x, -2.400000e+01 + ret float %0 +} diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll index fa897bf83f3a4..0822fbff653f6 100644 --- a/test/CodeGen/ARM/fpmem.ll +++ b/test/CodeGen/ARM/fpmem.ll @@ -1,21 +1,22 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep {mov r0, #0} | count 1 -; RUN: llc < %s -march=arm -mattr=+vfp2 | \ -; RUN: grep {flds.*\\\[} | count 1 -; RUN: llc < %s -march=arm -mattr=+vfp2 | \ -; RUN: grep {fsts.*\\\[} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s define float @f1(float %a) { +; CHECK: f1: +; CHECK: mov r0, #0 ret float 0.000000e+00 } define float @f2(float* %v, float %u) { +; CHECK: f2: +; CHECK: flds{{.*}}[ %tmp = load float* %v ; <float> [#uses=1] %tmp1 = fadd float %tmp, %u ; <float> [#uses=1] ret float %tmp1 } define void @f3(float %a, float %b, float* %v) { +; CHECK: f3: +; CHECK: fsts{{.*}}[ %tmp = fadd float %a, %b ; <float> [#uses=1] store float %tmp, float* %v ret void diff --git a/test/CodeGen/ARM/ispositive.ll b/test/CodeGen/ARM/ispositive.ll index 5116ac82862a4..245ed516f70bc 100644 --- a/test/CodeGen/ARM/ispositive.ll +++ b/test/CodeGen/ARM/ispositive.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=arm | grep {mov r0, r0, lsr #31} +; RUN: llc < %s -march=arm | FileCheck %s define i32 @test1(i32 %X) { +; CHECK: mov r0, r0, lsr #31 entry: icmp slt i32 %X, 0 ; <i1>:0 [#uses=1] zext i1 %0 to i32 ; <i32>:1 [#uses=1] diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 774b3c09bed42..1a016a0942d23 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -1,13 +1,10 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep ldmia | count 2 -; RUN: llc < %s -march=arm | \ -; RUN: grep ldmib | count 1 -; RUN: llc < %s -mtriple=arm-apple-darwin | \ -; RUN: grep {ldmfd sp\!} | count 3 +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s @X = external global [0 x i32] ; <[0 x i32]*> [#uses=5] define i32 @t1() { +; CHECK: t1: +; CHECK: ldmia %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1] @@ -15,6 +12,8 @@ define i32 @t1() { } define i32 @t2() { +; CHECK: t2: +; CHECK: ldmia %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1] @@ -23,6 +22,9 @@ define i32 @t2() { } define i32 @t3() { +; CHECK: t3: +; CHECK: ldmib +; CHECK: ldmfd sp! %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll index 954fb5b8ad311..011e61caea966 100644 --- a/test/CodeGen/ARM/ldr.ll +++ b/test/CodeGen/ARM/ldr.ll @@ -1,16 +1,16 @@ -; RUN: llc < %s -march=arm | grep {ldr r0} | count 7 -; RUN: llc < %s -march=arm | grep mov | grep 1 -; RUN: llc < %s -march=arm | not grep mvn -; RUN: llc < %s -march=arm | grep ldr | grep lsl -; RUN: llc < %s -march=arm | grep ldr | grep lsr +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1(i32* %v) { +; CHECK: f1: +; CHECK: ldr r0 entry: %tmp = load i32* %v ret i32 %tmp } define i32 @f2(i32* %v) { +; CHECK: f2: +; CHECK: ldr r0 entry: %tmp2 = getelementptr i32* %v, i32 1023 %tmp = load i32* %tmp2 @@ -18,6 +18,9 @@ entry: } define i32 @f3(i32* %v) { +; CHECK: f3: +; CHECK: mov +; CHECK: ldr r0 entry: %tmp2 = getelementptr i32* %v, i32 1024 %tmp = load i32* %tmp2 @@ -25,6 +28,9 @@ entry: } define i32 @f4(i32 %base) { +; CHECK: f4: +; CHECK-NOT: mvn +; CHECK: ldr r0 entry: %tmp1 = sub i32 %base, 128 %tmp2 = inttoptr i32 %tmp1 to i32* @@ -33,6 +39,8 @@ entry: } define i32 @f5(i32 %base, i32 %offset) { +; CHECK: f5: +; CHECK: ldr r0 entry: %tmp1 = add i32 %base, %offset %tmp2 = inttoptr i32 %tmp1 to i32* @@ -41,6 +49,8 @@ entry: } define i32 @f6(i32 %base, i32 %offset) { +; CHECK: f6: +; CHECK: ldr r0{{.*}}lsl{{.*}} entry: %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 @@ -50,6 +60,8 @@ entry: } define i32 @f7(i32 %base, i32 %offset) { +; CHECK: f7: +; CHECK: ldr r0{{.*}}lsr{{.*}} entry: %tmp1 = lshr i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index 2fcaac0d9c982..16ef7cc2cb6c7 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -1,47 +1,50 @@ -; RUN: llc < %s -march=arm -asm-verbose | \ -; RUN: grep -- {-2147483648} | count 3 -; RUN: llc < %s -march=arm | grep mvn | count 3 -; RUN: llc < %s -march=arm | grep adds | count 1 -; RUN: llc < %s -march=arm | grep adc | count 1 -; RUN: llc < %s -march=arm | grep {subs } | count 1 -; RUN: llc < %s -march=arm | grep sbc | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep smull | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep umull | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i64 @f1() { +; CHECK: f1: entry: ret i64 0 } define i64 @f2() { +; CHECK: f2: entry: ret i64 1 } define i64 @f3() { +; CHECK: f3: +; CHECK: mvn{{.*}}-2147483648 entry: ret i64 2147483647 } define i64 @f4() { +; CHECK: f4: +; CHECK: -2147483648 entry: ret i64 2147483648 } define i64 @f5() { +; CHECK: f5: +; CHECK: mvn +; CHECK: mvn{{.*}}-2147483648 entry: ret i64 9223372036854775807 } define i64 @f6(i64 %x, i64 %y) { +; CHECK: f6: +; CHECK: adds +; CHECK: adc entry: %tmp1 = add i64 %y, 1 ; <i64> [#uses=1] ret i64 %tmp1 } define void @f7() { +; CHECK: f7: entry: %tmp = call i64 @f8( ) ; <i64> [#uses=0] ret void @@ -50,12 +53,17 @@ entry: declare i64 @f8() define i64 @f9(i64 %a, i64 %b) { +; CHECK: f9: +; CHECK: subs r +; CHECK: sbc entry: %tmp = sub i64 %a, %b ; <i64> [#uses=1] ret i64 %tmp } define i64 @f(i32 %a, i32 %b) { +; CHECK: f: +; CHECK: smull entry: %tmp = sext i32 %a to i64 ; <i64> [#uses=1] %tmp1 = sext i32 %b to i64 ; <i64> [#uses=1] @@ -64,6 +72,8 @@ entry: } define i64 @g(i32 %a, i32 %b) { +; CHECK: g: +; CHECK: umull entry: %tmp = zext i32 %a to i64 ; <i64> [#uses=1] %tmp1 = zext i32 %b to i64 ; <i64> [#uses=1] @@ -72,9 +82,9 @@ entry: } define i64 @f10() { +; CHECK: f10: entry: %a = alloca i64, align 8 ; <i64*> [#uses=1] %retval = load i64* %a ; <i64> [#uses=1] ret i64 %retval } - diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 057b5f067f803..688b7bc312c7b 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep rrx %t | count 1 -; RUN: grep __ashldi3 %t -; RUN: grep __ashrdi3 %t -; RUN: grep __lshrdi3 %t +; RUN: llc < %s -march=arm | FileCheck %s define i64 @f0(i64 %A, i64 %B) { +; CHECK: f0 +; CHECK: movs r3, r3, lsr #1 +; CHECK-NEXT: mov r2, r2, rrx +; CHECK-NEXT: subs r0, r0, r2 +; CHECK-NEXT: sbc r1, r1, r3 %tmp = bitcast i64 %A to i64 %tmp2 = lshr i64 %B, 1 %tmp3 = sub i64 %tmp, %tmp2 @@ -12,18 +13,34 @@ define i64 @f0(i64 %A, i64 %B) { } define i32 @f1(i64 %x, i64 %y) { +; CHECK: f1 +; CHECK: mov r0, r0, lsl r2 %a = shl i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b } define i32 @f2(i64 %x, i64 %y) { +; CHECK: f2 +; CHECK: mov r0, r0, lsr r2 +; CHECK-NEXT: rsb r3, r2, #32 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 +; CHECK-NEXT: movge r0, r1, asr r2 %a = ashr i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b } define i32 @f3(i64 %x, i64 %y) { +; CHECK: f3 +; CHECK: mov r0, r0, lsr r2 +; CHECK-NEXT: rsb r3, r2, #32 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 +; CHECK-NEXT: movge r0, r1, lsr r2 %a = lshr i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll index ba9699efd5973..50da997ed468a 100644 --- a/test/CodeGen/ARM/remat.ll +++ b/test/CodeGen/ARM/remat.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 4 +; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 5 %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } %struct.LOCBOX = type { i32, i32, i32, i32 } diff --git a/test/CodeGen/ARM/str_post.ll b/test/CodeGen/ARM/str_post.ll index 801b9cee37d69..97916f169b0f4 100644 --- a/test/CodeGen/ARM/str_post.ll +++ b/test/CodeGen/ARM/str_post.ll @@ -1,9 +1,8 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep {strh .*\\\[.*\], #-4} | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep {str .*\\\[.*\],} | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i16 @test1(i32* %X, i16* %A) { +; CHECK: test1: +; CHECK: strh {{.*}}[{{.*}}], #-4 %Y = load i32* %X ; <i32> [#uses=1] %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1] store i16 %tmp1, i16* %A @@ -13,6 +12,8 @@ define i16 @test1(i32* %X, i16* %A) { } define i32 @test2(i32* %X, i32* %A) { +; CHECK: test2: +; CHECK: str {{.*}}[{{.*}}], %Y = load i32* %X ; <i32> [#uses=1] store i32 %Y, i32* %A %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll index 328472081e197..d932f90e4c10f 100644 --- a/test/CodeGen/ARM/tls2.ll +++ b/test/CodeGen/ARM/tls2.ll @@ -1,19 +1,27 @@ -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ -; RUN: grep {i(gottpoff)} -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ -; RUN: grep {ldr r., \[pc, r.\]} ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \ -; RUN: -relocation-model=pic | grep {__tls_get_addr} +; RUN: | FileCheck %s -check-prefix=CHECK-NONPIC +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \ +; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC @i = external thread_local global i32 ; <i32*> [#uses=2] define i32 @f() { +; CHECK-NONPIC: f: +; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: i(gottpoff) +; CHECK-PIC: f: +; CHECK-PIC: __tls_get_addr entry: %tmp1 = load i32* @i ; <i32> [#uses=1] ret i32 %tmp1 } define i32* @g() { +; CHECK-NONPIC: g: +; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: i(gottpoff) +; CHECK-PIC: g: +; CHECK-PIC: __tls_get_addr entry: ret i32* @i } |