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-rw-r--r--test/CodeGen/CellSPU/arg_ret.ll33
-rw-r--r--test/CodeGen/CellSPU/bigstack.ll6
-rw-r--r--test/CodeGen/CellSPU/call.ll26
-rw-r--r--test/CodeGen/CellSPU/call_indirect.ll2
-rw-r--r--test/CodeGen/CellSPU/shuffles.ll23
-rw-r--r--test/CodeGen/CellSPU/v2f32.ll75
-rw-r--r--test/CodeGen/CellSPU/v2i32.ll64
7 files changed, 223 insertions, 6 deletions
diff --git a/test/CodeGen/CellSPU/arg_ret.ll b/test/CodeGen/CellSPU/arg_ret.ll
new file mode 100644
index 0000000000000..743292a58d591
--- /dev/null
+++ b/test/CodeGen/CellSPU/arg_ret.ll
@@ -0,0 +1,33 @@
+; Test parameter passing and return values
+;RUN: llc --march=cellspu %s -o - | FileCheck %s
+
+; this fits into registers r3-r74
+%paramstruct = type { i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,
+ i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,
+ i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,
+ i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,
+ i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,
+ i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32}
+define ccc i32 @test_regs( %paramstruct %prm )
+{
+;CHECK: lr $3, $74
+;CHECK: bi $lr
+ %1 = extractvalue %paramstruct %prm, 71
+ ret i32 %1
+}
+
+define ccc i32 @test_regs_and_stack( %paramstruct %prm, i32 %stackprm )
+{
+;CHECK-NOT: a $3, $74, $75
+ %1 = extractvalue %paramstruct %prm, 71
+ %2 = add i32 %1, %stackprm
+ ret i32 %2
+}
+
+define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm )
+{
+;CHECK: lqd $75, 80($sp)
+;CHECK: lr $3, $4
+ ret %paramstruct %prm
+}
+
diff --git a/test/CodeGen/CellSPU/bigstack.ll b/test/CodeGen/CellSPU/bigstack.ll
index 5483f463732ba..63293e2aecb14 100644
--- a/test/CodeGen/CellSPU/bigstack.ll
+++ b/test/CodeGen/CellSPU/bigstack.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=cellspu -o %t1.s
-; RUN: grep lqx %t1.s | count 4
-; RUN: grep il %t1.s | grep -v file | count 7
-; RUN: grep stqx %t1.s | count 2
+; RUN: grep lqx %t1.s | count 3
+; RUN: grep il %t1.s | grep -v file | count 5
+; RUN: grep stqx %t1.s | count 1
define i32 @bigstack() nounwind {
entry:
diff --git a/test/CodeGen/CellSPU/call.ll b/test/CodeGen/CellSPU/call.ll
index eb7cf2c6467c8..559b266e59df3 100644
--- a/test/CodeGen/CellSPU/call.ll
+++ b/test/CodeGen/CellSPU/call.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=cellspu -regalloc=linearscan > %t1.s
; RUN: grep brsl %t1.s | count 1
-; RUN: grep brasl %t1.s | count 1
-; RUN: grep stqd %t1.s | count 80
+; RUN: grep brasl %t1.s | count 2
+; RUN: grep stqd %t1.s | count 82
; RUN: llc < %s -march=cellspu | FileCheck %s
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
@@ -29,3 +29,25 @@ define i32 @stub_2(...) {
entry:
ret i32 0
}
+
+; check that struct is passed in r3->
+; assert this by changing the second field in the struct
+%0 = type { i32, i32, i32 }
+declare %0 @callee()
+define %0 @test_structret()
+{
+;CHECK: stqd $lr, 16($sp)
+;CHECK: stqd $sp, -48($sp)
+;CHECK: ai $sp, $sp, -48
+;CHECK: brasl $lr, callee
+ %rv = call %0 @callee()
+;CHECK: ai $4, $4, 1
+;CHECK: lqd $lr, 64($sp)
+;CHECK: ai $sp, $sp, 48
+;CHECK: bi $lr
+ %oldval = extractvalue %0 %rv, 1
+ %newval = add i32 %oldval,1
+ %newrv = insertvalue %0 %rv, i32 %newval, 1
+ ret %0 %newrv
+}
+
diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll
index d94d77c9f1423..141361d5702b7 100644
--- a/test/CodeGen/CellSPU/call_indirect.ll
+++ b/test/CodeGen/CellSPU/call_indirect.ll
@@ -12,7 +12,7 @@
; RUN: grep rotqby %t2.s | count 5
; RUN: grep lqd %t2.s | count 13
; RUN: grep ilhu %t2.s | count 2
-; RUN: grep ai %t2.s | count 8
+; RUN: grep ai %t2.s | count 9
; RUN: grep dispatch_tab %t2.s | count 6
; ModuleID = 'call_indirect.bc'
diff --git a/test/CodeGen/CellSPU/shuffles.ll b/test/CodeGen/CellSPU/shuffles.ll
index 04accb9c56b8d..f37d2ae89b003 100644
--- a/test/CodeGen/CellSPU/shuffles.ll
+++ b/test/CodeGen/CellSPU/shuffles.ll
@@ -16,3 +16,26 @@ define <4 x float> @splat(float %param1) {
ret <4 x float> %val
}
+define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) {
+ %sl2_17_tmp1 = insertelement <2 x float> zeroinitializer, float %val1, i32 0
+;CHECK: lqa $6,
+;CHECK: shufb $4, $4, $5, $6
+ %sl2_17 = insertelement <2 x float> %sl2_17_tmp1, float %val2, i32 1
+
+;CHECK: cdd $5, 0($3)
+;CHECK: lqd $6, 0($3)
+;CHECK: shufb $4, $4, $6, $5
+;CHECK: stqd $4, 0($3)
+;CHECK: bi $lr
+ store <2 x float> %sl2_17, <2 x float>* %ptr
+ ret void
+}
+
+define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
+;CHECK: cwd $5, 4($sp)
+;CHECK: shufb $3, $4, $3, $5
+;CHECK: bi $lr
+ %rv = insertelement <4 x float> %vparam, float %eltparam, i32 1
+ ret <4 x float> %rv
+}
+
diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll
new file mode 100644
index 0000000000000..b81c0cdbb2994
--- /dev/null
+++ b/test/CodeGen/CellSPU/v2f32.ll
@@ -0,0 +1,75 @@
+;RUN: llc --march=cellspu %s -o - | FileCheck %s
+%vec = type <2 x float>
+
+define %vec @test_ret(%vec %param)
+{
+;CHECK: bi $lr
+ ret %vec %param
+}
+
+define %vec @test_add(%vec %param)
+{
+;CHECK: fa {{\$.}}, $3, $3
+ %1 = fadd %vec %param, %param
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define %vec @test_sub(%vec %param)
+{
+;CHECK: fs {{\$.}}, $3, $3
+ %1 = fsub %vec %param, %param
+
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define %vec @test_mul(%vec %param)
+{
+;CHECK: fm {{\$.}}, $3, $3
+ %1 = fmul %vec %param, %param
+
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define %vec @test_splat(float %param ) {
+;CHECK: lqa
+;CHECK: shufb
+ %sv = insertelement <1 x float> undef, float %param, i32 0
+ %rv = shufflevector <1 x float> %sv, <1 x float> undef, <2 x i32> zeroinitializer
+;CHECK: bi $lr
+ ret %vec %rv
+}
+
+define void @test_store(%vec %val, %vec* %ptr){
+
+;CHECK: stqd
+ store %vec undef, %vec* null
+
+;CHECK: stqd $3, 0(${{.}})
+;CHECK: bi $lr
+ store %vec %val, %vec* %ptr
+ ret void
+}
+
+define %vec @test_insert(){
+;CHECK: cwd
+;CHECK: shufb $3
+ %rv = insertelement %vec undef, float 0.0e+00, i32 undef
+;CHECK: bi $lr
+ ret %vec %rv
+}
+
+define void @test_unaligned_store() {
+;CHECK: cdd $3, 8($3)
+;CHECK: lqd
+;CHECK: shufb
+;CHECK: stqd
+ %data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1]
+ %ptr = getelementptr [4 x float]* %data, i32 0, i32 2 ; <float*> [#uses=1]
+ %vptr = bitcast float* %ptr to <2 x float>* ; <[1 x <2 x float>]*> [#uses=1]
+ store <2 x float> undef, <2 x float>* %vptr
+ ret void
+}
+
diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll
new file mode 100644
index 0000000000000..dd51be5a71d2e
--- /dev/null
+++ b/test/CodeGen/CellSPU/v2i32.ll
@@ -0,0 +1,64 @@
+;RUN: llc --march=cellspu %s -o - | FileCheck %s
+%vec = type <2 x i32>
+
+define %vec @test_ret(%vec %param)
+{
+;CHECK: bi $lr
+ ret %vec %param
+}
+
+define %vec @test_add(%vec %param)
+{
+;CHECK: a {{\$.}}, $3, $3
+ %1 = add %vec %param, %param
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define %vec @test_sub(%vec %param)
+{
+;CHECK: sf {{\$.}}, $4, $3
+ %1 = sub %vec %param, <i32 1, i32 1>
+
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define %vec @test_mul(%vec %param)
+{
+;CHECK: mpyu
+;CHECK: mpyh
+;CHECK: a {{\$., \$., \$.}}
+;CHECK: a {{\$., \$., \$.}}
+ %1 = mul %vec %param, %param
+
+;CHECK: bi $lr
+ ret %vec %1
+}
+
+define <2 x i32> @test_splat(i32 %param ) {
+;TODO insertelement transforms to a PREFSLOT2VEC, that trasforms to the
+; somewhat redundant:
+;CHECK-NOT or $3, $3, $3
+;CHECK: lqa
+;CHECK: shufb
+ %sv = insertelement <1 x i32> undef, i32 %param, i32 0
+ %rv = shufflevector <1 x i32> %sv, <1 x i32> undef, <2 x i32> zeroinitializer
+;CHECK: bi $lr
+ ret <2 x i32> %rv
+}
+
+define i32 @test_extract() {
+;CHECK: shufb $3
+ %rv = extractelement <2 x i32> zeroinitializer, i32 undef ; <i32> [#uses=1]
+;CHECK: bi $lr
+ ret i32 %rv
+}
+
+define void @test_store( %vec %val, %vec* %ptr)
+{
+;CHECK: stqd $3, 0(${{.}})
+;CHECK: bi $lr
+ store %vec %val, %vec* %ptr
+ ret void
+}