diff options
Diffstat (limited to 'test/CodeGen/MIR')
24 files changed, 177 insertions, 219 deletions
diff --git a/test/CodeGen/MIR/AArch64/atomic-memoperands.mir b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir new file mode 100644 index 0000000000000..1fe42a7314881 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir @@ -0,0 +1,30 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s + +--- | + + define void @atomic_memoperands() { + ret void + } + +... +--- +# CHECK-LABEL: name: atomic_memoperands +# CHECK: %1(s64) = G_LOAD %0(p0) :: (load unordered 8) +# CHECK: %2(s32) = G_LOAD %0(p0) :: (load monotonic 4) +# CHECK: %3(s16) = G_LOAD %0(p0) :: (load acquire 2) +# CHECK: G_STORE %3(s16), %0(p0) :: (store release 2) +# CHECK: G_STORE %2(s32), %0(p0) :: (store acq_rel 4) +# CHECK: G_STORE %1(s64), %0(p0) :: (store singlethread seq_cst 8) +name: atomic_memoperands +body: | + bb.0: + + %0:_(p0) = COPY %x0 + %1:_(s64) = G_LOAD %0(p0) :: (load unordered 8) + %2:_(s32) = G_LOAD %0(p0) :: (load monotonic 4) + %3:_(s16) = G_LOAD %0(p0) :: (load acquire 2) + G_STORE %3(s16), %0(p0) :: (store release 2) + G_STORE %2(s32), %0(p0) :: (store acq_rel 4) + G_STORE %1(s64), %0(p0) :: (store singlethread seq_cst 8) + RET_ReallyLR +... diff --git a/test/CodeGen/MIR/AArch64/register-operand-bank.mir b/test/CodeGen/MIR/AArch64/register-operand-bank.mir new file mode 100644 index 0000000000000..d48495167f152 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/register-operand-bank.mir @@ -0,0 +1,20 @@ +# RUN: llc -o - %s -mtriple=aarch64-- -run-pass=none | FileCheck %s +# REQUIRES: global-isel +# Test various aspects of register bank specification on machine operands. +--- | + define void @func() { ret void } +... +--- +# CHECK-LABEL: name: func +# CHECK: registers: +# CHECK: - { id: 0, class: gpr } +# CHECK: - { id: 1, class: fpr } +name: func +body: | + bb.0: + %0 : gpr(s64) = COPY %x9 + %x9 = COPY %0 + + %3 : fpr(s64) = COPY %d0 + %d1 = COPY %3 : fpr +... diff --git a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir index 47f0e168a722e..5da98fb9c2d1c 100644 --- a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir +++ b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -mcpu=SI -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @@ -6,7 +6,7 @@ @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 - define void @float(float addrspace(1)* %out, i32 %index) #0 { + define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 { entry: %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index %1 = load float, float addrspace(2)* %0 @@ -14,21 +14,7 @@ ret void } - declare { i1, i64 } @llvm.SI.if(i1) - - declare { i1, i64 } @llvm.SI.else(i64) - - declare i64 @llvm.SI.break(i64) - - declare i64 @llvm.SI.if.break(i1, i64) - - declare i64 @llvm.SI.else.break(i64, i64) - - declare i1 @llvm.SI.loop(i64) - - declare void @llvm.SI.end.cf(i64) - - attributes #0 = { "target-cpu"="SI" } + attributes #0 = { nounwind } ... --- diff --git a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir index 3277d37d7e4d3..7cef01c9d12d9 100644 --- a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir +++ b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir @@ -1,6 +1,6 @@ # RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s --- | - define void @add_f32_1.0_one_f16_use() #0 { + define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f32.val = load volatile float, float addrspace(1)* undef @@ -11,7 +11,7 @@ ret void } - define void @add_f32_1.0_multi_f16_use() #0 { + define amdgpu_kernel void @add_f32_1.0_multi_f16_use() #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f32.val = load volatile float, float addrspace(1)* undef @@ -22,7 +22,7 @@ ret void } - define void @add_f32_1.0_one_f32_use_one_f16_use () #0 { + define amdgpu_kernel void @add_f32_1.0_one_f32_use_one_f16_use () #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f32.val = load volatile float, float addrspace(1)* undef @@ -33,7 +33,7 @@ ret void } - define void @add_f32_1.0_one_f32_use_multi_f16_use () #0 { + define amdgpu_kernel void @add_f32_1.0_one_f32_use_multi_f16_use () #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f32.val = load volatile float, float addrspace(1)* undef @@ -46,7 +46,7 @@ ret void } - define void @add_i32_1_multi_f16_use() #0 { + define amdgpu_kernel void @add_i32_1_multi_f16_use() #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f16.add0 = fadd half %f16.val0, 0xH0001 @@ -56,7 +56,7 @@ ret void } - define void @add_i32_m2_one_f32_use_multi_f16_use () #0 { + define amdgpu_kernel void @add_i32_m2_one_f32_use_multi_f16_use () #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f32.val = load volatile float, float addrspace(1)* undef @@ -69,7 +69,7 @@ ret void } - define void @add_f16_1.0_multi_f32_use() #0 { + define amdgpu_kernel void @add_f16_1.0_multi_f32_use() #0 { %f32.val0 = load volatile float, float addrspace(1)* undef %f32.val1 = load volatile float, float addrspace(1)* undef %f32.val = load volatile float, float addrspace(1)* undef @@ -80,7 +80,7 @@ ret void } - define void @add_f16_1.0_other_high_bits_multi_f16_use() #0 { + define amdgpu_kernel void @add_f16_1.0_other_high_bits_multi_f16_use() #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f32.val = load volatile half, half addrspace(1)* undef @@ -91,7 +91,7 @@ ret void } - define void @add_f16_1.0_other_high_bits_use_f16_f32() #0 { + define amdgpu_kernel void @add_f16_1.0_other_high_bits_use_f16_f32() #0 { %f16.val0 = load volatile half, half addrspace(1)* undef %f16.val1 = load volatile half, half addrspace(1)* undef %f32.val = load volatile half, half addrspace(1)* undef diff --git a/test/CodeGen/MIR/AMDGPU/intrinsics.mir b/test/CodeGen/MIR/AMDGPU/intrinsics.mir index f43266eacbf03..cb6e6190990b0 100644 --- a/test/CodeGen/MIR/AMDGPU/intrinsics.mir +++ b/test/CodeGen/MIR/AMDGPU/intrinsics.mir @@ -2,18 +2,18 @@ --- | - define void @use_intrin() { + define amdgpu_kernel void @use_intrin() { ret void } ... --- # Completely invalid code, but it checks that intrinsics round-trip properly. -# CHECK: %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32) +# CHECK: %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe) name: use_intrin registers: - { id: 0, class: _ } body: | bb.0: - %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32) + %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe.i32) ... diff --git a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir index d73503223aa8e..8cffc86373a35 100644 --- a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir +++ b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -mcpu=SI -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @@ -6,7 +6,7 @@ @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 - define void @float(float addrspace(1)* %out, i32 %index) #0 { + define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 { entry: %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index %1 = load float, float addrspace(2)* %0 @@ -14,21 +14,7 @@ ret void } - declare { i1, i64 } @llvm.SI.if(i1) - - declare { i1, i64 } @llvm.SI.else(i64) - - declare i64 @llvm.SI.break(i64) - - declare i64 @llvm.SI.if.break(i1, i64) - - declare i64 @llvm.SI.else.break(i64, i64) - - declare i1 @llvm.SI.loop(i64) - - declare void @llvm.SI.end.cf(i64) - - attributes #0 = { "target-cpu"="SI" } + attributes #0 = { nounwind } ... --- diff --git a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir index a4e77f281ea6b..32669de15ea36 100644 --- a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir +++ b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir @@ -7,7 +7,7 @@ @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 - define void @float(float addrspace(1)* %out, i32 %index) #0 { + define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 { entry: %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index %1 = load float, float addrspace(2)* %0 @@ -15,29 +15,14 @@ ret void } - define void @float2(float addrspace(1)* %out, i32 %index) #0 { + define amdgpu_kernel void @float2(float addrspace(1)* %out, i32 %index) #0 { entry: %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index %1 = load float, float addrspace(2)* %0 store float %1, float addrspace(1)* %out ret void } - - declare { i1, i64 } @llvm.SI.if(i1) - - declare { i1, i64 } @llvm.SI.else(i64) - - declare i64 @llvm.SI.break(i64) - - declare i64 @llvm.SI.if.break(i1, i64) - - declare i64 @llvm.SI.else.break(i64, i64) - - declare i1 @llvm.SI.loop(i64) - - declare void @llvm.SI.end.cf(i64) - - attributes #0 = { "target-cpu"="SI" } + attributes #0 = { nounwind } ... --- diff --git a/test/CodeGen/MIR/Generic/llvmIR.mir b/test/CodeGen/MIR/Generic/llvmIR.mir index 432b18ff939d7..5c0e60e916f06 100644 --- a/test/CodeGen/MIR/Generic/llvmIR.mir +++ b/test/CodeGen/MIR/Generic/llvmIR.mir @@ -28,10 +28,8 @@ IfUnequal: ret i32 0 } - + ... --- name: foo -body: | - bb.0: ... diff --git a/test/CodeGen/MIR/Generic/llvmIRMissing.mir b/test/CodeGen/MIR/Generic/llvmIRMissing.mir index 9f361e8d3fe47..419f60be80619 100644 --- a/test/CodeGen/MIR/Generic/llvmIRMissing.mir +++ b/test/CodeGen/MIR/Generic/llvmIRMissing.mir @@ -1,9 +1,7 @@ -# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser accepts files without the LLVM IR. --- # CHECK: name: foo name: foo -body: | - bb.0: ... diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir index a5737c2c15269..cf095537bebdc 100644 --- a/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir +++ b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser preserves unnamed LLVM IR block # references. diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir b/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir deleted file mode 100644 index 1896371db36a7..0000000000000 --- a/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir +++ /dev/null @@ -1,15 +0,0 @@ -# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s -# This test ensures that the MIR parser reports an error when it encounters a -# machine function with an empty body. - ---- | - - define i32 @foo() { - ret i32 0 - } - -... ---- -# CHECK: machine function 'foo' requires at least one machine basic block in its body -name: foo -... diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-body.mir b/test/CodeGen/MIR/Generic/machine-function-missing-body.mir new file mode 100644 index 0000000000000..0fd970c3af7cc --- /dev/null +++ b/test/CodeGen/MIR/Generic/machine-function-missing-body.mir @@ -0,0 +1,15 @@ +# RUN: llc -run-pass none -o - %s | FileCheck %s +# This test ensures that the MIR parser accepts files with llvm IR but +# no machine function body. + +--- | + ; CHECK: define i32 @foo() + define i32 @foo() { + ret i32 0 + } + +... +--- +# CHECK: name: foo +name: foo +... diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-function.mir b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir index c547bb25d7532..b218afd72ea36 100644 --- a/test/CodeGen/MIR/Generic/machine-function-missing-function.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir @@ -12,12 +12,8 @@ ... --- name: foo -body: | - bb.0: ... --- # CHECK: function 'faa' isn't defined in the provided LLVM IR name: faa -body: | - bb.0: ... diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-name.mir b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir index 30f0e51b3b663..bc279a6ecfdc7 100644 --- a/test/CodeGen/MIR/Generic/machine-function-missing-name.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir @@ -16,11 +16,7 @@ --- # CHECK: [[@LINE+1]]:1: missing required key 'name' nme: foo -body: | - bb.0: ... --- name: bar -body: | - bb.0: ... diff --git a/test/CodeGen/MIR/Generic/machine-function.mir b/test/CodeGen/MIR/Generic/machine-function.mir index f9001cca4c26b..9c19b980e675f 100644 --- a/test/CodeGen/MIR/Generic/machine-function.mir +++ b/test/CodeGen/MIR/Generic/machine-function.mir @@ -18,7 +18,7 @@ define i32 @func2() { ret i32 0 } - + ... --- # CHECK: name: foo @@ -26,8 +26,6 @@ # CHECK-NEXT: exposesReturnsTwice: false # CHECK: ... name: foo -body: | - bb.0: ... --- # CHECK: name: bar @@ -35,8 +33,6 @@ body: | # CHECK-NEXT: exposesReturnsTwice: false # CHECK: ... name: bar -body: | - bb.0: ... --- # CHECK: name: func @@ -45,8 +41,6 @@ body: | # CHECK: ... name: func alignment: 8 -body: | - bb.0: ... --- # CHECK: name: func2 @@ -56,6 +50,4 @@ body: | name: func2 alignment: 16 exposesReturnsTwice: true -body: | - bb.0: ... diff --git a/test/CodeGen/MIR/Generic/register-info.mir b/test/CodeGen/MIR/Generic/register-info.mir index af3f44f9abcc4..84a6125abe883 100644 --- a/test/CodeGen/MIR/Generic/register-info.mir +++ b/test/CodeGen/MIR/Generic/register-info.mir @@ -20,8 +20,6 @@ # CHECK: tracksRegLiveness: false # CHECK: ... name: foo -body: | - bb.0: ... --- # CHECK: name: bar @@ -29,6 +27,4 @@ body: | # CHECK: ... name: bar tracksRegLiveness: true -body: | - bb.0: ... diff --git a/test/CodeGen/MIR/Generic/runPass.mir b/test/CodeGen/MIR/Generic/runPass.mir index bf37bdd1836b9..eeef9d526510d 100644 --- a/test/CodeGen/MIR/Generic/runPass.mir +++ b/test/CodeGen/MIR/Generic/runPass.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s +# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s | FileCheck %s # Check that passes are initialized correctly, so that it's possible to # use -run-pass. diff --git a/test/CodeGen/MIR/X86/dynamic-regmask.ll b/test/CodeGen/MIR/X86/dynamic-regmask.ll new file mode 100644 index 0000000000000..df58f4be79d75 --- /dev/null +++ b/test/CodeGen/MIR/X86/dynamic-regmask.ll @@ -0,0 +1,30 @@ +; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir
+; RUN: FileCheck %s < %t.mir
+; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink
+; Check that callee saved registers are printed in a format that can then be parsed.
+
+declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)
+
+define i32 @caller(i32 %a0) nounwind {
+ %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
+ %b2 = add i32 %b1, %a0
+ ret i32 %b2
+}
+; CHECK: name: caller
+; CHECK: CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%bpl,%bx,%ebp,%ebx,%esp,%rbp,%rbx,%rsp,%sp,%spl,%r10,%r11,%r12,%r13,%r14,%r15,%xmm8,%xmm9,%xmm10,%xmm11,%xmm12,%xmm13,%xmm14,%xmm15,%r10b,%r11b,%r12b,%r13b,%r14b,%r15b,%r10d,%r11d,%r12d,%r13d,%r14d,%r15d,%r10w,%r11w,%r12w,%r13w,%r14w,%r15w)
+; CHECK: RET 0, %eax
+
+define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
+ %b1 = mul i32 7, %e0
+ %b2 = udiv i32 5, %e0
+ %b3 = mul i32 7, %d0
+ %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
+ %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
+ %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
+ ret {i32, i32, i32} %b6
+}
+; CHECK: name: test_callee
+; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12',
+; CHECK: '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10',
+; CHECK: '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ]
+; CHECK: RET 0, %eax, %ecx, %edx
diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir index 5e7dde26769b2..9847d027ee023 100644 --- a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir +++ b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s 2>&1 | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir index cfa03247e31f8..57e11d39723a1 100644 --- a/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir +++ b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir @@ -17,7 +17,7 @@ liveins: body: | bb.0.entry: liveins: %rdi - ; CHECK: [[@LINE+1]]:53: expected the size integer literal after memory operation + ; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size integer literal %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a) RETQ %eax ... diff --git a/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir b/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir new file mode 100644 index 0000000000000..10a9f2d7ceb13 --- /dev/null +++ b/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir @@ -0,0 +1,13 @@ +# RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s +# This test ensures that an error is reported for specifying the register class +# of a physical register. +--- | + define void @t() { ret void } +... +--- +name: t +body: | + bb.0: + ; CHECK: [[@LINE+1]]:10: register class specification expects a virtual register + %eax : gr32 = COPY %rdx +... diff --git a/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir b/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir new file mode 100644 index 0000000000000..4be7fb38335e7 --- /dev/null +++ b/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir @@ -0,0 +1,14 @@ +# RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s +# This test ensures that an error is reported for specifying the register class +# of a physical register. +--- | + define void @t() { ret void } +... +--- +name: t +body: | + bb.0: + %0 : gr32 = COPY %rdx + ; CHECK: [[@LINE+1]]:24: conflicting register classes, previously: GR32 + NOOP implicit %0 : gr32_abcd +... diff --git a/test/CodeGen/MIR/X86/register-operand-class.mir b/test/CodeGen/MIR/X86/register-operand-class.mir new file mode 100644 index 0000000000000..63019daad7a18 --- /dev/null +++ b/test/CodeGen/MIR/X86/register-operand-class.mir @@ -0,0 +1,27 @@ +# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s +# Test various aspects of register class specification on machine operands. +--- | + define void @func() { ret void } +... +--- +# CHECK-LABEL: name: func +# CHECK: registers: +# CHECK: - { id: 0, class: gr32 } +# CHECK: - { id: 1, class: gr64 } +# CHECK: - { id: 2, class: gr32 } +# CHECK: - { id: 3, class: gr16 } +# CHECK: - { id: 4, class: _ } +name: func +body: | + bb.0: + %0 : gr32 = COPY %rax + %1.sub_32bit : gr64 = COPY %eax + %rdx = COPY %1 + %2 = COPY %ecx + %ecx = COPY %2 : gr32 + + %3 : gr16 = COPY %bx + %bx = COPY %3 : gr16 + + %4 : _(s32) = COPY %edx +... diff --git a/test/CodeGen/MIR/X86/used-physical-register-info.mir b/test/CodeGen/MIR/X86/used-physical-register-info.mir deleted file mode 100644 index 9edc4113b2791..0000000000000 --- a/test/CodeGen/MIR/X86/used-physical-register-info.mir +++ /dev/null @@ -1,109 +0,0 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s -# This test ensures that the MIR parser parses the callee saved register mask -# correctly and that the MIR parser can infer it as well. - ---- | - - define i32 @compute(i32 %a) #0 { - body: - %c = mul i32 %a, 11 - ret i32 %c - } - - define i32 @foo(i32 %a) #0 { - entry: - %b = call i32 @compute(i32 %a) - ret i32 %b - } - - define i32 @bar(i32 %a) #0 { - entry: - %b = call i32 @compute(i32 %a) - ret i32 %b - } - - define i32 @empty(i32 %a) #0 { - entry: - %b = call i32 @compute(i32 %a) - ret i32 %b - } - - attributes #0 = { "no-frame-pointer-elim"="false" } - -... ---- -# CHECK: name: compute -# CHECK: liveins: -# CHECK-NEXT: - { reg: '%edi' } -# CHECK-NEXT: frameInfo: -name: compute -liveins: - - { reg: '%edi' } -frameInfo: - stackSize: 8 -body: | - bb.0.body: - liveins: %edi - - %eax = IMUL32rri8 %edi, 11, implicit-def %eflags - RETQ %eax -... ---- -name: foo -liveins: - - { reg: '%edi' } -# CHECK: name: foo -# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', -# CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', -# CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', -# CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] -calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', - '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', - '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', - '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] -body: | - bb.0.entry: - liveins: %edi - - PUSH64r %rax, implicit-def %rsp, implicit %rsp - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - %rdx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax -... ---- -name: bar -liveins: - - { reg: '%edi' } -# Verify that the callee saved register can be inferred from register mask -# machine operands: -# CHECK: name: bar -# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', -# CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15', -# CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d', -# CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ] -body: | - bb.0.entry: - liveins: %edi - - PUSH64r %rax, implicit-def %rsp, implicit %rsp - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - %rdx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax -... ---- -name: empty -liveins: - - { reg: '%edi' } -# Verify that the callee saved register can be empty. -# CHECK: name: empty -# CHECK: calleeSavedRegisters: [ ] -calleeSavedRegisters: [ ] -body: | - bb.0.entry: - liveins: %edi - - PUSH64r %rax, implicit-def %rsp, implicit %rsp - CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax - %rdx = POP64r implicit-def %rsp, implicit %rsp - RETQ %eax -... |