diff options
Diffstat (limited to 'test/CodeGen/Mips')
42 files changed, 774 insertions, 260 deletions
diff --git a/test/CodeGen/Mips/2008-07-05-ByVal.ll b/test/CodeGen/Mips/2008-07-05-ByVal.ll deleted file mode 100644 index a1f05044b6c6c..0000000000000 --- a/test/CodeGen/Mips/2008-07-05-ByVal.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc < %s -march=mips | grep {lw.*(\$4)} | count 2 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" - %struct.byval0 = type { i32, i32 } - -define i64 @test0(%struct.byval0* byval %b, i64 %sum) nounwind { -entry: - getelementptr %struct.byval0* %b, i32 0, i32 0 ; <i32*>:0 [#uses=1] - load i32* %0, align 4 ; <i32>:1 [#uses=1] - getelementptr %struct.byval0* %b, i32 0, i32 1 ; <i32*>:2 [#uses=1] - load i32* %2, align 4 ; <i32>:3 [#uses=1] - add i32 %3, %1 ; <i32>:4 [#uses=1] - sext i32 %4 to i64 ; <i64>:5 [#uses=1] - add i64 %5, %sum ; <i64>:6 [#uses=1] - ret i64 %6 -} - diff --git a/test/CodeGen/Mips/2008-07-06-fadd64.ll b/test/CodeGen/Mips/2008-07-06-fadd64.ll index ecd8521027afb..ff8ed4d944037 100644 --- a/test/CodeGen/Mips/2008-07-06-fadd64.ll +++ b/test/CodeGen/Mips/2008-07-06-fadd64.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=mips | grep __adddf3 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s define double @dofloat(double %a, double %b) nounwind { entry: +; CHECK: __adddf3 fadd double %a, %b ; <double>:0 [#uses=1] ret double %0 } diff --git a/test/CodeGen/Mips/2008-07-07-FPExtend.ll b/test/CodeGen/Mips/2008-07-07-FPExtend.ll index 681788e98196f..29c8e8446e3d2 100644 --- a/test/CodeGen/Mips/2008-07-07-FPExtend.ll +++ b/test/CodeGen/Mips/2008-07-07-FPExtend.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=mips | grep __extendsfdf2 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s define double @dofloat(float %a) nounwind { entry: +; CHECK: __extendsfdf2 fpext float %a to double ; <double>:0 [#uses=1] ret double %0 } diff --git a/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll b/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll index b8b4c5c610de9..9a6bbdfb22ff5 100644 --- a/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll +++ b/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll @@ -1,32 +1,33 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep __floatsidf %t | count 1 -; RUN: grep __floatunsidf %t | count 1 -; RUN: grep __fixdfsi %t | count 1 -; RUN: grep __fixunsdfsi %t | count 1 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s define double @int2fp(i32 %a) nounwind { entry: +; CHECK: int2fp +; CHECK: __floatsidf sitofp i32 %a to double ; <double>:0 [#uses=1] ret double %0 } define double @uint2double(i32 %a) nounwind { entry: +; CHECK: uint2double +; CHECK: __floatunsidf uitofp i32 %a to double ; <double>:0 [#uses=1] ret double %0 } define i32 @double2int(double %a) nounwind { entry: +; CHECK: double2int +; CHECK: __fixdfsi fptosi double %a to i32 ; <i32>:0 [#uses=1] ret i32 %0 } define i32 @double2uint(double %a) nounwind { entry: +; CHECK: double2uint +; CHECK: __fixunsdfsi fptoui double %a to i32 ; <i32>:0 [#uses=1] ret i32 %0 } diff --git a/test/CodeGen/Mips/2008-07-15-InternalConstant.ll b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll index c3db6387aff30..29a7b5c3761a1 100644 --- a/test/CodeGen/Mips/2008-07-15-InternalConstant.ll +++ b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll @@ -1,22 +1,23 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep {rodata.str1.4,"aMS",@progbits} %t | count 1 -; RUN: grep {r.data,} %t | count 1 -; RUN: grep {\%hi} %t | count 2 -; RUN: grep {\%lo} %t | count 2 -; RUN: not grep {gp_rel} %t +; RUN: llc -march=mips -relocation-model=static < %s | FileCheck %s -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" @.str = internal unnamed_addr constant [10 x i8] c"AAAAAAAAA\00" -@i0 = internal unnamed_addr constant [5 x i32] [ i32 0, i32 1, i32 2, i32 3, i32 4 ] +@i0 = internal unnamed_addr constant [5 x i32] [ i32 0, i32 1, i32 2, i32 3, i32 4 ] define i8* @foo() nounwind { entry: +; CHECK: foo +; CHECK: %hi(.str) +; CHECK: %lo(.str) ret i8* getelementptr ([10 x i8]* @.str, i32 0, i32 0) } define i32* @bar() nounwind { entry: +; CHECK: bar +; CHECK: %hi(i0) +; CHECK: %lo(i0) ret i32* getelementptr ([5 x i32]* @i0, i32 0, i32 0) } +; CHECK: rodata.str1.4,"aMS",@progbits +; CHECK: rodata,"a",@progbits diff --git a/test/CodeGen/Mips/2008-07-15-SmallSection.ll b/test/CodeGen/Mips/2008-07-15-SmallSection.ll index 4795e478f761f..cbc3ecf5edc87 100644 --- a/test/CodeGen/Mips/2008-07-15-SmallSection.ll +++ b/test/CodeGen/Mips/2008-07-15-SmallSection.ll @@ -1,13 +1,16 @@ -; RUN: llc < %s -mips-ssection-threshold=8 -march=mips -o %t0 -; RUN: llc < %s -mips-ssection-threshold=0 -march=mips -o %t1 -; RUN: grep {sdata} %t0 | count 1 -; RUN: grep {sbss} %t0 | count 1 -; RUN: grep {gp_rel} %t0 | count 2 -; RUN: not grep {sdata} %t1 -; RUN: not grep {sbss} %t1 -; RUN: not grep {gp_rel} %t1 -; RUN: grep {\%hi} %t1 | count 2 -; RUN: grep {\%lo} %t1 | count 3 +; DISABLED: llc < %s -mips-ssection-threshold=8 -march=mips -o %t0 +; DISABLED: llc < %s -mips-ssection-threshold=0 -march=mips -o %t1 +; DISABLED: grep {sdata} %t0 | count 1 +; DISABLED: grep {sbss} %t0 | count 1 +; DISABLED: grep {gp_rel} %t0 | count 2 +; DISABLED: not grep {sdata} %t1 +; DISABLED: not grep {sbss} %t1 +; DISABLED: not grep {gp_rel} %t1 +; DISABLED: grep {\%hi} %t1 | count 2 +; DISABLED: grep {\%lo} %t1 | count 3 +; RUN: false +; XFAIL: * + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll index 855194aa077e5..e0c745f34917e 100644 --- a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll +++ b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep seh %t | count 1 -; RUN: grep seb %t | count 1 +; DISABLED: llc < %s -march=mips -o %t +; DISABLED: grep seh %t | count 1 +; DISABLED: grep seb %t | count 1 +; RUN: false +; XFAIL: * target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2008-08-03-fabs64.ll b/test/CodeGen/Mips/2008-08-03-fabs64.ll index 0fc45f7d1b05f..2b1713c39f726 100644 --- a/test/CodeGen/Mips/2008-08-03-fabs64.ll +++ b/test/CodeGen/Mips/2008-08-03-fabs64.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=mips -o %t -; RUN: grep {lui.*32767} %t | count 1 -; RUN: grep {ori.*65535} %t | count 1 +; DISABLED: llc < %s -march=mips -o %t +; DISABLED: grep {lui.*32767} %t | count 1 +; DISABLED: grep {ori.*65535} %t | count 1 +; RUN: false +; XFAIL: * target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2008-08-07-FPRound.ll b/test/CodeGen/Mips/2008-08-07-FPRound.ll index 67f86d7411417..4fa43b6833bde 100644 --- a/test/CodeGen/Mips/2008-08-07-FPRound.ll +++ b/test/CodeGen/Mips/2008-08-07-FPRound.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=mips | grep __truncdfsf2 | count 1 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s define float @round2float(double %a) nounwind { entry: +; CHECK: __truncdfsf2 fptrunc double %a to float ; <float>:0 [#uses=1] ret float %0 } diff --git a/test/CodeGen/Mips/2008-08-08-bswap.ll b/test/CodeGen/Mips/2008-08-08-bswap.ll index 83289d97cfd75..596da243057b1 100644 --- a/test/CodeGen/Mips/2008-08-08-bswap.ll +++ b/test/CodeGen/Mips/2008-08-08-bswap.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s | grep wsbw | count 1 +; DISABLED: llc < %s | grep wsbw | count 1 +; RUN: false +; XFAIL: * + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "psp" diff --git a/test/CodeGen/Mips/2010-07-20-Select.ll b/test/CodeGen/Mips/2010-07-20-Select.ll deleted file mode 100644 index e5e2c54737707..0000000000000 --- a/test/CodeGen/Mips/2010-07-20-Select.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s -; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s -; Fix PR7473 - -define i32 @main() nounwind readnone { -entry: - %a = alloca i32, align 4 ; <i32*> [#uses=2] - %c = alloca i32, align 4 ; <i32*> [#uses=2] - volatile store i32 1, i32* %a, align 4 - volatile store i32 0, i32* %c, align 4 - %0 = volatile load i32* %a, align 4 ; <i32> [#uses=1] - %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1] -; CHECK: addiu $[[R1:[0-9]+]], $zero, 0 - %iftmp.0.0 = select i1 %1, i32 3, i32 0 ; <i32> [#uses=1] - %2 = volatile load i32* %c, align 4 ; <i32> [#uses=1] - %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1] -; CHECK: addiu $[[R1]], $zero, 3 -; CHECK: addu $2, ${{.}}, $[[R1]] - %iftmp.2.0 = select i1 %3, i32 0, i32 5 ; <i32> [#uses=1] - %4 = add nsw i32 %iftmp.2.0, %iftmp.0.0 ; <i32> [#uses=1] - ret i32 %4 -} diff --git a/test/CodeGen/Mips/2010-11-09-CountLeading.ll b/test/CodeGen/Mips/2010-11-09-CountLeading.ll index d592fef331af9..c592b311782fc 100644 --- a/test/CodeGen/Mips/2010-11-09-CountLeading.ll +++ b/test/CodeGen/Mips/2010-11-09-CountLeading.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s ; CHECK: clz $2, $4 define i32 @t1(i32 %X) nounwind readnone { diff --git a/test/CodeGen/Mips/2010-11-09-Mul.ll b/test/CodeGen/Mips/2010-11-09-Mul.ll index 65a10b5836cc8..dcade3c671db1 100644 --- a/test/CodeGen/Mips/2010-11-09-Mul.ll +++ b/test/CodeGen/Mips/2010-11-09-Mul.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s ; CHECK: mul $2, $5, $4 define i32 @mul1(i32 %a, i32 %b) nounwind readnone { diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll index fb4f56cb5720c..15c73e2253008 100644 --- a/test/CodeGen/Mips/alloca.ll +++ b/test/CodeGen/Mips/alloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mipsel < %s | FileCheck %s define i32 @twoalloca(i32 %size) nounwind { entry: diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index 2d5555bd2cb97..a4763b130d460 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -1,30 +1,16 @@ -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s - - -declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind -declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* nocapture, i32) nounwind -declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind -declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind - -declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind -declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind - +; RUN: llc -march=mipsel < %s | FileCheck %s @x = common global i32 0, align 4 define i32 @AtomicLoadAdd32(i32 %incr) nounwind { entry: - %0 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* @x, i32 %incr) + %0 = atomicrmw add i32* @x, i32 %incr monotonic ret i32 %0 ; CHECK: AtomicLoadAdd32: ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) -; CHECK: or $2, $zero, $[[R1]] ; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 ; CHECK: sc $[[R2]], 0($[[R0]]) ; CHECK: beq $[[R2]], $zero, $[[BB0]] @@ -32,51 +18,49 @@ entry: define i32 @AtomicLoadNand32(i32 %incr) nounwind { entry: - %0 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* @x, i32 %incr) + %0 = atomicrmw nand i32* @x, i32 %incr monotonic ret i32 %0 ; CHECK: AtomicLoadNand32: ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) -; CHECK: or $2, $zero, $[[R1]] -; CHECK: and $[[R1]], $[[R1]], $4 -; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R1]] +; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4 +; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R3]] ; CHECK: sc $[[R2]], 0($[[R0]]) ; CHECK: beq $[[R2]], $zero, $[[BB0]] } -define i32 @AtomicSwap32(i32 %oldval) nounwind { +define i32 @AtomicSwap32(i32 %newval) nounwind { entry: - %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %oldval) + %newval.addr = alloca i32, align 4 + store i32 %newval, i32* %newval.addr, align 4 + %tmp = load i32* %newval.addr, align 4 + %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic ret i32 %0 ; CHECK: AtomicSwap32: ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) -; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: -; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) -; CHECK: or $2, $zero, $[[R1]] -; CHECK: lw $[[R2:[0-9]+]], [[OFFSET]]($sp) -; CHECK: or $[[R3:[0-9]+]], $zero, $[[R2]] -; CHECK: sc $[[R3]], 0($[[R0]]) -; CHECK: beq $[[R3]], $zero, $[[BB0]] +; CHECK: ll ${{[0-9]+}}, 0($[[R0]]) +; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] } define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind { entry: - %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %newval) + %newval.addr = alloca i32, align 4 + store i32 %newval, i32* %newval.addr, align 4 + %tmp = load i32* %newval.addr, align 4 + %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic ret i32 %0 ; CHECK: AtomicCmpSwap32: ; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) -; CHECK: sw $5, [[OFFSET:[0-9]+]]($sp) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $2, 0($[[R0]]) ; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] -; CHECK: lw $[[R1:[0-9]+]], [[OFFSET]]($sp) -; CHECK: or $[[R2:[0-9]+]], $zero, $[[R1]] -; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]]) ; CHECK: beq $[[R2]], $zero, $[[BB0]] ; CHECK: $[[BB1]]: } @@ -87,7 +71,7 @@ entry: define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { entry: - %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @y, i8 %incr) + %0 = atomicrmw add i8* @y, i8 %incr monotonic ret i8 %0 ; CHECK: AtomicLoadAdd8: @@ -97,10 +81,9 @@ entry: ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -112,14 +95,14 @@ entry: ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { entry: - %0 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @y, i8 %incr) + %0 = atomicrmw sub i8* @y, i8 %incr monotonic ret i8 %0 ; CHECK: AtomicLoadSub8: @@ -129,15 +112,13 @@ entry: ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: subu $[[R18:[0-9]+]], $zero, $4 -; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) -; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] @@ -145,14 +126,14 @@ entry: ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { entry: - %0 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @y, i8 %incr) + %0 = atomicrmw nand i8* @y, i8 %incr monotonic ret i8 %0 ; CHECK: AtomicLoadNand8: @@ -162,10 +143,9 @@ entry: ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) @@ -178,14 +158,14 @@ entry: ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } -define signext i8 @AtomicSwap8(i8 signext %oldval) nounwind { +define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { entry: - %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %oldval) + %0 = atomicrmw xchg i8* @y, i8 %newval monotonic ret i8 %0 ; CHECK: AtomicSwap8: @@ -195,31 +175,26 @@ entry: ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] -; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] -; CHECK: sw $[[R9]], [[OFFSET:[0-9]+]]($sp) +; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) -; CHECK: lw $[[R18:[0-9]+]], [[OFFSET]]($sp) -; CHECK: or $[[R11:[0-9]+]], $zero, $[[R18]] -; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] -; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]] ; CHECK: sc $[[R14]], 0($[[R2]]) ; CHECK: beq $[[R14]], $zero, $[[BB0]] ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] -; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind { entry: - %0 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @y, i8 %oldval, i8 %newval) + %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic ret i8 %0 ; CHECK: AtomicCmpSwap8: @@ -229,12 +204,12 @@ entry: ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 ; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255 -; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] ; CHECK: andi $[[R8:[0-9]+]], $4, 255 -; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]] ; CHECK: andi $[[R10:[0-9]+]], $5, 255 -; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]] +; CHECK: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]] ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]]) @@ -247,7 +222,23 @@ entry: ; CHECK: beq $[[R15]], $zero, $[[BB0]] ; CHECK: $[[BB1]]: -; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]] +; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]] ; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 ; CHECK: sra $2, $[[R17]], 24 } + +@countsint = common global i32 0, align 4 + +define i32 @CheckSync(i32 %v) nounwind noinline { +entry: + %0 = atomicrmw add i32* @countsint, i32 %v seq_cst + ret i32 %0 + +; CHECK: CheckSync: +; CHECK: sync 0 +; CHECK: ll +; CHECK: sc +; CHECK: beq +; CHECK: sync 0 +} + diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll new file mode 100644 index 0000000000000..b266ce61a8d16 --- /dev/null +++ b/test/CodeGen/Mips/brdelayslot.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mipsel -enable-mips-delay-filler < %s | FileCheck %s + +define void @foo1() nounwind { +entry: +; CHECK: jalr +; CHECK-NOT: nop +; CHECK: jr +; CHECK-NOT: nop +; CHECK: .end + + tail call void @foo2(i32 3) nounwind + ret void +} + +declare void @foo2(i32) diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index ec3796190cc0a..7851ba90d6b1d 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s -; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 diff --git a/test/CodeGen/Mips/constantfp0.ll b/test/CodeGen/Mips/constantfp0.ll new file mode 100644 index 0000000000000..191f31d013191 --- /dev/null +++ b/test/CodeGen/Mips/constantfp0.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=mips < %s | FileCheck %s + +define i32 @branch(double %d) nounwind readnone { +entry: +; CHECK: mtc1 $zero, $f[[R0:[0-9]+]] +; CHECK: c.eq.d $f{{[0-9]+}}, $f[[R0]] + + %tobool = fcmp une double %d, 0.000000e+00 + %. = zext i1 %tobool to i32 + ret i32 %. +} diff --git a/test/CodeGen/Mips/cprestore.ll b/test/CodeGen/Mips/cprestore.ll new file mode 100644 index 0000000000000..391f5c714dbba --- /dev/null +++ b/test/CodeGen/Mips/cprestore.ll @@ -0,0 +1,20 @@ +; DISABLED: llc -march=mipsel < %s | FileCheck %s +; RUN: false + +; byval is currently unsupported. +; XFAIL: * + +; CHECK: .set macro +; CHECK-NEXT: .cprestore +; CHECK-NEXT: .set nomacro + +%struct.S = type { [16384 x i32] } + +define void @foo2() nounwind { +entry: + %s = alloca %struct.S, align 4 + call void @foo1(%struct.S* byval %s) + ret void +} + +declare void @foo1(%struct.S* byval) diff --git a/test/CodeGen/Mips/double2int.ll b/test/CodeGen/Mips/double2int.ll index 3d033e1d10086..445ccb334a8ff 100644 --- a/test/CodeGen/Mips/double2int.ll +++ b/test/CodeGen/Mips/double2int.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s define i32 @f1(double %d) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index 765b7783e5d95..9cd34131a1313 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL -; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB +; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL +; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB @g1 = global double 0.000000e+00, align 8 @_ZTId = external constant i8* @@ -32,10 +32,12 @@ lpad: ; preds = %entry ; CHECK-EL: lw $gp ; CHECK-EL: beq $5 - %exn = tail call i8* @llvm.eh.exception() nounwind - %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTId to i8*)) nounwind + %exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 + catch i8* bitcast (i8** @_ZTId to i8*) + %exn = extractvalue { i8*, i32 } %exn.val, 0 + %sel = extractvalue { i8*, i32 } %exn.val, 1 %1 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTId to i8*)) nounwind - %2 = icmp eq i32 %eh.selector, %1 + %2 = icmp eq i32 %sel, %1 br i1 %2, label %catch, label %eh.resume catch: ; preds = %lpad @@ -48,8 +50,7 @@ catch: ; preds = %lpad ret void eh.resume: ; preds = %lpad - tail call void @llvm.eh.resume(i8* %exn, i32 %eh.selector) noreturn - unreachable + resume { i8*, i32 } %exn.val unreachable: ; preds = %entry unreachable diff --git a/test/CodeGen/Mips/extins.ll b/test/CodeGen/Mips/extins.ll new file mode 100644 index 0000000000000..69f53e503f6d3 --- /dev/null +++ b/test/CodeGen/Mips/extins.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone { +entry: +; CHECK: ext ${{[0-9]+}}, $4, 5, 9 + %shr = lshr i32 %s, 5 + %and = and i32 %shr, 511 + ret i32 %and +} + +define void @ins2_5_9(i32 %s, i32* nocapture %d) nounwind { +entry: +; CHECK: ins ${{[0-9]+}}, $4, 5, 9 + %and = shl i32 %s, 5 + %shl = and i32 %and, 16352 + %tmp3 = load i32* %d, align 4 + %and5 = and i32 %tmp3, -16353 + %or = or i32 %and5, %shl + store i32 %or, i32* %d, align 4 + ret void +} diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index 14c6507cc95b5..79f956d719c55 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL -; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB +; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL +; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB define double @func0(double %d0, double %d1) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/fpcmp.ll b/test/CodeGen/Mips/fpcmp.ll index c89ffe67f1b90..86545e347c14f 100644 --- a/test/CodeGen/Mips/fpcmp.ll +++ b/test/CodeGen/Mips/fpcmp.ll @@ -1,18 +1,13 @@ -; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2 -; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1 +; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32 @g1 = external global i32 define i32 @f(float %f0, float %f1) nounwind { entry: -; CHECK-MIPS32R2: c.olt.s -; CHECK-MIPS32R2: movt -; CHECK-MIPS32R2: c.olt.s -; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.olt.s -; CHECK-MIPS1: bc1t -; CHECK-MIPS1: c.olt.s -; CHECK-MIPS1: bc1t +; CHECK-MIPS32: c.olt.s +; CHECK-MIPS32: movt +; CHECK-MIPS32: c.olt.s +; CHECK-MIPS32: movt %cmp = fcmp olt float %f0, %f1 %conv = zext i1 %cmp to i32 %tmp2 = load i32* @g1, align 4 diff --git a/test/CodeGen/Mips/frame-address.ll b/test/CodeGen/Mips/frame-address.ll index c48ce7e73d4d4..9df1808fde534 100644 --- a/test/CodeGen/Mips/frame-address.ll +++ b/test/CodeGen/Mips/frame-address.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s +; RUN: llc -march=mipsel < %s | FileCheck %s declare i8* @llvm.frameaddress(i32) nounwind readnone diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index 560f2e9b08740..87cf2a63c5b56 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index c5658923dcc68..b5db58a57e381 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mipsel < %s | FileCheck %s @g1 = external global i32 diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll index c2a4e5cfc24fb..434b3868968ad 100644 --- a/test/CodeGen/Mips/internalfunc.ll +++ b/test/CodeGen/Mips/internalfunc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s +; RUN: llc < %s -march=mipsel | FileCheck %s @caller.sf1 = internal unnamed_addr global void (...)* null, align 4 @gf1 = external global void (...)* diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index fcc20f799440f..579a319d5f7a0 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -1,4 +1,8 @@ -; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s +; DISABLED: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s +; RUN: false + +; byval is currently unsupported. +; XFAIL: * %struct.S1 = type { [65536 x i8] } diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll index 4a205b1f3ffb7..0aeabb30e2892 100644 --- a/test/CodeGen/Mips/madd-msub.ll +++ b/test/CodeGen/Mips/madd-msub.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s -; CHECK: madd $5, $4 +; CHECK: madd define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 @@ -11,7 +11,7 @@ entry: ret i64 %add } -; CHECK: maddu $5, $4 +; CHECK: maddu define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = zext i32 %a to i64 @@ -22,7 +22,7 @@ entry: ret i64 %add } -; CHECK: madd $5, $4 +; CHECK: madd define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 @@ -32,7 +32,7 @@ entry: ret i64 %add } -; CHECK: msub $5, $4 +; CHECK: msub define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = sext i32 %c to i64 @@ -43,7 +43,7 @@ entry: ret i64 %sub } -; CHECK: msubu $5, $4 +; CHECK: msubu define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = zext i32 %c to i64 @@ -54,7 +54,7 @@ entry: ret i64 %sub } -; CHECK: msub $5, $4 +; CHECK: msub define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 diff --git a/test/CodeGen/Mips/mips64fpldst.ll b/test/CodeGen/Mips/mips64fpldst.ll new file mode 100644 index 0000000000000..b8f3ca9d79855 --- /dev/null +++ b/test/CodeGen/Mips/mips64fpldst.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32 + +@f0 = common global float 0.000000e+00, align 4 +@d0 = common global double 0.000000e+00, align 8 +@f1 = common global float 0.000000e+00, align 4 +@d1 = common global double 0.000000e+00, align 8 + +define float @funcfl1() nounwind readonly { +entry: +; CHECK-N64: funcfl1 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) +; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: funcfl1 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0) +; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]]) + %0 = load float* @f0, align 4 + ret float %0 +} + +define double @funcfl2() nounwind readonly { +entry: +; CHECK-N64: funcfl2 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) +; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: funcfl2 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0) +; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]]) + %0 = load double* @d0, align 8 + ret double %0 +} + +define void @funcfs1() nounwind { +entry: +; CHECK-N64: funcfs1 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) +; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: funcfs1 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(f0) +; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]]) + %0 = load float* @f1, align 4 + store float %0, float* @f0, align 4 + ret void +} + +define void @funcfs2() nounwind { +entry: +; CHECK-N64: funcfs2 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) +; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: funcfs2 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(d0) +; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]]) + %0 = load double* @d1, align 8 + store double %0, double* @d0, align 8 + ret void +} + diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll new file mode 100644 index 0000000000000..c9812a2769925 --- /dev/null +++ b/test/CodeGen/Mips/mips64instrs.ll @@ -0,0 +1,143 @@ +; RUN: llc -march=mips64el -mcpu=mips64r1 < %s | FileCheck %s + +define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: daddu + %add = add nsw i64 %a1, %a0 + ret i64 %add +} + +define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: dsubu + %sub = sub nsw i64 %a0, %a1 + ret i64 %sub +} + +define i64 @f4(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: and + %and = and i64 %a1, %a0 + ret i64 %and +} + +define i64 @f5(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: or + %or = or i64 %a1, %a0 + ret i64 %or +} + +define i64 @f6(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: xor + %xor = xor i64 %a1, %a0 + ret i64 %xor +} + +define i64 @f7(i64 %a0) nounwind readnone { +entry: +; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20 + %add = add nsw i64 %a0, 20 + ret i64 %add +} + +define i64 @f8(i64 %a0) nounwind readnone { +entry: +; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20 + %sub = add nsw i64 %a0, -20 + ret i64 %sub +} + +define i64 @f9(i64 %a0) nounwind readnone { +entry: +; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20 + %and = and i64 %a0, 20 + ret i64 %and +} + +define i64 @f10(i64 %a0) nounwind readnone { +entry: +; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20 + %or = or i64 %a0, 20 + ret i64 %or +} + +define i64 @f11(i64 %a0) nounwind readnone { +entry: +; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20 + %xor = xor i64 %a0, 20 + ret i64 %xor +} + +define i64 @f12(i64 %a, i64 %b) nounwind readnone { +entry: +; CHECK: mult + %mul = mul nsw i64 %b, %a + ret i64 %mul +} + +define i64 @f13(i64 %a, i64 %b) nounwind readnone { +entry: +; CHECK: mult + %mul = mul i64 %b, %a + ret i64 %mul +} + +define i64 @f14(i64 %a, i64 %b) nounwind readnone { +entry: +; CHECK: ddiv $zero +; CHECK: mflo + %div = sdiv i64 %a, %b + ret i64 %div +} + +define i64 @f15(i64 %a, i64 %b) nounwind readnone { +entry: +; CHECK: ddivu $zero +; CHECK: mflo + %div = udiv i64 %a, %b + ret i64 %div +} + +define i64 @f16(i64 %a, i64 %b) nounwind readnone { +entry: +; CHECK: ddiv $zero +; CHECK: mfhi + %rem = srem i64 %a, %b + ret i64 %rem +} + +define i64 @f17(i64 %a, i64 %b) nounwind readnone { +entry: +; CHECK: ddivu $zero +; CHECK: mfhi + %rem = urem i64 %a, %b + ret i64 %rem +} + +declare i64 @llvm.ctlz.i64(i64) nounwind readnone + +define i64 @f18(i64 %X) nounwind readnone { +entry: +; CHECK: dclz $2, $4 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X) + ret i64 %tmp1 +} + +define i64 @f19(i64 %X) nounwind readnone { +entry: +; CHECK: dclo $2, $4 + %neg = xor i64 %X, -1 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg) + ret i64 %tmp1 +} + +define i64 @f20(i64 %a, i64 %b) nounwind readnone { +entry: +; CHECK: nor + %or = or i64 %b, %a + %neg = xor i64 %or, -1 + ret i64 %neg +} + diff --git a/test/CodeGen/Mips/mips64intldst.ll b/test/CodeGen/Mips/mips64intldst.ll new file mode 100644 index 0000000000000..fdf496b19189a --- /dev/null +++ b/test/CodeGen/Mips/mips64intldst.ll @@ -0,0 +1,157 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n64 | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r1 -mattr=n32 | FileCheck %s -check-prefix=CHECK-N32 + +@c = common global i8 0, align 4 +@s = common global i16 0, align 4 +@i = common global i32 0, align 4 +@l = common global i64 0, align 8 +@uc = common global i8 0, align 4 +@us = common global i16 0, align 4 +@ui = common global i32 0, align 4 +@l1 = common global i64 0, align 8 + +define i64 @func1() nounwind readonly { +entry: +; CHECK-N64: func1 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c) +; CHECK-N64: lb ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: func1 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(c) +; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]]) + %0 = load i8* @c, align 4 + %conv = sext i8 %0 to i64 + ret i64 %conv +} + +define i64 @func2() nounwind readonly { +entry: +; CHECK-N64: func2 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s) +; CHECK-N64: lh ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: func2 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(s) +; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]]) + %0 = load i16* @s, align 4 + %conv = sext i16 %0 to i64 + ret i64 %conv +} + +define i64 @func3() nounwind readonly { +entry: +; CHECK-N64: func3 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i) +; CHECK-N64: lw ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: func3 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(i) +; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]]) + %0 = load i32* @i, align 4 + %conv = sext i32 %0 to i64 + ret i64 %conv +} + +define i64 @func4() nounwind readonly { +entry: +; CHECK-N64: func4 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l) +; CHECK-N64: ld ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: func4 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(l) +; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]]) + %0 = load i64* @l, align 8 + ret i64 %0 +} + +define i64 @ufunc1() nounwind readonly { +entry: +; CHECK-N64: ufunc1 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(uc) +; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: ufunc1 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(uc) +; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]]) + %0 = load i8* @uc, align 4 + %conv = zext i8 %0 to i64 + ret i64 %conv +} + +define i64 @ufunc2() nounwind readonly { +entry: +; CHECK-N64: ufunc2 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(us) +; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: ufunc2 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(us) +; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]]) + %0 = load i16* @us, align 4 + %conv = zext i16 %0 to i64 + ret i64 %conv +} + +define i64 @ufunc3() nounwind readonly { +entry: +; CHECK-N64: ufunc3 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(ui) +; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: ufunc3 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(ui) +; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]]) + %0 = load i32* @ui, align 4 + %conv = zext i32 %0 to i64 + ret i64 %conv +} + +define void @sfunc1() nounwind { +entry: +; CHECK-N64: sfunc1 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c) +; CHECK-N64: sb ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: sfunc1 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(c) +; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]]) + %0 = load i64* @l1, align 8 + %conv = trunc i64 %0 to i8 + store i8 %conv, i8* @c, align 4 + ret void +} + +define void @sfunc2() nounwind { +entry: +; CHECK-N64: sfunc2 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s) +; CHECK-N64: sh ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: sfunc2 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(s) +; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]]) + %0 = load i64* @l1, align 8 + %conv = trunc i64 %0 to i16 + store i16 %conv, i16* @s, align 4 + ret void +} + +define void @sfunc3() nounwind { +entry: +; CHECK-N64: sfunc3 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i) +; CHECK-N64: sw ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: sfunc3 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(i) +; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]]) + %0 = load i64* @l1, align 8 + %conv = trunc i64 %0 to i32 + store i32 %conv, i32* @i, align 4 + ret void +} + +define void @sfunc4() nounwind { +entry: +; CHECK-N64: sfunc4 +; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l) +; CHECK-N64: sd ${{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: sfunc4 +; CHECK-N32: lw $[[R0:[0-9]+]], %got(l) +; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]]) + %0 = load i64* @l1, align 8 + store i64 %0, i64* @l, align 8 + ret void +} + diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll new file mode 100644 index 0000000000000..cc5e508561479 --- /dev/null +++ b/test/CodeGen/Mips/mips64shift.ll @@ -0,0 +1,104 @@ +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s + +define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: dsllv + %shl = shl i64 %a0, %a1 + ret i64 %shl +} + +define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: dsrav + %shr = ashr i64 %a0, %a1 + ret i64 %shr +} + +define i64 @f2(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: dsrlv + %shr = lshr i64 %a0, %a1 + ret i64 %shr +} + +define i64 @f3(i64 %a0) nounwind readnone { +entry: +; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 + %shl = shl i64 %a0, 10 + ret i64 %shl +} + +define i64 @f4(i64 %a0) nounwind readnone { +entry: +; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 + %shr = ashr i64 %a0, 10 + ret i64 %shr +} + +define i64 @f5(i64 %a0) nounwind readnone { +entry: +; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 + %shr = lshr i64 %a0, 10 + ret i64 %shr +} + +define i64 @f6(i64 %a0) nounwind readnone { +entry: +; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8 + %shl = shl i64 %a0, 40 + ret i64 %shl +} + +define i64 @f7(i64 %a0) nounwind readnone { +entry: +; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8 + %shr = ashr i64 %a0, 40 + ret i64 %shr +} + +define i64 @f8(i64 %a0) nounwind readnone { +entry: +; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8 + %shr = lshr i64 %a0, 40 + ret i64 %shr +} + +define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: drotrv + %shr = lshr i64 %a0, %a1 + %sub = sub i64 64, %a1 + %shl = shl i64 %a0, %sub + %or = or i64 %shl, %shr + ret i64 %or +} + +define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { +entry: +; CHECK: drotrv + %shl = shl i64 %a0, %a1 + %sub = sub i64 64, %a1 + %shr = lshr i64 %a0, %sub + %or = or i64 %shr, %shl + ret i64 %or +} + +define i64 @f11(i64 %a0) nounwind readnone { +entry: +; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 + %shr = lshr i64 %a0, 10 + %shl = shl i64 %a0, 54 + %or = or i64 %shr, %shl + ret i64 %or +} + +define i64 @f12(i64 %a0) nounwind readnone { +entry: +; CHECK: drotr32 ${{[0-9]+}}, ${{[0-9]+}}, 22 + %shl = shl i64 %a0, 10 + %shr = lshr i64 %a0, 54 + %or = or i64 %shl, %shr + ret i64 %or +} + + diff --git a/test/CodeGen/Mips/mipslopat.ll b/test/CodeGen/Mips/mipslopat.ll new file mode 100644 index 0000000000000..02798285b4996 --- /dev/null +++ b/test/CodeGen/Mips/mipslopat.ll @@ -0,0 +1,19 @@ +; This test does not check the machine code output. +; RUN: llc -march=mips < %s + +@stat_vol_ptr_int = internal global i32* null, align 4 +@stat_ptr_vol_int = internal global i32* null, align 4 + +define void @simple_vol_file() nounwind { +entry: + %tmp = volatile load i32** @stat_vol_ptr_int, align 4 + %0 = bitcast i32* %tmp to i8* + call void @llvm.prefetch(i8* %0, i32 0, i32 0, i32 1) + %tmp1 = load i32** @stat_ptr_vol_int, align 4 + %1 = bitcast i32* %tmp1 to i8* + call void @llvm.prefetch(i8* %1, i32 0, i32 0, i32 1) + ret void +} + +declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind + diff --git a/test/CodeGen/Mips/o32_cc.ll b/test/CodeGen/Mips/o32_cc.ll index 3974cd4a6a764..70b66efee9a87 100644 --- a/test/CodeGen/Mips/o32_cc.ll +++ b/test/CodeGen/Mips/o32_cc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s ; FIXME: Disabled because it unpredictably fails on certain platforms. ; REQUIRES: disabled diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index f5e1a878dcfa4..e6734808ab770 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mipsel < %s | FileCheck %s %0 = type { i8, i16, i32, i64, double, i32, [4 x i8] } %struct.S1 = type { i8, i16, i32, i64, double, i32 } diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll index 14ce04b2b1a47..4a3d9ab8375c3 100644 --- a/test/CodeGen/Mips/o32_cc_vararg.ll +++ b/test/CodeGen/Mips/o32_cc_vararg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s +; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s ; All test functions do the same thing - they return the first variable diff --git a/test/CodeGen/Mips/rotate.ll b/test/CodeGen/Mips/rotate.ll index e7dc30932144a..8e27f4aad6eb7 100644 --- a/test/CodeGen/Mips/rotate.ll +++ b/test/CodeGen/Mips/rotate.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s -; CHECK: rotrv $2, $4, $2 +; CHECK: rotrv $2, $4 define i32 @rot0(i32 %a, i32 %b) nounwind readnone { entry: %shl = shl i32 %a, %b diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll index c83fa3ece0268..40115befc45d5 100644 --- a/test/CodeGen/Mips/select.ll +++ b/test/CodeGen/Mips/select.ll @@ -1,13 +1,11 @@ -; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2 -; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1 +; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK @d2 = external global double @d3 = external global double define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone { entry: -; CHECK-MIPS32R2: movn -; CHECK-MIPS1: beq +; CHECK: movn %tobool = icmp ne i32 %s, 0 %cond = select i1 %tobool, i32 %f1, i32 %f0 ret i32 %cond @@ -15,8 +13,7 @@ entry: define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone { entry: -; CHECK-MIPS32R2: movn.s -; CHECK-MIPS1: beq +; CHECK: movn.s %tobool = icmp ne i32 %s, 0 %cond = select i1 %tobool, float %f0, float %f1 ret float %cond @@ -24,8 +21,7 @@ entry: define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone { entry: -; CHECK-MIPS32R2: movn.d -; CHECK-MIPS1: beq +; CHECK: movn.d %tobool = icmp ne i32 %s, 0 %cond = select i1 %tobool, double %f0, double %f1 ret double %cond @@ -33,10 +29,8 @@ entry: define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.eq.s -; CHECK-MIPS32R2: movt.s -; CHECK-MIPS1: c.eq.s -; CHECK-MIPS1: bc1f +; CHECK: c.eq.s +; CHECK: movt.s %cmp = fcmp oeq float %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -44,10 +38,8 @@ entry: define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.olt.s -; CHECK-MIPS32R2: movt.s -; CHECK-MIPS1: c.olt.s -; CHECK-MIPS1: bc1f +; CHECK: c.olt.s +; CHECK: movt.s %cmp = fcmp olt float %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -55,10 +47,8 @@ entry: define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.ule.s -; CHECK-MIPS32R2: movf.s -; CHECK-MIPS1: c.ule.s -; CHECK-MIPS1: bc1t +; CHECK: c.ule.s +; CHECK: movf.s %cmp = fcmp ogt float %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -66,10 +56,8 @@ entry: define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.ule.s -; CHECK-MIPS32R2: movf.d -; CHECK-MIPS1: c.ule.s -; CHECK-MIPS1: bc1t +; CHECK: c.ule.s +; CHECK: movf.d %cmp = fcmp ogt float %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -77,10 +65,8 @@ entry: define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.eq.d -; CHECK-MIPS32R2: movt.d -; CHECK-MIPS1: c.eq.d -; CHECK-MIPS1: bc1f +; CHECK: c.eq.d +; CHECK: movt.d %cmp = fcmp oeq double %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -88,10 +74,8 @@ entry: define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.olt.d -; CHECK-MIPS32R2: movt.d -; CHECK-MIPS1: c.olt.d -; CHECK-MIPS1: bc1f +; CHECK: c.olt.d +; CHECK: movt.d %cmp = fcmp olt double %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -99,10 +83,8 @@ entry: define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.ule.d -; CHECK-MIPS32R2: movf.d -; CHECK-MIPS1: c.ule.d -; CHECK-MIPS1: bc1t +; CHECK: c.ule.d +; CHECK: movf.d %cmp = fcmp ogt double %f2, %f3 %cond = select i1 %cmp, double %f0, double %f1 ret double %cond @@ -110,10 +92,8 @@ entry: define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.ule.d -; CHECK-MIPS32R2: movf.s -; CHECK-MIPS1: c.ule.d -; CHECK-MIPS1: bc1t +; CHECK: c.ule.d +; CHECK: movf.s %cmp = fcmp ogt double %f2, %f3 %cond = select i1 %cmp, float %f0, float %f1 ret float %cond @@ -121,10 +101,8 @@ entry: define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.eq.s -; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.eq.s -; CHECK-MIPS1: bc1f +; CHECK: c.eq.s +; CHECK: movt %cmp = fcmp oeq float %f2, %f3 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -132,10 +110,8 @@ entry: define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.olt.s -; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.olt.s -; CHECK-MIPS1: bc1f +; CHECK: c.olt.s +; CHECK: movt %cmp = fcmp olt float %f2, %f3 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -143,10 +119,8 @@ entry: define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { entry: -; CHECK-MIPS32R2: c.ule.s -; CHECK-MIPS32R2: movf -; CHECK-MIPS1: c.ule.s -; CHECK-MIPS1: bc1t +; CHECK: c.ule.s +; CHECK: movf %cmp = fcmp ogt float %f2, %f3 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -154,10 +128,8 @@ entry: define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly { entry: -; CHECK-MIPS32R2: c.eq.d -; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.eq.d -; CHECK-MIPS1: bc1f +; CHECK: c.eq.d +; CHECK: movt %tmp = load double* @d2, align 8, !tbaa !0 %tmp1 = load double* @d3, align 8, !tbaa !0 %cmp = fcmp oeq double %tmp, %tmp1 @@ -167,10 +139,8 @@ entry: define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly { entry: -; CHECK-MIPS32R2: c.olt.d -; CHECK-MIPS32R2: movt -; CHECK-MIPS1: c.olt.d -; CHECK-MIPS1: bc1f +; CHECK: c.olt.d +; CHECK: movt %tmp = load double* @d2, align 8, !tbaa !0 %tmp1 = load double* @d3, align 8, !tbaa !0 %cmp = fcmp olt double %tmp, %tmp1 @@ -180,10 +150,8 @@ entry: define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly { entry: -; CHECK-MIPS32R2: c.ule.d -; CHECK-MIPS32R2: movf -; CHECK-MIPS1: c.ule.d -; CHECK-MIPS1: bc1t +; CHECK: c.ule.d +; CHECK: movf %tmp = load double* @d2, align 8, !tbaa !0 %tmp1 = load double* @d3, align 8, !tbaa !0 %cmp = fcmp ogt double %tmp, %tmp1 diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 034738b62627c..b0474b4c44349 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC -; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \ +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -march=mipsel -relocation-model=static < %s \ ; RUN: | FileCheck %s -check-prefix=STATIC diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll new file mode 100644 index 0000000000000..433e896d194b1 --- /dev/null +++ b/test/CodeGen/Mips/unalignedload.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL +; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB +%struct.S2 = type { %struct.S1, %struct.S1 } +%struct.S1 = type { i8, i8 } +%struct.S4 = type { [7 x i8] } + +@s2 = common global %struct.S2 zeroinitializer, align 1 +@s4 = common global %struct.S4 zeroinitializer, align 1 + +define void @foo1() nounwind { +entry: +; CHECK-EL: lw $25, %call16(foo2) +; CHECK-EL: ulhu $4, 2 +; CHECK-EL: lw $[[R0:[0-9]+]], %got(s4) +; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]]) +; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]]) +; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16 +; CHECK-EL: ulw $4, 0($[[R0]]) +; CHECK-EL: lw $25, %call16(foo4) +; CHECK-EL: or $5, $[[R2]], $[[R3]] + +; CHECK-EB: ulhu $[[R0:[0-9]+]], 2 +; CHECK-EB: lw $25, %call16(foo2) +; CHECK-EB: sll $4, $[[R0]], 16 +; CHECK-EB: lw $[[R1:[0-9]+]], %got(s4) +; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]]) +; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]]) +; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16 +; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8 +; CHECK-EB: ulw $4, 0($[[R1]]) +; CHECK-EB: lw $25, %call16(foo4) +; CHECK-EB: or $5, $[[R4]], $[[R5]] + + tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind + tail call void @foo4(%struct.S4* byval @s4) nounwind + ret void +} + +declare void @foo2(%struct.S1* byval) + +declare void @foo4(%struct.S4* byval) |