3 files changed, 66 insertions, 1 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/extractelement.ll b/test/CodeGen/Mips/llvm-ir/extractelement.ll
index f7b8ea5f9e15e..4f926cbee0b21 100644
--- a/test/CodeGen/Mips/llvm-ir/extractelement.ll
+++ b/test/CodeGen/Mips/llvm-ir/extractelement.ll
@@ -15,5 +15,5 @@ define i1 @via_stack_bug(i8 signext %idx) {
 ; ALL-DAG:       sh     [[ONE]], 6($sp)
 ; ALL-DAG:       andi   [[MASKED_IDX:\$[0-9]+]], $4, 1
 ; ALL-DAG:       addiu  [[VPTR:\$[0-9]+]], $sp, 6
-; ALL-DAG:       or   [[EPTR:\$[0-9]+]], [[MASKED_IDX]], [[VPTR]]
+; ALL-DAG:       or   [[EPTR:\$[0-9]+]], [[VPTR]], [[MASKED_IDX]]
 ; ALL:           lbu    $2, 0([[EPTR]])
diff --git a/test/CodeGen/Mips/long-call-mcount.ll b/test/CodeGen/Mips/long-call-mcount.ll
new file mode 100644
index 0000000000000..70a4410d060ba
--- /dev/null
+++ b/test/CodeGen/Mips/long-call-mcount.ll
@@ -0,0 +1,19 @@
+; Check call to mcount in case of long/short call options.
+; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK,LONG %s
+; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK,SHORT %s
+
+; Function Attrs: noinline nounwind optnone
+define void @foo() #0 {
+entry:
+  ret void
+
+; CHECK-LABEL: foo
+; LONG:          lui     $1, %hi(_mcount)
+; LONG-NEXT:     addiu   $25, $1, %lo(_mcount)
+; LONG-NEXT:     jalr    $25
+; SHORT:         jal     _mcount
+}
+
+attributes #0 = { "instrument-function-entry-inlined"="_mcount" }
diff --git a/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
new file mode 100644
index 0000000000000..85ce251ac3151
--- /dev/null
+++ b/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -0,0 +1,46 @@
+# RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s
+
+# Test that the 'sll $zero, $zero, 0' is correctly recognized as a real
+# instruction rather than some unimplemented opcode for the purposes of
+# encoding an instruction.
+
+# CHECK-LABEL: a:
+# CHECK:  nop                           # encoding: [0x00,0x00,0x00,0x00]
+# CHECK:  jrc   $ra                     # encoding: [0x45,0xbf]
+---
+name:            a
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: false
+registers:
+liveins:
+  - { reg: '%a0', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+constants:
+body:             |
+  bb.0.entry:
+    renamable %zero = SLL_MMR6 killed renamable %zero, 0
+    JRC16_MM undef %ra, implicit %v0
+
+...