diff options
Diffstat (limited to 'test/CodeGen/PowerPC/ppc64-anyregcc.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/ppc64-anyregcc.ll | 61 |
1 files changed, 43 insertions, 18 deletions
diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/test/CodeGen/PowerPC/ppc64-anyregcc.ll index 7cd3c4b382000..66f6a2c790c61 100644 --- a/test/CodeGen/PowerPC/ppc64-anyregcc.ll +++ b/test/CodeGen/PowerPC/ppc64-anyregcc.ll @@ -2,6 +2,31 @@ target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" +; CHECK-LABEL: test: +; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}} + +; CHECK-LABEL: property_access1: +; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}} + +; CHECK-LABEL: property_access2: +; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}} + +; CHECK-LABEL: property_access3: +; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}} + +; CHECK-LABEL: anyreg_test1: +; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}} + +; CHECK-LABEL: anyreg_test2: +; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}} + +; CHECK-LABEL: patchpoint_spilldef: +; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}} + +; CHECK-LABEL: patchpoint_spillargs: +; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}} + + ; Stackmap Header: no constants - 6 callsites ; CHECK-LABEL: .section .llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: @@ -26,9 +51,9 @@ target triple = "powerpc64-unknown-linux-gnu" ; CHECK-NEXT: .quad property_access3 ; CHECK-NEXT: .quad 128 ; CHECK-NEXT: .quad anyreg_test1 -; CHECK-NEXT: .quad 160 +; CHECK-NEXT: .quad 144 ; CHECK-NEXT: .quad anyreg_test2 -; CHECK-NEXT: .quad 160 +; CHECK-NEXT: .quad 144 ; CHECK-NEXT: .quad patchpoint_spilldef ; CHECK-NEXT: .quad 256 ; CHECK-NEXT: .quad patchpoint_spillargs @@ -36,7 +61,7 @@ target triple = "powerpc64-unknown-linux-gnu" ; test -; CHECK-LABEL: .long .L{{.*}}-.L.test +; CHECK: .long .L{{.*}}-.L[[test_BEGIN]] ; CHECK-NEXT: .short 0 ; 3 locations ; CHECK-NEXT: .short 3 @@ -57,12 +82,12 @@ target triple = "powerpc64-unknown-linux-gnu" ; CHECK-NEXT: .long 3 define i64 @test() nounwind ssp uwtable { entry: - call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3) + call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3) ret i64 0 } ; property access 1 - %obj is an anyreg call argument and should therefore be in a register -; CHECK-LABEL: .long .L{{.*}}-.L.property_access1 +; CHECK: .long .L{{.*}}-.L[[property_access1_BEGIN]] ; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 @@ -79,12 +104,12 @@ entry: define i64 @property_access1(i8* %obj) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj) ret i64 %ret } ; property access 2 - %obj is an anyreg call argument and should therefore be in a register -; CHECK-LABEL: .long .L{{.*}}-.L.property_access2 +; CHECK: .long .L{{.*}}-.L[[property_access2_BEGIN]] ; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 @@ -102,12 +127,12 @@ define i64 @property_access2() nounwind ssp uwtable { entry: %obj = alloca i64, align 8 %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj) ret i64 %ret } ; property access 3 - %obj is a frame index -; CHECK-LABEL: .long .L{{.*}}-.L.property_access3 +; CHECK: .long .L{{.*}}-.L[[property_access3_BEGIN]] ; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 @@ -125,12 +150,12 @@ define i64 @property_access3() nounwind ssp uwtable { entry: %obj = alloca i64, align 8 %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj) ret i64 %ret } ; anyreg_test1 -; CHECK-LABEL: .long .L{{.*}}-.L.anyreg_test1 +; CHECK: .long .L{{.*}}-.L[[anyreg_test1_BEGIN]] ; CHECK-NEXT: .short 0 ; 14 locations ; CHECK-NEXT: .short 14 @@ -207,12 +232,12 @@ entry: define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) ret i64 %ret } ; anyreg_test2 -; CHECK-LABEL: .long .L{{.*}}-.L.anyreg_test2 +; CHECK: .long .L{{.*}}-.L[[anyreg_test2_BEGIN]] ; CHECK-NEXT: .short 0 ; 14 locations ; CHECK-NEXT: .short 14 @@ -289,7 +314,7 @@ entry: define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) ret i64 %ret } @@ -297,7 +322,7 @@ entry: ; ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!" ; -; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spilldef +; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]] ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 3 ; Loc 0: Register (some register that will be spilled to the stack) @@ -317,7 +342,7 @@ entry: ; CHECK-NEXT: .long 0 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind ret i64 %result @@ -327,7 +352,7 @@ entry: ; ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled ; -; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spillargs +; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]] ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 5 ; Loc 0: Return a register @@ -359,7 +384,7 @@ define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17 },~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) ret i64 %result } |