diff options
Diffstat (limited to 'test/CodeGen/PowerPC/vec_constants.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vec_constants.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll index e4799e50e6ad6..f16b9f511f532 100644 --- a/test/CodeGen/PowerPC/vec_constants.ll +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -17,14 +17,14 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { store <4 x float> %tmp13, <4 x float>* %P3 ret void -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: CPI } define <4 x i32> @test_30() nounwind { ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > -; CHECK: test_30: +; CHECK-LABEL: test_30: ; CHECK: vspltisw ; CHECK-NEXT: vadduwm ; CHECK-NEXT: blr @@ -33,7 +33,7 @@ define <4 x i32> @test_30() nounwind { define <4 x i32> @test_29() nounwind { ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > -; CHECK: test_29: +; CHECK-LABEL: test_29: ; CHECK: vspltisw ; CHECK-NEXT: vspltisw ; CHECK-NEXT: vsubuwm @@ -43,7 +43,7 @@ define <4 x i32> @test_29() nounwind { define <8 x i16> @test_n30() nounwind { ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > -; CHECK: test_n30: +; CHECK-LABEL: test_n30: ; CHECK: vspltish ; CHECK-NEXT: vadduhm ; CHECK-NEXT: blr @@ -52,7 +52,7 @@ define <8 x i16> @test_n30() nounwind { define <16 x i8> @test_n104() nounwind { ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > -; CHECK: test_n104: +; CHECK-LABEL: test_n104: ; CHECK: vspltisb ; CHECK-NEXT: vslb ; CHECK-NEXT: blr @@ -61,7 +61,7 @@ define <16 x i8> @test_n104() nounwind { define <4 x i32> @test_vsldoi() nounwind { ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > -; CHECK: test_vsldoi: +; CHECK-LABEL: test_vsldoi: ; CHECK: vspltisw ; CHECK-NEXT: vsldoi ; CHECK-NEXT: blr @@ -70,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind { define <8 x i16> @test_vsldoi_65023() nounwind { ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > -; CHECK: test_vsldoi_65023: +; CHECK-LABEL: test_vsldoi_65023: ; CHECK: vspltish ; CHECK-NEXT: vsldoi ; CHECK-NEXT: blr @@ -79,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind { define <4 x i32> @test_rol() nounwind { ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > -; CHECK: test_rol: +; CHECK-LABEL: test_rol: ; CHECK: vspltisw ; CHECK-NEXT: vrlw ; CHECK-NEXT: blr |