1 files changed, 31 insertions, 19 deletions

diff --git a/test/CodeGen/SystemZ/bswap-05.ll b/test/CodeGen/SystemZ/bswap-05.ll
index e58cb80c39815..5c8361e26cea9 100644
--- a/test/CodeGen/SystemZ/bswap-05.ll
+++ b/test/CodeGen/SystemZ/bswap-05.ll
@@ -5,21 +5,21 @@
 declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check STRVG with no displacement.
-define void @f1(i64 *%src, i64 %a) {
-; CHECK: f1:
+define void @f1(i64 *%dst, i64 %a) {
+; CHECK-LABEL: f1:
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
-  store i64 %swapped, i64 *%src
+  store i64 %swapped, i64 *%dst
   ret void
 }
 
 ; Check the high end of the aligned STRVG range.
-define void @f2(i64 *%src, i64 %a) {
-; CHECK: f2:
+define void @f2(i64 *%dst, i64 %a) {
+; CHECK-LABEL: f2:
 ; CHECK: strvg %r3, 524280(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65535
+  %ptr = getelementptr i64 *%dst, i64 65535
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
@@ -27,34 +27,34 @@ define void @f2(i64 *%src, i64 %a) {
 
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
-define void @f3(i64 *%src, i64 %a) {
-; CHECK: f3:
+define void @f3(i64 *%dst, i64 %a) {
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 65536
+  %ptr = getelementptr i64 *%dst, i64 65536
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
 }
 
 ; Check the high end of the negative aligned STRVG range.
-define void @f4(i64 *%src, i64 %a) {
-; CHECK: f4:
+define void @f4(i64 *%dst, i64 %a) {
+; CHECK-LABEL: f4:
 ; CHECK: strvg %r3, -8(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -1
+  %ptr = getelementptr i64 *%dst, i64 -1
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
 }
 
 ; Check the low end of the STRVG range.
-define void @f5(i64 *%src, i64 %a) {
-; CHECK: f5:
+define void @f5(i64 *%dst, i64 %a) {
+; CHECK-LABEL: f5:
 ; CHECK: strvg %r3, -524288(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65536
+  %ptr = getelementptr i64 *%dst, i64 -65536
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
@@ -62,12 +62,12 @@ define void @f5(i64 *%src, i64 %a) {
 
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
-define void @f6(i64 *%src, i64 %a) {
-; CHECK: f6:
+define void @f6(i64 *%dst, i64 %a) {
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
-  %ptr = getelementptr i64 *%src, i64 -65537
+  %ptr = getelementptr i64 *%dst, i64 -65537
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   store i64 %swapped, i64 *%ptr
   ret void
@@ -75,7 +75,7 @@ define void @f6(i64 *%src, i64 %a) {
 
 ; Check that STRVG allows an index.
 define void @f7(i64 %src, i64 %index, i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: strvg %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -85,3 +85,15 @@ define void @f7(i64 %src, i64 %index, i64 %a) {
   store i64 %swapped, i64 *%ptr
   ret void
 }
+
+; Check that volatile stores do not use STRVG, which might access the
+; storage multple times.
+define void @f8(i64 *%dst, i64 %a) {
+; CHECK-LABEL: f8:
+; CHECK: lrvgr [[REG:%r[0-5]]], %r3
+; CHECK: stg [[REG]], 0(%r2)
+; CHECK: br %r14
+  %swapped = call i64 @llvm.bswap.i64(i64 %a)
+  store volatile i64 %swapped, i64 *%dst
+  ret void
+}