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-rw-r--r--test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll2
-rw-r--r--test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll29
-rw-r--r--test/CodeGen/Thumb2/cross-rc-coalescing-1.ll52
-rw-r--r--test/CodeGen/Thumb2/cross-rc-coalescing-2.ll67
-rw-r--r--test/CodeGen/Thumb2/ldr-str-imm12.ll75
-rw-r--r--test/CodeGen/Thumb2/machine-licm.ll36
-rw-r--r--test/CodeGen/Thumb2/thumb2-bcc.ll4
-rw-r--r--test/CodeGen/Thumb2/thumb2-bfc.ll9
-rw-r--r--test/CodeGen/Thumb2/thumb2-branch.ll10
-rw-r--r--test/CodeGen/Thumb2/thumb2-cbnz.ll32
-rw-r--r--test/CodeGen/Thumb2/thumb2-clz.ll4
-rw-r--r--test/CodeGen/Thumb2/thumb2-cmn2.ll10
-rw-r--r--test/CodeGen/Thumb2/thumb2-eor2.ll12
-rw-r--r--test/CodeGen/Thumb2/thumb2-mov.ll165
-rw-r--r--test/CodeGen/Thumb2/thumb2-str_post.ll9
15 files changed, 474 insertions, 42 deletions
diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
index 3cbb212b628bc..76474746ee487 100644
--- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
@@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | grep fcpys | count 1
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | not grep fcpys
; rdar://7117307
%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
diff --git a/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll
new file mode 100644
index 0000000000000..216f3e3f9cc84
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8
+
+define arm_apcscc void @get_initial_mb16x16_cost() nounwind {
+entry:
+ br i1 undef, label %bb4, label %bb1
+
+bb1: ; preds = %entry
+ br label %bb7
+
+bb4: ; preds = %entry
+ br i1 undef, label %bb7.thread, label %bb5
+
+bb5: ; preds = %bb4
+ br label %bb7
+
+bb7.thread: ; preds = %bb4
+ br label %bb8
+
+bb7: ; preds = %bb5, %bb1
+ br i1 undef, label %bb8, label %bb10
+
+bb8: ; preds = %bb7, %bb7.thread
+ %0 = phi double [ 5.120000e+02, %bb7.thread ], [ undef, %bb7 ] ; <double> [#uses=1]
+ %1 = fdiv double %0, undef ; <double> [#uses=0]
+ unreachable
+
+bb10: ; preds = %bb7
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll
new file mode 100644
index 0000000000000..572f1e8975a3a
--- /dev/null
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll
@@ -0,0 +1,52 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8
+
+%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__sFILEX = type opaque
+%struct.__sbuf = type { i8*, i32 }
+
+declare arm_apcscc i32 @fgetc(%struct.FILE* nocapture) nounwind
+
+define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+ br i1 undef, label %bb, label %bb1
+
+bb: ; preds = %entry
+ unreachable
+
+bb1: ; preds = %entry
+ br i1 undef, label %bb.i1, label %bb1.i2
+
+bb.i1: ; preds = %bb1
+ unreachable
+
+bb1.i2: ; preds = %bb1
+ %0 = call arm_apcscc i32 @fgetc(%struct.FILE* undef) nounwind ; <i32> [#uses=0]
+ br i1 undef, label %bb2.i3, label %bb3.i4
+
+bb2.i3: ; preds = %bb1.i2
+ br i1 undef, label %bb4.i, label %bb3.i4
+
+bb3.i4: ; preds = %bb2.i3, %bb1.i2
+ unreachable
+
+bb4.i: ; preds = %bb2.i3
+ br i1 undef, label %bb5.i, label %get_image.exit
+
+bb5.i: ; preds = %bb4.i
+ unreachable
+
+get_image.exit: ; preds = %bb4.i
+ br i1 undef, label %bb28, label %bb27
+
+bb27: ; preds = %get_image.exit
+ br label %bb.i
+
+bb.i: ; preds = %bb.i, %bb27
+ %1 = fptrunc double undef to float ; <float> [#uses=1]
+ %2 = fptoui float %1 to i8 ; <i8> [#uses=1]
+ store i8 %2, i8* undef, align 1
+ br label %bb.i
+
+bb28: ; preds = %get_image.exit
+ unreachable
+}
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
new file mode 100644
index 0000000000000..4320328e9c102
--- /dev/null
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep fcpys | count 4
+
+define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind {
+entry:
+ br label %bb5
+
+bb5: ; preds = %bb5, %entry
+ br i1 undef, label %bb5, label %bb.nph
+
+bb.nph: ; preds = %bb5
+ br label %bb7
+
+bb7: ; preds = %bb9, %bb.nph
+ %s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3]
+ %tmp79 = add i32 undef, undef ; <i32> [#uses=1]
+ %tmp53 = sub i32 undef, undef ; <i32> [#uses=1]
+ %0 = fadd float 0.000000e+00, 1.000000e+00 ; <float> [#uses=2]
+ %1 = fmul float 0.000000e+00, 0.000000e+00 ; <float> [#uses=2]
+ br label %bb8
+
+bb8: ; preds = %bb8, %bb7
+ %tmp54 = add i32 0, %tmp53 ; <i32> [#uses=0]
+ %fi.1 = getelementptr float* %fz, i32 undef ; <float*> [#uses=2]
+ %tmp80 = add i32 0, %tmp79 ; <i32> [#uses=1]
+ %scevgep81 = getelementptr float* %fz, i32 %tmp80 ; <float*> [#uses=1]
+ %2 = load float* undef, align 4 ; <float> [#uses=1]
+ %3 = fmul float %2, %1 ; <float> [#uses=1]
+ %4 = load float* null, align 4 ; <float> [#uses=2]
+ %5 = fmul float %4, %0 ; <float> [#uses=1]
+ %6 = fsub float %3, %5 ; <float> [#uses=1]
+ %7 = fmul float %4, %1 ; <float> [#uses=1]
+ %8 = fadd float undef, %7 ; <float> [#uses=2]
+ %9 = load float* %fi.1, align 4 ; <float> [#uses=2]
+ %10 = fsub float %9, %8 ; <float> [#uses=1]
+ %11 = fadd float %9, %8 ; <float> [#uses=1]
+ %12 = fsub float 0.000000e+00, %6 ; <float> [#uses=1]
+ %13 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
+ %14 = fmul float undef, %0 ; <float> [#uses=1]
+ %15 = fadd float %14, undef ; <float> [#uses=2]
+ %16 = load float* %scevgep81, align 4 ; <float> [#uses=2]
+ %17 = fsub float %16, %15 ; <float> [#uses=1]
+ %18 = fadd float %16, %15 ; <float> [#uses=2]
+ %19 = load float* undef, align 4 ; <float> [#uses=2]
+ %20 = fsub float %19, %13 ; <float> [#uses=2]
+ %21 = fadd float %19, %13 ; <float> [#uses=1]
+ %22 = fmul float %s1.02, %18 ; <float> [#uses=1]
+ %23 = fmul float 0.000000e+00, %20 ; <float> [#uses=1]
+ %24 = fsub float %22, %23 ; <float> [#uses=1]
+ %25 = fmul float 0.000000e+00, %18 ; <float> [#uses=1]
+ %26 = fmul float %s1.02, %20 ; <float> [#uses=1]
+ %27 = fadd float %25, %26 ; <float> [#uses=1]
+ %28 = fadd float %11, %27 ; <float> [#uses=1]
+ store float %28, float* %fi.1, align 4
+ %29 = fadd float %12, %24 ; <float> [#uses=1]
+ store float %29, float* null, align 4
+ %30 = fmul float 0.000000e+00, %21 ; <float> [#uses=1]
+ %31 = fmul float %s1.02, %17 ; <float> [#uses=1]
+ %32 = fsub float %30, %31 ; <float> [#uses=1]
+ %33 = fsub float %10, %32 ; <float> [#uses=1]
+ store float %33, float* undef, align 4
+ %34 = icmp slt i32 undef, undef ; <i1> [#uses=1]
+ br i1 %34, label %bb8, label %bb9
+
+bb9: ; preds = %bb8
+ %35 = fadd float 0.000000e+00, undef ; <float> [#uses=1]
+ br label %bb7
+}
diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll
new file mode 100644
index 0000000000000..4c8ffe882896a
--- /dev/null
+++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
+; rdar://7352504
+; Make sure we use "str r9, [sp, #+28]" instead of "sub.w r4, r7, #256" followed by "str r9, [r4, #-32]".
+
+%0 = type { i16, i8, i8 }
+%1 = type { [2 x i32], [2 x i32] }
+%2 = type { %union.rec* }
+%struct.FILE_POS = type { i8, i8, i16, i32 }
+%struct.GAP = type { i8, i8, i16 }
+%struct.LIST = type { %union.rec*, %union.rec* }
+%struct.STYLE = type { %union.anon, %union.anon, i16, i16, i32 }
+%struct.head_type = type { [2 x %struct.LIST], %union.FIRST_UNION, %union.SECOND_UNION, %union.THIRD_UNION, %union.FOURTH_UNION, %union.rec*, %2, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, i32 }
+%union.FIRST_UNION = type { %struct.FILE_POS }
+%union.FOURTH_UNION = type { %struct.STYLE }
+%union.SECOND_UNION = type { %0 }
+%union.THIRD_UNION = type { %1 }
+%union.anon = type { %struct.GAP }
+%union.rec = type { %struct.head_type }
+
+@zz_hold = external global %union.rec* ; <%union.rec**> [#uses=2]
+@zz_res = external global %union.rec* ; <%union.rec**> [#uses=1]
+
+define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
+entry:
+; CHECK: ldr.w r9, [r7, #+32]
+; CHECK-NEXT : str.w r9, [sp, #+28]
+ %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
+ %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
+ br i1 false, label %bb, label %bb20
+
+bb: ; preds = %entry
+ unreachable
+
+bb20: ; preds = %entry
+ switch i32 undef, label %bb1287 [
+ i32 11, label %bb119
+ i32 12, label %bb119
+ i32 21, label %bb420
+ i32 23, label %bb420
+ i32 45, label %bb438
+ i32 46, label %bb438
+ i32 55, label %bb533
+ i32 56, label %bb569
+ i32 64, label %bb745
+ i32 78, label %bb1098
+ ]
+
+bb119: ; preds = %bb20, %bb20
+ unreachable
+
+bb420: ; preds = %bb20, %bb20
+ store %union.rec* null, %union.rec** @zz_hold, align 4
+ store %union.rec* null, %union.rec** @zz_res, align 4
+ store %union.rec* %x, %union.rec** @zz_hold, align 4
+ %0 = call arm_apcscc %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0]
+ unreachable
+
+bb438: ; preds = %bb20, %bb20
+ unreachable
+
+bb533: ; preds = %bb20
+ ret %union.rec* %x
+
+bb569: ; preds = %bb20
+ unreachable
+
+bb745: ; preds = %bb20
+ unreachable
+
+bb1098: ; preds = %bb20
+ unreachable
+
+bb1287: ; preds = %bb20
+ unreachable
+}
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
new file mode 100644
index 0000000000000..64309c492dd8a
--- /dev/null
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s
+; rdar://7353541
+
+; The generated code is no where near ideal. It's not recognizing the two
+; constantpool entries being loaded can be merged into one.
+
+@GV = external global i32 ; <i32*> [#uses=2]
+
+define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind {
+entry:
+; CHECK: t:
+; CHECK: cbz
+ %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb.nph
+
+bb.nph: ; preds = %entry
+; CHECK: BB#1
+; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_0
+; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_1
+ %.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.nph
+ %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
+ %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
+ %scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
+ %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
+ %3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
+ store i32 %3, i32* @GV, align 4
+ %4 = add i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll
index e1f9cdbf8c643..aae9f5c0af714 100644
--- a/test/CodeGen/Thumb2/thumb2-bcc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -2,8 +2,8 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it
define i32 @t1(i32 %a, i32 %b, i32 %c) {
-; CHECK: t1
-; CHECK: beq
+; CHECK: t1:
+; CHECK: cbz
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true
diff --git a/test/CodeGen/Thumb2/thumb2-bfc.ll b/test/CodeGen/Thumb2/thumb2-bfc.ll
index d33cf7ebdb27f..b486045ab5015 100644
--- a/test/CodeGen/Thumb2/thumb2-bfc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bfc.ll
@@ -1,25 +1,32 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "bfc " | count 3
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 4278190095 = 0xff00000f
define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: bfc r
%tmp = and i32 %a, 4278190095
ret i32 %tmp
}
; 4286578688 = 0xff800000
define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: bfc r
%tmp = and i32 %a, 4286578688
ret i32 %tmp
}
; 4095 = 0x00000fff
define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: bfc r
%tmp = and i32 %a, 4095
ret i32 %tmp
}
; 2147483646 = 0x7ffffffe not implementable w/ BFC
define i32 @f4(i32 %a) {
+; CHECK: f4:
%tmp = and i32 %a, 2147483646
ret i32 %tmp
}
diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
index b46cb5f7c70e9..129838457b261 100644
--- a/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
define void @f1(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f1:
-; CHECK bne LBB
+; CHECK: bne LBB
%tmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
@@ -18,7 +18,7 @@ return: ; preds = %entry
define void @f2(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f2:
-; CHECK bge LBB
+; CHECK: bge LBB
%tmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
@@ -33,7 +33,7 @@ return: ; preds = %entry
define void @f3(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f3:
-; CHECK bhs LBB
+; CHECK: bhs LBB
%tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
@@ -48,7 +48,7 @@ return: ; preds = %entry
define void @f4(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f4:
-; CHECK blo LBB
+; CHECK: blo LBB
%tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %return, label %cond_true
diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll
new file mode 100644
index 0000000000000..64587c13fdd11
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
+; rdar://7354379
+
+declare arm_apcscc double @floor(double) nounwind readnone
+
+define void @t(i1 %a, double %b) {
+entry:
+ br i1 %a, label %bb3, label %bb1
+
+bb1: ; preds = %entry
+ unreachable
+
+bb3: ; preds = %entry
+ br i1 %a, label %bb7, label %bb5
+
+bb5: ; preds = %bb3
+ unreachable
+
+bb7: ; preds = %bb3
+ br i1 %a, label %bb11, label %bb9
+
+bb9: ; preds = %bb7
+; CHECK: @ BB#2:
+; CHECK-NEXT: cbnz
+ %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0]
+ br label %bb11
+
+bb11: ; preds = %bb9, %bb7
+ %1 = getelementptr i32* undef, i32 0
+ store i32 0, i32* %1
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/thumb2-clz.ll b/test/CodeGen/Thumb2/thumb2-clz.ll
index 0bed0585b5d16..74728bfcc5a99 100644
--- a/test/CodeGen/Thumb2/thumb2-clz.ll
+++ b/test/CodeGen/Thumb2/thumb2-clz.ll
@@ -1,6 +1,8 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | grep "clz " | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: clz r
%tmp = tail call i32 @llvm.ctlz.i32(i32 %a)
ret i32 %tmp
}
diff --git a/test/CodeGen/Thumb2/thumb2-cmn2.ll b/test/CodeGen/Thumb2/thumb2-cmn2.ll
index c1fcac00e643b..c0e19f63a3095 100644
--- a/test/CodeGen/Thumb2/thumb2-cmn2.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmn2.ll
@@ -1,25 +1,33 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "cmn\\.w " | grep {#187\\|#11141290\\|#-872363008\\|#1114112} | count 4
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; -0x000000bb = 4294967109
define i1 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: cmn.w {{r.*}}, #187
%tmp = icmp ne i32 %a, 4294967109
ret i1 %tmp
}
; -0x00aa00aa = 4283826006
define i1 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: cmn.w {{r.*}}, #11141290
%tmp = icmp eq i32 %a, 4283826006
ret i1 %tmp
}
; -0xcc00cc00 = 872363008
define i1 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: cmn.w {{r.*}}, #-872363008
%tmp = icmp ne i32 %a, 872363008
ret i1 %tmp
}
; -0x00110000 = 4293853184
define i1 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: cmn.w {{r.*}}, #1114112
%tmp = icmp eq i32 %a, 4293853184
ret i1 %tmp
}
diff --git a/test/CodeGen/Thumb2/thumb2-eor2.ll b/test/CodeGen/Thumb2/thumb2-eor2.ll
index 185634cdd6fc9..6b2e9dcf3d1f8 100644
--- a/test/CodeGen/Thumb2/thumb2-eor2.ll
+++ b/test/CodeGen/Thumb2/thumb2-eor2.ll
@@ -1,31 +1,41 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "eor " | grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 5
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; 0x000000bb = 187
define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: eor {{.*}}#187
%tmp = xor i32 %a, 187
ret i32 %tmp
}
; 0x00aa00aa = 11141290
define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: eor {{.*}}#11141290
%tmp = xor i32 %a, 11141290
ret i32 %tmp
}
; 0xcc00cc00 = 3422604288
define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: eor {{.*}}#-872363008
%tmp = xor i32 %a, 3422604288
ret i32 %tmp
}
; 0xdddddddd = 3722304989
define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: eor {{.*}}#-572662307
%tmp = xor i32 %a, 3722304989
ret i32 %tmp
}
; 0x00110000 = 1114112
define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: eor {{.*}}#1114112
%tmp = xor i32 %a, 1114112
ret i32 %tmp
}
diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll
index 8606e327a637b..1dc3614993bd3 100644
--- a/test/CodeGen/Thumb2/thumb2-mov.ll
+++ b/test/CodeGen/Thumb2/thumb2-mov.ll
@@ -5,38 +5,40 @@
; var 2.1 - 0x00ab00ab
define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_1:
-;CHECK: #11206827
+;CHECK: add.w r0, r0, #11206827
%ret = add i32 %lhs, 11206827 ; 0x00ab00ab
ret i32 %ret
}
define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_2:
-;CHECK: #11206656
-;CHECK: #187
+;CHECK: add.w r0, r0, #11206656
+;CHECK: adds r0, #187
%ret = add i32 %lhs, 11206843 ; 0x00ab00bb
ret i32 %ret
}
define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_3:
-;CHECK: #11206827
-;CHECK: #16777216
+;CHECK: add.w r0, r0, #11206827
+;CHECK: add.w r0, r0, #16777216
%ret = add i32 %lhs, 27984043 ; 0x01ab00ab
ret i32 %ret
}
define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_4:
-;CHECK: #16777472
-;CHECK: #11206827
+;CHECK: add.w r0, r0, #16777472
+;CHECK: add.w r0, r0, #11206827
%ret = add i32 %lhs, 27984299 ; 0x01ab01ab
ret i32 %ret
}
define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
;CHECK: t2_const_var2_1_fail_1:
-;CHECK: movt
+;CHECK: movw r1, #43777
+;CHECK: movt r1, #427
+;CHECK: add r0, r1
%ret = add i32 %lhs, 28027649 ; 0x01abab01
ret i32 %ret
}
@@ -44,37 +46,40 @@ define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
; var 2.2 - 0xab00ab00
define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_1:
-;CHECK: #-1426019584
+;CHECK: add.w r0, r0, #-1426019584
%ret = add i32 %lhs, 2868947712 ; 0xab00ab00
ret i32 %ret
}
define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_2:
-;CHECK: #-1426063360
-;CHECK: #47616
+;CHECK: add.w r0, r0, #-1426063360
+;CHECK: add.w r0, r0, #47616
%ret = add i32 %lhs, 2868951552 ; 0xab00ba00
ret i32 %ret
}
define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_3:
-;CHECK: #-1426019584
+;CHECK: add.w r0, r0, #-1426019584
+;CHECK: adds r0, #16
%ret = add i32 %lhs, 2868947728 ; 0xab00ab10
ret i32 %ret
}
define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_4:
-;CHECK: #-1426019584
-;CHECK: #1048592
+;CHECK: add.w r0, r0, #-1426019584
+;CHECK: add.w r0, r0, #1048592
%ret = add i32 %lhs, 2869996304 ; 0xab10ab10
ret i32 %ret
}
define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
;CHECK: t2_const_var2_2_fail_1:
-;CHECK: movt
+;CHECK: movw r1, #43792
+;CHECK: movt r1, #4267
+;CHECK: add r0, r1
%ret = add i32 %lhs, 279685904 ; 0x10abab10
ret i32 %ret
}
@@ -82,35 +87,43 @@ define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
; var 2.3 - 0xabababab
define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_3_ok_1:
-;CHECK: #-1414812757
+;CHECK: add.w r0, r0, #-1414812757
%ret = add i32 %lhs, 2880154539 ; 0xabababab
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_1:
-;CHECK: movt
+;CHECK: movw r1, #43962
+;CHECK: movt r1, #43947
+;CHECK: add r0, r1
%ret = add i32 %lhs, 2880154554 ; 0xabababba
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_2:
-;CHECK: movt
+;CHECK: movw r1, #47787
+;CHECK: movt r1, #43947
+;CHECK: add r0, r1
%ret = add i32 %lhs, 2880158379 ; 0xababbaab
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_3:
-;CHECK: movt
+;CHECK: movw r1, #43947
+;CHECK: movt r1, #43962
+;CHECK: add r0, r1
%ret = add i32 %lhs, 2881137579 ; 0xabbaabab
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_4:
-;CHECK: movt
+;CHECK: movw r1, #43947
+;CHECK: movt r1, #47787
+;CHECK: add r0, r1
%ret = add i32 %lhs, 3131812779 ; 0xbaababab
ret i32 %ret
}
@@ -118,36 +131,136 @@ define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
; var 3 - 0x0F000000
define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_1_ok_1:
-;CHECK: #251658240
+;CHECK: add.w r0, r0, #251658240
%ret = add i32 %lhs, 251658240 ; 0x0F000000
ret i32 %ret
}
define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_2_ok_1:
-;CHECK: #3948544
+;CHECK: add.w r0, r0, #3948544
%ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
ret i32 %ret
}
define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
;CHECK: t2_const_var3_2_ok_2:
-;CHECK: #2097152
-;CHECK: #1843200
+;CHECK: add.w r0, r0, #2097152
+;CHECK: add.w r0, r0, #1843200
%ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
ret i32 %ret
}
define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_3_ok_1:
-;CHECK: #258
+;CHECK: add.w r0, r0, #258
%ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
ret i32 %ret
}
define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_4_ok_1:
-;CHECK: #-268435456
+;CHECK: add.w r0, r0, #-268435456
%ret = add i32 %lhs, 4026531840 ; 0xF0000000
ret i32 %ret
}
+
+define i32 @t2MOVTi16_ok_1(i32 %a) {
+; CHECK: t2MOVTi16_ok_1:
+; CHECK: movt r0, #1234
+ %1 = and i32 %a, 65535
+ %2 = shl i32 1234, 16
+ %3 = or i32 %1, %2
+
+ ret i32 %3
+}
+
+define i32 @t2MOVTi16_test_1(i32 %a) {
+; CHECK: t2MOVTi16_test_1:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4
+ %5 = and i32 %a, %3
+ %6 = or i32 %4, %5
+
+ ret i32 %6
+}
+
+define i32 @t2MOVTi16_test_2(i32 %a) {
+; CHECK: t2MOVTi16_test_2:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 6
+ %5 = and i32 %a, %3
+ %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
+ %7 = or i32 %5, %6
+
+ ret i32 %7
+}
+
+define i32 @t2MOVTi16_test_3(i32 %a) {
+; CHECK: t2MOVTi16_test_3:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 6
+ %5 = and i32 %a, %3
+ %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
+ %7 = lshr i32 %6, 6
+ %8 = shl i32 %7, 6
+ %9 = or i32 %5, %8
+
+ ret i32 %8
+}
+
+; 171 = 0x000000ab
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: movs r0, #171
+ %tmp = add i32 0, 171
+ ret i32 %tmp
+}
+
+; 1179666 = 0x00120012
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: mov.w r0, #1179666
+ %tmp = add i32 0, 1179666
+ ret i32 %tmp
+}
+
+; 872428544 = 0x34003400
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: mov.w r0, #872428544
+ %tmp = add i32 0, 872428544
+ ret i32 %tmp
+}
+
+; 1448498774 = 0x56565656
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: mov.w r0, #1448498774
+ %tmp = add i32 0, 1448498774
+ ret i32 %tmp
+}
+
+; 66846720 = 0x03fc0000
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: mov.w r0, #66846720
+ %tmp = add i32 0, 66846720
+ ret i32 %tmp
+}
+
+define i32 @f6(i32 %a) {
+;CHECK: f6
+;CHECK: movw r0, #65535
+ %tmp = add i32 0, 65535
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-str_post.ll b/test/CodeGen/Thumb2/thumb2-str_post.ll
index bee58105daebb..bbfb447ca3efd 100644
--- a/test/CodeGen/Thumb2/thumb2-str_post.ll
+++ b/test/CodeGen/Thumb2/thumb2-str_post.ll
@@ -1,9 +1,8 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
-; RUN: grep {strh .*\\\[.*\], #-4} | count 1
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
-; RUN: grep {str .*\\\[.*\],} | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i16 @test1(i32* %X, i16* %A) {
+; CHECK: test1:
+; CHECK: strh {{.*}}[{{.*}}], #-4
%Y = load i32* %X ; <i32> [#uses=1]
%tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
store i16 %tmp1, i16* %A
@@ -13,6 +12,8 @@ define i16 @test1(i32* %X, i16* %A) {
}
define i32 @test2(i32* %X, i32* %A) {
+; CHECK: test2:
+; CHECK: str {{.*}}[{{.*}}],
%Y = load i32* %X ; <i32> [#uses=1]
store i32 %Y, i32* %A
%tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1]
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-02 18:28:24 +0000