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-rw-r--r--test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir119
1 files changed, 119 insertions, 0 deletions
diff --git a/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir b/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
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+++ b/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
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+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+--- |
+
+ define float @test_fdiv_float(float %arg1, float %arg2) {
+ %ret = fdiv float %arg1, %arg2
+ ret float %ret
+ }
+
+ define double @test_fdiv_double(double %arg1, double %arg2) {
+ %ret = fdiv double %arg1, %arg2
+ ret double %ret
+ }
+
+...
+---
+name: test_fdiv_float
+# ALL-LABEL: name: test_fdiv_float
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = DIVSSrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VDIVSSrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VDIVSSZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s32) = COPY %xmm0
+ %1(s32) = COPY %xmm1
+ %2(s32) = G_FDIV %0, %1
+ %xmm0 = COPY %2(s32)
+ RET 0, implicit %xmm0
+
+...
+---
+name: test_fdiv_double
+# ALL-LABEL: name: test_fdiv_double
+alignment: 4
+legalized: true
+regBankSelected: true
+# NO_AVX512F: registers:
+# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
+#
+# AVX512ALL: registers:
+# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
+registers:
+ - { id: 0, class: vecr, preferred-register: '' }
+ - { id: 1, class: vecr, preferred-register: '' }
+ - { id: 2, class: vecr, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+# SSE: %0 = COPY %xmm0
+# SSE-NEXT: %1 = COPY %xmm1
+# SSE-NEXT: %2 = DIVSDrr %0, %1
+# SSE-NEXT: %xmm0 = COPY %2
+# SSE-NEXT: RET 0, implicit %xmm0
+#
+# AVX: %0 = COPY %xmm0
+# AVX-NEXT: %1 = COPY %xmm1
+# AVX-NEXT: %2 = VDIVSDrr %0, %1
+# AVX-NEXT: %xmm0 = COPY %2
+# AVX-NEXT: RET 0, implicit %xmm0
+#
+# AVX512ALL: %0 = COPY %xmm0
+# AVX512ALL-NEXT: %1 = COPY %xmm1
+# AVX512ALL-NEXT: %2 = VDIVSDZrr %0, %1
+# AVX512ALL-NEXT: %xmm0 = COPY %2
+# AVX512ALL-NEXT: RET 0, implicit %xmm0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %xmm0, %xmm1
+
+ %0(s64) = COPY %xmm0
+ %1(s64) = COPY %xmm1
+ %2(s64) = G_FDIV %0, %1
+ %xmm0 = COPY %2(s64)
+ RET 0, implicit %xmm0
+
+...