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-rw-r--r--test/CodeGen/X86/anyregcc.ll182
1 files changed, 136 insertions, 46 deletions
diff --git a/test/CodeGen/X86/anyregcc.ll b/test/CodeGen/X86/anyregcc.ll
index 1b51b53bd2266..b75774ab12c07 100644
--- a/test/CodeGen/X86/anyregcc.ll
+++ b/test/CodeGen/X86/anyregcc.ll
@@ -7,7 +7,7 @@
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
; CHECK-NEXT: __LLVM_StackMaps:
; Header
-; CHECK-NEXT: .byte 2
+; CHECK-NEXT: .byte 3
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 0
; Num Functions
@@ -53,18 +53,24 @@
; CHECK-NEXT: .short 3
; Loc 0: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Constant 3
; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 3
define i64 @test() nounwind ssp uwtable {
entry:
@@ -79,13 +85,17 @@ entry:
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
entry:
@@ -101,13 +111,17 @@ entry:
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @property_access2() nounwind ssp uwtable {
entry:
@@ -124,13 +138,17 @@ entry:
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Direct RBP - ofs
; CHECK-NEXT: .byte 2
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
define i64 @property_access3() nounwind ssp uwtable {
entry:
@@ -147,73 +165,101 @@ entry:
; CHECK-NEXT: .short 14
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 4: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 5: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 6: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 7: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 8: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 9: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 10: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 11: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 12: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 13: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
entry:
@@ -229,73 +275,101 @@ entry:
; CHECK-NEXT: .short 14
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 4: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 5: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 6: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 7: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 8: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 9: Argument, still on stack
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
; Loc 10: Argument, still on stack
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
; Loc 11: Argument, still on stack
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
; Loc 12: Argument, still on stack
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
; Loc 13: Argument, still on stack
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
entry:
@@ -313,18 +387,24 @@ entry:
; CHECK-NEXT: .short 3
; Loc 0: Register (some register that will be spilled to the stack)
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register RDI
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 5
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register RSI
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 4
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
@@ -342,28 +422,38 @@ entry:
; CHECK-NEXT: .short 5
; Loc 0: Return a register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Arg0 in a Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Arg1 in a Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Arg2 spilled to RBP +
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
; Loc 4: Arg3 spilled to RBP +
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 6
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-02 06:29:45 +0000