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-rw-r--r--test/CodeGen/X86/implicit-null-checks.mir266
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diff --git a/test/CodeGen/X86/implicit-null-checks.mir b/test/CodeGen/X86/implicit-null-checks.mir
new file mode 100644
index 0000000000000..9e83964247e7e
--- /dev/null
+++ b/test/CodeGen/X86/implicit-null-checks.mir
@@ -0,0 +1,266 @@
+# RUN: llc -run-pass implicit-null-checks -mtriple=x86_64-apple-macosx -o - %s | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+ target triple = "x86_64-apple-macosx"
+
+ ;; Positive test
+ define i32 @imp_null_check_with_bitwise_op_0(i32* %x, i32 %val) {
+ entry:
+ br i1 undef, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret i32 42
+
+ not_null:
+ br i1 undef, label %ret_100, label %ret_200
+
+ ret_100:
+ ret i32 100
+
+ ret_200:
+ ret i32 200
+ }
+
+ ;; Negative test. The regalloc is such that we cannot hoist the
+ ;; instruction materializing 2200000 into %eax
+ define i32 @imp_null_check_with_bitwise_op_1(i32* %x, i32 %val, i32* %ptr) {
+ entry:
+ br i1 undef, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret i32 undef
+
+ not_null:
+ br i1 undef, label %ret_100, label %ret_200
+
+ ret_100:
+ ret i32 100
+
+ ret_200:
+ ret i32 200
+ }
+
+ ;; Negative test: IR is identical to
+ ;; @imp_null_check_with_bitwise_op_0 but MIR differs.
+ define i32 @imp_null_check_with_bitwise_op_2(i32* %x, i32 %val) {
+ entry:
+ br i1 undef, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret i32 42
+
+ not_null:
+ br i1 undef, label %ret_100, label %ret_200
+
+ ret_100:
+ ret i32 100
+
+ ret_200:
+ ret i32 200
+ }
+
+ ;; Negative test: IR is identical to
+ ;; @imp_null_check_with_bitwise_op_0 but MIR differs.
+ define i32 @imp_null_check_with_bitwise_op_3(i32* %x, i32 %val) {
+ entry:
+ br i1 undef, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret i32 42
+
+ not_null:
+ br i1 undef, label %ret_100, label %ret_200
+
+ ret_100:
+ ret i32 100
+
+ ret_200:
+ ret i32 200
+ }
+
+ !0 = !{}
+...
+---
+name: imp_null_check_with_bitwise_op_0
+# CHECK-LABEL: name: imp_null_check_with_bitwise_op_0
+alignment: 4
+allVRegsAllocated: true
+tracksRegLiveness: true
+tracksSubRegLiveness: false
+liveins:
+ - { reg: '%rdi' }
+ - { reg: '%esi' }
+# CHECK: bb.0.entry:
+# CHECK: %eax = MOV32ri 2200000
+# CHECK-NEXT: %eax = FAULTING_LOAD_OP %bb.3.is_null, {{[0-9]+}}, killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
+# CHECK-NEXT: JMP_1 %bb.1.not_null
+
+body: |
+ bb.0.entry:
+ successors: %bb.3.is_null, %bb.1.not_null
+ liveins: %esi, %rdi
+
+ TEST64rr %rdi, %rdi, implicit-def %eflags
+ JE_1 %bb.3.is_null, implicit %eflags
+
+ bb.1.not_null:
+ successors: %bb.4.ret_100, %bb.2.ret_200
+ liveins: %esi, %rdi
+
+ %eax = MOV32ri 2200000
+ %eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
+ CMP32rr killed %eax, killed %esi, implicit-def %eflags
+ JE_1 %bb.4.ret_100, implicit %eflags
+
+ bb.2.ret_200:
+ %eax = MOV32ri 200
+ RET 0, %eax
+
+ bb.3.is_null:
+ %eax = MOV32ri 42
+ RET 0, %eax
+
+ bb.4.ret_100:
+ %eax = MOV32ri 100
+ RET 0, %eax
+
+...
+---
+name: imp_null_check_with_bitwise_op_1
+alignment: 4
+allVRegsAllocated: true
+isSSA: false
+tracksRegLiveness: true
+tracksSubRegLiveness: false
+liveins:
+ - { reg: '%rdi' }
+ - { reg: '%esi' }
+ - { reg: '%rdx' }
+# CHECK: bb.0.entry:
+# CHECK: %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
+# CHECK-NEXT: TEST64rr %rdi, %rdi, implicit-def %eflags
+# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
+
+body: |
+ bb.0.entry:
+ successors: %bb.3.is_null, %bb.1.not_null
+ liveins: %esi, %rdi, %rdx
+
+ %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr)
+ TEST64rr %rdi, %rdi, implicit-def %eflags
+ JE_1 %bb.3.is_null, implicit %eflags
+
+ bb.1.not_null:
+ successors: %bb.4.ret_100, %bb.2.ret_200
+ liveins: %esi, %rdi
+
+ %eax = MOV32ri 2200000
+ %eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
+ CMP32rr killed %eax, killed %esi, implicit-def %eflags
+ JE_1 %bb.4.ret_100, implicit %eflags
+
+ bb.2.ret_200:
+ successors: %bb.3.is_null
+
+ %eax = MOV32ri 200
+
+ bb.3.is_null:
+ liveins: %eax, %ah, %al, %ax, %bh, %bl, %bp, %bpl, %bx, %eax, %ebp, %ebx, %rax, %rbp, %rbx, %r12, %r13, %r14, %r15, %r12b, %r13b, %r14b, %r15b, %r12d, %r13d, %r14d, %r15d, %r12w, %r13w, %r14w, %r15w
+
+ RET 0, %eax
+
+ bb.4.ret_100:
+ %eax = MOV32ri 100
+ RET 0, %eax
+
+...
+---
+name: imp_null_check_with_bitwise_op_2
+# CHECK-LABEL: name: imp_null_check_with_bitwise_op_2
+alignment: 4
+allVRegsAllocated: true
+tracksRegLiveness: true
+tracksSubRegLiveness: false
+liveins:
+ - { reg: '%rdi' }
+ - { reg: '%esi' }
+# CHECK: bb.0.entry:
+# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
+# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
+
+body: |
+ bb.0.entry:
+ successors: %bb.3.is_null, %bb.1.not_null
+ liveins: %esi, %rdi
+
+ TEST64rr %rdi, %rdi, implicit-def %eflags
+ JE_1 %bb.3.is_null, implicit %eflags
+
+ bb.1.not_null:
+ successors: %bb.4.ret_100, %bb.2.ret_200
+ liveins: %esi, %rdi
+
+ %eax = MOV32ri 2200000
+ %eax = ADD32ri killed %eax, 100, implicit-def dead %eflags
+ %eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
+ CMP32rr killed %eax, killed %esi, implicit-def %eflags
+ JE_1 %bb.4.ret_100, implicit %eflags
+
+ bb.2.ret_200:
+ %eax = MOV32ri 200
+ RET 0, %eax
+
+ bb.3.is_null:
+ %eax = MOV32ri 42
+ RET 0, %eax
+
+ bb.4.ret_100:
+ %eax = MOV32ri 100
+ RET 0, %eax
+
+...
+---
+name: imp_null_check_with_bitwise_op_3
+# CHECK-LABEL: name: imp_null_check_with_bitwise_op_3
+alignment: 4
+allVRegsAllocated: true
+tracksRegLiveness: true
+tracksSubRegLiveness: false
+liveins:
+ - { reg: '%rdi' }
+ - { reg: '%rsi' }
+# CHECK: bb.0.entry:
+# CHECK: TEST64rr %rdi, %rdi, implicit-def %eflags
+# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
+
+body: |
+ bb.0.entry:
+ successors: %bb.3.is_null, %bb.1.not_null
+ liveins: %rsi, %rdi
+
+ TEST64rr %rdi, %rdi, implicit-def %eflags
+ JE_1 %bb.3.is_null, implicit %eflags
+
+ bb.1.not_null:
+ successors: %bb.4.ret_100, %bb.2.ret_200
+ liveins: %rsi, %rdi
+
+ %rdi = MOV64ri 5000
+ %rdi = AND64rm killed %rdi, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
+ CMP64rr killed %rdi, killed %rsi, implicit-def %eflags
+ JE_1 %bb.4.ret_100, implicit %eflags
+
+ bb.2.ret_200:
+ %eax = MOV32ri 200
+ RET 0, %eax
+
+ bb.3.is_null:
+ %eax = MOV32ri 42
+ RET 0, %eax
+
+ bb.4.ret_100:
+ %eax = MOV32ri 100
+ RET 0, %eax
+
+...
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