diff options
Diffstat (limited to 'test/CodeGen/X86/sse4a-schedule.ll')
| -rw-r--r-- | test/CodeGen/X86/sse4a-schedule.ll | 40 |
1 files changed, 35 insertions, 5 deletions
diff --git a/test/CodeGen/X86/sse4a-schedule.ll b/test/CodeGen/X86/sse4a-schedule.ll index 11afdb7989f15..9ad6b0dfd4d61 100644 --- a/test/CodeGen/X86/sse4a-schedule.ll +++ b/test/CodeGen/X86/sse4a-schedule.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mattr=+sse4a | FileCheck %s --check-prefix=GENERIC ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=BTVER2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=ZNVER1 define <2 x i64> @test_extrq(<2 x i64> %a0, <16 x i8> %a1) { ; GENERIC-LABEL: test_extrq: @@ -11,8 +11,13 @@ define <2 x i64> @test_extrq(<2 x i64> %a0, <16 x i8> %a1) { ; ; BTVER2-LABEL: test_extrq: ; BTVER2: # BB#0: -; BTVER2-NEXT: extrq %xmm1, %xmm0 +; BTVER2-NEXT: extrq %xmm1, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] +; +; ZNVER1-LABEL: test_extrq: +; ZNVER1: # BB#0: +; ZNVER1-NEXT: extrq %xmm1, %xmm0 # sched: [?:0.000000e+00] +; ZNVER1-NEXT: retq # sched: [5:0.50] %1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %a0, <16 x i8> %a1) ret <2 x i64> %1 } @@ -26,8 +31,13 @@ define <2 x i64> @test_extrqi(<2 x i64> %a0) { ; ; BTVER2-LABEL: test_extrqi: ; BTVER2: # BB#0: -; BTVER2-NEXT: extrq $2, $3, %xmm0 +; BTVER2-NEXT: extrq $2, $3, %xmm0 # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] +; +; ZNVER1-LABEL: test_extrqi: +; ZNVER1: # BB#0: +; ZNVER1-NEXT: extrq $2, $3, %xmm0 # sched: [?:0.000000e+00] +; ZNVER1-NEXT: retq # sched: [5:0.50] %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %a0, i8 3, i8 2) ret <2 x i64> %1 } @@ -41,8 +51,13 @@ define <2 x i64> @test_insertq(<2 x i64> %a0, <2 x i64> %a1) { ; ; BTVER2-LABEL: test_insertq: ; BTVER2: # BB#0: -; BTVER2-NEXT: insertq %xmm1, %xmm0 +; BTVER2-NEXT: insertq %xmm1, %xmm0 # sched: [2:2.00] ; BTVER2-NEXT: retq # sched: [4:1.00] +; +; ZNVER1-LABEL: test_insertq: +; ZNVER1: # BB#0: +; ZNVER1-NEXT: insertq %xmm1, %xmm0 # sched: [?:0.000000e+00] +; ZNVER1-NEXT: retq # sched: [5:0.50] %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %a0, <2 x i64> %a1) ret <2 x i64> %1 } @@ -56,8 +71,13 @@ define <2 x i64> @test_insertqi(<2 x i64> %a0, <2 x i64> %a1) { ; ; BTVER2-LABEL: test_insertqi: ; BTVER2: # BB#0: -; BTVER2-NEXT: insertq $6, $5, %xmm1, %xmm0 +; BTVER2-NEXT: insertq $6, $5, %xmm1, %xmm0 # sched: [2:2.00] ; BTVER2-NEXT: retq # sched: [4:1.00] +; +; ZNVER1-LABEL: test_insertqi: +; ZNVER1: # BB#0: +; ZNVER1-NEXT: insertq $6, $5, %xmm1, %xmm0 # sched: [?:0.000000e+00] +; ZNVER1-NEXT: retq # sched: [5:0.50] %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %a0, <2 x i64> %a1, i8 5, i8 6) ret <2 x i64> %1 } @@ -73,6 +93,11 @@ define void @test_movntsd(i8* %p, <2 x double> %a) { ; BTVER2: # BB#0: ; BTVER2-NEXT: movntsd %xmm0, (%rdi) # sched: [1:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00] +; +; ZNVER1-LABEL: test_movntsd: +; ZNVER1: # BB#0: +; ZNVER1-NEXT: movntsd %xmm0, (%rdi) # sched: [1:0.50] +; ZNVER1-NEXT: retq # sched: [5:0.50] tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) ret void } @@ -88,6 +113,11 @@ define void @test_movntss(i8* %p, <4 x float> %a) { ; BTVER2: # BB#0: ; BTVER2-NEXT: movntss %xmm0, (%rdi) # sched: [1:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00] +; +; ZNVER1-LABEL: test_movntss: +; ZNVER1: # BB#0: +; ZNVER1-NEXT: movntss %xmm0, (%rdi) # sched: [1:0.50] +; ZNVER1-NEXT: retq # sched: [5:0.50] tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) ret void } |