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-rw-r--r--test/CodeGen/X86/vec_minmax_match.ll77
1 files changed, 64 insertions, 13 deletions
diff --git a/test/CodeGen/X86/vec_minmax_match.ll b/test/CodeGen/X86/vec_minmax_match.ll
index af4410a898e3c..98f77912779f9 100644
--- a/test/CodeGen/X86/vec_minmax_match.ll
+++ b/test/CodeGen/X86/vec_minmax_match.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
; These are actually tests of ValueTracking, and so may have test coverage in InstCombine or other
@@ -11,7 +11,6 @@ define <4 x i32> @smin_vec1(<4 x i32> %x) {
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%cmp = icmp sgt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -25,7 +24,6 @@ define <4 x i32> @smin_vec2(<4 x i32> %x) {
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %not_x
@@ -41,7 +39,6 @@ define <4 x i32> @smin_vec3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp sgt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub
@@ -57,7 +54,6 @@ define <4 x i32> @smin_vec4(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp slt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer
@@ -71,7 +67,6 @@ define <4 x i32> @smax_vec1(<4 x i32> %x) {
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -85,7 +80,6 @@ define <4 x i32> @smax_vec2(<4 x i32> %x) {
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%cmp = icmp sgt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %not_x
@@ -101,7 +95,6 @@ define <4 x i32> @smax_vec3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp slt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub
@@ -117,7 +110,6 @@ define <4 x i32> @smax_vec4(<4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp sgt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer
@@ -129,7 +121,6 @@ define <4 x i32> @umax_vec1(<4 x i32> %x) {
; CHECK: # BB#0:
; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
ret <4 x i32> %sel
@@ -140,7 +131,6 @@ define <4 x i32> @umax_vec2(<4 x i32> %x) {
; CHECK: # BB#0:
; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>, <4 x i32> %x
ret <4 x i32> %sel
@@ -151,7 +141,6 @@ define <4 x i32> @umin_vec1(<4 x i32> %x) {
; CHECK: # BB#0:
; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %x
ret <4 x i32> %sel
@@ -162,9 +151,71 @@ define <4 x i32> @umin_vec2(<4 x i32> %x) {
; CHECK: # BB#0:
; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
-;
%cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
ret <4 x i32> %sel
}
+; The next 4 tests are value clamping with constants:
+; https://llvm.org/bugs/show_bug.cgi?id=31693
+
+; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)
+
+define <4 x i32> @clamp_signed1(<4 x i32> %x) {
+; CHECK-LABEL: clamp_signed1:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %cmp2 = icmp slt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
+ %min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>
+ %cmp1 = icmp slt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
+ %r = select <4 x i1> %cmp1, <4 x i32><i32 15, i32 15, i32 15, i32 15>, <4 x i32> %min
+ ret <4 x i32> %r
+}
+
+; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)
+
+define <4 x i32> @clamp_signed2(<4 x i32> %x) {
+; CHECK-LABEL: clamp_signed2:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %cmp2 = icmp sgt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
+ %max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>
+ %cmp1 = icmp sgt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
+ %r = select <4 x i1> %cmp1, <4 x i32><i32 255, i32 255, i32 255, i32 255>, <4 x i32> %max
+ ret <4 x i32> %r
+}
+
+; (X <u C1) ? C1 : UMIN(X, C2) ==> UMAX(UMIN(X, C2), C1)
+
+define <4 x i32> @clamp_unsigned1(<4 x i32> %x) {
+; CHECK-LABEL: clamp_unsigned1:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %cmp2 = icmp ult <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
+ %min = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 255, i32 255, i32 255, i32 255>
+ %cmp1 = icmp ult <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
+ %r = select <4 x i1> %cmp1, <4 x i32><i32 15, i32 15, i32 15, i32 15>, <4 x i32> %min
+ ret <4 x i32> %r
+}
+
+; (X >u C1) ? C1 : UMAX(X, C2) ==> UMIN(UMAX(X, C2), C1)
+
+define <4 x i32> @clamp_unsigned2(<4 x i32> %x) {
+; CHECK-LABEL: clamp_unsigned2:
+; CHECK: # BB#0:
+; CHECK-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %cmp2 = icmp ugt <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
+ %max = select <4 x i1> %cmp2, <4 x i32> %x, <4 x i32><i32 15, i32 15, i32 15, i32 15>
+ %cmp1 = icmp ugt <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
+ %r = select <4 x i1> %cmp1, <4 x i32><i32 255, i32 255, i32 255, i32 255>, <4 x i32> %max
+ ret <4 x i32> %r
+}
+
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 08:48:19 +0000