diff options
Diffstat (limited to 'test/CodeGen/X86')
250 files changed, 12276 insertions, 1105 deletions
diff --git a/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll index 0af2445d7fbae..2e4cb1fe7eda0 100644 --- a/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll +++ b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; The old instruction selector used to load all arguments to a call up in ; registers, then start pushing them all onto the stack. This is bad news as ; it makes a ton of annoying overlapping live ranges. This code should not diff --git a/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll b/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll index 1a3d74918d1a6..7673124d5dda9 100644 --- a/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll +++ b/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | \ ; RUN: grep asm-printer | grep 7 diff --git a/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll index 5cba3efeefb87..faa3e21a934d7 100644 --- a/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll +++ b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mcpu=yonah -stats 2>&1 | \ ; RUN: not grep "Number of register spills" ; END. diff --git a/test/CodeGen/X86/2006-05-02-InstrSched1.ll b/test/CodeGen/X86/2006-05-02-InstrSched1.ll index 1c75f93915a7d..0afddd8f876f2 100644 --- a/test/CodeGen/X86/2006-05-02-InstrSched1.ll +++ b/test/CodeGen/X86/2006-05-02-InstrSched1.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -relocation-model=static -stats 2>&1 | \ ; RUN: grep asm-printer | grep 14 ; diff --git a/test/CodeGen/X86/2006-05-02-InstrSched2.ll b/test/CodeGen/X86/2006-05-02-InstrSched2.ll index 95eefa1e7196f..222b7a0b41fd4 100644 --- a/test/CodeGen/X86/2006-05-02-InstrSched2.ll +++ b/test/CodeGen/X86/2006-05-02-InstrSched2.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | \ ; RUN: grep asm-printer | grep 13 diff --git a/test/CodeGen/X86/2006-05-11-InstrSched.ll b/test/CodeGen/X86/2006-05-11-InstrSched.ll index 37c510786a5e1..6912351d7b7e1 100644 --- a/test/CodeGen/X86/2006-05-11-InstrSched.ll +++ b/test/CodeGen/X86/2006-05-11-InstrSched.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=+sse2 -stats -realign-stack=0 2>&1 | \ ; RUN: grep "asm-printer" | grep 35 diff --git a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll index a1b973d7ccfa6..363a6008a00de 100644 --- a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll +++ b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mcpu=yonah -stats 2>&1 | grep "Number of block tails merged" | grep 16 ; PR1909 diff --git a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll index 19a73543c65e6..fc38135032c2b 100644 --- a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll +++ b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movups | count 2 +; RUN: llc < %s -march=x86 -mcpu=penryn | FileCheck %s define void @a(<4 x float>* %x) nounwind { entry: @@ -8,4 +8,10 @@ entry: ret void } +; CHECK: a: +; CHECK: movups +; CHECK: movups +; CHECK-NOT: movups +; CHECK: ret + declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll index d423bfc389df9..496779c468f42 100644 --- a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll +++ b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll @@ -1,10 +1,15 @@ ; Check that eh_return & unwind_init were properly lowered -; RUN: llc < %s | grep %rbp | count 7 -; RUN: llc < %s | grep %rcx | count 3 +; RUN: llc < %s -verify-machineinstrs | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" +; CHECK: test +; CHECK: pushq %rbp +; CHECK: movq %rsp, %rbp +; CHECK: popq %rbp +; CHECK: movq %rcx, %rsp +; CHECK: ret # eh_return, addr: %rcx define i8* @test(i64 %a, i8* %b) { entry: call void @llvm.eh.unwind.init() @@ -15,3 +20,36 @@ entry: declare void @llvm.eh.return.i64(i64, i8*) declare void @llvm.eh.unwind.init() + +@b = common global i32 0, align 4 +@a = common global i32 0, align 4 + +; PR14750 +; This function contains a normal return as well as eh_return. +; CHECK: _Unwind_Resume_or_Rethrow +define i32 @_Unwind_Resume_or_Rethrow() nounwind uwtable ssp { +entry: + %0 = load i32* @b, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + ret i32 0 + +if.end: ; preds = %entry + %call = tail call i32 (...)* @_Unwind_ForcedUnwind_Phase2() nounwind + store i32 %call, i32* @a, align 4 + %tobool1 = icmp eq i32 %call, 0 + br i1 %tobool1, label %cond.end, label %cond.true + +cond.true: ; preds = %if.end + tail call void @abort() noreturn nounwind + unreachable + +cond.end: ; preds = %if.end + tail call void @llvm.eh.return.i64(i64 0, i8* null) + unreachable +} + +declare i32 @_Unwind_ForcedUnwind_Phase2(...) +declare void @abort() noreturn diff --git a/test/CodeGen/X86/2008-10-27-CoalescerBug.ll b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll index b2cf34cd2033b..0310a5dcb565b 100644 --- a/test/CodeGen/X86/2008-10-27-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -stats 2>&1 | FileCheck %s ; Now this test spills one register. But a reload in the loop is cheaper than ; the divsd so it's a win. diff --git a/test/CodeGen/X86/2008-10-27-StackRealignment.ll b/test/CodeGen/X86/2008-10-27-StackRealignment.ll deleted file mode 100644 index a57f7166cadc4..0000000000000 --- a/test/CodeGen/X86/2008-10-27-StackRealignment.ll +++ /dev/null @@ -1,22 +0,0 @@ -; Linux doesn't support stack realignment for functions with allocas (PR2888). -; Until it does, we shouldn't use movaps to access the stack. On targets with -; sufficiently aligned stack (e.g. darwin) we should. -; PR8969 - make 32-bit linux have a 16-byte aligned stack -; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mcpu=yonah | grep movaps | count 2 -; RUN: llc < %s -mtriple=i686-apple-darwin9 -mcpu=yonah | grep movaps | count 2 - - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i386-pc-linux-gnu" - -define void @foo(i32 %t) nounwind { - %tmp1210 = alloca i8, i32 32, align 4 - call void @llvm.memset.p0i8.i64(i8* %tmp1210, i8 0, i64 32, i32 4, i1 false) - %x = alloca i8, i32 %t - call void @dummy(i8* %x) - ret void -} - -declare void @dummy(i8*) - -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll index 0dca14d064eb1..890fd0f067cfe 100644 --- a/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll +++ b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll @@ -78,7 +78,7 @@ declare void @llvm.stackrestore(i8*) nounwind !9 = metadata !{i32 458767, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !10} ; [ DW_TAG_pointer_type ] !10 = metadata !{i32 458753, metadata !2, metadata !"", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, metadata !5, metadata !11, i32 0, null} ; [ DW_TAG_array_type ] !11 = metadata !{metadata !12} -!12 = metadata !{i32 458785, i64 0, i64 0} ; [ DW_TAG_subrange_type ] +!12 = metadata !{i32 458785, i64 0, i64 1} ; [ DW_TAG_subrange_type ] !13 = metadata !{i32 3, i32 0, metadata !14, null} !14 = metadata !{i32 458763, metadata !1, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !15 = metadata !{i32 4, i32 0, metadata !14, null} diff --git a/test/CodeGen/X86/2009-02-25-CommuteBug.ll b/test/CodeGen/X86/2009-02-25-CommuteBug.ll index 9cbf350940613..9ea34e27a17ee 100644 --- a/test/CodeGen/X86/2009-02-25-CommuteBug.ll +++ b/test/CodeGen/X86/2009-02-25-CommuteBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -stats 2>&1 | not grep commuted ; rdar://6608609 diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll index d50fe6f73a004..68a9fafb6de83 100644 --- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn -stats 2>&1 | grep "5 machine-licm" ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn | FileCheck %s ; rdar://6627786 diff --git a/test/CodeGen/X86/2009-03-23-MultiUseSched.ll b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll index d934ec9a88f8d..351a1722a231e 100644 --- a/test/CodeGen/X86/2009-03-23-MultiUseSched.ll +++ b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static -o /dev/null -stats -info-output-file - > %t ; RUN: not grep spill %t ; RUN: not grep "%rsp" %t diff --git a/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll index ad18a0c5b94d4..0607eda271afa 100644 --- a/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll +++ b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats 2>&1 | grep "Number of modref unfolded" ; XFAIL: * ; 69408 removed the opportunity for this optimization to work diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll index 94075e78a28ae..c2d9d84d4c5a1 100644 --- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll +++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll @@ -6,15 +6,16 @@ define void @t(i32 %count) ssp nounwind { entry: ; CHECK: t: -; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip) -; CHECK: movups L_str(%rip), %xmm0 +; CHECK: movups L_str+12(%rip), %xmm0 +; CHECK: movups L_str(%rip), %xmm1 %tmp0 = alloca [60 x i8], align 1 %tmp1 = getelementptr inbounds [60 x i8]* %tmp0, i64 0, i64 0 br label %bb1 bb1: ; CHECK: LBB0_1: -; CHECK: movaps %xmm0, (%rsp) +; CHECK: movups %xmm0, 12(%rsp) +; CHECK: movaps %xmm1, (%rsp) %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ] call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1, i1 false) %tmp3 = add i32 %tmp2, 1 diff --git a/test/CodeGen/X86/2010-01-18-DbgValue.ll b/test/CodeGen/X86/2010-01-18-DbgValue.ll index 85ee091c34789..7dba332b1becc 100644 --- a/test/CodeGen/X86/2010-01-18-DbgValue.ll +++ b/test/CodeGen/X86/2010-01-18-DbgValue.ll @@ -28,21 +28,25 @@ return: ; preds = %entry declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone -!0 = metadata !{i32 524545, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 524329, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!llvm.dbg.cu = !{!3} + +!0 = metadata !{i32 786689, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !7} -!6 = metadata !{i32 524324, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 524307, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] +!6 = metadata !{i32 786468, metadata !19, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Rect", i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] !8 = metadata !{metadata !9, metadata !14} -!9 = metadata !{i32 524301, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] -!10 = metadata !{i32 524307, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!9 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P1", i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Pt", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] !11 = metadata !{metadata !12, metadata !13} -!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] -!13 = metadata !{i32 524301, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] -!14 = metadata !{i32 524301, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] +!12 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"x", i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"y", i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!14 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P2", i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] !15 = metadata !{i32 11, i32 0, metadata !1, null} !16 = metadata !{i32 12, i32 0, metadata !17, null} -!17 = metadata !{i32 524299, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] +!17 = metadata !{i32 786443, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] +!18 = metadata !{metadata !1} +!19 = metadata !{metadata !"b2.c", metadata !"/tmp/"} diff --git a/test/CodeGen/X86/2010-01-19-OptExtBug.ll b/test/CodeGen/X86/2010-01-19-OptExtBug.ll index eb4a5c04a2ae5..ec24e73c34acc 100644 --- a/test/CodeGen/X86/2010-01-19-OptExtBug.ll +++ b/test/CodeGen/X86/2010-01-19-OptExtBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -relocation-model=pic -disable-fp-elim -stats 2>&1 | not grep ext-opt define fastcc i8* @S_scan_str(i8* %start, i32 %keep_quoted, i32 %keep_delims) nounwind ssp { diff --git a/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll deleted file mode 100644 index 42f19b3ad86ab..0000000000000 --- a/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc -O0 -march=x86 -asm-verbose < %s | FileCheck %s -; RUN: llc -O0 -march=x86-64 -asm-verbose < %s | FileCheck %s -; Check that DEBUG_VALUE comments come through on a variety of targets. - -define i32 @main() nounwind ssp { -entry: -; CHECK: DEBUG_VALUE - call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 - ret i32 0, !dbg !10 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone - -!llvm.dbg.sp = !{!0} - -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 0} -!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!9 = metadata !{i32 3, i32 11, metadata !8, null} -!10 = metadata !{i32 4, i32 2, metadata !8, null} diff --git a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll index 2fceab6f091fc..8ab93fcb978f0 100644 --- a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll @@ -198,27 +198,27 @@ declare float @copysignf(float, float) nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.lv = !{!0, !11, !12, !13, !14, !16, !17, !18} +!llvm.dbg.cu = !{!3} -!0 = metadata !{i32 524545, metadata !1, metadata !"a", metadata !2, i32 1921, metadata !9} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"__divsc3", metadata !"__divsc3", metadata !"__divsc3", metadata !2, i32 1922, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 524329, metadata !"libgcc2.c", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"libgcc2.c", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 786478, metadata !2, metadata !"__divsc3", metadata !"__divsc3", metadata !"__divsc3", metadata !2, i32 1922, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, %0 (float, float, float, float)* @__divsc3, null, null, metadata !43, i32 1922} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !45} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !44, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !45, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !9, metadata !9, metadata !9, metadata !9} -!6 = metadata !{i32 524310, metadata !7, metadata !"SCtype", metadata !7, i32 170, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] -!7 = metadata !{i32 524329, metadata !"libgcc2.h", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc", metadata !3} ; [ DW_TAG_file_type ] -!8 = metadata !{i32 524324, metadata !2, metadata !"complex float", metadata !2, i32 0, i64 64, i64 32, i64 0, i32 0, i32 3} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 524310, metadata !7, metadata !"SFtype", metadata !7, i32 167, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] -!10 = metadata !{i32 524324, metadata !2, metadata !"float", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!11 = metadata !{i32 524545, metadata !1, metadata !"b", metadata !2, i32 1921, metadata !9} ; [ DW_TAG_arg_variable ] -!12 = metadata !{i32 524545, metadata !1, metadata !"c", metadata !2, i32 1921, metadata !9} ; [ DW_TAG_arg_variable ] -!13 = metadata !{i32 524545, metadata !1, metadata !"d", metadata !2, i32 1921, metadata !9} ; [ DW_TAG_arg_variable ] -!14 = metadata !{i32 524544, metadata !15, metadata !"denom", metadata !2, i32 1923, metadata !9} ; [ DW_TAG_auto_variable ] -!15 = metadata !{i32 524299, metadata !1, i32 1922, i32 0} ; [ DW_TAG_lexical_block ] -!16 = metadata !{i32 524544, metadata !15, metadata !"ratio", metadata !2, i32 1923, metadata !9} ; [ DW_TAG_auto_variable ] -!17 = metadata !{i32 524544, metadata !15, metadata !"x", metadata !2, i32 1923, metadata !9} ; [ DW_TAG_auto_variable ] -!18 = metadata !{i32 524544, metadata !15, metadata !"y", metadata !2, i32 1923, metadata !9} ; [ DW_TAG_auto_variable ] +!6 = metadata !{i32 786454, metadata !46, metadata !7, metadata !"SCtype", i32 170, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 786473, metadata !46} ; [ DW_TAG_file_type ] +!8 = metadata !{i32 786468, metadata !45, metadata !2, metadata !"complex float", i32 0, i64 64, i64 32, i64 0, i32 0, i32 3} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 786454, metadata !46, metadata !7, metadata !"SFtype", i32 167, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] +!10 = metadata !{i32 786468, metadata !45, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!11 = metadata !{i32 786689, metadata !1, metadata !"b", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] +!12 = metadata !{i32 786689, metadata !1, metadata !"c", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] +!13 = metadata !{i32 786689, metadata !1, metadata !"d", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] +!14 = metadata !{i32 786688, metadata !15, metadata !"denom", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] +!15 = metadata !{i32 786443, metadata !2, metadata !1, i32 1922, i32 0} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786688, metadata !15, metadata !"ratio", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] +!17 = metadata !{i32 786688, metadata !15, metadata !"x", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] +!18 = metadata !{i32 786688, metadata !15, metadata !"y", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] !19 = metadata !{i32 1929, i32 0, metadata !15, null} !20 = metadata !{i32 1931, i32 0, metadata !15, null} !21 = metadata !{i32 1932, i32 0, metadata !15, null} @@ -243,3 +243,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !40 = metadata !{i32 1964, i32 0, metadata !15, null} !41 = metadata !{i32 1965, i32 0, metadata !15, null} !42 = metadata !{i32 1969, i32 0, metadata !15, null} +!43 = metadata !{metadata !0, metadata !11, metadata !12, metadata !13, metadata !14, metadata !16, metadata !17, metadata !18} +!44 = metadata !{metadata !1} +!45 = metadata !{metadata !"libgcc2.c", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"} +!46 = metadata !{metadata !"libgcc2.h", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"} diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll index 7909d2736b9c3..6519ca063a7c4 100644 --- a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll @@ -21,40 +21,45 @@ declare void @foo(i32) nounwind optsize noinline ssp declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.gv = !{!0} -!llvm.dbg.lv = !{!4, !8, !18, !25, !26} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 524340, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 7, metadata !3, i1 false, i1 true, null} ; [ DW_TAG_variable ] -!1 = metadata !{i32 524329, metadata !"foo.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!4 = metadata !{i32 524545, metadata !5, metadata !"x", metadata !1, i32 12, metadata !3} ; [ DW_TAG_arg_variable ] -!5 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!6 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786484, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 7, metadata !3, i1 false, i1 true, null} ; [ DW_TAG_variable ] +!1 = metadata !{i32 786473, metadata !36} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !36, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !32, metadata !31, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!4 = metadata !{i32 786689, metadata !5, metadata !"x", metadata !1, i32 12, metadata !3, i32 0, null} ; [ DW_TAG_arg_variable ] +!5 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void (i32)* @foo, null, null, metadata !33, i32 13} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] !7 = metadata !{null, metadata !3} -!8 = metadata !{i32 524545, metadata !9, metadata !"myvar", metadata !1, i32 17, metadata !13} ; [ DW_TAG_arg_variable ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 17, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!8 = metadata !{i32 786689, metadata !9, metadata !"myvar", metadata !1, i32 17, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 17, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i8* (%struct.a*)* @bar, null, null, metadata !34, i32 17} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{metadata !12, metadata !13} -!12 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] -!13 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] -!14 = metadata !{i32 524307, metadata !1, metadata !"a", metadata !1, i32 2, i64 128, i64 64, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_structure_type ] +!12 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!13 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 786451, metadata !1, metadata !"a", metadata !1, i32 2, i64 128, i64 64, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_structure_type ] !15 = metadata !{metadata !16, metadata !17} -!16 = metadata !{i32 524301, metadata !14, metadata !"c", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !3} ; [ DW_TAG_member ] -!17 = metadata !{i32 524301, metadata !14, metadata !"d", metadata !1, i32 4, i64 64, i64 64, i64 64, i32 0, metadata !13} ; [ DW_TAG_member ] -!18 = metadata !{i32 524545, metadata !19, metadata !"argc", metadata !1, i32 22, metadata !3} ; [ DW_TAG_arg_variable ] -!19 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 22, metadata !20, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!20 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !21, i32 0, null} ; [ DW_TAG_subroutine_type ] +!16 = metadata !{i32 786445, metadata !14, metadata !"c", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !3} ; [ DW_TAG_member ] +!17 = metadata !{i32 786445, metadata !14, metadata !"d", metadata !1, i32 4, i64 64, i64 64, i64 64, i32 0, metadata !13} ; [ DW_TAG_member ] +!18 = metadata !{i32 786689, metadata !19, metadata !"argc", metadata !1, i32 22, metadata !3, i32 0, null} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 22, metadata !20, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !35, i32 22} ; [ DW_TAG_subprogram ] +!20 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !21, i32 0, null} ; [ DW_TAG_subroutine_type ] !21 = metadata !{metadata !3, metadata !3, metadata !22} -!22 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] -!23 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !24} ; [ DW_TAG_pointer_type ] -!24 = metadata !{i32 524324, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] -!25 = metadata !{i32 524545, metadata !19, metadata !"argv", metadata !1, i32 22, metadata !22} ; [ DW_TAG_arg_variable ] -!26 = metadata !{i32 524544, metadata !27, metadata !"e", metadata !1, i32 23, metadata !14} ; [ DW_TAG_auto_variable ] -!27 = metadata !{i32 524299, metadata !19, i32 22, i32 0} ; [ DW_TAG_lexical_block ] +!22 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !24} ; [ DW_TAG_pointer_type ] +!24 = metadata !{i32 786468, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!25 = metadata !{i32 786689, metadata !19, metadata !"argv", metadata !1, i32 22, metadata !22, i32 0, null} ; [ DW_TAG_arg_variable ] +!26 = metadata !{i32 786688, metadata !27, metadata !"e", metadata !1, i32 23, metadata !14, i32 0, null} ; [ DW_TAG_auto_variable ] +!27 = metadata !{i32 786443, metadata !36, metadata !19, i32 22, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !28 = metadata !{i32 18, i32 0, metadata !29, null} -!29 = metadata !{i32 524299, metadata !9, i32 17, i32 0} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 786443, metadata !36, metadata !9, i32 17, i32 0, i32 1} ; [ DW_TAG_lexical_block ] !30 = metadata !{i32 19, i32 0, metadata !29, null} +!31 = metadata !{metadata !0} +!32 = metadata !{metadata !5, metadata !9, metadata !19} +!33 = metadata !{metadata !4} +!34 = metadata !{metadata !8} +!35 = metadata !{metadata !18, metadata !25, metadata !26} +!36 = metadata !{metadata !"foo.c", metadata !"/tmp/"} ; The variable bar:myvar changes registers after the first movq. ; It is cobbered by popq %rbx @@ -79,4 +84,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone ; CHECK-NEXT: .short Lset{{.*}} ; CHECK-NEXT: Ltmp{{.*}}: ; CHECK-NEXT: .byte 83 -; CHECK-NEXT: Ltmp{{.*}}:
\ No newline at end of file +; CHECK-NEXT: Ltmp{{.*}}: diff --git a/test/CodeGen/X86/2010-05-28-Crash.ll b/test/CodeGen/X86/2010-05-28-Crash.ll index 1a0da3177a229..4ea3bf077841a 100644 --- a/test/CodeGen/X86/2010-05-28-Crash.ll +++ b/test/CodeGen/X86/2010-05-28-Crash.ll @@ -22,23 +22,27 @@ entry: ret i32 %1, !dbg !13 } -!llvm.dbg.lv = !{!0, !7} +!llvm.dbg.cu = !{!3} -!0 = metadata !{i32 524545, metadata !1, metadata !"y", metadata !2, i32 2, metadata !6} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 524329, metadata !"f.c", metadata !"/tmp", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"f.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786689, metadata !1, metadata !"y", metadata !2, i32 2, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo, null, null, metadata !15, i32 2} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !17, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !6} -!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 524545, metadata !8, metadata !"x", metadata !2, i32 6, metadata !6} ; [ DW_TAG_arg_variable ] -!8 = metadata !{i32 524334, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 6, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786689, metadata !8, metadata !"x", metadata !2, i32 6, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 786478, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 6, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @bar, null, null, metadata !16, i32 6} ; [ DW_TAG_subprogram ] !9 = metadata !{i32 3, i32 0, metadata !10, null} -!10 = metadata !{i32 524299, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 786443, metadata !2, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ] !11 = metadata !{i32 1} !12 = metadata !{i32 3, i32 0, metadata !10, metadata !13} !13 = metadata !{i32 7, i32 0, metadata !14, null} -!14 = metadata !{i32 524299, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] +!14 = metadata !{i32 786443, metadata !2, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] +!15 = metadata !{metadata !0} +!16 = metadata !{metadata !7} +!17 = metadata !{metadata !1, metadata !8} +!18 = metadata !{metadata !"f.c", metadata !"/tmp"} ;CHECK: DEBUG_VALUE: bar:x <- E ;CHECK: Ltmp diff --git a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll index a9c03ee563d88..b764b0b345977 100644 --- a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll +++ b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll @@ -21,34 +21,35 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.lv = !{!0, !14, !15, !16, !17, !24, !25, !28} -!0 = metadata !{i32 524545, metadata !1, metadata !"this", metadata !3, i32 11, metadata !12} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEi", metadata !3, i32 11, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 524307, metadata !3, metadata !"foo", metadata !3, i32 3, i64 32, i64 32, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{i32 524329, metadata !"foo.cp", metadata !"/tmp/", metadata !4} ; [ DW_TAG_file_type ] -!4 = metadata !{i32 524305, i32 0, i32 4, metadata !"foo.cp", metadata !"/tmp/", metadata !"4.2.1 LLVM build", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786689, metadata !1, metadata !"this", metadata !3, i32 11, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 786478, metadata !3, metadata !2, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEi", i32 11, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786451, metadata !3, metadata !"foo", metadata !3, i32 3, i64 32, i64 32, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{i32 786473, metadata !31} ; [ DW_TAG_file_type ] +!4 = metadata !{i32 786449, i32 0, i32 4, metadata !"foo.cp", metadata !"/tmp/", metadata !"4.2.1 LLVM build", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] !5 = metadata !{metadata !6, metadata !1, metadata !8} -!6 = metadata !{i32 524301, metadata !2, metadata !"y", metadata !3, i32 8, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_member ] -!7 = metadata !{i32 524324, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!8 = metadata !{i32 524334, i32 0, metadata !2, metadata !"baz", metadata !"baz", metadata !"_ZN3foo3bazEi", metadata !3, i32 15, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_subroutine_type ] +!6 = metadata !{i32 786445, metadata !2, metadata !"y", metadata !3, i32 8, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_member ] +!7 = metadata !{i32 786468, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 786478, metadata !3, metadata !2, metadata !"baz", metadata !"baz", metadata !"_ZN3foo3bazEi", i32 15, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 15} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_subroutine_type ] !10 = metadata !{metadata !7, metadata !11, metadata !7} -!11 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !2} ; [ DW_TAG_pointer_type ] -!12 = metadata !{i32 524326, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !13} ; [ DW_TAG_const_type ] -!13 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_pointer_type ] -!14 = metadata !{i32 524545, metadata !1, metadata !"x", metadata !3, i32 11, metadata !7} ; [ DW_TAG_arg_variable ] -!15 = metadata !{i32 524545, metadata !8, metadata !"this", metadata !3, i32 15, metadata !12} ; [ DW_TAG_arg_variable ] -!16 = metadata !{i32 524545, metadata !8, metadata !"x", metadata !3, i32 15, metadata !7} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 524545, metadata !18, metadata !"argc", metadata !3, i32 19, metadata !7} ; [ DW_TAG_arg_variable ] -!18 = metadata !{i32 524334, i32 0, metadata !3, metadata !"main", metadata !"main", metadata !"main", metadata !3, i32 19, metadata !19, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true} ; [ DW_TAG_subprogram ] -!19 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !20, i32 0, null} ; [ DW_TAG_subroutine_type ] +!11 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !2} ; [ DW_TAG_pointer_type ] +!12 = metadata !{i32 786470, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !13} ; [ DW_TAG_const_type ] +!13 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !3, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] +!15 = metadata !{i32 786689, metadata !8, metadata !"this", metadata !3, i32 15, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ] +!16 = metadata !{i32 786689, metadata !8, metadata !"x", metadata !3, i32 15, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 786689, metadata !18, metadata !"argc", metadata !3, i32 19, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 786478, metadata !3, metadata !3, metadata !"main", metadata !"main", metadata !"main", i32 19, metadata !19, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, null, null, null, null, i32 19} ; [ DW_TAG_subprogram ] +!19 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !20, i32 0, null} ; [ DW_TAG_subroutine_type ] !20 = metadata !{metadata !7, metadata !7, metadata !21} -!21 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] -!22 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] -!23 = metadata !{i32 524324, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] -!24 = metadata !{i32 524545, metadata !18, metadata !"argv", metadata !3, i32 19, metadata !21} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 524544, metadata !26, metadata !"a", metadata !3, i32 20, metadata !2} ; [ DW_TAG_auto_variable ] -!26 = metadata !{i32 524299, metadata !27, i32 19, i32 0} ; [ DW_TAG_lexical_block ] -!27 = metadata !{i32 524299, metadata !18, i32 19, i32 0} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 524544, metadata !26, metadata !"b", metadata !3, i32 21, metadata !7} ; [ DW_TAG_auto_variable ] +!21 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] +!22 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 786468, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!24 = metadata !{i32 786689, metadata !18, metadata !"argv", metadata !3, i32 19, metadata !21, i32 0, null} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 786688, metadata !26, metadata !"a", metadata !3, i32 20, metadata !2, i32 0, null} ; [ DW_TAG_auto_variable ] +!26 = metadata !{i32 786443, metadata !27, i32 19, i32 0} ; [ DW_TAG_lexical_block ] +!27 = metadata !{i32 786443, metadata !18, i32 19, i32 0} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786688, metadata !26, metadata !"b", metadata !3, i32 21, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ] !29 = metadata !{i32 16, i32 0, metadata !30, null} -!30 = metadata !{i32 524299, metadata !8, i32 15, i32 0} ; [ DW_TAG_lexical_block ] +!30 = metadata !{i32 786443, metadata !8, i32 15, i32 0} ; [ DW_TAG_lexical_block ] +!31 = metadata !{metadata !"foo.cp", metadata !"/tmp/"} diff --git a/test/CodeGen/X86/2010-07-06-DbgCrash.ll b/test/CodeGen/X86/2010-07-06-DbgCrash.ll index edd6015b0d280..208e93e098e6e 100644 --- a/test/CodeGen/X86/2010-07-06-DbgCrash.ll +++ b/test/CodeGen/X86/2010-07-06-DbgCrash.ll @@ -16,7 +16,7 @@ !103 = metadata !{i32 524299, metadata !97, i32 73, i32 0} ; [ DW_TAG_lexical_block ] !104 = metadata !{i32 524289, metadata !38, metadata !"", metadata !38, i32 0, i64 85312, i64 64, i64 0, i32 0, metadata !46, metadata !105, i32 0, null} ; [ DW_TAG_array_type ] !105 = metadata !{metadata !106} -!106 = metadata !{i32 524321, i64 0, i64 1332} ; [ DW_TAG_subrange_type ] +!106 = metadata !{i32 524321, i64 0, i64 1333} ; [ DW_TAG_subrange_type ] !107 = metadata !{i32 73, i32 0, metadata !103, null} define i32 @main() nounwind ssp { diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll index ba36fe7c12fd3..aaa562a439d53 100644 --- a/test/CodeGen/X86/2010-08-04-StackVariable.ll +++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll @@ -74,51 +74,52 @@ return: ; preds = %entry declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.sp = !{!0, !9, !16, !17, !20} +!llvm.dbg.cu = !{!3} +!46 = metadata !{metadata !0, metadata !9, metadata !16, metadata !17, metadata !20} -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524307, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] -!2 = metadata !{i32 524329, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 524305, i32 0, i32 4, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] +!2 = metadata !{i32 786473, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !46, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} -!5 = metadata !{i32 524301, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] -!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] -!7 = metadata !{i32 524301, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] -!8 = metadata !{i32 524324, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 786445, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] +!8 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 786478, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 12} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{null, metadata !12, metadata !13} -!12 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] -!13 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] +!13 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] !15 = metadata !{null, metadata !12} -!16 = metadata !{i32 524334, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ] -!17 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ] -!18 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] +!16 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null, i32 16} ; [ DW_TAG_subprogram ] +!18 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] !19 = metadata !{metadata !13, metadata !13, metadata !1} -!20 = metadata !{i32 524334, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!21 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] +!20 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main, null, null, null, i32 23} ; [ DW_TAG_subprogram ] +!21 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] !22 = metadata !{metadata !13} -!23 = metadata !{i32 524545, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13} ; [ DW_TAG_arg_variable ] +!23 = metadata !{i32 786689, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] !24 = metadata !{i32 16, i32 0, metadata !17, null} -!25 = metadata !{i32 524545, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26} ; [ DW_TAG_arg_variable ] -!26 = metadata !{i32 524304, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] +!25 = metadata !{i32 786689, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26, i32 0, null} ; [ DW_TAG_arg_variable ] +!26 = metadata !{i32 786448, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] !27 = metadata !{i32 17, i32 0, metadata !28, null} -!28 = metadata !{i32 524299, metadata !17, i32 16, i32 0, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786443, metadata !2, metadata !17, i32 16, i32 0, i32 2} ; [ DW_TAG_lexical_block ] !29 = metadata !{i32 18, i32 0, metadata !28, null} !30 = metadata !{i32 20, i32 0, metadata !28, null} -!31 = metadata !{i32 524545, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32} ; [ DW_TAG_arg_variable ] -!32 = metadata !{i32 524326, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ] -!33 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] +!31 = metadata !{i32 786689, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32, i32 0, null} ; [ DW_TAG_arg_variable ] +!32 = metadata !{i32 786470, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ] +!33 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] !34 = metadata !{i32 11, i32 0, metadata !16, null} !35 = metadata !{i32 11, i32 0, metadata !36, null} -!36 = metadata !{i32 524299, metadata !37, i32 11, i32 0, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] -!37 = metadata !{i32 524299, metadata !16, i32 11, i32 0, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] -!38 = metadata !{i32 524544, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1} ; [ DW_TAG_auto_variable ] -!39 = metadata !{i32 524299, metadata !40, i32 23, i32 0, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524299, metadata !20, i32 23, i32 0, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 786443, metadata !2, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ] +!37 = metadata !{i32 786443, metadata !2, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ] +!38 = metadata !{i32 786688, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1, i32 0, null} ; [ DW_TAG_auto_variable ] +!39 = metadata !{i32 786443, metadata !2, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 786443, metadata !2, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ] !41 = metadata !{i32 24, i32 0, metadata !39, null} !42 = metadata !{i32 25, i32 0, metadata !39, null} !43 = metadata !{i32 26, i32 0, metadata !39, null} -!44 = metadata !{i32 524544, metadata !39, metadata !"k", metadata !2, i32 26, metadata !13} ; [ DW_TAG_auto_variable ] +!44 = metadata !{i32 786688, metadata !39, metadata !"k", metadata !2, i32 26, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ] !45 = metadata !{i32 27, i32 0, metadata !39, null} diff --git a/test/CodeGen/X86/2010-08-10-DbgConstant.ll b/test/CodeGen/X86/2010-08-10-DbgConstant.ll deleted file mode 100644 index b3cc35d723f7f..0000000000000 --- a/test/CodeGen/X86/2010-08-10-DbgConstant.ll +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: llc -mtriple=i686-linux -O0 < %s | FileCheck %s -; CHECK: DW_TAG_constant -; CHECK-NEXT: .long .Lstring3 #{{#?}} DW_AT_name - -define void @foo() nounwind ssp { -entry: - call void @bar(i32 201), !dbg !8 - ret void, !dbg !8 -} - -declare void @bar(i32) - -!llvm.dbg.sp = !{!0} -!llvm.dbg.gv = !{!5} - -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void ()* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"/tmp/l.c", metadata !"/Volumes/Lalgate/clean/D", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/tmp/l.c", metadata !"/Volumes/Lalgate/clean/D", metadata !"clang 2.8", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{null} -!5 = metadata !{i32 524327, i32 0, metadata !1, metadata !"ro", metadata !"ro", metadata !"ro", metadata !1, i32 1, metadata !6, i1 true, i1 true, i32 201} ; [ DW_TAG_constant ] -!6 = metadata !{i32 524326, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_const_type ] -!7 = metadata !{i32 524324, metadata !1, metadata !"unsigned int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!8 = metadata !{i32 3, i32 14, metadata !9, null} -!9 = metadata !{i32 524299, metadata !0, i32 3, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll index bed8c8a77b9a7..de0d216e266f5 100644 --- a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll +++ b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll @@ -12,18 +12,21 @@ entry: ret i32 21, !dbg !10 } -!llvm.dbg.sp = !{!0, !6} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 53, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"bug.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 114084)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 53, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !15, i32 12, metadata !"clang version 2.9 (trunk 114084)", i1 false, metadata !"", i32 0, null, null, metadata !13, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null, null, metadata !13, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 524334, i32 0, metadata !7, metadata !"bar", metadata !"bar", metadata !"bar", metadata !7, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 524329, metadata !"bug.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !7, metadata !"bar", metadata !"bar", metadata !"bar", metadata !7, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ] !8 = metadata !{i32 53, i32 13, metadata !9, null} -!9 = metadata !{i32 524299, metadata !0, i32 53, i32 11, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 786443, metadata !0, i32 53, i32 11, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] !10 = metadata !{i32 4, i32 13, metadata !11, null} -!11 = metadata !{i32 524299, metadata !12, i32 4, i32 13, metadata !7, i32 2} ; [ DW_TAG_lexical_block ] -!12 = metadata !{i32 524299, metadata !6, i32 4, i32 11, metadata !7, i32 1} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 786443, metadata !12, i32 4, i32 13, metadata !7, i32 2} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 786443, metadata !6, i32 4, i32 11, metadata !7, i32 1} ; [ DW_TAG_lexical_block ] +!13 = metadata !{metadata !0, metadata !6} +!14 = metadata !{metadata !"", metadata !"/private/tmp"} +!15 = metadata !{metadata !"bug.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/2010-11-02-DbgParameter.ll b/test/CodeGen/X86/2010-11-02-DbgParameter.ll index 79c0cf35c6600..31a6822b34b87 100644 --- a/test/CodeGen/X86/2010-11-02-DbgParameter.ll +++ b/test/CodeGen/X86/2010-11-02-DbgParameter.ll @@ -15,21 +15,23 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.sp = !{!0} -!llvm.dbg.lv.foo = !{!6} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"one.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"one.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 117922)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo, null, null, metadata !16, i32 3} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !17} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 117922)", i1 true, metadata !"", i32 0, null, null, metadata !15, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 590081, metadata !0, metadata !"i", metadata !1, i32 3, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] -!7 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] -!8 = metadata !{i32 589843, metadata !1, metadata !"bar", metadata !1, i32 2, i64 64, i64 32, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_structure_type ] +!5 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786689, metadata !0, metadata !"i", metadata !1, i32 3, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] +!7 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] +!8 = metadata !{i32 786451, metadata !1, metadata !"bar", metadata !1, i32 2, i64 64, i64 32, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_structure_type ] !9 = metadata !{metadata !10, metadata !11} -!10 = metadata !{i32 589837, metadata !1, metadata !"x", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!11 = metadata !{i32 589837, metadata !1, metadata !"y", metadata !1, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!10 = metadata !{i32 786445, metadata !1, metadata !"x", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!11 = metadata !{i32 786445, metadata !1, metadata !"y", metadata !1, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] !12 = metadata !{i32 3, i32 47, metadata !0, null} !13 = metadata !{i32 4, i32 2, metadata !14, null} -!14 = metadata !{i32 589835, metadata !0, i32 3, i32 50, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!14 = metadata !{i32 786443, metadata !0, i32 3, i32 50, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!15 = metadata !{metadata !0} +!16 = metadata !{metadata !6} +!17 = metadata !{metadata !"one.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/2010-12-02-MC-Set.ll b/test/CodeGen/X86/2010-12-02-MC-Set.ll index 31446786ec150..4d8d974f703e7 100644 --- a/test/CodeGen/X86/2010-12-02-MC-Set.ll +++ b/test/CodeGen/X86/2010-12-02-MC-Set.ll @@ -6,17 +6,18 @@ entry: ret void, !dbg !5 } -!llvm.dbg.sp = !{!0} +!llvm.dbg.cu = !{!2} +!7 = metadata !{metadata !0} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"e.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"e.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 120563)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !"e.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 120563)", i1 false, metadata !"", i32 0, null, null, metadata !7, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null} !5 = metadata !{i32 5, i32 1, metadata !6, null} -!6 = metadata !{i32 589835, metadata !0, i32 3, i32 16, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!6 = metadata !{i32 786443, metadata !0, i32 3, i32 16, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] ; CHECK: .subsections_via_symbols ; CHECK-NEXT: __debug_line -; CHECK-NEXT: Ltmp +; CHECK-NEXT: Lline_table_start0 ; CHECK-NEXT: Ltmp{{[0-9]}} = (Ltmp diff --git a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll index 166dcf2599898..2355528a81e86 100644 --- a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll +++ b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin10.0.0" ; Check debug info for variable z_s -;CHECK: .long Lset13 +;CHECK: .long Lset14 ;CHECK-NEXT: ## DW_AT_decl_file ;CHECK-NEXT: ## DW_AT_decl_line ;CHECK-NEXT: ## DW_AT_type @@ -69,35 +69,37 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone declare i32 @puts(i8* nocapture) nounwind -!llvm.dbg.sp = !{!0, !6} -!llvm.dbg.lv.gcd = !{!10, !11, !12} -!llvm.dbg.lv.main = !{!14, !17} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"gcd", metadata !"gcd", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i64 (i64, i64)* @gcd} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"rem_small.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"rem_small.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 124117)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"gcd", metadata !"gcd", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i64 (i64, i64)* @gcd, null, null, metadata !29, i32 0} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !31} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !31, i32 12, metadata !"clang version 2.9 (trunk 124117)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"long int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 25, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @main} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786468, null, metadata !2, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 25, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @main, null, null, metadata !30, i32 0} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !9} -!9 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!10 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 5, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!11 = metadata !{i32 590081, metadata !0, metadata !"b", metadata !1, i32 5, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!12 = metadata !{i32 590080, metadata !13, metadata !"c", metadata !1, i32 6, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!13 = metadata !{i32 589835, metadata !0, i32 5, i32 52, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!14 = metadata !{i32 590080, metadata !15, metadata !"m", metadata !1, i32 26, metadata !16, i32 0} ; [ DW_TAG_auto_variable ] -!15 = metadata !{i32 589835, metadata !6, i32 25, i32 12, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!16 = metadata !{i32 589860, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!17 = metadata !{i32 590080, metadata !15, metadata !"z_s", metadata !1, i32 27, metadata !9, i32 0} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!10 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 786689, metadata !0, metadata !"b", metadata !1, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!12 = metadata !{i32 786688, metadata !13, metadata !"c", metadata !1, i32 6, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!13 = metadata !{i32 786443, metadata !1, metadata !0, i32 5, i32 52, i32 0} ; [ DW_TAG_lexical_block ] +!14 = metadata !{i32 786688, metadata !15, metadata !"m", metadata !1, i32 26, metadata !16, i32 0, null} ; [ DW_TAG_auto_variable ] +!15 = metadata !{i32 786443, metadata !1, metadata !6, i32 25, i32 12, i32 2} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!17 = metadata !{i32 786688, metadata !15, metadata !"z_s", metadata !1, i32 27, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] !18 = metadata !{i32 5, i32 41, metadata !0, null} !19 = metadata !{i32 5, i32 49, metadata !0, null} !20 = metadata !{i32 7, i32 5, metadata !13, null} !21 = metadata !{i32 8, i32 9, metadata !22, null} -!22 = metadata !{i32 589835, metadata !13, i32 7, i32 14, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!22 = metadata !{i32 786443, metadata !1, metadata !13, i32 7, i32 14, i32 1} ; [ DW_TAG_lexical_block ] !23 = metadata !{i32 9, i32 9, metadata !22, null} !24 = metadata !{i32 26, i32 38, metadata !15, null} !25 = metadata !{i32 27, i32 38, metadata !15, null} !26 = metadata !{i32 28, i32 9, metadata !15, null} !27 = metadata !{i32 30, i32 1, metadata !15, null} +!28 = metadata !{metadata !0, metadata !6} +!29 = metadata !{metadata !10, metadata !11, metadata !12} +!30 = metadata !{metadata !14, metadata !17} +!31 = metadata !{metadata !"rem_small.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll index 47ef693cc25e6..6f43b94b264a2 100644 --- a/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll +++ b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -O0 -disable-fp-elim -relocation-model=pic -stats 2>&1 | FileCheck %s ; ; This test should not cause any spilling with RAFast. diff --git a/test/CodeGen/X86/2011-09-14-valcoalesce.ll b/test/CodeGen/X86/2011-09-14-valcoalesce.ll index a5ec614a943b7..54d2b403509d8 100644 --- a/test/CodeGen/X86/2011-09-14-valcoalesce.ll +++ b/test/CodeGen/X86/2011-09-14-valcoalesce.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -disable-code-place | FileCheck %s +; RUN: llc < %s -march=x86 -disable-block-placement | FileCheck %s ; ; Test RegistersDefinedFromSameValue. We have multiple copies of the same vreg: ; while.body85.i: diff --git a/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll b/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll index a7207537de21c..da734d4b64543 100644 --- a/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll +++ b/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll @@ -16,8 +16,8 @@ target triple = "x86_64-unknown-linux-gnu" ; CHECK: main define i32 @main() nounwind uwtable { entry: -; CHECK: movsbq j(%rip), % -; CHECK: movsbq i(%rip), % +; CHECK: pmovsxbq j(%rip), % +; CHECK: pmovsxbq i(%rip), % %0 = load <2 x i8>* @i, align 8 %1 = load <2 x i8>* @j, align 8 %div = sdiv <2 x i8> %1, %0 diff --git a/test/CodeGen/X86/2011-11-30-or.ll b/test/CodeGen/X86/2011-11-30-or.ll index 0a949eb29b898..8ac4632329b33 100644 --- a/test/CodeGen/X86/2011-11-30-or.ll +++ b/test/CodeGen/X86/2011-11-30-or.ll @@ -8,15 +8,15 @@ target triple = "x86_64-apple-macosx10.6.6" ; CHECK: pblendvb %xmm1, %xmm2 ; CHECK: ret -define void @select_func() { +define void @select_func(<8 x i16> %in) { entry: - %c.lobit.i.i.i = ashr <8 x i16> <i16 17, i16 5, i16 1, i16 15, i16 19, i16 15, i16 4, i16 1> , <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> - %a35 = bitcast <8 x i16> %c.lobit.i.i.i to <2 x i64> + %c.lobit.i.i.i = ashr <8 x i16> %in, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> %and.i56.i.i.i = and <8 x i16> %c.lobit.i.i.i, <i16 25, i16 8, i16 65, i16 25, i16 8, i16 95, i16 15, i16 45> %and.i5.i.i.i = bitcast <8 x i16> %and.i56.i.i.i to <2 x i64> - %neg.i.i.i.i = xor <2 x i64> %a35, <i64 -1, i64 -1> - %and.i.i.i.i = and <2 x i64> zeroinitializer, %neg.i.i.i.i - %or.i.i.i.i = or <2 x i64> %and.i.i.i.i, %and.i5.i.i.i + %neg.i.i.i.i = xor <8 x i16> %c.lobit.i.i.i, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> + %and.i.i.i = and <8 x i16> %neg.i.i.i.i, <i16 45, i16 15, i16 95, i16 8, i16 25, i16 65, i16 8, i16 25> + %and.i2.i.i.i = bitcast <8 x i16> %and.i.i.i to <2 x i64> + %or.i.i.i.i = or <2 x i64> %and.i2.i.i.i, %and.i5.i.i.i %a37 = bitcast <2 x i64> %or.i.i.i.i to <8 x i16> store <8 x i16> %a37, <8 x i16> addrspace(1)* undef, align 4 ret void diff --git a/test/CodeGen/X86/2012-01-11-split-cv.ll b/test/CodeGen/X86/2012-01-11-split-cv.ll index 6b90072919016..7e914984fe445 100644 --- a/test/CodeGen/X86/2012-01-11-split-cv.ll +++ b/test/CodeGen/X86/2012-01-11-split-cv.ll @@ -2,7 +2,7 @@ ;CHECK: add18i16 define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind { -;CHECK: vmovups +;CHECK: vmovaps %b = load <18 x i16>* %bp, align 16 %x = add <18 x i16> zeroinitializer, %b store <18 x i16> %x, <18 x i16>* %ret, align 16 diff --git a/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll b/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll index 18a3313773534..90d8d3d2dd6d9 100644 --- a/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll +++ b/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -stats 2>&1 | \ ; RUN: not grep "Number of machine instructions hoisted out of loops post regalloc" diff --git a/test/CodeGen/X86/2012-07-15-BuildVectorPromote.ll b/test/CodeGen/X86/2012-07-15-BuildVectorPromote.ll new file mode 100644 index 0000000000000..078f1b05c3fc6 --- /dev/null +++ b/test/CodeGen/X86/2012-07-15-BuildVectorPromote.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7 +; We don't care about the output, just that it doesn't crash + +define <1 x i1> @buildvec_promote() { + %cmp = icmp ule <1 x i32> undef, undef + %sel = select i1 undef, <1 x i1> undef, <1 x i1> %cmp + ret <1 x i1> %sel +} diff --git a/test/CodeGen/X86/2012-07-15-broadcastfold.ll b/test/CodeGen/X86/2012-07-15-broadcastfold.ll index 3b7a8a7b871c9..2c7dfc8dfd452 100644 --- a/test/CodeGen/X86/2012-07-15-broadcastfold.ll +++ b/test/CodeGen/X86/2012-07-15-broadcastfold.ll @@ -3,7 +3,7 @@ declare x86_fastcallcc i64 @barrier() ;CHECK: bcast_fold -;CHECK: vmovaps %xmm{{[0-9]+}}, [[SPILLED:[^\)]+\)]] +;CHECK: vmov{{[au]}}ps %xmm{{[0-9]+}}, [[SPILLED:[^\)]+\)]] ;CHECK: barrier ;CHECK: vbroadcastss [[SPILLED]], %ymm0 ;CHECK: ret diff --git a/test/CodeGen/X86/2012-11-28-merge-store-alias.ll b/test/CodeGen/X86/2012-11-28-merge-store-alias.ll new file mode 100644 index 0000000000000..756e86e0f8016 --- /dev/null +++ b/test/CodeGen/X86/2012-11-28-merge-store-alias.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s + +; CHECK: merge_stores_can +; CHECK: callq foo +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: movups %xmm0 +; CHECK: callq foo +; CHECK: ret +declare i32 @foo([10 x i32]* ) + +define i32 @merge_stores_can() nounwind ssp { + %object1 = alloca [10 x i32] + + %ret0 = call i32 @foo([10 x i32]* %object1) nounwind + + %O1_1 = getelementptr [10 x i32]* %object1, i64 0, i32 1 + %O1_2 = getelementptr [10 x i32]* %object1, i64 0, i32 2 + %O1_3 = getelementptr [10 x i32]* %object1, i64 0, i32 3 + %O1_4 = getelementptr [10 x i32]* %object1, i64 0, i32 4 + %ld_ptr = getelementptr [10 x i32]* %object1, i64 0, i32 9 + + store i32 0, i32* %O1_1 + store i32 0, i32* %O1_2 + %ret = load i32* %ld_ptr ; <--- does not alias. + store i32 0, i32* %O1_3 + store i32 0, i32* %O1_4 + + %ret1 = call i32 @foo([10 x i32]* %object1) nounwind + + ret i32 %ret +} + +; CHECK: merge_stores_cant +; CHECK-NOT: xorps %xmm0, %xmm0 +; CHECK-NOT: movups %xmm0 +; CHECK: ret +define i32 @merge_stores_cant([10 x i32]* %in0, [10 x i32]* %in1) nounwind ssp { + + %O1_1 = getelementptr [10 x i32]* %in1, i64 0, i32 1 + %O1_2 = getelementptr [10 x i32]* %in1, i64 0, i32 2 + %O1_3 = getelementptr [10 x i32]* %in1, i64 0, i32 3 + %O1_4 = getelementptr [10 x i32]* %in1, i64 0, i32 4 + %ld_ptr = getelementptr [10 x i32]* %in0, i64 0, i32 2 + + store i32 0, i32* %O1_1 + store i32 0, i32* %O1_2 + %ret = load i32* %ld_ptr ; <--- may alias + store i32 0, i32* %O1_3 + store i32 0, i32* %O1_4 + + ret i32 %ret +} diff --git a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll new file mode 100644 index 0000000000000..9525653f3fffe --- /dev/null +++ b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll @@ -0,0 +1,51 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx -enable-misched \ +; RUN: -verify-machineinstrs | FileCheck %s +; +; Test LiveInterval update handling of DBG_VALUE. +; rdar://12777252. +; +; CHECK: %entry +; CHECK: DEBUG_VALUE: hg +; CHECK: je + +%struct.node.0.27 = type { i16, double, [3 x double], i32, i32 } +%struct.hgstruct.2.29 = type { %struct.bnode.1.28*, [3 x double], double, [3 x double] } +%struct.bnode.1.28 = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode.1.28*, %struct.bnode.1.28* } + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define signext i16 @subdivp(%struct.node.0.27* nocapture %p, double %dsq, double %tolsq, %struct.hgstruct.2.29* nocapture byval align 8 %hg) nounwind uwtable readonly ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.hgstruct.2.29* %hg}, metadata !4) + %type = getelementptr inbounds %struct.node.0.27* %p, i64 0, i32 0 + %0 = load i16* %type, align 2, !tbaa !8 + %cmp = icmp eq i16 %0, 1 + br i1 %cmp, label %return, label %for.cond.preheader + +for.cond.preheader: ; preds = %entry + %arrayidx6.1 = getelementptr inbounds %struct.hgstruct.2.29* %hg, i64 0, i32 1, i64 1 + %cmp22 = fcmp olt double 0.000000e+00, %dsq + %conv24 = zext i1 %cmp22 to i16 + br label %return + +return: ; preds = %for.cond.preheader, %entry + %retval.0 = phi i16 [ %conv24, %for.cond.preheader ], [ 0, %entry ] + ret i16 %retval.0 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"MultiSource/Benchmarks/Olden/bh/newbh.c", metadata !"MultiSource/Benchmarks/Olden/bh", metadata !"clang version 3.3 (trunk 168918) (llvm/trunk 168920)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Olden/bh/newbh.c] [DW_LANG_C99] +!1 = metadata !{metadata !2} +!2 = metadata !{i32 0} +!3 = metadata !{null} +!4 = metadata !{i32 786689, null, metadata !"hg", metadata !5, i32 67109589, metadata !6, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [hg] [line 725] +!5 = metadata !{i32 786473, metadata !11} ; [ DW_TAG_file_type ] +!6 = metadata !{i32 786454, metadata !11, null, metadata !"hgstruct", i32 492, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] [hgstruct] [line 492, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 786451, metadata !11, null, metadata !"", i32 487, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, i32 0, i32 0} ; [ DW_TAG_structure_type ] [line 487, size 512, align 64, offset 0] [from ] +!8 = metadata !{metadata !"short", metadata !9} +!9 = metadata !{metadata !"omnipotent char", metadata !10} +!10 = metadata !{metadata !"Simple C/C++ TBAA"} +!11 = metadata !{metadata !"MultiSource/Benchmarks/Olden/bh/newbh.c", metadata !"MultiSource/Benchmarks/Olden/bh"} diff --git a/test/CodeGen/X86/2012-11-30-misched-dbg.ll b/test/CodeGen/X86/2012-11-30-misched-dbg.ll new file mode 100644 index 0000000000000..a0fbbb2ff9ef3 --- /dev/null +++ b/test/CodeGen/X86/2012-11-30-misched-dbg.ll @@ -0,0 +1,136 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx -enable-misched \ +; RUN: -verify-machineinstrs | FileCheck %s +; +; Test MachineScheduler handling of DBG_VALUE. +; rdar://12776937. +; +; CHECK: %if.else581 +; CHECK: DEBUG_VALUE: num1 +; CHECK: call + +%union.rec = type {} + +@.str15 = external hidden unnamed_addr constant [6 x i8], align 1 + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define i32 @AttachGalley(%union.rec** nocapture %suspend_pt) nounwind uwtable ssp { +entry: + %num14075 = alloca [20 x i8], align 16 + br label %if.end33 + +if.end33: ; preds = %entry + %cmp1733 = icmp eq i32 undef, 0 + br label %if.else581 + +if.else581: ; preds = %if.end33 + %cmp586 = icmp eq i8 undef, -123 + br i1 %cmp586, label %if.then588, label %if.else594 + +if.then588: ; preds = %if.else581 + br label %for.cond1710.preheader + +if.else594: ; preds = %if.else581 + unreachable + +for.cond1710.preheader: ; preds = %if.then588 + br label %for.cond1710 + +for.cond1710: ; preds = %for.cond1710, %for.cond1710.preheader + br i1 undef, label %for.cond1710, label %if.then3344 + +if.then3344: + br label %if.then4073 + +if.then4073: ; preds = %if.then3344 + call void @llvm.dbg.declare(metadata !{[20 x i8]* %num14075}, metadata !4) + %arraydecay4078 = getelementptr inbounds [20 x i8]* %num14075, i64 0, i64 0 + %0 = load i32* undef, align 4 + %add4093 = add nsw i32 %0, 0 + %conv4094 = sitofp i32 %add4093 to float + %div4095 = fdiv float %conv4094, 5.670000e+02 + %conv4096 = fpext float %div4095 to double + %call4097 = call i32 (i8*, i32, i64, i8*, ...)* @__sprintf_chk(i8* %arraydecay4078, i32 0, i64 20, i8* getelementptr inbounds ([6 x i8]* @.str15, i64 0, i64 0), double %conv4096) nounwind + br i1 %cmp1733, label %if.then4107, label %if.else4114 + +if.then4107: ; preds = %if.then4073 + unreachable + +if.else4114: ; preds = %if.then4073 + unreachable +} + +declare i32 @__sprintf_chk(i8*, i32, i64, i8*, ...) + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset", metadata !"clang version 3.3 (trunk 168918) (llvm/trunk 168920)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/MiBench/consumer-typeset/MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] [DW_LANG_C99] +!1 = metadata !{metadata !2} +!2 = metadata !{i32 0} +!3 = metadata !{} +!4 = metadata !{i32 786688, metadata !5, metadata !"num1", metadata !14, i32 815, metadata !15, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [num1] [line 815] +!5 = metadata !{i32 786443, metadata !6, i32 815, i32 0, metadata !14, i32 177} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!6 = metadata !{i32 786443, metadata !7, i32 812, i32 0, metadata !14, i32 176} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!7 = metadata !{i32 786443, metadata !8, i32 807, i32 0, metadata !14, i32 175} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!8 = metadata !{i32 786443, metadata !9, i32 440, i32 0, metadata !14, i32 94} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!9 = metadata !{i32 786443, metadata !10, i32 435, i32 0, metadata !14, i32 91} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!10 = metadata !{i32 786443, metadata !11, i32 434, i32 0, metadata !14, i32 90} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!11 = metadata !{i32 786443, metadata !12, i32 250, i32 0, metadata !14, i32 24} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!12 = metadata !{i32 786443, metadata !13, i32 249, i32 0, metadata !14, i32 23} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!13 = metadata !{i32 786443, metadata !3, i32 221, i32 0, metadata !14, i32 19} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] +!14 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!15 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 160, i64 8, i32 0, i32 0, metadata !16, metadata !17, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char] +!16 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char] +!17 = metadata !{metadata !18} +!18 = metadata !{i32 786465, i64 0, i64 20} ; [ DW_TAG_subrange_type ] [0, 19] +!19 = metadata !{metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset"} + +; Test DebugValue uses visited by RegisterPressureTracker findUseBetween(). +; +; CHECK: @main +; CHECK: DEBUG_VALUE: X +; CHECK: call + +%"class.__gnu_cxx::hash_map" = type { %"class.__gnu_cxx::hashtable" } +%"class.__gnu_cxx::hashtable" = type { i64, i64, i64, i64, i64, i64 } + +define void @main() uwtable ssp { +entry: + %X = alloca %"class.__gnu_cxx::hash_map", align 8 + br i1 undef, label %cond.true, label %cond.end + +cond.true: ; preds = %entry + unreachable + +cond.end: ; preds = %entry + call void @llvm.dbg.declare(metadata !{%"class.__gnu_cxx::hash_map"* %X}, metadata !31) + %_M_num_elements.i.i.i.i = getelementptr inbounds %"class.__gnu_cxx::hash_map"* %X, i64 0, i32 0, i32 5 + invoke void @_Znwm() + to label %exit.i unwind label %lpad2.i.i.i.i + +exit.i: ; preds = %cond.end + unreachable + +lpad2.i.i.i.i: ; preds = %cond.end + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + br i1 undef, label %lpad.body.i.i, label %if.then.i.i.i.i.i.i.i.i + +if.then.i.i.i.i.i.i.i.i: ; preds = %lpad2.i.i.i.i + unreachable + +lpad.body.i.i: ; preds = %lpad2.i.i.i.i + resume { i8*, i32 } %0 +} + +declare i32 @__gxx_personality_v0(...) + +declare void @_Znwm() + +!llvm.dbg.cu = !{!30} + +!30 = metadata !{i32 786449, i32 0, i32 4, metadata !"SingleSource/Benchmarks/Shootout-C++/hash.cpp", metadata !"SingleSource/Benchmarks/Shootout-C++", metadata !"clang version 3.3 (trunk 169129) (llvm/trunk 169135)", i1 true, i1 true, metadata !"", i32 0, null, null, null, null} ; [ DW_TAG_compile_unit ] [SingleSource/Benchmarks/Shootout-C++/hash.cpp] [DW_LANG_C_plus_plus] +!31 = metadata !{i32 786688, null, metadata !"X", null, i32 29, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [X] [line 29] +!32 = metadata !{i32 786454, metadata !34, null, metadata !"HM", i32 28, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_typedef ] [HM] [line 28, size 0, align 0, offset 0] [from ] +!33 = metadata !{i32 786473, metadata !34} ; [ DW_TAG_file_type ] +!34 = metadata !{metadata !"SingleSource/Benchmarks/Shootout-C++/hash.cpp", metadata !"SingleSource/Benchmarks/Shootout-C++"} diff --git a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll new file mode 100644 index 0000000000000..df93c5647d954 --- /dev/null +++ b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx -enable-misched \ +; RUN: -verify-machineinstrs | FileCheck %s +; +; Test RegisterPressure handling of DBG_VALUE. +; +; CHECK: %entry +; CHECK: DEBUG_VALUE: callback +; CHECK: ret + +%struct.btCompoundLeafCallback = type { i32, i32 } + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define void @test() unnamed_addr uwtable ssp align 2 { +entry: + %callback = alloca %struct.btCompoundLeafCallback, align 8 + br i1 undef, label %if.end, label %if.then + +if.then: ; preds = %entry + unreachable + +if.end: ; preds = %entry + call void @llvm.dbg.declare(metadata !{%struct.btCompoundLeafCallback* %callback}, metadata !3) + %m = getelementptr inbounds %struct.btCompoundLeafCallback* %callback, i64 0, i32 1 + store i32 0, i32* undef, align 8 + %cmp12447 = icmp sgt i32 undef, 0 + br i1 %cmp12447, label %for.body.lr.ph, label %invoke.cont44 + +for.body.lr.ph: ; preds = %if.end + unreachable + +invoke.cont44: ; preds = %if.end + ret void +} + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet", metadata !"clang version 3.3 (trunk 168984) (llvm/trunk 168983)", i1 true, i1 true, metadata !"", i32 0, metadata !1, null, null, null} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Bullet/MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !2} +!2 = metadata !{null, null} +!3 = metadata !{i32 786688, null, metadata !"callback", null, i32 214, metadata !4, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [callback] [line 214] +!4 = metadata !{i32 786451, metadata !6, null, metadata !"btCompoundLeafCallback", i32 90, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, null, null} ; [ DW_TAG_structure_type ] [btCompoundLeafCallback] [line 90, size 512, align 64, offset 0] [from ] +!5 = metadata !{i32 786473, metadata !6} ; [ DW_TAG_file_type ] +!6 = metadata !{metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet"} diff --git a/test/CodeGen/X86/2012-12-06-python27-miscompile.ll b/test/CodeGen/X86/2012-12-06-python27-miscompile.ll new file mode 100644 index 0000000000000..d9effc92fa927 --- /dev/null +++ b/test/CodeGen/X86/2012-12-06-python27-miscompile.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7 -mtriple=i686-pc-win32 | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; Make sure that we are zeroing one memory location at a time using xorl and +; not both using XMM registers. + +;CHECK: @foo +;CHECK: xorl +;CHECK-NOT: xmm +;CHECK: ret +define i32 @foo (i64* %so) nounwind uwtable ssp { +entry: + %used = getelementptr inbounds i64* %so, i32 3 + store i64 0, i64* %used, align 8 + %fill = getelementptr inbounds i64* %so, i32 2 + %L = load i64* %fill, align 8 + store i64 0, i64* %fill, align 8 + %cmp28 = icmp sgt i64 %L, 0 + %R = sext i1 %cmp28 to i32 + ret i32 %R +} diff --git a/test/CodeGen/X86/2012-12-1-merge-multiple.ll b/test/CodeGen/X86/2012-12-1-merge-multiple.ll new file mode 100644 index 0000000000000..5931c3d27be19 --- /dev/null +++ b/test/CodeGen/X86/2012-12-1-merge-multiple.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s + +; CHECK: multiple_stores_on_chain +; CHECK: movabsq +; CHECK: movq +; CHECK: movabsq +; CHECK: movq +; CHECK: ret +define void @multiple_stores_on_chain(i16 * %A) { +entry: + %a0 = getelementptr inbounds i16* %A, i64 0 + %a1 = getelementptr inbounds i16* %A, i64 1 + %a2 = getelementptr inbounds i16* %A, i64 2 + %a3 = getelementptr inbounds i16* %A, i64 3 + %a4 = getelementptr inbounds i16* %A, i64 4 + %a5 = getelementptr inbounds i16* %A, i64 5 + %a6 = getelementptr inbounds i16* %A, i64 6 + %a7 = getelementptr inbounds i16* %A, i64 7 + + store i16 0, i16* %a0 + store i16 1, i16* %a1 + store i16 2, i16* %a2 + store i16 3, i16* %a3 + store i16 4, i16* %a4 + store i16 5, i16* %a5 + store i16 6, i16* %a6 + store i16 7, i16* %a7 + + ret void +} + diff --git a/test/CodeGen/X86/2012-12-12-DAGCombineCrash.ll b/test/CodeGen/X86/2012-12-12-DAGCombineCrash.ll new file mode 100644 index 0000000000000..8cef2c8201c67 --- /dev/null +++ b/test/CodeGen/X86/2012-12-12-DAGCombineCrash.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=x86 -mtriple=i686-apple-ios -mcpu=yonah < %s +; rdar://12868039 + +define void @t() nounwind ssp { + %1 = alloca i32 + %2 = ptrtoint i32* %1 to i32 + br label %3 + +; <label>:3 ; preds = %5, %3, %0 + switch i32 undef, label %3 [ + i32 611946160, label %5 + i32 954117870, label %4 + ] + +; <label>:4 ; preds = %3 + ret void + +; <label>:5 ; preds = %5, %3 + %6 = add i32 0, 148 + %7 = and i32 %6, 48 + %8 = add i32 %7, 0 + %9 = or i32 %2, %8 + %10 = xor i32 -1, %2 + %11 = or i32 %8, %10 + %12 = or i32 %9, %11 + %13 = xor i32 %9, %11 + %14 = sub i32 %12, %13 + %15 = xor i32 2044674005, %14 + %16 = xor i32 %15, 0 + %17 = shl nuw nsw i32 %16, 1 + %18 = sub i32 0, %17 + %19 = and i32 %18, 2051242402 + %20 = sub i32 0, %19 + %21 = xor i32 %20, 0 + %22 = xor i32 %21, 0 + %23 = add i32 0, %22 + %24 = shl i32 %23, 1 + %25 = or i32 1, %24 + %26 = add i32 0, %25 + %27 = trunc i32 %26 to i8 + %28 = xor i8 %27, 125 + %29 = add i8 %28, -16 + %30 = add i8 0, %29 + store i8 %30, i8* null + br i1 undef, label %5, label %3 +} diff --git a/test/CodeGen/X86/2012-12-14-v8fp80-crash.ll b/test/CodeGen/X86/2012-12-14-v8fp80-crash.ll new file mode 100644 index 0000000000000..c465527bd867d --- /dev/null +++ b/test/CodeGen/X86/2012-12-14-v8fp80-crash.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7 -mtriple=i686-pc-win32 + +; Make sure we don't crash on this testcase. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +define void @_ZN6VectorIfE3equIeEEvfRKS_IT_E() nounwind uwtable ssp align 2 { +entry: + br i1 undef, label %while.end, label %while.body.lr.ph + +while.body.lr.ph: ; preds = %entry + br label %vector.body + +vector.body: ; preds = %vector.body, %while.body.lr.ph + %0 = fptrunc <8 x x86_fp80> undef to <8 x float> + store <8 x float> %0, <8 x float>* undef, align 4 + br label %vector.body + +while.end: ; preds = %entry + ret void +} diff --git a/test/CodeGen/X86/2012-12-19-NoImplicitFloat.ll b/test/CodeGen/X86/2012-12-19-NoImplicitFloat.ll new file mode 100644 index 0000000000000..3025665206713 --- /dev/null +++ b/test/CodeGen/X86/2012-12-19-NoImplicitFloat.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core2 < %s | FileCheck %s +; Test that we do not introduce vector operations with noimplicitfloat. +; rdar://12879313 + +%struct1 = type { i32*, i32* } + +define void @test() nounwind noimplicitfloat { +entry: +; CHECK-NOT: xmm +; CHECK: ret + %0 = load %struct1** undef, align 8 + %1 = getelementptr inbounds %struct1* %0, i64 0, i32 0 + store i32* null, i32** %1, align 8 + %2 = getelementptr inbounds %struct1* %0, i64 0, i32 1 + store i32* null, i32** %2, align 8 + ret void +} diff --git a/test/CodeGen/X86/2013-01-09-DAGCombineBug.ll b/test/CodeGen/X86/2013-01-09-DAGCombineBug.ll new file mode 100644 index 0000000000000..1b417e54a2f74 --- /dev/null +++ b/test/CodeGen/X86/2013-01-09-DAGCombineBug.ll @@ -0,0 +1,74 @@ +; RUN: llc -mtriple=x86_64-apple-macosx10.5.0 < %s + +; rdar://12968664 + +define void @t() nounwind uwtable ssp { + br label %4 + +; <label>:1 ; preds = %4, %2 + ret void + +; <label>:2 ; preds = %6, %5, %3, %2 + switch i32 undef, label %2 [ + i32 1090573978, label %1 + i32 1090573938, label %3 + i32 1090573957, label %5 + ] + +; <label>:3 ; preds = %4, %2 + br i1 undef, label %2, label %4 + +; <label>:4 ; preds = %6, %5, %3, %0 + switch i32 undef, label %11 [ + i32 1090573938, label %3 + i32 1090573957, label %5 + i32 1090573978, label %1 + i32 165205179, label %6 + ] + +; <label>:5 ; preds = %4, %2 + br i1 undef, label %2, label %4 + +; <label>:6 ; preds = %4 + %7 = icmp eq i32 undef, 590901838 + %8 = or i1 false, %7 + %9 = or i1 true, %8 + %10 = xor i1 %8, %9 + br i1 %10, label %4, label %2 + +; <label>:11 ; preds = %11, %4 + br label %11 +} + +; PR15608 +@global = external constant [2 x i8] + +define void @PR15608() { +bb: + br label %bb3 + +bb1: ; No predecessors! + br i1 icmp ult (i64 xor (i64 zext (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1) to i64), i64 1), i64 1), label %bb2, label %bb3 + +bb2: ; preds = %bb1 + unreachable + +bb3: ; preds = %bb1, %bb + br i1 xor (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1), i1 trunc (i192 lshr (i192 or (i192 and (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 -340282366920938463463374607431768211457), i192 shl (i192 zext (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1) to i192), i192 128)), i192 128) to i1)), label %bb7, label %bb4 + +bb4: ; preds = %bb6, %bb3 + %tmp = phi i1 [ true, %bb6 ], [ trunc (i192 lshr (i192 or (i192 and (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 -340282366920938463463374607431768211457), i192 shl (i192 zext (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1) to i192), i192 128)), i192 128) to i1), %bb3 ] + br i1 false, label %bb8, label %bb5 + +bb5: ; preds = %bb4 + br i1 %tmp, label %bb8, label %bb6 + +bb6: ; preds = %bb5 + br i1 false, label %bb8, label %bb4 + +bb7: ; preds = %bb3 + unreachable + +bb8: ; preds = %bb6, %bb5, %bb4 + unreachable +} diff --git a/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll b/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll new file mode 100644 index 0000000000000..614ccda5e250a --- /dev/null +++ b/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mtriple=x86_64-pc-win32 | FileCheck %s + +; CHECK: test +; CHECK: vpmovzxwd +; CHECK: vpmovzxwd +define void @test(<4 x i64> %a, <4 x i16>* %buf) { + %ex1 = extractelement <4 x i64> %a, i32 0 + %ex2 = extractelement <4 x i64> %a, i32 1 + %x1 = bitcast i64 %ex1 to <4 x i16> + %x2 = bitcast i64 %ex2 to <4 x i16> + %Sh = shufflevector <4 x i16> %x1, <4 x i16> %x2, <4 x i32> <i32 0, i32 1, i32 4, i32 5> + store <4 x i16> %Sh, <4 x i16>* %buf, align 1 + ret void +} diff --git a/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll new file mode 100644 index 0000000000000..03b6bdeafa873 --- /dev/null +++ b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core-avx-i -show-mc-encoding + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +@b = external global [8 x float], align 32 +@e = external global [8 x float], align 16 + +define void @main() #0 { +entry: + %0 = load <8 x float>* bitcast ([8 x float]* @b to <8 x float>*), align 32, !tbaa !0 + %bitcast.i = extractelement <8 x float> %0, i32 0 + %vecinit.i.i = insertelement <4 x float> undef, float %bitcast.i, i32 0 + %vecinit2.i.i = insertelement <4 x float> %vecinit.i.i, float 0.000000e+00, i32 1 + %vecinit3.i.i = insertelement <4 x float> %vecinit2.i.i, float 0.000000e+00, i32 2 + %vecinit4.i.i = insertelement <4 x float> %vecinit3.i.i, float 0.000000e+00, i32 3 + %1 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecinit4.i.i) #2 + %vecext.i.i = extractelement <4 x float> %1, i32 0 + store float %vecext.i.i, float* getelementptr inbounds ([8 x float]* @e, i64 0, i64 0), align 16, !tbaa !0 + unreachable +} + +declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) #1 + +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/Atomics-64.ll b/test/CodeGen/X86/Atomics-64.ll index 8e93762cec17b..8b0a349a8be35 100644 --- a/test/CodeGen/X86/Atomics-64.ll +++ b/test/CodeGen/X86/Atomics-64.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: llc < %s -march=x86 > %t +; RUN: llc < %s -march=x86-64 > %t.x86-64 +; RUN: llc < %s -march=x86 > %t.x86 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin8" diff --git a/test/CodeGen/X86/DbgValueOtherTargets.test b/test/CodeGen/X86/DbgValueOtherTargets.test new file mode 100644 index 0000000000000..7b4d431c93b1b --- /dev/null +++ b/test/CodeGen/X86/DbgValueOtherTargets.test @@ -0,0 +1,2 @@ +RUN: llc -O0 -march=x86 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=x86-64 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/X86/GC/erlang-gc.ll b/test/CodeGen/X86/GC/erlang-gc.ll new file mode 100644 index 0000000000000..c55b7f6dcf610 --- /dev/null +++ b/test/CodeGen/X86/GC/erlang-gc.ll @@ -0,0 +1,25 @@ +; RUN: llc -mtriple=x86_64-linux-gnu < %s | FileCheck %s --check-prefix=CHECK64 +; RUN: llc -mtriple=i686-linux-gnu < %s | FileCheck %s --check-prefix=CHECK32 + +define i32 @main(i32 %x) nounwind gc "erlang" { + %puts = tail call i32 @foo(i32 %x) + ret i32 0 + +; CHECK64: .section .note.gc,"",@progbits +; CHECK64-NEXT: .align 8 +; CHECK64-NEXT: .short 1 # safe point count +; CHECK64-NEXT: .long .Ltmp0 # safe point address +; CHECK64-NEXT: .short 1 # stack frame size (in words) +; CHECK64-NEXT: .short 0 # stack arity +; CHECK64-NEXT: .short 0 # live root count + +; CHECK32: .section .note.gc,"",@progbits +; CHECK32-NEXT: .align 4 +; CHECK32-NEXT: .short 1 # safe point count +; CHECK32-NEXT: .long .Ltmp0 # safe point address +; CHECK32-NEXT: .short 3 # stack frame size (in words) +; CHECK32-NEXT: .short 0 # stack arity +; CHECK32-NEXT: .short 0 # live root count +} + +declare i32 @foo(i32) diff --git a/test/CodeGen/X86/GC/ocaml-gc.ll b/test/CodeGen/X86/GC/ocaml-gc.ll new file mode 100644 index 0000000000000..44241a90d0e7a --- /dev/null +++ b/test/CodeGen/X86/GC/ocaml-gc.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s + +define i32 @main(i32 %x) nounwind gc "ocaml" { +; CHECK: .text +; CHECK-NEXT: .globl caml_3C_stdin_3E___code_begin +; CHECK-NEXT: caml_3C_stdin_3E___code_begin: +; CHECK-NEXT: .data +; CHECK-NEXT: .globl caml_3C_stdin_3E___data_begin +; CHECK-NEXT: caml_3C_stdin_3E___data_begin: + + %puts = tail call i32 @foo(i32 %x) + ret i32 0 + +; CHECK: .globl caml_3C_stdin_3E___code_end +; CHECK-NEXT: caml_3C_stdin_3E___code_end: +; CHECK-NEXT: .data +; CHECK-NEXT: .globl caml_3C_stdin_3E___data_end +; CHECK-NEXT: caml_3C_stdin_3E___data_end: +; CHECK-NEXT: .quad 0 +; CHECK-NEXT: .globl caml_3C_stdin_3E___frametable +; CHECK-NEXT: caml_3C_stdin_3E___frametable: +; CHECK-NEXT: .short 1 +; CHECK-NEXT: .align 8 +; CHECK-NEXT: # live roots for main +; CHECK-NEXT: .quad .Ltmp0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .align 8 +} + +declare i32 @foo(i32) diff --git a/test/CodeGen/X86/MachineSink-DbgValue.ll b/test/CodeGen/X86/MachineSink-DbgValue.ll index ea791a3c083ce..227ef3466e0a7 100644 --- a/test/CodeGen/X86/MachineSink-DbgValue.ll +++ b/test/CodeGen/X86/MachineSink-DbgValue.ll @@ -26,24 +26,25 @@ bb2: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!llvm.dbg.sp = !{!1} -!llvm.dbg.lv.foo = !{!6, !7, !10} -!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 590081, metadata !1, metadata !"i", metadata !2, i32 16777218, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!7 = metadata !{i32 590081, metadata !1, metadata !"c", metadata !2, i32 33554434, metadata !8, i32 0} ; [ DW_TAG_arg_variable ] -!8 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] -!9 = metadata !{i32 589860, metadata !0, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] -!10 = metadata !{i32 590080, metadata !11, metadata !"a", metadata !2, i32 3, metadata !9, i32 0} ; [ DW_TAG_auto_variable ] -!11 = metadata !{i32 589835, metadata !1, i32 2, i32 25, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786689, metadata !1, metadata !"i", metadata !2, i32 16777218, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] +!7 = metadata !{i32 786689, metadata !1, metadata !"c", metadata !2, i32 33554434, metadata !8, i32 0, null} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] +!9 = metadata !{i32 786468, metadata !0, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!10 = metadata !{i32 786688, metadata !11, metadata !"a", metadata !2, i32 3, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] +!11 = metadata !{i32 786443, metadata !20, metadata !1, i32 2, i32 25, i32 0} ; [ DW_TAG_lexical_block ] !12 = metadata !{i32 2, i32 13, metadata !1, null} !13 = metadata !{i32 2, i32 22, metadata !1, null} !14 = metadata !{i32 3, i32 14, metadata !11, null} !15 = metadata !{i32 4, i32 3, metadata !11, null} !16 = metadata !{i32 5, i32 5, metadata !11, null} !17 = metadata !{i32 7, i32 1, metadata !11, null} +!18 = metadata !{metadata !1} +!19 = metadata !{metadata !6, metadata !7, metadata !10} +!20 = metadata !{metadata !"a.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/MachineSink-PHIUse.ll b/test/CodeGen/X86/MachineSink-PHIUse.ll index 33141680aa92e..1329200c3e6e5 100644 --- a/test/CodeGen/X86/MachineSink-PHIUse.ll +++ b/test/CodeGen/X86/MachineSink-PHIUse.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats 2>&1 | grep "machine-sink" define fastcc void @t() nounwind ssp { diff --git a/test/CodeGen/X86/MergeConsecutiveStores.ll b/test/CodeGen/X86/MergeConsecutiveStores.ll index 64825bac97190..bb227a0185dfa 100644 --- a/test/CodeGen/X86/MergeConsecutiveStores.ll +++ b/test/CodeGen/X86/MergeConsecutiveStores.ll @@ -40,9 +40,43 @@ define void @merge_const_store(i32 %count, %struct.A* nocapture %p) nounwind uwt ret void } +; No vectors because we use noimplicitfloat +; CHECK: merge_const_store_no_vec +; CHECK-NOT: vmovups +; CHECK: ret +define void @merge_const_store_no_vec(i32 %count, %struct.B* nocapture %p) noimplicitfloat{ + %1 = icmp sgt i32 %count, 0 + br i1 %1, label %.lr.ph, label %._crit_edge +.lr.ph: + %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ] + %.01 = phi %struct.B* [ %11, %.lr.ph ], [ %p, %0 ] + %2 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0 + store i32 0, i32* %2, align 4 + %3 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1 + store i32 0, i32* %3, align 4 + %4 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2 + store i32 0, i32* %4, align 4 + %5 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3 + store i32 0, i32* %5, align 4 + %6 = getelementptr inbounds %struct.B* %.01, i64 0, i32 4 + store i32 0, i32* %6, align 4 + %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 5 + store i32 0, i32* %7, align 4 + %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 6 + store i32 0, i32* %8, align 4 + %9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 7 + store i32 0, i32* %9, align 4 + %10 = add nsw i32 %i.02, 1 + %11 = getelementptr inbounds %struct.B* %.01, i64 1 + %exitcond = icmp eq i32 %10, %count + br i1 %exitcond, label %._crit_edge, label %.lr.ph +._crit_edge: + ret void +} + ; Move the constants using a single vector store. ; CHECK: merge_const_store_vec -; CHECK: vmovups %ymm0, (%rsi) +; CHECK: vmovups ; CHECK: ret define void @merge_const_store_vec(i32 %count, %struct.B* nocapture %p) nounwind uwtable noinline ssp { %1 = icmp sgt i32 %count, 0 @@ -303,3 +337,99 @@ block4: ; preds = %4, %.lr.ph ret void } +; Make sure that we merge the consecutive load/store sequence below and use a +; word (16 bit) instead of a byte copy. +; CHECK: MergeLoadStoreBaseIndexOffset +; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]] +; CHECK: movw [[REG]], (%{{.*}}) +define void @MergeLoadStoreBaseIndexOffset(i64* %a, i8* %b, i8* %c, i32 %n) { + br label %1 + +; <label>:1 + %.09 = phi i32 [ %n, %0 ], [ %11, %1 ] + %.08 = phi i8* [ %b, %0 ], [ %10, %1 ] + %.0 = phi i64* [ %a, %0 ], [ %2, %1 ] + %2 = getelementptr inbounds i64* %.0, i64 1 + %3 = load i64* %.0, align 1 + %4 = getelementptr inbounds i8* %c, i64 %3 + %5 = load i8* %4, align 1 + %6 = add i64 %3, 1 + %7 = getelementptr inbounds i8* %c, i64 %6 + %8 = load i8* %7, align 1 + store i8 %5, i8* %.08, align 1 + %9 = getelementptr inbounds i8* %.08, i64 1 + store i8 %8, i8* %9, align 1 + %10 = getelementptr inbounds i8* %.08, i64 2 + %11 = add nsw i32 %.09, -1 + %12 = icmp eq i32 %11, 0 + br i1 %12, label %13, label %1 + +; <label>:13 + ret void +} + +; Make sure that we merge the consecutive load/store sequence below and use a +; word (16 bit) instead of a byte copy even if there are intermediate sign +; extensions. +; CHECK: MergeLoadStoreBaseIndexOffsetSext +; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]] +; CHECK: movw [[REG]], (%{{.*}}) +define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) { + br label %1 + +; <label>:1 + %.09 = phi i32 [ %n, %0 ], [ %12, %1 ] + %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] + %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] + %2 = getelementptr inbounds i8* %.0, i64 1 + %3 = load i8* %.0, align 1 + %4 = sext i8 %3 to i64 + %5 = getelementptr inbounds i8* %c, i64 %4 + %6 = load i8* %5, align 1 + %7 = add i64 %4, 1 + %8 = getelementptr inbounds i8* %c, i64 %7 + %9 = load i8* %8, align 1 + store i8 %6, i8* %.08, align 1 + %10 = getelementptr inbounds i8* %.08, i64 1 + store i8 %9, i8* %10, align 1 + %11 = getelementptr inbounds i8* %.08, i64 2 + %12 = add nsw i32 %.09, -1 + %13 = icmp eq i32 %12, 0 + br i1 %13, label %14, label %1 + +; <label>:14 + ret void +} + +; However, we can only merge ignore sign extensions when they are on all memory +; computations; +; CHECK: loadStoreBaseIndexOffsetSextNoSex +; CHECK-NOT: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]] +; CHECK-NOT: movw [[REG]], (%{{.*}}) +define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) { + br label %1 + +; <label>:1 + %.09 = phi i32 [ %n, %0 ], [ %12, %1 ] + %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] + %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] + %2 = getelementptr inbounds i8* %.0, i64 1 + %3 = load i8* %.0, align 1 + %4 = sext i8 %3 to i64 + %5 = getelementptr inbounds i8* %c, i64 %4 + %6 = load i8* %5, align 1 + %7 = add i8 %3, 1 + %wrap.4 = sext i8 %7 to i64 + %8 = getelementptr inbounds i8* %c, i64 %wrap.4 + %9 = load i8* %8, align 1 + store i8 %6, i8* %.08, align 1 + %10 = getelementptr inbounds i8* %.08, i64 1 + store i8 %9, i8* %10, align 1 + %11 = getelementptr inbounds i8* %.08, i64 2 + %12 = add nsw i32 %.09, -1 + %13 = icmp eq i32 %12, 0 + br i1 %13, label %14, label %1 + +; <label>:14 + ret void +} diff --git a/test/CodeGen/X86/WidenArith.ll b/test/CodeGen/X86/WidenArith.ll new file mode 100644 index 0000000000000..0383bd665b0fd --- /dev/null +++ b/test/CodeGen/X86/WidenArith.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s + +;CHECK: test +;CHECK: vaddps +;CHECK: vmulps +;CHECK: vsubps +;CHECK: vcmpltps +;CHECK: vcmpltps +;CHECK: vandps +;CHECK: vandps +;CHECK: ret +define <8 x i32> @test(<8 x float> %a, <8 x float> %b) { + %c1 = fadd <8 x float> %a, %b + %b1 = fmul <8 x float> %b, %a + %d = fsub <8 x float> %b1, %c1 + %res1 = fcmp olt <8 x float> %a, %b1 + %res2 = fcmp olt <8 x float> %c1, %d + %andr = and <8 x i1>%res1, %res2 + %ex = zext <8 x i1> %andr to <8 x i32> + ret <8 x i32>%ex +} + + diff --git a/test/CodeGen/X86/atom-bypass-slow-division-64.ll b/test/CodeGen/X86/atom-bypass-slow-division-64.ll new file mode 100644 index 0000000000000..a3bbea3c996b6 --- /dev/null +++ b/test/CodeGen/X86/atom-bypass-slow-division-64.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux -march=x86-64 | FileCheck %s + +; Additional tests for 64-bit divide bypass + +define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind { +; CHECK: Test_get_quotient: +; CHECK: orq %rsi, %rcx +; CHECK-NEXT: testq $-65536, %rcx +; CHECK-NEXT: je +; CHECK: idivq +; CHECK: ret +; CHECK: divw +; CHECK: ret + %result = sdiv i64 %a, %b + ret i64 %result +} + +define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind { +; CHECK: Test_get_remainder: +; CHECK: orq %rsi, %rcx +; CHECK-NEXT: testq $-65536, %rcx +; CHECK-NEXT: je +; CHECK: idivq +; CHECK: ret +; CHECK: divw +; CHECK: ret + %result = srem i64 %a, %b + ret i64 %result +} + +define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind { +; CHECK: Test_get_quotient_and_remainder: +; CHECK: orq %rsi, %rcx +; CHECK-NEXT: testq $-65536, %rcx +; CHECK-NEXT: je +; CHECK: idivq +; CHECK: divw +; CHECK: addq +; CHECK: ret +; CHECK-NOT: idivq +; CHECK-NOT: divw + %resultdiv = sdiv i64 %a, %b + %resultrem = srem i64 %a, %b + %result = add i64 %resultdiv, %resultrem + ret i64 %result +} diff --git a/test/CodeGen/X86/atom-bypass-slow-division.ll b/test/CodeGen/X86/atom-bypass-slow-division.ll index e7c9605d3e887..4612940445cb5 100644 --- a/test/CodeGen/X86/atom-bypass-slow-division.ll +++ b/test/CodeGen/X86/atom-bypass-slow-division.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s -define i32 @test_get_quotient(i32 %a, i32 %b) nounwind { -; CHECK: test_get_quotient +define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind { +; CHECK: Test_get_quotient: ; CHECK: orl %ecx, %edx ; CHECK-NEXT: testl $-256, %edx ; CHECK-NEXT: je @@ -13,8 +13,8 @@ define i32 @test_get_quotient(i32 %a, i32 %b) nounwind { ret i32 %result } -define i32 @test_get_remainder(i32 %a, i32 %b) nounwind { -; CHECK: test_get_remainder +define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind { +; CHECK: Test_get_remainder: ; CHECK: orl %ecx, %edx ; CHECK-NEXT: testl $-256, %edx ; CHECK-NEXT: je @@ -26,8 +26,8 @@ define i32 @test_get_remainder(i32 %a, i32 %b) nounwind { ret i32 %result } -define i32 @test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind { -; CHECK: test_get_quotient_and_remainder +define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind { +; CHECK: Test_get_quotient_and_remainder: ; CHECK: orl %ecx, %edx ; CHECK-NEXT: testl $-256, %edx ; CHECK-NEXT: je @@ -35,7 +35,7 @@ define i32 @test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind { ; CHECK: divb ; CHECK: addl ; CHECK: ret -; CEECK-NOT: idivl +; CHECK-NOT: idivl ; CHECK-NOT: divb %resultdiv = sdiv i32 %a, %b %resultrem = srem i32 %a, %b @@ -43,8 +43,8 @@ define i32 @test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind { ret i32 %result } -define i32 @test_use_div_and_idiv(i32 %a, i32 %b) nounwind { -; CHECK: test_use_div_and_idiv +define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind { +; CHECK: Test_use_div_and_idiv: ; CHECK: idivl ; CHECK: divb ; CHECK: divl @@ -57,34 +57,34 @@ define i32 @test_use_div_and_idiv(i32 %a, i32 %b) nounwind { ret i32 %result } -define i32 @test_use_div_imm_imm() nounwind { -; CHECK: test_use_div_imm_imm +define i32 @Test_use_div_imm_imm() nounwind { +; CHECK: Test_use_div_imm_imm: ; CHECK: movl $64 %resultdiv = sdiv i32 256, 4 ret i32 %resultdiv } -define i32 @test_use_div_reg_imm(i32 %a) nounwind { -; CHECK: test_use_div_reg_imm -; CEHCK-NOT: test +define i32 @Test_use_div_reg_imm(i32 %a) nounwind { +; CHECK: Test_use_div_reg_imm: +; CHECK-NOT: test ; CHECK-NOT: idiv ; CHECK-NOT: divb %resultdiv = sdiv i32 %a, 33 ret i32 %resultdiv } -define i32 @test_use_rem_reg_imm(i32 %a) nounwind { -; CHECK: test_use_rem_reg_imm -; CEHCK-NOT: test +define i32 @Test_use_rem_reg_imm(i32 %a) nounwind { +; CHECK: Test_use_rem_reg_imm: +; CHECK-NOT: test ; CHECK-NOT: idiv ; CHECK-NOT: divb %resultrem = srem i32 %a, 33 ret i32 %resultrem } -define i32 @test_use_divrem_reg_imm(i32 %a) nounwind { -; CHECK: test_use_divrem_reg_imm -; CEHCK-NOT: test +define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind { +; CHECK: Test_use_divrem_reg_imm: +; CHECK-NOT: test ; CHECK-NOT: idiv ; CHECK-NOT: divb %resultdiv = sdiv i32 %a, 33 @@ -93,8 +93,8 @@ define i32 @test_use_divrem_reg_imm(i32 %a) nounwind { ret i32 %result } -define i32 @test_use_div_imm_reg(i32 %a) nounwind { -; CHECK: test_use_div_imm_reg +define i32 @Test_use_div_imm_reg(i32 %a) nounwind { +; CHECK: Test_use_div_imm_reg: ; CHECK: test ; CHECK: idiv ; CHECK: divb @@ -102,8 +102,8 @@ define i32 @test_use_div_imm_reg(i32 %a) nounwind { ret i32 %resultdiv } -define i32 @test_use_rem_imm_reg(i32 %a) nounwind { -; CHECK: test_use_rem_imm_reg +define i32 @Test_use_rem_imm_reg(i32 %a) nounwind { +; CHECK: Test_use_rem_imm_reg: ; CHECK: test ; CHECK: idiv ; CHECK: divb diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll new file mode 100644 index 0000000000000..2a34e0298f30c --- /dev/null +++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll @@ -0,0 +1,77 @@ +; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=atom 2>&1 | \ +; RUN: grep "calll" | not grep "(" +; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=core2 2>&1 | \ +; RUN: grep "calll" | grep "*funcp" +; +; original source code built with clang -S -emit-llvm -M32 test32.c: +; +; int a, b, c, d, e, f, g, h, i, j; +; extern int (*funcp)(int, int, int, int, int, int, int, int); +; extern int sum; +; +; void func() +; { +; sum = 0; +; for( i = a; i < b; ++i ) +; { +; sum += (*funcp)(i, b, c, d, e, f, g, h); +; } +; } +; +; ModuleID = 'test32.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" +target triple = "i386-unknown-linux-gnu" + +@sum = external global i32 +@a = common global i32 0, align 4 +@i = common global i32 0, align 4 +@b = common global i32 0, align 4 +@funcp = external global i32 (i32, i32, i32, i32, i32, i32, i32, i32)* +@c = common global i32 0, align 4 +@d = common global i32 0, align 4 +@e = common global i32 0, align 4 +@f = common global i32 0, align 4 +@g = common global i32 0, align 4 +@h = common global i32 0, align 4 +@j = common global i32 0, align 4 + +define void @func() #0 { +entry: + store i32 0, i32* @sum, align 4 + %0 = load i32* @a, align 4 + store i32 %0, i32* @i, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %1 = load i32* @i, align 4 + %2 = load i32* @b, align 4 + %cmp = icmp slt i32 %1, %2 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %3 = load i32 (i32, i32, i32, i32, i32, i32, i32, i32)** @funcp, align 4 + %4 = load i32* @i, align 4 + %5 = load i32* @b, align 4 + %6 = load i32* @c, align 4 + %7 = load i32* @d, align 4 + %8 = load i32* @e, align 4 + %9 = load i32* @f, align 4 + %10 = load i32* @g, align 4 + %11 = load i32* @h, align 4 + %call = call i32 %3(i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11) + %12 = load i32* @sum, align 4 + %add = add nsw i32 %12, %call + store i32 %add, i32* @sum, align 4 + br label %for.inc + +for.inc: ; preds = %for.body + %13 = load i32* @i, align 4 + %inc = add nsw i32 %13, 1 + store i32 %inc, i32* @i, align 4 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll new file mode 100644 index 0000000000000..bcfbd6107a56d --- /dev/null +++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll @@ -0,0 +1,91 @@ +; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=atom 2>&1 | \ +; RUN: grep "callq" | not grep "(" +; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core2 2>&1 | \ +; RUN: grep "callq" | grep "*funcp" +; +; Original source code built with clang -S -emit-llvm -m64 test64.c: +; int a, b, c, d, e, f, g, h, i, j, k, l, m, n; +; extern int (*funcp)(int, int, int, int, int, int, +; int, int, int, int, int, int, +; int, int); +; extern int sum; +; +; void func() +; { +; sum = 0; +; for( i = a; i < b; ++i ) +; { +; sum += (*funcp)(a, i, i*2, i/b, c, d, e, f, g, h, j, k, l, n); +; } +; } +; +; ModuleID = 'test64.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@sum = external global i32 +@a = common global i32 0, align 4 +@i = common global i32 0, align 4 +@b = common global i32 0, align 4 +@funcp = external global i32 (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)* +@c = common global i32 0, align 4 +@d = common global i32 0, align 4 +@e = common global i32 0, align 4 +@f = common global i32 0, align 4 +@g = common global i32 0, align 4 +@h = common global i32 0, align 4 +@j = common global i32 0, align 4 +@k = common global i32 0, align 4 +@l = common global i32 0, align 4 +@n = common global i32 0, align 4 +@m = common global i32 0, align 4 + +define void @func() #0 { +entry: + store i32 0, i32* @sum, align 4 + %0 = load i32* @a, align 4 + store i32 %0, i32* @i, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %1 = load i32* @i, align 4 + %2 = load i32* @b, align 4 + %cmp = icmp slt i32 %1, %2 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %3 = load i32 (i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)** @funcp, align 8 + %4 = load i32* @a, align 4 + %5 = load i32* @i, align 4 + %6 = load i32* @i, align 4 + %mul = mul nsw i32 %6, 2 + %7 = load i32* @i, align 4 + %8 = load i32* @b, align 4 + %div = sdiv i32 %7, %8 + %9 = load i32* @c, align 4 + %10 = load i32* @d, align 4 + %11 = load i32* @e, align 4 + %12 = load i32* @f, align 4 + %13 = load i32* @g, align 4 + %14 = load i32* @h, align 4 + %15 = load i32* @j, align 4 + %16 = load i32* @k, align 4 + %17 = load i32* @l, align 4 + %18 = load i32* @n, align 4 + %call = call i32 %3(i32 %4, i32 %5, i32 %mul, i32 %div, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16, i32 %17, i32 %18) + %19 = load i32* @sum, align 4 + %add = add nsw i32 %19, %call + store i32 %add, i32* @sum, align 4 + br label %for.inc + +for.inc: ; preds = %for.body + %20 = load i32* @i, align 4 + %inc = add nsw i32 %20, 1 + store i32 %inc, i32* @i, align 4 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/X86/atom-call-reg-indirect.ll b/test/CodeGen/X86/atom-call-reg-indirect.ll new file mode 100644 index 0000000000000..632781130d06f --- /dev/null +++ b/test/CodeGen/X86/atom-call-reg-indirect.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=ATOM32 %s +; RUN: llc < %s -mcpu=core2 -mtriple=i686-linux | FileCheck -check-prefix=ATOM-NOT32 %s +; RUN: llc < %s -mcpu=atom -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM64 %s +; RUN: llc < %s -mcpu=core2 -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM-NOT64 %s + + +; fn_ptr.ll +%class.A = type { i32 (...)** } + +define i32 @test1() #0 { + ;ATOM: test1 +entry: + %call = tail call %class.A* @_Z3facv() + %0 = bitcast %class.A* %call to void (%class.A*)*** + %vtable = load void (%class.A*)*** %0, align 8 + %1 = load void (%class.A*)** %vtable, align 8 + ;ATOM32: movl (%ecx), %ecx + ;ATOM32: calll *%ecx + ;ATOM-NOT32: calll *(%ecx) + ;ATOM64: movq (%rcx), %rcx + ;ATOM64: callq *%rcx + ;ATOM-NOT64: callq *(%rcx) + tail call void %1(%class.A* %call) + ret i32 0 +} + +declare %class.A* @_Z3facv() #1 + +; virt_fn.ll +@p = external global void (i32)** + +define i32 @test2() #0 { + ;ATOM: test2 +entry: + %0 = load void (i32)*** @p, align 8 + %1 = load void (i32)** %0, align 8 + ;ATOM32: movl (%eax), %eax + ;ATOM32: calll *%eax + ;ATOM-NOT: calll *(%eax) + ;ATOM64: movq (%rax), %rax + ;ATOM64: callq *%rax + ;ATOM-NOT64: callq *(%rax) + tail call void %1(i32 2) + ret i32 0 +} diff --git a/test/CodeGen/X86/atom-pad-short-functions.ll b/test/CodeGen/X86/atom-pad-short-functions.ll new file mode 100644 index 0000000000000..b9a39e08cb519 --- /dev/null +++ b/test/CodeGen/X86/atom-pad-short-functions.ll @@ -0,0 +1,103 @@ +; RUN: llc < %s -O1 -mcpu=atom -mtriple=i686-linux | FileCheck %s + +declare void @external_function(...) + +define i32 @test_return_val(i32 %a) nounwind { +; CHECK: test_return_val +; CHECK: movl +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: ret + ret i32 %a +} + +define i32 @test_optsize(i32 %a) nounwind optsize { +; CHECK: test_optsize +; CHECK: movl +; CHECK-NEXT: ret + ret i32 %a +} + +define i32 @test_minsize(i32 %a) nounwind minsize { +; CHECK: test_minsize +; CHECK: movl +; CHECK-NEXT: ret + ret i32 %a +} + +define i32 @test_add(i32 %a, i32 %b) nounwind { +; CHECK: test_add +; CHECK: addl +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: ret + %result = add i32 %a, %b + ret i32 %result +} + +define i32 @test_multiple_ret(i32 %a, i32 %b, i1 %c) nounwind { +; CHECK: @test_multiple_ret +; CHECK: je + +; CHECK: nop +; CHECK: nop +; CHECK: ret + +; CHECK: nop +; CHECK: nop +; CHECK: ret + + br i1 %c, label %bb1, label %bb2 + +bb1: + ret i32 %a + +bb2: + ret i32 %b +} + +define void @test_call_others(i32 %x) nounwind +{ +; CHECK: test_call_others +; CHECK: je + %tobool = icmp eq i32 %x, 0 + br i1 %tobool, label %if.end, label %true.case + +; CHECK: jmp external_function +true.case: + tail call void bitcast (void (...)* @external_function to void ()*)() nounwind + br label %if.end + +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: ret +if.end: + ret void + +} + +define void @test_branch_to_same_bb(i32 %x, i32 %y) nounwind { +; CHECK: @test_branch_to_same_bb + %cmp = icmp sgt i32 %x, 0 + br i1 %cmp, label %while.cond, label %while.end + +while.cond: + br label %while.cond + +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: nop +; CHECK: ret +while.end: + ret void +} + diff --git a/test/CodeGen/X86/atomic-dagsched.ll b/test/CodeGen/X86/atomic-dagsched.ll new file mode 100644 index 0000000000000..0e7cf8c09668b --- /dev/null +++ b/test/CodeGen/X86/atomic-dagsched.ll @@ -0,0 +1,110 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s + +define void @test(i8** %a, i64* %b, i64 %c, i64 %d) nounwind { +entry: + %ptrtoarg4 = load i8** %a, align 8 + %brglist1 = getelementptr i8** %a, i64 1 + %ptrtoarg25 = load i8** %brglist1, align 8 + %0 = load i64* %b, align 8 + %1 = mul i64 %0, 4 + %scevgep = getelementptr i8* %ptrtoarg25, i64 %1 + %2 = mul i64 %d, 4 + br label %loop.cond + +loop.cond: ; preds = %test.exit, %entry + %asr.iv6 = phi i8* [ %29, %test.exit ], [ %scevgep, %entry ] + %iv = phi i64 [ %0, %entry ], [ %28, %test.exit ] + %3 = icmp eq i64 %iv, %c + br i1 %3, label %return, label %loop + +loop: ; preds = %loop.cond + %4 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8, !tbaa !0 + %5 = load i64* %4, align 8, !tbaa !3 + %vector.size.i = ashr i64 %5, 3 + %num.vector.wi.i = shl i64 %vector.size.i, 3 + %6 = icmp eq i64 %vector.size.i, 0 + br i1 %6, label %scalarIf.i, label %dim_0_vector_pre_head.i + +dim_0_vector_pre_head.i: ; preds = %loop + %7 = trunc i64 %5 to i32 + %tempvector_func.i = insertelement <8 x i32> undef, i32 %7, i32 0 + %vectorvector_func.i = shufflevector <8 x i32> %tempvector_func.i, <8 x i32> undef, <8 x i32> zeroinitializer + br label %vector_kernel_entry.i + +vector_kernel_entry.i: ; preds = %vector_kernel_entry.i, %dim_0_vector_pre_head.i + %asr.iv9 = phi i8* [ %scevgep10, %vector_kernel_entry.i ], [ %asr.iv6, %dim_0_vector_pre_head.i ] + %asr.iv = phi i64 [ %asr.iv.next, %vector_kernel_entry.i ], [ %vector.size.i, %dim_0_vector_pre_head.i ] + %8 = bitcast i8* %ptrtoarg4 to i32 addrspace(1)* + %asr.iv911 = bitcast i8* %asr.iv9 to <8 x i32> addrspace(1)* + %9 = load <8 x i32> addrspace(1)* %asr.iv911, align 4 + %extract8vector_func.i = extractelement <8 x i32> %9, i32 0 + %extract9vector_func.i = extractelement <8 x i32> %9, i32 1 + %extract10vector_func.i = extractelement <8 x i32> %9, i32 2 + %extract11vector_func.i = extractelement <8 x i32> %9, i32 3 + %extract12vector_func.i = extractelement <8 x i32> %9, i32 4 + %extract13vector_func.i = extractelement <8 x i32> %9, i32 5 + %extract14vector_func.i = extractelement <8 x i32> %9, i32 6 + %extract15vector_func.i = extractelement <8 x i32> %9, i32 7 + %10 = atomicrmw min i32 addrspace(1)* %8, i32 %extract8vector_func.i seq_cst + %11 = atomicrmw min i32 addrspace(1)* %8, i32 %extract9vector_func.i seq_cst + %12 = atomicrmw min i32 addrspace(1)* %8, i32 %extract10vector_func.i seq_cst + %13 = atomicrmw min i32 addrspace(1)* %8, i32 %extract11vector_func.i seq_cst + %14 = atomicrmw min i32 addrspace(1)* %8, i32 %extract12vector_func.i seq_cst + %15 = atomicrmw min i32 addrspace(1)* %8, i32 %extract13vector_func.i seq_cst + %16 = atomicrmw min i32 addrspace(1)* %8, i32 %extract14vector_func.i seq_cst + %17 = atomicrmw min i32 addrspace(1)* %8, i32 %extract15vector_func.i seq_cst + store <8 x i32> %vectorvector_func.i, <8 x i32> addrspace(1)* %asr.iv911, align 4 + %asr.iv.next = add i64 %asr.iv, -1 + %scevgep10 = getelementptr i8* %asr.iv9, i64 32 + %dim_0_vector_cmp.to.max.i = icmp eq i64 %asr.iv.next, 0 + br i1 %dim_0_vector_cmp.to.max.i, label %scalarIf.i, label %vector_kernel_entry.i + +scalarIf.i: ; preds = %vector_kernel_entry.i, %loop + %exec_wi.i = phi i64 [ 0, %loop ], [ %num.vector.wi.i, %vector_kernel_entry.i ] + %18 = icmp eq i64 %exec_wi.i, %5 + br i1 %18, label %test.exit, label %dim_0_pre_head.i + +dim_0_pre_head.i: ; preds = %scalarIf.i + %19 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8, !tbaa !0 + %20 = load i64* %19, align 8, !tbaa !3 + %21 = trunc i64 %20 to i32 + %22 = mul i64 %vector.size.i, 8 + br label %scalar_kernel_entry.i + +scalar_kernel_entry.i: ; preds = %scalar_kernel_entry.i, %dim_0_pre_head.i + %asr.iv12 = phi i64 [ %asr.iv.next13, %scalar_kernel_entry.i ], [ %22, %dim_0_pre_head.i ] + %23 = bitcast i8* %asr.iv6 to i32 addrspace(1)* + %24 = bitcast i8* %ptrtoarg4 to i32 addrspace(1)* + %scevgep16 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12 + %25 = load i32 addrspace(1)* %scevgep16, align 4, !tbaa !4 + %26 = atomicrmw min i32 addrspace(1)* %24, i32 %25 seq_cst + %scevgep15 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12 + store i32 %21, i32 addrspace(1)* %scevgep15, align 4, !tbaa !4 + %asr.iv.next13 = add i64 %asr.iv12, 1 + %dim_0_cmp.to.max.i = icmp eq i64 %5, %asr.iv.next13 + br i1 %dim_0_cmp.to.max.i, label %test.exit, label %scalar_kernel_entry.i + +test.exit: ; preds = %scalar_kernel_entry.i, %scalarIf.i + %27 = bitcast i8* %asr.iv6 to i1* + %28 = add i64 %iv, %d + store i64 %28, i64* %b, align 8 + %scevgep8 = getelementptr i1* %27, i64 %2 + %29 = bitcast i1* %scevgep8 to i8* + br label %loop.cond + +return: ; preds = %loop.cond + store i64 %0, i64* %b, align 8 + ret void +} + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"long", metadata !1} +!4 = metadata !{metadata !"int", metadata !1} + +; CHECK: test +; CHECK: decq +; CHECK-NOT: cmpxchgl +; CHECK: jne +; CHECK: ret diff --git a/test/CodeGen/X86/atomic-load-store-wide.ll b/test/CodeGen/X86/atomic-load-store-wide.ll index a9ebfef2ebeb1..17e04f059034a 100644 --- a/test/CodeGen/X86/atomic-load-store-wide.ll +++ b/test/CodeGen/X86/atomic-load-store-wide.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -verify-machineinstrs | FileCheck %s ; 64-bit load/store on x86-32 ; FIXME: The generated code can be substantially improved. diff --git a/test/CodeGen/X86/atomic-load-store.ll b/test/CodeGen/X86/atomic-load-store.ll index fee45859c16a7..86a744ed00f0d 100644 --- a/test/CodeGen/X86/atomic-load-store.ll +++ b/test/CodeGen/X86/atomic-load-store.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -O0 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 | FileCheck %s define void @test1(i32* %ptr, i32 %val1) { ; CHECK: test1 diff --git a/test/CodeGen/X86/atomic-minmax-i6432.ll b/test/CodeGen/X86/atomic-minmax-i6432.ll index e3ef605f7f1cf..62f784f69608e 100644 --- a/test/CodeGen/X86/atomic-minmax-i6432.ll +++ b/test/CodeGen/X86/atomic-minmax-i6432.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux < %s | FileCheck %s -check-prefix=LINUX -; RUN: llc -march=x86 -mtriple=i386-macosx -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux -verify-machineinstrs < %s | FileCheck %s -check-prefix=LINUX +; RUN: llc -march=x86 -mattr=-cmov -mtriple=i386-pc-linux -verify-machineinstrs < %s | FileCheck %s -check-prefix=NOCMOV +; RUN: llc -march=x86 -mtriple=i386-macosx -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC @sc64 = external global i64 @@ -16,6 +17,16 @@ define void @atomic_maxmin_i6432() { ; LINUX: lock ; LINUX-NEXT: cmpxchg8b ; LINUX: jne [[LABEL]] +; NOCMOV: [[LABEL:.LBB[0-9]+_[0-9]+]] +; NOCMOV: cmpl +; NOCMOV: setl +; NOCMOV: cmpl +; NOCMOV: setl +; NOCMOV: jne +; NOCMOV: jne +; NOCMOV: lock +; NOCMOV-NEXT: cmpxchg8b +; NOCMOV: jne [[LABEL]] %2 = atomicrmw min i64* @sc64, i64 6 acquire ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: cmpl @@ -27,6 +38,16 @@ define void @atomic_maxmin_i6432() { ; LINUX: lock ; LINUX-NEXT: cmpxchg8b ; LINUX: jne [[LABEL]] +; NOCMOV: [[LABEL:.LBB[0-9]+_[0-9]+]] +; NOCMOV: cmpl +; NOCMOV: setg +; NOCMOV: cmpl +; NOCMOV: setg +; NOCMOV: jne +; NOCMOV: jne +; NOCMOV: lock +; NOCMOV-NEXT: cmpxchg8b +; NOCMOV: jne [[LABEL]] %3 = atomicrmw umax i64* @sc64, i64 7 acquire ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: cmpl @@ -38,6 +59,16 @@ define void @atomic_maxmin_i6432() { ; LINUX: lock ; LINUX-NEXT: cmpxchg8b ; LINUX: jne [[LABEL]] +; NOCMOV: [[LABEL:.LBB[0-9]+_[0-9]+]] +; NOCMOV: cmpl +; NOCMOV: setb +; NOCMOV: cmpl +; NOCMOV: setb +; NOCMOV: jne +; NOCMOV: jne +; NOCMOV: lock +; NOCMOV-NEXT: cmpxchg8b +; NOCMOV: jne [[LABEL]] %4 = atomicrmw umin i64* @sc64, i64 8 acquire ; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] ; LINUX: cmpl @@ -49,6 +80,16 @@ define void @atomic_maxmin_i6432() { ; LINUX: lock ; LINUX-NEXT: cmpxchg8b ; LINUX: jne [[LABEL]] +; NOCMOV: [[LABEL:.LBB[0-9]+_[0-9]+]] +; NOCMOV: cmpl +; NOCMOV: seta +; NOCMOV: cmpl +; NOCMOV: seta +; NOCMOV: jne +; NOCMOV: jne +; NOCMOV: lock +; NOCMOV-NEXT: cmpxchg8b +; NOCMOV: jne [[LABEL]] ret void } diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll index 3f02eafb44a22..d759beb2caa88 100644 --- a/test/CodeGen/X86/atomic-or.ll +++ b/test/CodeGen/X86/atomic-or.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s ; rdar://9692967 diff --git a/test/CodeGen/X86/atomic-pointer.ll b/test/CodeGen/X86/atomic-pointer.ll index a455277be4dbf..ec3e6c3a8c190 100644 --- a/test/CodeGen/X86/atomic-pointer.ll +++ b/test/CodeGen/X86/atomic-pointer.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-none-linux | FileCheck %s +; RUN: llc < %s -mtriple=i686-none-linux -verify-machineinstrs | FileCheck %s define i32* @test_atomic_ptr_load(i32** %a0) { ; CHECK: test_atomic_ptr_load diff --git a/test/CodeGen/X86/atomic16.ll b/test/CodeGen/X86/atomic16.ll index 824995d6cb98a..ec2887e29f810 100644 --- a/test/CodeGen/X86/atomic16.ll +++ b/test/CodeGen/X86/atomic16.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=corei7 -show-mc-encoding | FileCheck %s --check-prefix X64 -; RUN: llc < %s -O0 -mtriple=i386-unknown-unknown -mcpu=corei7 | FileCheck %s --check-prefix X32 +; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=corei7 -verify-machineinstrs -show-mc-encoding | FileCheck %s --check-prefix X64 +; RUN: llc < %s -O0 -mtriple=i386-unknown-unknown -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32 @sc16 = external global i16 diff --git a/test/CodeGen/X86/atomic32.ll b/test/CodeGen/X86/atomic32.ll index dc927d8cb6f6f..3cb9ca1c76c75 100644 --- a/test/CodeGen/X86/atomic32.ll +++ b/test/CodeGen/X86/atomic32.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 | FileCheck %s --check-prefix X64 -; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 | FileCheck %s --check-prefix X32 +; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X64 +; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32 +; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -mattr=-cmov -verify-machineinstrs | FileCheck %s --check-prefix NOCMOV @sc32 = external global i32 @@ -164,9 +165,15 @@ define void @atomic_fetch_max32(i32 %x) nounwind { ; X32: cmov ; X32: lock ; X32: cmpxchgl + +; NOCMOV: cmpl +; NOCMOV: jl +; NOCMOV: lock +; NOCMOV: cmpxchgl ret void ; X64: ret ; X32: ret +; NOCMOV: ret } define void @atomic_fetch_min32(i32 %x) nounwind { @@ -180,9 +187,15 @@ define void @atomic_fetch_min32(i32 %x) nounwind { ; X32: cmov ; X32: lock ; X32: cmpxchgl + +; NOCMOV: cmpl +; NOCMOV: jg +; NOCMOV: lock +; NOCMOV: cmpxchgl ret void ; X64: ret ; X32: ret +; NOCMOV: ret } define void @atomic_fetch_umax32(i32 %x) nounwind { @@ -196,9 +209,15 @@ define void @atomic_fetch_umax32(i32 %x) nounwind { ; X32: cmov ; X32: lock ; X32: cmpxchgl + +; NOCMOV: cmpl +; NOCMOV: jb +; NOCMOV: lock +; NOCMOV: cmpxchgl ret void ; X64: ret ; X32: ret +; NOCMOV: ret } define void @atomic_fetch_umin32(i32 %x) nounwind { @@ -207,13 +226,20 @@ define void @atomic_fetch_umin32(i32 %x) nounwind { ; X64: cmov ; X64: lock ; X64: cmpxchgl + ; X32: cmpl ; X32: cmov ; X32: lock ; X32: cmpxchgl + +; NOCMOV: cmpl +; NOCMOV: ja +; NOCMOV: lock +; NOCMOV: cmpxchgl ret void ; X64: ret ; X32: ret +; NOCMOV: ret } define void @atomic_fetch_cmpxchg32() nounwind { diff --git a/test/CodeGen/X86/atomic64.ll b/test/CodeGen/X86/atomic64.ll index 45785cc8fe525..aa000455753fd 100644 --- a/test/CodeGen/X86/atomic64.ll +++ b/test/CodeGen/X86/atomic64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 | FileCheck %s --check-prefix X64 +; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X64 @sc64 = external global i64 diff --git a/test/CodeGen/X86/atomic6432.ll b/test/CodeGen/X86/atomic6432.ll index f9b21c5bc75e0..31e66c876e3da 100644 --- a/test/CodeGen/X86/atomic6432.ll +++ b/test/CodeGen/X86/atomic6432.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 | FileCheck %s --check-prefix X32 +; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32 @sc64 = external global i64 diff --git a/test/CodeGen/X86/atomic8.ll b/test/CodeGen/X86/atomic8.ll index 412428406dcff..3278ed1f504e6 100644 --- a/test/CodeGen/X86/atomic8.ll +++ b/test/CodeGen/X86/atomic8.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 | FileCheck %s --check-prefix X64 -; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 | FileCheck %s --check-prefix X32 +; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X64 +; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32 @sc8 = external global i8 diff --git a/test/CodeGen/X86/atomic_add.ll b/test/CodeGen/X86/atomic_add.ll index d94499889de41..6b3a6b224dbac 100644 --- a/test/CodeGen/X86/atomic_add.ll +++ b/test/CodeGen/X86/atomic_add.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s ; rdar://7103704 diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll index c5fa07d07d802..a378d6e8d684f 100644 --- a/test/CodeGen/X86/atomic_op.ll +++ b/test/CodeGen/X86/atomic_op.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+cmov | FileCheck %s +; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+cmov -verify-machineinstrs | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll index d0a7fe01009e0..22fad7ce4b7d9 100644 --- a/test/CodeGen/X86/avx-cvt.ll +++ b/test/CodeGen/X86/avx-cvt.ll @@ -18,6 +18,12 @@ define <4 x double> @sitofp01(<4 x i32> %a) { ret <4 x double> %b } +; CHECK: vcvtdq2ps %ymm +define <8 x float> @sitofp02(<8 x i16> %a) { + %b = sitofp <8 x i16> %a to <8 x float> + ret <8 x float> %b +} + ; CHECK: vcvttpd2dqy %ymm define <4 x i32> @fptosi01(<4 x double> %a) { %b = fptosi <4 x double> %a to <4 x i32> @@ -46,7 +52,7 @@ entry: ret double %conv } -; CHECK: vcvtsi2sd (% +; CHECK: vcvtsi2sdl (% define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp { entry: %tmp1 = load i32* %e, align 4 @@ -54,7 +60,7 @@ entry: ret double %conv } -; CHECK: vcvtsi2ss (% +; CHECK: vcvtsi2ssl (% define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp { entry: %tmp1 = load i32* %e, align 4 diff --git a/test/CodeGen/X86/avx-intel-ocl.ll b/test/CodeGen/X86/avx-intel-ocl.ll index 1446b36a0fb42..055072098a25e 100644 --- a/test/CodeGen/X86/avx-intel-ocl.ll +++ b/test/CodeGen/X86/avx-intel-ocl.ll @@ -1,9 +1,12 @@ -; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=WIN32 %s +; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X32 %s +; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X32 %s ; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=WIN64 %s -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=NOT_WIN %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=X64 %s declare <16 x float> @func_float16_ptr(<16 x float>, <16 x float> *) declare <16 x float> @func_float16(<16 x float>, <16 x float>) +declare i32 @func_int(i32, i32) + ; WIN64: testf16_inp ; WIN64: vaddps {{.*}}, {{%ymm[0-1]}} ; WIN64: vaddps {{.*}}, {{%ymm[0-1]}} @@ -11,19 +14,19 @@ declare <16 x float> @func_float16(<16 x float>, <16 x float>) ; WIN64: call ; WIN64: ret -; WIN32: testf16_inp -; WIN32: movl %eax, (%esp) -; WIN32: vaddps {{.*}}, {{%ymm[0-1]}} -; WIN32: vaddps {{.*}}, {{%ymm[0-1]}} -; WIN32: call -; WIN32: ret +; X32: testf16_inp +; X32: movl %eax, (%esp) +; X32: vaddps {{.*}}, {{%ymm[0-1]}} +; X32: vaddps {{.*}}, {{%ymm[0-1]}} +; X32: call +; X32: ret -; NOT_WIN: testf16_inp -; NOT_WIN: vaddps {{.*}}, {{%ymm[0-1]}} -; NOT_WIN: vaddps {{.*}}, {{%ymm[0-1]}} -; NOT_WIN: leaq {{.*}}(%rsp), %rdi -; NOT_WIN: call -; NOT_WIN: ret +; X64: testf16_inp +; X64: vaddps {{.*}}, {{%ymm[0-1]}} +; X64: vaddps {{.*}}, {{%ymm[0-1]}} +; X64: leaq {{.*}}(%rsp), %rdi +; X64: call +; X64: ret ;test calling conventions - input parameters define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind { @@ -45,11 +48,11 @@ define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind { ; WIN64: ret ; preserved ymm8-ymm15 -; NOT_WIN: testf16_regs -; NOT_WIN: call -; NOT_WIN: vaddps {{%ymm[8-9]}}, %ymm0, %ymm0 -; NOT_WIN: vaddps {{%ymm[8-9]}}, %ymm1, %ymm1 -; NOT_WIN: ret +; X64: testf16_regs +; X64: call +; X64: vaddps {{%ymm[8-9]}}, %ymm0, %ymm0 +; X64: vaddps {{%ymm[8-9]}}, %ymm1, %ymm1 +; X64: ret define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind { %y = alloca <16 x float>, align 16 @@ -84,24 +87,83 @@ define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind { ; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload ; WIN64: vmovaps {{.*(%rsp).*}}, {{%ymm([6-9]|1[0-5])}} # 32-byte Reload -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: vmovaps {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rbp) ## 32-byte Spill -; NOT_WIN: call -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload -; NOT_WIN: vmovaps {{.*}}(%rbp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Reload +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: vmovups {{%ymm([8-9]|1[0-5])}}, {{.*}}(%rsp) ## 32-byte Folded Spill +; X64: call +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload +; X64: vmovups {{.*}}(%rsp), {{%ymm([8-9]|1[0-5])}} ## 32-byte Folded Reload define intel_ocl_bicc <16 x float> @test_prolog_epilog(<16 x float> %a, <16 x float> %b) nounwind { %c = call <16 x float> @func_float16(<16 x float> %a, <16 x float> %b) ret <16 x float> %c } + +; test functions with integer parameters +; pass parameters on stack for 32-bit platform +; X32: movl {{.*}}, 4(%esp) +; X32: movl {{.*}}, (%esp) +; X32: call +; X32: addl {{.*}}, %eax + +; pass parameters in registers for 64-bit platform +; X64: leal {{.*}}, %edi +; X64: movl {{.*}}, %esi +; X64: call +; X64: addl {{.*}}, %eax +define i32 @test_int(i32 %a, i32 %b) nounwind { + %c1 = add i32 %a, %b + %c2 = call intel_ocl_bicc i32 @func_int(i32 %c1, i32 %a) + %c = add i32 %c2, %b + ret i32 %c +} + +; WIN64: test_float4 +; WIN64-NOT: vzeroupper +; WIN64: call +; WIN64-NOT: vzeroupper +; WIN64: call +; WIN64: ret + +; X64: test_float4 +; X64-NOT: vzeroupper +; X64: call +; X64-NOT: vzeroupper +; X64: call +; X64: ret + +; X32: test_float4 +; X32: vzeroupper +; X32: call +; X32: vzeroupper +; X32: call +; X32: ret + +declare <4 x float> @func_float4(<4 x float>, <4 x float>, <4 x float>) + +define <8 x float> @test_float4(<8 x float> %a, <8 x float> %b, <8 x float> %c) nounwind readnone { +entry: + %0 = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %1 = shufflevector <8 x float> %b, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %2 = shufflevector <8 x float> %c, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %call.i = tail call intel_ocl_bicc <4 x float> @func_float4(<4 x float> %0, <4 x float> %1, <4 x float> %2) nounwind + %3 = shufflevector <4 x float> %call.i, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + %4 = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %5 = shufflevector <8 x float> %b, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %6 = shufflevector <8 x float> %c, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + %call.i2 = tail call intel_ocl_bicc <4 x float> @func_float4(<4 x float> %4, <4 x float> %5, <4 x float> %6) nounwind + %7 = shufflevector <4 x float> %call.i2, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> + %8 = shufflevector <8 x float> %3, <8 x float> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> + ret <8 x float> %8 +} + diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index 88ecd5a5d34f9..0be83f648d1a2 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -671,7 +671,9 @@ define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) { ; CHECK: test_x86_sse2_storeu_dq ; CHECK: movl ; CHECK: vmovdqu - call void @llvm.x86.sse2.storeu.dq(i8* %a0, <16 x i8> %a1) + ; add operation forces the execution domain. + %a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + call void @llvm.x86.sse2.storeu.dq(i8* %a0, <16 x i8> %a2) ret void } declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind @@ -681,6 +683,7 @@ define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) { ; CHECK: test_x86_sse2_storeu_pd ; CHECK: movl ; CHECK: vmovupd + ; fadd operation forces the execution domain. %a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000> call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a2) ret void @@ -2345,7 +2348,7 @@ declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8) nounwind rea define <4 x float> @test_x86_avx_vpermil_ps(<4 x float> %a0) { - ; CHECK: vpermilps + ; CHECK: vpshufd %res = call <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float> %a0, i8 7) ; <<4 x float>> [#uses=1] ret <4 x float> %res } diff --git a/test/CodeGen/X86/avx-load-store.ll b/test/CodeGen/X86/avx-load-store.ll index c9fc66a8a7917..a6775aba09893 100644 --- a/test/CodeGen/X86/avx-load-store.ll +++ b/test/CodeGen/X86/avx-load-store.ll @@ -53,19 +53,24 @@ define void @storev16i16(<16 x i16> %a) nounwind { unreachable } -; CHECK: vmovups %ymm +; CHECK: storev16i16_01 +; CHECK: vextractf128 +; CHECK: vmovups %xmm define void @storev16i16_01(<16 x i16> %a) nounwind { store <16 x i16> %a, <16 x i16>* undef, align 4 unreachable } +; CHECK: storev32i8 ; CHECK: vmovaps %ymm define void @storev32i8(<32 x i8> %a) nounwind { store <32 x i8> %a, <32 x i8>* undef, align 32 unreachable } -; CHECK: vmovups %ymm +; CHECK: storev32i8_01 +; CHECK: vextractf128 +; CHECK: vmovups %xmm define void @storev32i8_01(<32 x i8> %a) nounwind { store <32 x i8> %a, <32 x i8>* undef, align 4 unreachable @@ -109,3 +114,38 @@ cif_mixed_test_any_check: ; preds = %cif_mask_mixed unreachable } +; CHECK: add8i32 +; CHECK: vmovups +; CHECK: vmovups +; CHECK-NOT: vinsertf128 +; CHECK-NOT: vextractf128 +; CHECK: vmovups +; CHECK: vmovups +define void @add8i32(<8 x i32>* %ret, <8 x i32>* %bp) nounwind { + %b = load <8 x i32>* %bp, align 1 + %x = add <8 x i32> zeroinitializer, %b + store <8 x i32> %x, <8 x i32>* %ret, align 1 + ret void +} + +; CHECK: add4i64a64 +; CHECK: vmovaps ({{.*}}), %ymm{{.*}} +; CHECK: vmovaps %ymm{{.*}}, ({{.*}}) +define void @add4i64a64(<4 x i64>* %ret, <4 x i64>* %bp) nounwind { + %b = load <4 x i64>* %bp, align 64 + %x = add <4 x i64> zeroinitializer, %b + store <4 x i64> %x, <4 x i64>* %ret, align 64 + ret void +} + +; CHECK: add4i64a16 +; CHECK: vmovaps {{.*}}({{.*}}), %xmm{{.*}} +; CHECK: vmovaps {{.*}}({{.*}}), %xmm{{.*}} +; CHECK: vmovaps %xmm{{.*}}, {{.*}}({{.*}}) +; CHECK: vmovaps %xmm{{.*}}, {{.*}}({{.*}}) +define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind { + %b = load <4 x i64>* %bp, align 16 + %x = add <4 x i64> zeroinitializer, %b + store <4 x i64> %x, <4 x i64>* %ret, align 16 + ret void +} diff --git a/test/CodeGen/X86/avx-sext.ll b/test/CodeGen/X86/avx-sext.ll index 3713a8c377996..b9c700051005c 100755 --- a/test/CodeGen/X86/avx-sext.ll +++ b/test/CodeGen/X86/avx-sext.ll @@ -1,17 +1,188 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSSE3 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=pentium4 | FileCheck %s -check-prefix=SSE2 define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp { -;CHECK: sext_8i16_to_8i32 -;CHECK: vpmovsxwd +; AVX: sext_8i16_to_8i32 +; AVX: vpmovsxwd %B = sext <8 x i16> %A to <8 x i32> ret <8 x i32>%B } define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp { -;CHECK: sext_4i32_to_4i64 -;CHECK: vpmovsxdq +; AVX: sext_4i32_to_4i64 +; AVX: vpmovsxdq %B = sext <4 x i32> %A to <4 x i64> ret <4 x i64>%B } + +; AVX: load_sext_test1 +; AVX: vpmovsxwd (%r{{[^,]*}}), %xmm{{.*}} +; AVX: ret + +; SSSE3: load_sext_test1 +; SSSE3: movq +; SSSE3: punpcklwd %xmm{{.*}}, %xmm{{.*}} +; SSSE3: psrad $16 +; SSSE3: ret + +; SSE2: load_sext_test1 +; SSE2: movq +; SSE2: punpcklwd %xmm{{.*}}, %xmm{{.*}} +; SSE2: psrad $16 +; SSE2: ret +define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) { + %X = load <4 x i16>* %ptr + %Y = sext <4 x i16> %X to <4 x i32> + ret <4 x i32>%Y +} + +; AVX: load_sext_test2 +; AVX: vpmovsxbd (%r{{[^,]*}}), %xmm{{.*}} +; AVX: ret + +; SSSE3: load_sext_test2 +; SSSE3: movd +; SSSE3: pshufb +; SSSE3: psrad $24 +; SSSE3: ret + +; SSE2: load_sext_test2 +; SSE2: movl +; SSE2: psrad $24 +; SSE2: ret +define <4 x i32> @load_sext_test2(<4 x i8> *%ptr) { + %X = load <4 x i8>* %ptr + %Y = sext <4 x i8> %X to <4 x i32> + ret <4 x i32>%Y +} + +; AVX: load_sext_test3 +; AVX: vpmovsxbq (%r{{[^,]*}}), %xmm{{.*}} +; AVX: ret + +; SSSE3: load_sext_test3 +; SSSE3: movsbq +; SSSE3: movsbq +; SSSE3: punpcklqdq +; SSSE3: ret + +; SSE2: load_sext_test3 +; SSE2: movsbq +; SSE2: movsbq +; SSE2: punpcklqdq +; SSE2: ret +define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) { + %X = load <2 x i8>* %ptr + %Y = sext <2 x i8> %X to <2 x i64> + ret <2 x i64>%Y +} + +; AVX: load_sext_test4 +; AVX: vpmovsxwq (%r{{[^,]*}}), %xmm{{.*}} +; AVX: ret + +; SSSE3: load_sext_test4 +; SSSE3: movswq +; SSSE3: movswq +; SSSE3: punpcklqdq +; SSSE3: ret + +; SSE2: load_sext_test4 +; SSE2: movswq +; SSE2: movswq +; SSE2: punpcklqdq +; SSE2: ret +define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) { + %X = load <2 x i16>* %ptr + %Y = sext <2 x i16> %X to <2 x i64> + ret <2 x i64>%Y +} + +; AVX: load_sext_test5 +; AVX: vpmovsxdq (%r{{[^,]*}}), %xmm{{.*}} +; AVX: ret + +; SSSE3: load_sext_test5 +; SSSE3: movslq +; SSSE3: movslq +; SSSE3: punpcklqdq +; SSSE3: ret + +; SSE2: load_sext_test5 +; SSE2: movslq +; SSE2: movslq +; SSE2: punpcklqdq +; SSE2: ret +define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) { + %X = load <2 x i32>* %ptr + %Y = sext <2 x i32> %X to <2 x i64> + ret <2 x i64>%Y +} + +; AVX: load_sext_test6 +; AVX: vpmovsxbw (%r{{[^,]*}}), %xmm{{.*}} +; AVX: ret + +; SSSE3: load_sext_test6 +; SSSE3: movq +; SSSE3: punpcklbw +; SSSE3: psraw $8 +; SSSE3: ret + +; SSE2: load_sext_test6 +; SSE2: movq +; SSE2: punpcklbw +; SSE2: psraw $8 +; SSE2: ret +define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) { + %X = load <8 x i8>* %ptr + %Y = sext <8 x i8> %X to <8 x i16> + ret <8 x i16>%Y +} + +; AVX: sext_4i1_to_4i64 +; AVX: vpslld $31 +; AVX: vpsrad $31 +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) { + %extmask = sext <4 x i1> %mask to <4 x i64> + ret <4 x i64> %extmask +} + +; AVX: sext_4i8_to_4i64 +; AVX: vpslld $24 +; AVX: vpsrad $24 +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) { + %extmask = sext <4 x i8> %mask to <4 x i64> + ret <4 x i64> %extmask +} + +; AVX: sext_4i8_to_4i64 +; AVX: vpmovsxbd +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) { + %X = load <4 x i8>* %ptr + %Y = sext <4 x i8> %X to <4 x i64> + ret <4 x i64>%Y +} + +; AVX: sext_4i16_to_4i64 +; AVX: vpmovsxwd +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) { + %X = load <4 x i16>* %ptr + %Y = sext <4 x i16> %X to <4 x i64> + ret <4 x i64>%Y +} diff --git a/test/CodeGen/X86/avx-shift.ll b/test/CodeGen/X86/avx-shift.ll index 681747b844a03..01eb7361e2932 100644 --- a/test/CodeGen/X86/avx-shift.ll +++ b/test/CodeGen/X86/avx-shift.ll @@ -105,13 +105,22 @@ define <32 x i8> @vshift12(<32 x i8> %a) nounwind readnone { ; CHECK: _vshift08 ; CHECK: vextractf128 $1 ; CHECK: vpslld $23 -; CHECK: vextractf128 $1 ; CHECK: vpslld $23 define <8 x i32> @vshift08(<8 x i32> %a) nounwind { %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a ret <8 x i32> %bitop } +; PR15141 +; CHECK: _vshift13: +; CHECK-NOT: vpsll +; CHECK: vcvttps2dq +; CHECK-NEXT: vpmulld +define <4 x i32> @vshift13(<4 x i32> %in) { + %T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4> + ret <4 x i32> %T +} + ;;; Uses shifts for sign extension ; CHECK: _sext_v16i16 ; CHECK: vpsllw diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll index ec11654b35560..73faa1fe0d409 100644 --- a/test/CodeGen/X86/avx-shuffle.ll +++ b/test/CodeGen/X86/avx-shuffle.ll @@ -6,7 +6,7 @@ define <4 x float> @test1(<4 x float> %a) nounwind { ret <4 x float> %b ; CHECK: test1: ; CHECK: vshufps -; CHECK: vpermilps +; CHECK: vpshufd } ; rdar://10538417 @@ -98,23 +98,23 @@ define i32 @test10(<4 x i32> %a) nounwind { } define <4 x float> @test11(<4 x float> %a) nounwind { -; check: test11 -; check: vpermilps $27 +; CHECK: test11 +; CHECK: vpshufd $27 %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ret <4 x float> %tmp1 } define <4 x float> @test12(<4 x float>* %a) nounwind { ; CHECK: test12 -; CHECK: vpermilps $27, ( +; CHECK: vpshufd %tmp0 = load <4 x float>* %a %tmp1 = shufflevector <4 x float> %tmp0, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ret <4 x float> %tmp1 } define <4 x i32> @test13(<4 x i32> %a) nounwind { -; check: test13 -; check: vpshufd $27 +; CHECK: test13 +; CHECK: vpshufd $27 %tmp1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ret <4 x i32> %tmp1 } @@ -246,3 +246,54 @@ define <8 x float> @test19(<8 x float> %A, <8 x float>%B) nounwind { ret <8 x float>%S } +; rdar://12684358 +; Make sure loads happen before stores. +; CHECK: swap8doubles +; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}} +; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}} +; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}} +; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}} +; CHECK: vmovaps {{[0-9]*}}(%rsi), %ymm{{[0-9]+}} +; CHECK: vmovaps {{[0-9]*}}(%rsi), %ymm{{[0-9]+}} +; CHECK: vmovaps %xmm{{[0-9]+}}, {{[0-9]*}}(%rdi) +; CHECK: vextractf128 +; CHECK: vmovaps %xmm{{[0-9]+}}, {{[0-9]*}}(%rdi) +; CHECK: vextractf128 +; CHECK: vmovaps %ymm{{[0-9]+}}, {{[0-9]*}}(%rsi) +; CHECK: vmovaps %ymm{{[0-9]+}}, {{[0-9]*}}(%rsi) +define void @swap8doubles(double* nocapture %A, double* nocapture %C) nounwind uwtable ssp { +entry: + %add.ptr = getelementptr inbounds double* %A, i64 2 + %v.i = bitcast double* %A to <2 x double>* + %0 = load <2 x double>* %v.i, align 1 + %shuffle.i.i = shufflevector <2 x double> %0, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2> + %v1.i = bitcast double* %add.ptr to <2 x double>* + %1 = load <2 x double>* %v1.i, align 1 + %2 = tail call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %shuffle.i.i, <2 x double> %1, i8 1) nounwind + %add.ptr1 = getelementptr inbounds double* %A, i64 6 + %add.ptr2 = getelementptr inbounds double* %A, i64 4 + %v.i27 = bitcast double* %add.ptr2 to <2 x double>* + %3 = load <2 x double>* %v.i27, align 1 + %shuffle.i.i28 = shufflevector <2 x double> %3, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2> + %v1.i29 = bitcast double* %add.ptr1 to <2 x double>* + %4 = load <2 x double>* %v1.i29, align 1 + %5 = tail call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %shuffle.i.i28, <2 x double> %4, i8 1) nounwind + %6 = bitcast double* %C to <4 x double>* + %7 = load <4 x double>* %6, align 32 + %add.ptr5 = getelementptr inbounds double* %C, i64 4 + %8 = bitcast double* %add.ptr5 to <4 x double>* + %9 = load <4 x double>* %8, align 32 + %shuffle.i26 = shufflevector <4 x double> %7, <4 x double> undef, <2 x i32> <i32 0, i32 1> + %10 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %7, i8 1) + %shuffle.i = shufflevector <4 x double> %9, <4 x double> undef, <2 x i32> <i32 0, i32 1> + %11 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %9, i8 1) + store <2 x double> %shuffle.i26, <2 x double>* %v.i, align 16 + store <2 x double> %10, <2 x double>* %v1.i, align 16 + store <2 x double> %shuffle.i, <2 x double>* %v.i27, align 16 + store <2 x double> %11, <2 x double>* %v1.i29, align 16 + store <4 x double> %2, <4 x double>* %6, align 32 + store <4 x double> %5, <4 x double>* %8, align 32 + ret void +} +declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone +declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone diff --git a/test/CodeGen/X86/avx-splat.ll b/test/CodeGen/X86/avx-splat.ll index 94bcddd975928..5c01c2cc5b509 100644 --- a/test/CodeGen/X86/avx-splat.ll +++ b/test/CodeGen/X86/avx-splat.ll @@ -3,8 +3,8 @@ ; CHECK: vpunpcklbw %xmm ; CHECK-NEXT: vpunpckhbw %xmm +; CHECK-NEXT: vpshufd $85 ; CHECK-NEXT: vinsertf128 $1 -; CHECK-NEXT: vpermilps $85 define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> @@ -12,8 +12,8 @@ entry: } ; CHECK: vpunpckhwd %xmm +; CHECK-NEXT: vpshufd $85 ; CHECK-NEXT: vinsertf128 $1 -; CHECK-NEXT: vpermilps $85 define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> @@ -47,9 +47,9 @@ entry: ; shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> ; To: ; shuffle (vload ptr)), undef, <1, 1, 1, 1> -; CHECK: vmovaps +; CHECK: vmovdqa +; CHECK-NEXT: vpshufd $-1 ; CHECK-NEXT: vinsertf128 $1 -; CHECK-NEXT: vpermilps $-1 define <8 x float> @funcE() nounwind { allocas: %udx495 = alloca [18 x [18 x float]], align 32 @@ -75,8 +75,8 @@ __load_and_broadcast_32.exit1249: ; preds = %load.i1247, %for_ex ret <8 x float> %load_broadcast12281250 } -; CHECK: vinsertf128 $1 -; CHECK-NEXT: vpermilps $0 +; CHECK: vpshufd $0 +; CHECK-NEXT: vinsertf128 $1 define <8 x float> @funcF(i32 %val) nounwind { %ret6 = insertelement <8 x i32> undef, i32 %val, i32 6 %ret7 = insertelement <8 x i32> %ret6, i32 %val, i32 7 @@ -84,8 +84,8 @@ define <8 x float> @funcF(i32 %val) nounwind { ret <8 x float> %tmp } -; CHECK: vinsertf128 $1 -; CHECK-NEXT: vpermilps $0 +; CHECK: vpshufd $0 +; CHECK-NEXT: vinsertf128 $1 define <8 x float> @funcG(<8 x float> %a) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> @@ -93,8 +93,8 @@ entry: } ; CHECK: vextractf128 $1 +; CHECK-NEXT: vpshufd ; CHECK-NEXT: vinsertf128 $1 -; CHECK-NEXT: vpermilps $85 define <8 x float> @funcH(<8 x float> %a) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> diff --git a/test/CodeGen/X86/avx-vextractf128.ll b/test/CodeGen/X86/avx-vextractf128.ll index ff56a454996e8..ad8365bb59c03 100644 --- a/test/CodeGen/X86/avx-vextractf128.ll +++ b/test/CodeGen/X86/avx-vextractf128.ll @@ -102,3 +102,21 @@ entry: store <2 x i64> %2, <2 x i64>* %addr, align 1 ret void } + +; PR15462 +define void @t9(i64* %p) { + store i64 0, i64* %p + %q = getelementptr i64* %p, i64 1 + store i64 0, i64* %q + %r = getelementptr i64* %p, i64 2 + store i64 0, i64* %r + %s = getelementptr i64* %p, i64 3 + store i64 0, i64* %s + ret void + +; CHECK: t9: +; CHECK: vxorps %xmm +; CHECK-NOT: vextractf +; CHECK: vmovups +; CHECK: vmovups +} diff --git a/test/CodeGen/X86/avx-vpermil.ll b/test/CodeGen/X86/avx-vpermil.ll index cb904b93313ad..7f2f9d821dd5b 100644 --- a/test/CodeGen/X86/avx-vpermil.ll +++ b/test/CodeGen/X86/avx-vpermil.ll @@ -45,8 +45,8 @@ entry: ret <8 x float> %shuffle } -; CHECK: palignr -; CHECK: palignr +; CHECK: palignr $8 +; CHECK: psrldq $8 define <8 x float> @funcF(<8 x float> %a) nounwind uwtable readnone ssp { entry: %shuffle = shufflevector <8 x float> %a, <8 x float> zeroinitializer, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> diff --git a/test/CodeGen/X86/avx-zext.ll b/test/CodeGen/X86/avx-zext.ll index b630e9d146125..582537ea906f7 100755 --- a/test/CodeGen/X86/avx-zext.ll +++ b/test/CodeGen/X86/avx-zext.ll @@ -18,11 +18,10 @@ define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp ret <4 x i64>%B } - define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) { ;CHECK: zext_8i8_to_8i32 ;CHECK: vpunpckhwd -;CHECK: vpunpcklwd +;CHECK: vpmovzxwd ;CHECK: vinsertf128 ;CHECK: ret %t = zext <8 x i8> %z to <8 x i32> diff --git a/test/CodeGen/X86/avx2-conversions.ll b/test/CodeGen/X86/avx2-conversions.ll index b47491335a312..3ce08dcc73704 100755 --- a/test/CodeGen/X86/avx2-conversions.ll +++ b/test/CodeGen/X86/avx2-conversions.ll @@ -63,6 +63,47 @@ define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind { ret <8 x i32>%B } +; CHECK: load_sext_test1 +; CHECK: vpmovsxdq (%r{{[^,]*}}), %ymm{{.*}} +; CHECK: ret +define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) { + %X = load <4 x i32>* %ptr + %Y = sext <4 x i32> %X to <4 x i64> + ret <4 x i64>%Y +} + +; CHECK: load_sext_test2 +; CHECK: vpmovsxbq (%r{{[^,]*}}), %ymm{{.*}} +; CHECK: ret +define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) { + %X = load <4 x i8>* %ptr + %Y = sext <4 x i8> %X to <4 x i64> + ret <4 x i64>%Y +} +; CHECK: load_sext_test3 +; CHECK: vpmovsxwq (%r{{[^,]*}}), %ymm{{.*}} +; CHECK: ret +define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) { + %X = load <4 x i16>* %ptr + %Y = sext <4 x i16> %X to <4 x i64> + ret <4 x i64>%Y +} +; CHECK: load_sext_test4 +; CHECK: vpmovsxwd (%r{{[^,]*}}), %ymm{{.*}} +; CHECK: ret +define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) { + %X = load <8 x i16>* %ptr + %Y = sext <8 x i16> %X to <8 x i32> + ret <8 x i32>%Y +} +; CHECK: load_sext_test5 +; CHECK: vpmovsxbd (%r{{[^,]*}}), %ymm{{.*}} +; CHECK: ret +define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) { + %X = load <8 x i8>* %ptr + %Y = sext <8 x i8> %X to <8 x i32> + ret <8 x i32>%Y +} diff --git a/test/CodeGen/X86/avx2-logic.ll b/test/CodeGen/X86/avx2-logic.ll index 13ebaa6f87970..a5bb1a8f8e44b 100644 --- a/test/CodeGen/X86/avx2-logic.ll +++ b/test/CodeGen/X86/avx2-logic.ll @@ -48,9 +48,8 @@ entry: ; CHECK: vpblendvb ; CHECK: vpblendvb %ymm ; CHECK: ret -define <32 x i8> @vpblendvb(<32 x i8> %x, <32 x i8> %y) { - %min_is_x = icmp ult <32 x i8> %x, %y - %min = select <32 x i1> %min_is_x, <32 x i8> %x, <32 x i8> %y +define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) { + %min = select <32 x i1> %cond, <32 x i8> %x, <32 x i8> %y ret <32 x i8> %min } diff --git a/test/CodeGen/X86/avx2-shuffle.ll b/test/CodeGen/X86/avx2-shuffle.ll index a414e6880c325..cf319cb7fe1d2 100644 --- a/test/CodeGen/X86/avx2-shuffle.ll +++ b/test/CodeGen/X86/avx2-shuffle.ll @@ -4,15 +4,62 @@ ; The mask for the vpblendw instruction needs to be identical for both halves ; of the YMM. Need to use two vpblendw instructions. -; CHECK: blendw1 -; CHECK: vpblendw -; CHECK: vpblendw +; CHECK: vpblendw_test1 +; mask = 10010110,b = 150,d +; CHECK: vpblendw $150, %ymm ; CHECK: ret -define <16 x i16> @blendw1(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline { - %t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 31> +define <16 x i16> @vpblendw_test1(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline { + %t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 23, + i32 8, i32 25, i32 26, i32 11, i32 28, i32 13, i32 14, i32 31> ret <16 x i16> %t } +; CHECK: vpblendw_test2 +; mask1 = 00010110 = 22 +; mask2 = 10000000 = 128 +; CHECK: vpblendw $128, %xmm +; CHECK: vpblendw $22, %xmm +; CHECK: vinserti128 +; CHECK: ret +define <16 x i16> @vpblendw_test2(<16 x i16> %a, <16 x i16> %b) nounwind alwaysinline { + %t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 17, i32 18, i32 3, i32 20, i32 5, i32 6, i32 7, + i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 31> + ret <16 x i16> %t +} + +; CHECK: blend_test1 +; CHECK: vpblendd +; CHECK: ret +define <8 x i32> @blend_test1(<8 x i32> %a, <8 x i32> %b) nounwind alwaysinline { + %t = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7> + ret <8 x i32> %t +} + +; CHECK: blend_test2 +; CHECK: vpblendd +; CHECK: ret +define <8 x i32> @blend_test2(<8 x i32> %a, <8 x i32> %b) nounwind alwaysinline { + %t = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7> + ret <8 x i32> %t +} + + +; CHECK: blend_test3 +; CHECK: vblendps +; CHECK: ret +define <8 x float> @blend_test3(<8 x float> %a, <8 x float> %b) nounwind alwaysinline { + %t = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 12, i32 5, i32 6, i32 7> + ret <8 x float> %t +} + +; CHECK: blend_test4 +; CHECK: vblendpd +; CHECK: ret
+define <4 x i64> @blend_test4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
+ %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+ ret <4 x i64> %t
+} + ; CHECK: vpshufhw $27, %ymm define <16 x i16> @vpshufhw(<16 x i16> %src1) nounwind uwtable readnone ssp { entry: diff --git a/test/CodeGen/X86/blend-msb.ll b/test/CodeGen/X86/blend-msb.ll index 11f811f8cf63d..e565da74a082e 100644 --- a/test/CodeGen/X86/blend-msb.ll +++ b/test/CodeGen/X86/blend-msb.ll @@ -5,7 +5,8 @@ ; shifting the needed bit to the MSB, and not using shl+sra. ;CHECK: vsel_float -;CHECK: pslld +;CHECK: movl $-2147483648 +;CHECK-NEXT: movd ;CHECK-NEXT: blendvps ;CHECK: ret define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { @@ -14,7 +15,8 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { } ;CHECK: vsel_4xi8 -;CHECK: pslld +;CHECK: movl $-2147483648 +;CHECK-NEXT: movd ;CHECK-NEXT: blendvps ;CHECK: ret define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) { diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll index 43c47c0fa8a51..b89e648c52d9e 100644 --- a/test/CodeGen/X86/bmi.ll +++ b/test/CodeGen/X86/bmi.ll @@ -26,6 +26,14 @@ define i32 @t3(i32 %x) nounwind { ; CHECK: tzcntl } +define i32 @tzcnt32_load(i32* %x) nounwind { + %x1 = load i32* %x + %tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false ) + ret i32 %tmp +; CHECK: tzcnt32_load: +; CHECK: tzcntl ({{.*}}) +} + define i64 @t4(i64 %x) nounwind { %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false ) ret i64 %tmp @@ -69,6 +77,15 @@ define i32 @andn32(i32 %x, i32 %y) nounwind readnone { ; CHECK: andnl } +define i32 @andn32_load(i32 %x, i32* %y) nounwind readnone { + %y1 = load i32* %y + %tmp1 = xor i32 %x, -1 + %tmp2 = and i32 %y1, %tmp1 + ret i32 %tmp2 +; CHECK: andn32_load: +; CHECK: andnl ({{.*}}) +} + define i64 @andn64(i64 %x, i64 %y) nounwind readnone { %tmp1 = xor i64 %x, -1 %tmp2 = and i64 %tmp1, %y @@ -84,6 +101,14 @@ define i32 @bextr32(i32 %x, i32 %y) nounwind readnone { ; CHECK: bextrl } +define i32 @bextr32_load(i32* %x, i32 %y) nounwind readnone { + %x1 = load i32* %x + %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y) + ret i32 %tmp +; CHECK: bextr32_load: +; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}} +} + declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone define i64 @bextr64(i64 %x, i64 %y) nounwind readnone { @@ -102,6 +127,14 @@ define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone { ; CHECK: bzhil } +define i32 @bzhi32_load(i32* %x, i32 %y) nounwind readnone { + %x1 = load i32* %x + %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y) + ret i32 %tmp +; CHECK: bzhi32_load: +; CHECK: bzhil {{.*}}, ({{.*}}), {{.*}} +} + declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone { @@ -121,6 +154,15 @@ define i32 @blsi32(i32 %x) nounwind readnone { ; CHECK: blsil } +define i32 @blsi32_load(i32* %x) nounwind readnone { + %x1 = load i32* %x + %tmp = sub i32 0, %x1 + %tmp2 = and i32 %x1, %tmp + ret i32 %tmp2 +; CHECK: blsi32_load: +; CHECK: blsil ({{.*}}) +} + define i64 @blsi64(i64 %x) nounwind readnone { %tmp = sub i64 0, %x %tmp2 = and i64 %tmp, %x @@ -137,6 +179,15 @@ define i32 @blsmsk32(i32 %x) nounwind readnone { ; CHECK: blsmskl } +define i32 @blsmsk32_load(i32* %x) nounwind readnone { + %x1 = load i32* %x + %tmp = sub i32 %x1, 1 + %tmp2 = xor i32 %x1, %tmp + ret i32 %tmp2 +; CHECK: blsmsk32_load: +; CHECK: blsmskl ({{.*}}) +} + define i64 @blsmsk64(i64 %x) nounwind readnone { %tmp = sub i64 %x, 1 %tmp2 = xor i64 %tmp, %x @@ -153,6 +204,15 @@ define i32 @blsr32(i32 %x) nounwind readnone { ; CHECK: blsrl } +define i32 @blsr32_load(i32* %x) nounwind readnone { + %x1 = load i32* %x + %tmp = sub i32 %x1, 1 + %tmp2 = and i32 %x1, %tmp + ret i32 %tmp2 +; CHECK: blsr32_load: +; CHECK: blsrl ({{.*}}) +} + define i64 @blsr64(i64 %x) nounwind readnone { %tmp = sub i64 %x, 1 %tmp2 = and i64 %tmp, %x @@ -168,6 +228,14 @@ define i32 @pdep32(i32 %x, i32 %y) nounwind readnone { ; CHECK: pdepl } +define i32 @pdep32_load(i32 %x, i32* %y) nounwind readnone { + %y1 = load i32* %y + %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1) + ret i32 %tmp +; CHECK: pdep32_load: +; CHECK: pdepl ({{.*}}) +} + declare i32 @llvm.x86.bmi.pdep.32(i32, i32) nounwind readnone define i64 @pdep64(i64 %x, i64 %y) nounwind readnone { @@ -186,6 +254,14 @@ define i32 @pext32(i32 %x, i32 %y) nounwind readnone { ; CHECK: pextl } +define i32 @pext32_load(i32 %x, i32* %y) nounwind readnone { + %y1 = load i32* %y + %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1) + ret i32 %tmp +; CHECK: pext32_load: +; CHECK: pextl ({{.*}}) +} + declare i32 @llvm.x86.bmi.pext.32(i32, i32) nounwind readnone define i64 @pext64(i64 %x, i64 %y) nounwind readnone { diff --git a/test/CodeGen/X86/bool-simplify.ll b/test/CodeGen/X86/bool-simplify.ll index 09eb5d1038f75..fa6f6e85e9b81 100644 --- a/test/CodeGen/X86/bool-simplify.ll +++ b/test/CodeGen/X86/bool-simplify.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand,+rdseed | FileCheck %s define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) { %t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c) @@ -39,7 +39,22 @@ define i32 @bax(<2 x i64> %c) { ; CHECK: ret } -define i32 @rnd(i32 %arg) nounwind uwtable { +define i16 @rnd16(i16 %arg) nounwind uwtable { + %1 = tail call { i16, i32 } @llvm.x86.rdrand.16() nounwind + %2 = extractvalue { i16, i32 } %1, 0 + %3 = extractvalue { i16, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i16 0, i16 %arg + %6 = add i16 %5, %2 + ret i16 %6 +; CHECK: rnd16 +; CHECK: rdrand +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i32 @rnd32(i32 %arg) nounwind uwtable { %1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind %2 = extractvalue { i32, i32 } %1, 0 %3 = extractvalue { i32, i32 } %1, 1 @@ -47,12 +62,77 @@ define i32 @rnd(i32 %arg) nounwind uwtable { %5 = select i1 %4, i32 0, i32 %arg %6 = add i32 %5, %2 ret i32 %6 -; CHECK: rnd +; CHECK: rnd32 ; CHECK: rdrand ; CHECK: cmov ; CHECK-NOT: cmov ; CHECK: ret } +define i64 @rnd64(i64 %arg) nounwind uwtable { + %1 = tail call { i64, i32 } @llvm.x86.rdrand.64() nounwind + %2 = extractvalue { i64, i32 } %1, 0 + %3 = extractvalue { i64, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i64 0, i64 %arg + %6 = add i64 %5, %2 + ret i64 %6 +; CHECK: rnd64 +; CHECK: rdrand +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i16 @seed16(i16 %arg) nounwind uwtable { + %1 = tail call { i16, i32 } @llvm.x86.rdseed.16() nounwind + %2 = extractvalue { i16, i32 } %1, 0 + %3 = extractvalue { i16, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i16 0, i16 %arg + %6 = add i16 %5, %2 + ret i16 %6 +; CHECK: seed16 +; CHECK: rdseed +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i32 @seed32(i32 %arg) nounwind uwtable { + %1 = tail call { i32, i32 } @llvm.x86.rdseed.32() nounwind + %2 = extractvalue { i32, i32 } %1, 0 + %3 = extractvalue { i32, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i32 0, i32 %arg + %6 = add i32 %5, %2 + ret i32 %6 +; CHECK: seed32 +; CHECK: rdseed +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i64 @seed64(i64 %arg) nounwind uwtable { + %1 = tail call { i64, i32 } @llvm.x86.rdseed.64() nounwind + %2 = extractvalue { i64, i32 } %1, 0 + %3 = extractvalue { i64, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i64 0, i64 %arg + %6 = add i64 %5, %2 + ret i64 %6 +; CHECK: seed64 +; CHECK: rdseed +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone +declare { i16, i32 } @llvm.x86.rdrand.16() nounwind declare { i32, i32 } @llvm.x86.rdrand.32() nounwind +declare { i64, i32 } @llvm.x86.rdrand.64() nounwind +declare { i16, i32 } @llvm.x86.rdseed.16() nounwind +declare { i32, i32 } @llvm.x86.rdseed.32() nounwind +declare { i64, i32 } @llvm.x86.rdseed.64() nounwind diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll index ec447e5e9c813..39a784dec37d3 100644 --- a/test/CodeGen/X86/bt.ll +++ b/test/CodeGen/X86/bt.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=x86 | grep btl | count 28 -; RUN: llc < %s -march=x86 -mcpu=pentium4 | grep btl | not grep esp -; RUN: llc < %s -march=x86 -mcpu=penryn | grep btl | not grep esp +; RUN: llc < %s -mtriple=i386-apple-macosx -mcpu=penryn | FileCheck %s ; PR3253 ; The register+memory form of the BT instruction should be usable on @@ -21,6 +19,9 @@ define void @test2(i32 %x, i32 %n) nounwind { entry: +; CHECK: test2 +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1] @@ -36,6 +37,9 @@ UnifiedReturnBlock: ; preds = %entry define void @test2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: test2b +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1] @@ -51,6 +55,9 @@ UnifiedReturnBlock: ; preds = %entry define void @atest2(i32 %x, i32 %n) nounwind { entry: +; CHECK: atest2 +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1] @@ -66,6 +73,8 @@ UnifiedReturnBlock: ; preds = %entry define void @atest2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: atest2b +; CHECK: btl %eax, %ecx %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1] @@ -81,6 +90,9 @@ UnifiedReturnBlock: ; preds = %entry define void @test3(i32 %x, i32 %n) nounwind { entry: +; CHECK: test3 +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1] %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1] @@ -96,6 +108,9 @@ UnifiedReturnBlock: ; preds = %entry define void @test3b(i32 %x, i32 %n) nounwind { entry: +; CHECK: test3b +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %x, %tmp29 %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1] @@ -111,6 +126,9 @@ UnifiedReturnBlock: ; preds = %entry define void @testne2(i32 %x, i32 %n) nounwind { entry: +; CHECK: testne2 +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1] @@ -126,6 +144,9 @@ UnifiedReturnBlock: ; preds = %entry define void @testne2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: testne2b +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1] @@ -141,6 +162,9 @@ UnifiedReturnBlock: ; preds = %entry define void @atestne2(i32 %x, i32 %n) nounwind { entry: +; CHECK: atestne2 +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1] @@ -156,6 +180,9 @@ UnifiedReturnBlock: ; preds = %entry define void @atestne2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: atestne2b +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1] @@ -171,6 +198,9 @@ UnifiedReturnBlock: ; preds = %entry define void @testne3(i32 %x, i32 %n) nounwind { entry: +; CHECK: testne3 +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1] %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1] @@ -186,6 +216,9 @@ UnifiedReturnBlock: ; preds = %entry define void @testne3b(i32 %x, i32 %n) nounwind { entry: +; CHECK: testne3b +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %x, %tmp29 %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1] @@ -201,6 +234,9 @@ UnifiedReturnBlock: ; preds = %entry define void @query2(i32 %x, i32 %n) nounwind { entry: +; CHECK: query2 +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1] @@ -216,6 +252,9 @@ UnifiedReturnBlock: ; preds = %entry define void @query2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: query2b +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1] @@ -231,6 +270,9 @@ UnifiedReturnBlock: ; preds = %entry define void @aquery2(i32 %x, i32 %n) nounwind { entry: +; CHECK: aquery2 +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1] @@ -246,6 +288,9 @@ UnifiedReturnBlock: ; preds = %entry define void @aquery2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: aquery2b +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1] @@ -261,6 +306,9 @@ UnifiedReturnBlock: ; preds = %entry define void @query3(i32 %x, i32 %n) nounwind { entry: +; CHECK: query3 +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1] %tmp4 = icmp eq i32 %tmp3, %tmp29 ; <i1> [#uses=1] @@ -276,6 +324,9 @@ UnifiedReturnBlock: ; preds = %entry define void @query3b(i32 %x, i32 %n) nounwind { entry: +; CHECK: query3b +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %x, %tmp29 %tmp4 = icmp eq i32 %tmp3, %tmp29 ; <i1> [#uses=1] @@ -291,6 +342,9 @@ UnifiedReturnBlock: ; preds = %entry define void @query3x(i32 %x, i32 %n) nounwind { entry: +; CHECK: query3x +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1] %tmp4 = icmp eq i32 %tmp29, %tmp3 ; <i1> [#uses=1] @@ -306,6 +360,9 @@ UnifiedReturnBlock: ; preds = %entry define void @query3bx(i32 %x, i32 %n) nounwind { entry: +; CHECK: query3bx +; CHECK: btl %eax, %ecx +; CHECK: jae %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %x, %tmp29 %tmp4 = icmp eq i32 %tmp29, %tmp3 ; <i1> [#uses=1] @@ -321,6 +378,9 @@ UnifiedReturnBlock: ; preds = %entry define void @queryne2(i32 %x, i32 %n) nounwind { entry: +; CHECK: queryne2 +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1] @@ -336,6 +396,9 @@ UnifiedReturnBlock: ; preds = %entry define void @queryne2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: queryne2b +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1] @@ -351,6 +414,9 @@ UnifiedReturnBlock: ; preds = %entry define void @aqueryne2(i32 %x, i32 %n) nounwind { entry: +; CHECK: aqueryne2 +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1] %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1] @@ -366,6 +432,9 @@ UnifiedReturnBlock: ; preds = %entry define void @aqueryne2b(i32 %x, i32 %n) nounwind { entry: +; CHECK: aqueryne2b +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1] %tmp3 = and i32 1, %tmp29 %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1] @@ -381,6 +450,9 @@ UnifiedReturnBlock: ; preds = %entry define void @queryne3(i32 %x, i32 %n) nounwind { entry: +; CHECK: queryne3 +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1] %tmp4 = icmp ne i32 %tmp3, %tmp29 ; <i1> [#uses=1] @@ -396,6 +468,9 @@ UnifiedReturnBlock: ; preds = %entry define void @queryne3b(i32 %x, i32 %n) nounwind { entry: +; CHECK: queryne3b +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %x, %tmp29 %tmp4 = icmp ne i32 %tmp3, %tmp29 ; <i1> [#uses=1] @@ -411,6 +486,9 @@ UnifiedReturnBlock: ; preds = %entry define void @queryne3x(i32 %x, i32 %n) nounwind { entry: +; CHECK: queryne3x +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1] %tmp4 = icmp ne i32 %tmp29, %tmp3 ; <i1> [#uses=1] @@ -426,6 +504,9 @@ UnifiedReturnBlock: ; preds = %entry define void @queryne3bx(i32 %x, i32 %n) nounwind { entry: +; CHECK: queryne3bx +; CHECK: btl %eax, %ecx +; CHECK: jb %tmp29 = shl i32 1, %n ; <i32> [#uses=1] %tmp3 = and i32 %x, %tmp29 %tmp4 = icmp ne i32 %tmp29, %tmp3 ; <i1> [#uses=1] @@ -440,3 +521,16 @@ UnifiedReturnBlock: ; preds = %entry } declare void @foo() + +; rdar://12755626 +define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind { +; CHECK: invert +; CHECK: btl %eax, %ecx +; CHECK: setae +entry: + %neg = xor i32 %flags, -1 + %shl = shl i32 1, %flag + %and = and i32 %shl, %neg + %tobool = icmp ne i32 %and, 0 + ret i1 %tobool +} diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll index 196efe58e6f3e..c5187db6de4bc 100644 --- a/test/CodeGen/X86/byval2.ll +++ b/test/CodeGen/X86/byval2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=-avx | FileCheck %s -check-prefix=X64 ; X64-NOT: movsq ; X64: rep ; X64-NOT: rep @@ -12,7 +12,7 @@ ; Win64 has not supported byval yet. -; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=x86 -mattr=-avx | FileCheck %s -check-prefix=X32 ; X32-NOT: movsl ; X32: rep ; X32-NOT: rep diff --git a/test/CodeGen/X86/byval3.ll b/test/CodeGen/X86/byval3.ll index f3b125c6e3bac..d06fd8898e7fb 100644 --- a/test/CodeGen/X86/byval3.ll +++ b/test/CodeGen/X86/byval3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=-avx | FileCheck %s -check-prefix=X64 ; X64-NOT: movsq ; X64: rep ; X64-NOT: rep @@ -12,7 +12,7 @@ ; Win64 has not supported byval yet. -; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=x86 -mattr=-avx | FileCheck %s -check-prefix=X32 ; X32-NOT: movsl ; X32: rep ; X32-NOT: rep diff --git a/test/CodeGen/X86/byval4.ll b/test/CodeGen/X86/byval4.ll index b7a4aa3f9b016..4711e45111127 100644 --- a/test/CodeGen/X86/byval4.ll +++ b/test/CodeGen/X86/byval4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=-avx | FileCheck %s -check-prefix=X64 ; X64-NOT: movsq ; X64: rep ; X64-NOT: rep @@ -12,7 +12,7 @@ ; Win64 has not supported byval yet. -; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=x86 -mattr=-avx | FileCheck %s -check-prefix=X32 ; X32-NOT: movsl ; X32: rep ; X32-NOT: rep diff --git a/test/CodeGen/X86/byval5.ll b/test/CodeGen/X86/byval5.ll index dca093602241f..f24a5f9aa3b49 100644 --- a/test/CodeGen/X86/byval5.ll +++ b/test/CodeGen/X86/byval5.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=-avx | FileCheck %s -check-prefix=X64 ; X64-NOT: movsq ; X64: rep ; X64-NOT: rep @@ -12,7 +12,7 @@ ; Win64 has not supported byval yet. -; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=x86 -mattr=-avx | FileCheck %s -check-prefix=X32 ; X32-NOT: movsl ; X32: rep ; X32-NOT: rep diff --git a/test/CodeGen/X86/cas.ll b/test/CodeGen/X86/cas.ll new file mode 100644 index 0000000000000..c2dd05ef7302f --- /dev/null +++ b/test/CodeGen/X86/cas.ll @@ -0,0 +1,73 @@ +; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s + +; C code this came from +;bool cas(float volatile *p, float *expected, float desired) { +; bool success; +; __asm__ __volatile__("lock; cmpxchg %[desired], %[mem]; " +; "mov %[expected], %[expected_out]; " +; "sete %[success]" +; : [success] "=a" (success), +; [expected_out] "=rm" (*expected) +; : [expected] "a" (*expected), +; [desired] "q" (desired), +; [mem] "m" (*p) +; : "memory", "cc"); +; return success; +;} + +define zeroext i1 @cas(float* %p, float* %expected, float %desired) nounwind { +entry: + %p.addr = alloca float*, align 8 + %expected.addr = alloca float*, align 8 + %desired.addr = alloca float, align 4 + %success = alloca i8, align 1 + store float* %p, float** %p.addr, align 8 + store float* %expected, float** %expected.addr, align 8 + store float %desired, float* %desired.addr, align 4 + %0 = load float** %expected.addr, align 8 + %1 = load float** %expected.addr, align 8 + %2 = load float* %1, align 4 + %3 = load float* %desired.addr, align 4 + %4 = load float** %p.addr, align 8 + %5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(float* %0, float %2, float %3, float* %4) nounwind + store i8 %5, i8* %success, align 1 + %6 = load i8* %success, align 1 + %tobool = trunc i8 %6 to i1 + ret i1 %tobool +} + +; CHECK: @cas +; Make sure we're emitting a move from eax. +; CHECK: #APP +; CHECK-NEXT: lock;{{.*}}mov %eax,{{.*}} +; CHECK-NEXT: #NO_APP + +define zeroext i1 @cas2(i8* %p, i8* %expected, i1 zeroext %desired) nounwind { +entry: + %p.addr = alloca i8*, align 8 + %expected.addr = alloca i8*, align 8 + %desired.addr = alloca i8, align 1 + %success = alloca i8, align 1 + store i8* %p, i8** %p.addr, align 8 + store i8* %expected, i8** %expected.addr, align 8 + %frombool = zext i1 %desired to i8 + store i8 %frombool, i8* %desired.addr, align 1 + %0 = load i8** %expected.addr, align 8 + %1 = load i8** %expected.addr, align 8 + %2 = load i8* %1, align 1 + %tobool = trunc i8 %2 to i1 + %3 = load i8* %desired.addr, align 1 + %tobool1 = trunc i8 %3 to i1 + %4 = load i8** %p.addr, align 8 + %5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i8* %0, i1 %tobool, i1 %tobool1, i8* %4) nounwind + store i8 %5, i8* %success, align 1 + %6 = load i8* %success, align 1 + %tobool2 = trunc i8 %6 to i1 + ret i1 %tobool2 +} + +; CHECK: @cas2 +; Make sure we're emitting a move from %al here. +; CHECK: #APP +; CHECK-NEXT: lock;{{.*}}mov %al,{{.*}} +; CHECK-NEXT: #NO_APP diff --git a/test/CodeGen/X86/clobber-fi0.ll b/test/CodeGen/X86/clobber-fi0.ll new file mode 100644 index 0000000000000..38a42dbf1aa16 --- /dev/null +++ b/test/CodeGen/X86/clobber-fi0.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.0" + +; In the code below we need to copy the EFLAGS because of scheduling constraints. +; When copying the EFLAGS we need to write to the stack with push/pop. This forces +; us to emit the prolog. + +; CHECK: main +; CHECK: subq{{.*}}rsp +; CHECK: ret +define i32 @main(i32 %arg, i8** %arg1) nounwind { +bb: + %tmp = alloca i32, align 4 ; [#uses=3 type=i32*] + %tmp2 = alloca i32, align 4 ; [#uses=3 type=i32*] + %tmp3 = alloca i32 ; [#uses=1 type=i32*] + store i32 1, i32* %tmp, align 4 + store i32 1, i32* %tmp2, align 4 + br label %bb4 + +bb4: ; preds = %bb4, %bb + %tmp6 = load i32* %tmp2, align 4 ; [#uses=1 type=i32] + %tmp7 = add i32 %tmp6, -1 ; [#uses=2 type=i32] + store i32 %tmp7, i32* %tmp2, align 4 + %tmp8 = icmp eq i32 %tmp7, 0 ; [#uses=1 type=i1] + %tmp9 = load i32* %tmp ; [#uses=1 type=i32] + %tmp10 = add i32 %tmp9, -1 ; [#uses=1 type=i32] + store i32 %tmp10, i32* %tmp3 + br i1 %tmp8, label %bb11, label %bb4 + +bb11: ; preds = %bb4 + %tmp12 = load i32* %tmp, align 4 ; [#uses=1 type=i32] + ret i32 %tmp12 +} + + diff --git a/test/CodeGen/X86/cmp.ll b/test/CodeGen/X86/cmp.ll index eb06327f55a69..1855fe2fb89e3 100644 --- a/test/CodeGen/X86/cmp.ll +++ b/test/CodeGen/X86/cmp.ll @@ -151,3 +151,18 @@ entry: %conv = zext i1 %cmp to i32 ret i32 %conv } + +define i32 @test12() uwtable ssp { +; CHECK: test12: +; CHECK: testb + %1 = call zeroext i1 @test12b() + br i1 %1, label %2, label %3 + +; <label>:2 ; preds = %0 + ret i32 1 + +; <label>:3 ; preds = %0 + ret i32 2 +} + +declare zeroext i1 @test12b() diff --git a/test/CodeGen/X86/coalesce-implicitdef.ll b/test/CodeGen/X86/coalesce-implicitdef.ll new file mode 100644 index 0000000000000..19cd08cf3797c --- /dev/null +++ b/test/CodeGen/X86/coalesce-implicitdef.ll @@ -0,0 +1,130 @@ +; RUN: llc < %s -verify-coalescing +; PR14732 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10" + +@c = common global i32 0, align 4 +@b = common global i32 0, align 4 +@a = common global i32 0, align 4 +@d = common global i32 0, align 4 + +; This function creates an IMPLICIT_DEF with a long live range, even after +; ProcessImplicitDefs. +; +; The coalescer should be able to deal with all kinds of IMPLICIT_DEF live +; ranges, even if they are not common. + +define void @f() nounwind uwtable ssp { +entry: + %i = alloca i32, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc34, %entry + %i.0.load44 = phi i32 [ %inc35, %for.inc34 ], [ undef, %entry ] + %pi.0 = phi i32* [ %pi.4, %for.inc34 ], [ undef, %entry ] + %tobool = icmp eq i32 %i.0.load44, 0 + br i1 %tobool, label %for.end36, label %for.body + +for.body: ; preds = %for.cond + store i32 0, i32* @c, align 4, !tbaa !0 + br label %for.body2 + +for.body2: ; preds = %for.body, %for.inc + %i.0.load45 = phi i32 [ %i.0.load44, %for.body ], [ 0, %for.inc ] + %tobool3 = icmp eq i32 %i.0.load45, 0 + br i1 %tobool3, label %if.then10, label %if.then + +if.then: ; preds = %for.body2 + store i32 0, i32* %i, align 4, !tbaa !0 + br label %for.body6 + +for.body6: ; preds = %if.then, %for.body6 + store i32 0, i32* %i, align 4 + br i1 true, label %for.body6, label %for.inc + +if.then10: ; preds = %for.body2 + store i32 1, i32* @b, align 4, !tbaa !0 + ret void + +for.inc: ; preds = %for.body6 + br i1 undef, label %for.body2, label %if.end30 + +while.condthread-pre-split: ; preds = %label.loopexit, %while.condthread-pre-split.lr.ph.lr.ph, %for.inc27.backedge + %0 = phi i32 [ %inc28, %for.inc27.backedge ], [ %inc285863, %while.condthread-pre-split.lr.ph.lr.ph ], [ %inc2858, %label.loopexit ] + %inc2060 = phi i32 [ %inc20, %for.inc27.backedge ], [ %a.promoted.pre, %while.condthread-pre-split.lr.ph.lr.ph ], [ %inc20, %label.loopexit ] + br label %while.cond + +while.cond: ; preds = %while.condthread-pre-split, %while.cond + %p2.1.in = phi i32* [ %pi.3.ph, %while.cond ], [ %i, %while.condthread-pre-split ] + %p2.1 = bitcast i32* %p2.1.in to i16* + br i1 %tobool19, label %while.end, label %while.cond + +while.end: ; preds = %while.cond + %inc20 = add nsw i32 %inc2060, 1 + %tobool21 = icmp eq i32 %inc2060, 0 + br i1 %tobool21, label %for.inc27.backedge, label %if.then22 + +for.inc27.backedge: ; preds = %while.end, %if.then22 + %inc28 = add nsw i32 %0, 1 + store i32 %inc28, i32* @b, align 4, !tbaa !0 + %tobool17 = icmp eq i32 %inc28, 0 + br i1 %tobool17, label %for.inc27.if.end30.loopexit56_crit_edge, label %while.condthread-pre-split + +if.then22: ; preds = %while.end + %1 = load i16* %p2.1, align 2, !tbaa !3 + %tobool23 = icmp eq i16 %1, 0 + br i1 %tobool23, label %for.inc27.backedge, label %label.loopexit + +label.loopexit: ; preds = %if.then22 + store i32 %inc20, i32* @a, align 4, !tbaa !0 + %inc2858 = add nsw i32 %0, 1 + store i32 %inc2858, i32* @b, align 4, !tbaa !0 + %tobool1759 = icmp eq i32 %inc2858, 0 + br i1 %tobool1759, label %if.end30, label %while.condthread-pre-split + +for.inc27.if.end30.loopexit56_crit_edge: ; preds = %for.inc27.backedge + store i32 %inc20, i32* @a, align 4, !tbaa !0 + br label %if.end30 + +if.end30: ; preds = %for.inc27.if.end30.loopexit56_crit_edge, %label.loopexit, %label.preheader, %for.inc + %i.0.load46 = phi i32 [ 0, %for.inc ], [ %i.0.load4669, %label.preheader ], [ %i.0.load4669, %label.loopexit ], [ %i.0.load4669, %for.inc27.if.end30.loopexit56_crit_edge ] + %pi.4 = phi i32* [ %i, %for.inc ], [ %pi.3.ph, %label.preheader ], [ %pi.3.ph, %label.loopexit ], [ %pi.3.ph, %for.inc27.if.end30.loopexit56_crit_edge ] + %2 = load i32* %pi.4, align 4, !tbaa !0 + %tobool31 = icmp eq i32 %2, 0 + br i1 %tobool31, label %for.inc34, label %label.preheader + +for.inc34: ; preds = %if.end30 + %inc35 = add nsw i32 %i.0.load46, 1 + store i32 %inc35, i32* %i, align 4 + br label %for.cond + +for.end36: ; preds = %for.cond + store i32 1, i32* %i, align 4 + %3 = load i32* @c, align 4, !tbaa !0 + %tobool37 = icmp eq i32 %3, 0 + br i1 %tobool37, label %label.preheader, label %land.rhs + +land.rhs: ; preds = %for.end36 + store i32 0, i32* @a, align 4, !tbaa !0 + br label %label.preheader + +label.preheader: ; preds = %for.end36, %if.end30, %land.rhs + %i.0.load4669 = phi i32 [ 1, %land.rhs ], [ %i.0.load46, %if.end30 ], [ 1, %for.end36 ] + %pi.3.ph = phi i32* [ %pi.0, %land.rhs ], [ %pi.4, %if.end30 ], [ %pi.0, %for.end36 ] + %4 = load i32* @b, align 4, !tbaa !0 + %inc285863 = add nsw i32 %4, 1 + store i32 %inc285863, i32* @b, align 4, !tbaa !0 + %tobool175964 = icmp eq i32 %inc285863, 0 + br i1 %tobool175964, label %if.end30, label %while.condthread-pre-split.lr.ph.lr.ph + +while.condthread-pre-split.lr.ph.lr.ph: ; preds = %label.preheader + %.pr50 = load i32* @d, align 4, !tbaa !0 + %tobool19 = icmp eq i32 %.pr50, 0 + %a.promoted.pre = load i32* @a, align 4, !tbaa !0 + br label %while.condthread-pre-split +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"short", metadata !1} diff --git a/test/CodeGen/X86/coldcc64.ll b/test/CodeGen/X86/coldcc64.ll new file mode 100644 index 0000000000000..4db56bbaea2dc --- /dev/null +++ b/test/CodeGen/X86/coldcc64.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s | FileCheck %s + +target triple = "x86_64-linux-gnu" + +define coldcc void @foo() { +; CHECK: pushq %rbp +; CHECK: pushq %r15 +; CHECK: pushq %r14 +; CHECK: pushq %r13 +; CHECK: pushq %r12 +; CHECK: pushq %r11 +; CHECK: pushq %r10 +; CHECK: pushq %r9 +; CHECK: pushq %r8 +; CHECK: pushq %rdi +; CHECK: pushq %rsi +; CHECK: pushq %rdx +; CHECK: pushq %rcx +; CHECK: pushq %rbx +; CHECK: movaps %xmm15 +; CHECK: movaps %xmm0 + call void asm sideeffect "", "~{xmm15},~{xmm0},~{rbp},~{r15},~{r14},~{r13},~{r12},~{r11},~{r10},~{r9},~{r8},~{rdi},~{rsi},~{rdx},~{rcx},~{rbx}"() + ret void +} diff --git a/test/CodeGen/X86/complex-fca.ll b/test/CodeGen/X86/complex-fca.ll index 7e7acaa98a764..8ad38a4ee5c03 100644 --- a/test/CodeGen/X86/complex-fca.ll +++ b/test/CodeGen/X86/complex-fca.ll @@ -1,5 +1,8 @@ ; RUN: llc < %s -march=x86 | grep mov | count 2 +; Skip this on Windows as there is no ccosl and sret behaves differently. +; XFAIL: pc-win32 + define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %z) nounwind { entry: %z8 = extractvalue { x86_fp80, x86_fp80 } %z, 0 diff --git a/test/CodeGen/X86/constant-pool-remat-0.ll b/test/CodeGen/X86/constant-pool-remat-0.ll index 4be14d2128efa..4a0110896cedb 100644 --- a/test/CodeGen/X86/constant-pool-remat-0.ll +++ b/test/CodeGen/X86/constant-pool-remat-0.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-linux -regalloc=greedy | FileCheck %s ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll index 064ee364d14e1..74a7240c81905 100644 --- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll +++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-linux -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS ; RUN: llc < %s -mtriple=x86_64-win32 -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS ; STATS: 9 asm-printer diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 276d0db9a4f3a..6d2196206e7c0 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -431,7 +431,7 @@ return: ; preds = %entry ; uitofp expands to an FCMOV instruction which splits the basic block. ; Make sure the live range of %AL isn't split. @.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32 -define void @pr13188(i64* nocapture %this) uwtable ssp address_safety align 2 { +define void @pr13188(i64* nocapture %this) uwtable ssp sanitize_address align 2 { entry: %x7 = load i64* %this, align 8 %sub = add i64 %x7, -1 diff --git a/test/CodeGen/X86/cvtv2f32.ll b/test/CodeGen/X86/cvtv2f32.ll index 466b09606786f..d11bb9ee3e754 100644 --- a/test/CodeGen/X86/cvtv2f32.ll +++ b/test/CodeGen/X86/cvtv2f32.ll @@ -1,3 +1,7 @@ +; A bug fix in the DAGCombiner made this test fail, so marking as xfail +; until this can be investigated further. +; XFAIL: * + ; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s define <2 x float> @foo(i32 %x, i32 %y, <2 x float> %v) { diff --git a/test/CodeGen/X86/dagcombine-cse.ll b/test/CodeGen/X86/dagcombine-cse.ll index af69531246cf2..75d3d93ddb896 100644 --- a/test/CodeGen/X86/dagcombine-cse.ll +++ b/test/CodeGen/X86/dagcombine-cse.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -stats 2>&1 | grep asm-printer | grep 14 define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) nounwind { diff --git a/test/CodeGen/X86/dagcombine_unsafe_math.ll b/test/CodeGen/X86/dagcombine_unsafe_math.ll new file mode 100644 index 0000000000000..592cf1bec2e5e --- /dev/null +++ b/test/CodeGen/X86/dagcombine_unsafe_math.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -enable-unsafe-fp-math -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s + + +; rdar://13126763 +; Expression "x + x*x" was mistakenly transformed into "x * 3.0f". + +define float @test1(float %x) { + %t1 = fmul fast float %x, %x + %t2 = fadd fast float %t1, %x + ret float %t2 +; CHECK: test1 +; CHECK: vaddss +} + +; (x + x) + x => x * 3.0 +define float @test2(float %x) { + %t1 = fadd fast float %x, %x + %t2 = fadd fast float %t1, %x + ret float %t2 +; CHECK: .long 1077936128 +; CHECK: test2 +; CHECK: vmulss LCPI1_0(%rip), %xmm0, %xmm0 +} + +; x + (x + x) => x * 3.0 +define float @test3(float %x) { + %t1 = fadd fast float %x, %x + %t2 = fadd fast float %t1, %x + ret float %t2 +; CHECK: .long 1077936128 +; CHECK: test3 +; CHECK: vmulss LCPI2_0(%rip), %xmm0, %xmm0 +} + +; (y + x) + x != x * 3.0 +define float @test4(float %x, float %y) { + %t1 = fadd fast float %x, %y + %t2 = fadd fast float %t1, %x + ret float %t2 +; CHECK: test4 +; CHECK: vaddss +} + +; rdar://13445387 +; "x + x + x => 3.0 * x" should be disabled after legalization because +; Instruction-Selection dosen't know how to handle "3.0" +; +define float @test5() { + %mul.i.i151 = fmul <4 x float> zeroinitializer, zeroinitializer + %vecext.i8.i152 = extractelement <4 x float> %mul.i.i151, i32 1 + %vecext1.i9.i153 = extractelement <4 x float> %mul.i.i151, i32 0 + %add.i10.i154 = fadd float %vecext1.i9.i153, %vecext.i8.i152 + %vecext.i7.i155 = extractelement <4 x float> %mul.i.i151, i32 2 + %add.i.i156 = fadd float %vecext.i7.i155, %add.i10.i154 + ret float %add.i.i156 +} diff --git a/test/CodeGen/X86/dbg-at-specficiation.ll b/test/CodeGen/X86/dbg-at-specficiation.ll index aa5e6efede274..48b8202bd5fa1 100644 --- a/test/CodeGen/X86/dbg-at-specficiation.ll +++ b/test/CodeGen/X86/dbg-at-specficiation.ll @@ -17,4 +17,4 @@ !7 = metadata !{i32 720897, null, metadata !"", null, i32 0, i64 320, i64 32, i32 0, i32 0, metadata !8, metadata !9, i32 0, i32 0} ; [ DW_TAG_array_type ] !8 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !9 = metadata !{metadata !10} -!10 = metadata !{i32 720929, i64 0, i64 9} ; [ DW_TAG_subrange_type ] +!10 = metadata !{i32 720929, i64 0, i64 10} ; [ DW_TAG_subrange_type ] diff --git a/test/CodeGen/X86/dbg-byval-parameter.ll b/test/CodeGen/X86/dbg-byval-parameter.ll index 5e5577620d97b..aca06a27a1df5 100644 --- a/test/CodeGen/X86/dbg-byval-parameter.ll +++ b/test/CodeGen/X86/dbg-byval-parameter.ll @@ -25,21 +25,25 @@ return: ; preds = %entry declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone -!0 = metadata !{i32 524545, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 524329, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!llvm.dbg.cu = !{!3} + +!0 = metadata !{i32 786689, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !7} -!6 = metadata !{i32 524324, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 524307, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] +!6 = metadata !{i32 786468, metadata !19, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Rect", i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] !8 = metadata !{metadata !9, metadata !14} -!9 = metadata !{i32 524301, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] -!10 = metadata !{i32 524307, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!9 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P1", i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Pt", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] !11 = metadata !{metadata !12, metadata !13} -!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] -!13 = metadata !{i32 524301, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] -!14 = metadata !{i32 524301, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] +!12 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"x", i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"y", i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!14 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P2", i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] !15 = metadata !{i32 11, i32 0, metadata !1, null} !16 = metadata !{i32 12, i32 0, metadata !17, null} -!17 = metadata !{i32 524299, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] +!17 = metadata !{i32 786443, metadata !2, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] +!18 = metadata !{metadata !1} +!19 = metadata !{metadata !"b2.c", metadata !"/tmp/"} diff --git a/test/CodeGen/X86/dbg-const-int.ll b/test/CodeGen/X86/dbg-const-int.ll index bfc96f17ec9bd..aabc2068068d9 100644 --- a/test/CodeGen/X86/dbg-const-int.ll +++ b/test/CodeGen/X86/dbg-const-int.ll @@ -13,17 +13,18 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!llvm.dbg.sp = !{!1} -!llvm.dbg.lv.foo = !{!6} -!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 132191)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 132191)", i1 true, metadata !"", i32 0, null, null, metadata !11, null, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !12, i32 0} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 590080, metadata !7, metadata !"i", metadata !2, i32 2, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!7 = metadata !{i32 589835, metadata !1, i32 1, i32 11, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786688, metadata !7, metadata !"i", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!7 = metadata !{i32 786443, metadata !2, metadata !1, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] !8 = metadata !{i32 42} !9 = metadata !{i32 2, i32 12, metadata !7, null} !10 = metadata !{i32 3, i32 2, metadata !7, null} +!11 = metadata !{metadata !1} +!12 = metadata !{metadata !6} +!13 = metadata !{metadata !"a.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/dbg-const.ll b/test/CodeGen/X86/dbg-const.ll index 5a51eb88b895e..a9b8f1fdc4f3b 100644 --- a/test/CodeGen/X86/dbg-const.ll +++ b/test/CodeGen/X86/dbg-const.ll @@ -16,19 +16,21 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone declare i32 @bar() nounwind readnone -!llvm.dbg.sp = !{!0} -!llvm.dbg.lv.foobar = !{!6} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar} -!1 = metadata !{i32 524329, metadata !"mu.c", metadata !"/private/tmp", metadata !2} -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"mu.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 114183)", i1 true, i1 true, metadata !"", i32 0} -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} +!0 = metadata !{i32 786478, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar, null, null, metadata !14, i32 0} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 114183)", i1 true, metadata !"", i32 0, null, null, metadata !13, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} !4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} -!6 = metadata !{i32 524544, metadata !7, metadata !"j", metadata !1, i32 15, metadata !5} -!7 = metadata !{i32 524299, metadata !0, i32 12, i32 52, metadata !1, i32 0} +!5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} +!6 = metadata !{i32 786688, metadata !7, metadata !"j", metadata !1, i32 15, metadata !5, i32 0, null} +!7 = metadata !{i32 786443, metadata !1, metadata !0, i32 12, i32 52, i32 0} ; [ DW_TAG_lexical_block ] !8 = metadata !{i32 42} !9 = metadata !{i32 15, i32 12, metadata !7, null} !10 = metadata !{i32 23, i32 3, metadata !7, null} !11 = metadata !{i32 17, i32 3, metadata !7, null} !12 = metadata !{i32 18, i32 3, metadata !7, null} +!13 = metadata !{metadata !0} +!14 = metadata !{metadata !6} +!15 = metadata !{metadata !"mu.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/dbg-declare-arg.ll b/test/CodeGen/X86/dbg-declare-arg.ll index 367c1ef36c60e..f7e0c91cdff25 100644 --- a/test/CodeGen/X86/dbg-declare-arg.ll +++ b/test/CodeGen/X86/dbg-declare-arg.ll @@ -69,55 +69,57 @@ entry: ret void, !dbg !48 } -!llvm.dbg.sp = !{!0, !10, !14, !19, !22, !25} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"~A", metadata !"~A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 589826, metadata !2, metadata !"A", metadata !3, i32 2, i64 128, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ] -!2 = metadata !{i32 589841, i32 0, i32 4, metadata !"a.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 130127)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589865, metadata !"a.cc", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 4, metadata !3, metadata !"clang version 3.0 (trunk 130127)", i1 false, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786473, metadata !51} ; [ DW_TAG_file_type ] !4 = metadata !{metadata !5, metadata !7, metadata !8, metadata !9, metadata !0, metadata !10, metadata !14} -!5 = metadata !{i32 589837, metadata !3, metadata !"x", metadata !3, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] -!6 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 589837, metadata !3, metadata !"y", metadata !3, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !6} ; [ DW_TAG_member ] -!8 = metadata !{i32 589837, metadata !3, metadata !"z", metadata !3, i32 2, i64 32, i64 32, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] -!9 = metadata !{i32 589837, metadata !3, metadata !"o", metadata !3, i32 2, i64 32, i64 32, i64 96, i32 0, metadata !6} ; [ DW_TAG_member ] -!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786445, metadata !3, metadata !"x", metadata !3, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786445, metadata !3, metadata !"y", metadata !3, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !6} ; [ DW_TAG_member ] +!8 = metadata !{i32 786445, metadata !3, metadata !"z", metadata !3, i32 2, i64 32, i64 32, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!9 = metadata !{i32 786445, metadata !3, metadata !"o", metadata !3, i32 2, i64 32, i64 32, i64 96, i32 0, metadata !6} ; [ DW_TAG_member ] +!10 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"A", metadata !"A", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !12 = metadata !{null, metadata !13} -!13 = metadata !{i32 589839, metadata !2, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] -!14 = metadata !{i32 589870, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!13 = metadata !{i32 786447, metadata !2, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"A", metadata !"A", metadata !3, i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !16 = metadata !{null, metadata !13, metadata !17} !17 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_reference_type ] -!18 = metadata !{i32 589862, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_const_type ] -!19 = metadata !{i32 589870, i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !"_Z3fooi", metadata !3, i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null} ; [ DW_TAG_subprogram ] -!20 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!18 = metadata !{i32 786470, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_const_type ] +!19 = metadata !{i32 786478, metadata !"_Z3fooi", i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !3, i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null} ; [ DW_TAG_subprogram ] +!20 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !21 = metadata !{metadata !1} -!22 = metadata !{i32 589870, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD1Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null} ; [ DW_TAG_subprogram ] -!23 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!22 = metadata !{i32 786478, metadata !"_ZN1AD1Ev", i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null} ; [ DW_TAG_subprogram ] +!23 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !24 = metadata !{null} -!25 = metadata !{i32 589870, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD2Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null} ; [ DW_TAG_subprogram ] -!26 = metadata !{i32 590081, metadata !19, metadata !"i", metadata !3, i32 16777220, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 786478, metadata !"_ZN1AD2Ev", i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null} ; [ DW_TAG_subprogram ] +!26 = metadata !{i32 786689, metadata !19, metadata !"i", metadata !3, i32 16777220, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !27 = metadata !{i32 4, i32 11, metadata !19, null} -!28 = metadata !{i32 590080, metadata !29, metadata !"j", metadata !3, i32 5, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] -!29 = metadata !{i32 589835, metadata !19, i32 4, i32 14, metadata !3, i32 0} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786688, metadata !29, metadata !"j", metadata !3, i32 5, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 786443, metadata !19, i32 4, i32 14, metadata !3, i32 0} ; [ DW_TAG_lexical_block ] !30 = metadata !{i32 5, i32 7, metadata !29, null} !31 = metadata !{i32 5, i32 12, metadata !29, null} !32 = metadata !{i32 6, i32 3, metadata !29, null} !33 = metadata !{i32 7, i32 5, metadata !34, null} -!34 = metadata !{i32 589835, metadata !29, i32 6, i32 16, metadata !3, i32 1} ; [ DW_TAG_lexical_block ] +!34 = metadata !{i32 786443, metadata !29, i32 6, i32 16, metadata !3, i32 1} ; [ DW_TAG_lexical_block ] !35 = metadata !{i32 8, i32 3, metadata !34, null} !36 = metadata !{i32 9, i32 9, metadata !29, null} -!37 = metadata !{i32 590080, metadata !29, metadata !"my_a", metadata !3, i32 9, metadata !38, i32 0} ; [ DW_TAG_auto_variable ] +!37 = metadata !{i32 786688, metadata !29, metadata !"my_a", metadata !3, i32 9, metadata !38, i32 0, null} ; [ DW_TAG_auto_variable ] !38 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] !39 = metadata !{i32 9, i32 5, metadata !29, null} !40 = metadata !{i32 10, i32 3, metadata !29, null} !41 = metadata !{i32 11, i32 3, metadata !29, null} !42 = metadata !{i32 12, i32 1, metadata !29, null} -!43 = metadata !{i32 590081, metadata !22, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64} ; [ DW_TAG_arg_variable ] +!43 = metadata !{i32 786689, metadata !22, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64, null} ; [ DW_TAG_arg_variable ] !44 = metadata !{i32 2, i32 47, metadata !22, null} !45 = metadata !{i32 2, i32 61, metadata !22, null} -!46 = metadata !{i32 590081, metadata !25, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64} ; [ DW_TAG_arg_variable ] +!46 = metadata !{i32 786689, metadata !25, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64, null} ; [ DW_TAG_arg_variable ] !47 = metadata !{i32 2, i32 47, metadata !25, null} !48 = metadata !{i32 2, i32 54, metadata !49, null} -!49 = metadata !{i32 589835, metadata !25, i32 2, i32 52, metadata !3, i32 2} ; [ DW_TAG_lexical_block ] +!49 = metadata !{i32 786443, metadata !25, i32 2, i32 52, metadata !3, i32 2} ; [ DW_TAG_lexical_block ] +!50 = metadata !{metadata !0, metadata !10, metadata !14, metadata !19, metadata !22, metadata !25} +!51 = metadata !{metadata !"a.cc", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/dbg-declare.ll b/test/CodeGen/X86/dbg-declare.ll index 5d4cedc5c4e33..6ac397ac42e19 100644 --- a/test/CodeGen/X86/dbg-declare.ll +++ b/test/CodeGen/X86/dbg-declare.ll @@ -29,12 +29,10 @@ declare void @llvm.stackrestore(i8*) nounwind !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"20020104-2.c", metadata !"/Volumes/Sandbox/llvm", metadata !"clang version 3.1 (trunk 153698)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] -!1 = metadata !{metadata !2} -!2 = metadata !{i32 0} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !5} -!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*)* @foo, null, null, metadata !12} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 153698)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 0} +!3 = metadata !{metadata !5} +!5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*)* @foo, null, null, metadata !12} ; [ DW_TAG_subprogram ] !6 = metadata !{i32 786473, metadata !"20020104-2.c", metadata !"/Volumes/Sandbox/llvm", null} ; [ DW_TAG_file_type ] !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !9, metadata !10} @@ -51,7 +49,7 @@ declare void @llvm.stackrestore(i8*) nounwind !19 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 0, i64 8, i32 0, i32 0, metadata !20, metadata !21, i32 0, i32 0} ; [ DW_TAG_array_type ] !20 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] !21 = metadata !{metadata !22} -!22 = metadata !{i32 786465, i64 1, i64 0} ; [ DW_TAG_subrange_type ] +!22 = metadata !{i32 786465, i64 0, i64 -1} ; [ DW_TAG_subrange_type ] !23 = metadata !{i32 7, i32 8, metadata !17, null} !24 = metadata !{i32 9, i32 1, metadata !17, null} !25 = metadata !{i32 8, i32 3, metadata !17, null} diff --git a/test/CodeGen/X86/dbg-file-name.ll b/test/CodeGen/X86/dbg-file-name.ll index adf9854610551..1bd3d77522a3e 100644 --- a/test/CodeGen/X86/dbg-file-name.ll +++ b/test/CodeGen/X86/dbg-file-name.ll @@ -9,11 +9,13 @@ define i32 @main() nounwind { ret i32 0 } -!llvm.dbg.sp = !{ !6} +!llvm.dbg.cu = !{!2} -!1 = metadata !{i32 589865, metadata !"simple.c", metadata !"/Users/manav/one/two", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"simple.c", metadata !"/Users/manav/one/two", metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!5 = metadata !{i32 589860, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ] +!1 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !10, i32 1, metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !9, null} ; [ DW_TAG_compile_unit ] +!5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, null, i32 0} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !5} +!9 = metadata !{metadata !6} +!10 = metadata !{metadata !"simple.c", metadata !"/Users/manav/one/two"} diff --git a/test/CodeGen/X86/dbg-i128-const.ll b/test/CodeGen/X86/dbg-i128-const.ll index bd96d9195d021..17d645757d996 100644 --- a/test/CodeGen/X86/dbg-i128-const.ll +++ b/test/CodeGen/X86/dbg-i128-const.ll @@ -12,15 +12,20 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +!llvm.dbg.cu = !{!5} + !0 = metadata !{i128 42 } -!1 = metadata !{i32 524544, metadata !2, metadata !"MAX", metadata !4, i32 29, metadata !8} ; [ DW_TAG_auto_variable ] -!2 = metadata !{i32 524299, metadata !3, i32 26, i32 0} ; [ DW_TAG_lexical_block ] -!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] -!4 = metadata !{i32 524329, metadata !"foo.c", metadata !"/tmp", metadata !5} ; [ DW_TAG_file_type ] -!5 = metadata !{i32 524305, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp", metadata !"clang", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!1 = metadata !{i32 786688, metadata !2, metadata !"MAX", metadata !4, i32 29, metadata !8, i32 0, null} ; [ DW_TAG_auto_variable ] +!2 = metadata !{i32 786443, metadata !4, metadata !3, i32 26, i32 0, i32 0} ; [ DW_TAG_lexical_block ] +!3 = metadata !{i32 786478, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i128 (i128, i128)* @__foo, null, null, null, i32 26} ; [ DW_TAG_subprogram ] +!4 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ] +!5 = metadata !{i32 786449, i32 1, metadata !4, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !12, null, metadata !""} ; [ DW_TAG_compile_unit ] +!6 = metadata !{i32 786453, metadata !13, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] !7 = metadata !{metadata !8, metadata !8, metadata !8} -!8 = metadata !{i32 524310, metadata !4, metadata !"ti_int", metadata !9, i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] -!9 = metadata !{i32 524329, metadata !"myint.h", metadata !"/tmp", metadata !5} ; [ DW_TAG_file_type ] -!10 = metadata !{i32 524324, metadata !4, metadata !"", metadata !4, i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 786454, metadata !14, metadata !4, metadata !"ti_int", i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] +!9 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ] +!10 = metadata !{i32 786468, metadata !13, metadata !4, metadata !"", i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !11 = metadata !{i32 29, i32 0, metadata !2, null} +!12 = metadata !{metadata !3} +!13 = metadata !{metadata !"foo.c", metadata !"/tmp"} +!14 = metadata !{metadata !"myint.h", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-large-unsigned-const.ll b/test/CodeGen/X86/dbg-large-unsigned-const.ll index fc295c679445f..ff16318efcec4 100644 --- a/test/CodeGen/X86/dbg-large-unsigned-const.ll +++ b/test/CodeGen/X86/dbg-large-unsigned-const.ll @@ -26,36 +26,36 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!llvm.dbg.sp = !{!1, !6} -!llvm.dbg.lv._Z3iseRKxS0_ = !{!7, !11} -!llvm.dbg.lv._Z2fnx = !{!12} +!29 = metadata !{metadata !1, metadata !6} +!30 = metadata !{metadata !7, metadata !11} +!31 = metadata !{metadata !12} -!0 = metadata !{i32 655377, i32 0, i32 4, metadata !"lli.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 135593)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 655406, i32 0, metadata !2, metadata !"ise", metadata !"ise", metadata !"_Z3iseRKxS0_", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64*, i64*)* @_Z3iseRKxS0_, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 655401, metadata !"lli.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 655381, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786449, i32 4, metadata !2, metadata !"clang version 3.0 (trunk 135593)", i1 true, metadata !"", i32 0, null, null, metadata !29, null, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !"_Z3iseRKxS0_", i32 0, metadata !2, metadata !"ise", metadata !"ise", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64*, i64*)* @_Z3iseRKxS0_, null, null, metadata !30, i32 2} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !"lli.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 655396, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 655406, i32 0, metadata !2, metadata !"fn", metadata !"fn", metadata !"_Z2fnx", metadata !2, i32 6, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64)* @_Z2fnx, null, null} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 655617, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] -!8 = metadata !{i32 655376, metadata !0, null, null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !9} ; [ DW_TAG_reference_type ] -!9 = metadata !{i32 655398, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_const_type ] -!10 = metadata !{i32 655396, metadata !0, metadata !"long long int", null, i32 0, i64 64, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!11 = metadata !{i32 655617, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] -!12 = metadata !{i32 655617, metadata !6, metadata !"a", metadata !2, i32 16777222, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!5 = metadata !{i32 786468, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !"_Z2fnx", i32 0, metadata !2, metadata !"fn", metadata !"fn", metadata !2, i32 6, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64)* @_Z2fnx, null, null, metadata !31, i32 6} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786689, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 786448, metadata !0, null, null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !9} ; [ DW_TAG_reference_type ] +!9 = metadata !{i32 786470, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_const_type ] +!10 = metadata !{i32 786468, metadata !0, metadata !"long long int", null, i32 0, i64 64, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!11 = metadata !{i32 786689, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] +!12 = metadata !{i32 786689, metadata !6, metadata !"a", metadata !2, i32 16777222, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] !13 = metadata !{i32 2, i32 27, metadata !1, null} !14 = metadata !{i32 2, i32 49, metadata !1, null} !15 = metadata !{i32 3, i32 3, metadata !16, null} -!16 = metadata !{i32 655371, metadata !1, i32 2, i32 54, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786443, metadata !2, metadata !1, i32 2, i32 54, i32 0} ; [ DW_TAG_lexical_block ] !17 = metadata !{metadata !"long long", metadata !18} !18 = metadata !{metadata !"omnipotent char", metadata !19} !19 = metadata !{metadata !"Simple C/C++ TBAA", null} !20 = metadata !{i32 6, i32 19, metadata !6, null} -!21 = metadata !{i32 655617, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 786689, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] !22 = metadata !{i32 7, i32 10, metadata !23, null} -!23 = metadata !{i32 655371, metadata !6, i32 6, i32 22, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!23 = metadata !{i32 786443, metadata !2, metadata !6, i32 6, i32 22, i32 1} ; [ DW_TAG_lexical_block ] !24 = metadata !{i32 2, i32 27, metadata !1, metadata !22} !25 = metadata !{i64 9223372036854775807} -!26 = metadata !{i32 655617, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] +!26 = metadata !{i32 786689, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] !27 = metadata !{i32 2, i32 49, metadata !1, metadata !22} !28 = metadata !{i32 3, i32 3, metadata !16, metadata !22} diff --git a/test/CodeGen/X86/dbg-merge-loc-entry.ll b/test/CodeGen/X86/dbg-merge-loc-entry.ll index d1e349f79d6fa..baad6c0b60e65 100644 --- a/test/CodeGen/X86/dbg-merge-loc-entry.ll +++ b/test/CodeGen/X86/dbg-merge-loc-entry.ll @@ -43,33 +43,36 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone -!llvm.dbg.sp = !{!0, !9} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"__udivmodti4", metadata !"__udivmodti4", metadata !"", metadata !1, i32 879, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"foobar.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"foobar.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"__udivmodti4", metadata !"__udivmodti4", metadata !"", metadata !1, i32 879, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, null, i32 879} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !29} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !29, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5, metadata !5, metadata !8} -!5 = metadata !{i32 589846, metadata !6, metadata !"UTItype", metadata !6, i32 166, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] -!6 = metadata !{i32 589865, metadata !"foobar.h", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!7 = metadata !{i32 589860, metadata !1, metadata !"", metadata !1, i32 0, i64 128, i64 128, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!8 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ] -!9 = metadata !{i32 589870, i32 0, metadata !1, metadata !"__divti3", metadata !"__divti3", metadata !"__divti3", metadata !1, i32 1094, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i128 (i128, i128)* @__divti3} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"UTItype", i32 166, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] +!6 = metadata !{i32 786473, metadata !30} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"", i32 0, i64 128, i64 128, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 786447, metadata !29, metadata !1, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ] +!9 = metadata !{i32 786478, metadata !1, metadata !"__divti3", metadata !"__divti3", metadata !"__divti3", metadata !1, i32 1094, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i128 (i128, i128)* @__divti3, null, null, null, i32 1094} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786453, metadata !29, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{metadata !12, metadata !12, metadata !12} -!12 = metadata !{i32 589846, metadata !6, metadata !"TItype", metadata !6, i32 160, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ] -!13 = metadata !{i32 589860, metadata !1, metadata !"", metadata !1, i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 590081, metadata !9, metadata !"u", metadata !1, i32 1093, metadata !12, i32 0} ; [ DW_TAG_arg_variable ] +!12 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"TItype", i32 160, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ] +!13 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"", i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 786689, metadata !9, metadata !"u", metadata !1, i32 1093, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ] !15 = metadata !{i32 1093, i32 0, metadata !9, null} !16 = metadata !{i64 0} -!17 = metadata !{i32 590080, metadata !18, metadata !"c", metadata !1, i32 1095, metadata !19, i32 0} ; [ DW_TAG_auto_variable ] -!18 = metadata !{i32 589835, metadata !9, i32 1094, i32 0, metadata !1, i32 13} ; [ DW_TAG_lexical_block ] -!19 = metadata !{i32 589846, metadata !6, metadata !"word_type", metadata !6, i32 424, i64 0, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_typedef ] -!20 = metadata !{i32 589860, metadata !1, metadata !"long int", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!17 = metadata !{i32 786688, metadata !18, metadata !"c", metadata !1, i32 1095, metadata !19, i32 0, null} ; [ DW_TAG_auto_variable ] +!18 = metadata !{i32 786443, metadata !1, metadata !9, i32 1094, i32 0, i32 13} ; [ DW_TAG_lexical_block ] +!19 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"word_type", i32 424, i64 0, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_typedef ] +!20 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !21 = metadata !{i32 1095, i32 0, metadata !18, null} !22 = metadata !{i32 1103, i32 0, metadata !18, null} !23 = metadata !{i32 1104, i32 0, metadata !18, null} !24 = metadata !{i32 1003, i32 0, metadata !25, metadata !26} -!25 = metadata !{i32 589835, metadata !0, i32 879, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!25 = metadata !{i32 786443, metadata !1, metadata !0, i32 879, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !26 = metadata !{i32 1107, i32 0, metadata !18, null} !27 = metadata !{i32 1111, i32 0, metadata !18, null} +!28 = metadata !{metadata !0, metadata !9} +!29 = metadata !{metadata !"foobar.c", metadata !"/tmp"} +!30 = metadata !{metadata !"foobar.h", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-prolog-end.ll b/test/CodeGen/X86/dbg-prolog-end.ll index 81303bb3d2ba8..26bac2e08286a 100644 --- a/test/CodeGen/X86/dbg-prolog-end.ll +++ b/test/CodeGen/X86/dbg-prolog-end.ll @@ -33,23 +33,23 @@ entry: } !llvm.dbg.cu = !{!0} -!llvm.dbg.sp = !{!1, !6} +!18 = metadata !{metadata !1, metadata !6} -!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 131100)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 589865, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 131100)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 590081, metadata !1, metadata !"i", metadata !2, i32 16777217, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 7} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786689, metadata !1, metadata !"i", metadata !2, i32 16777217, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !8 = metadata !{i32 1, i32 13, metadata !1, null} -!9 = metadata !{i32 590080, metadata !10, metadata !"j", metadata !2, i32 2, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!10 = metadata !{i32 589835, metadata !1, i32 1, i32 16, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 786688, metadata !10, metadata !"j", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!10 = metadata !{i32 786443, metadata !2, metadata !1, i32 1, i32 16, i32 0} ; [ DW_TAG_lexical_block ] !11 = metadata !{i32 2, i32 6, metadata !10, null} !12 = metadata !{i32 2, i32 11, metadata !10, null} !13 = metadata !{i32 3, i32 2, metadata !10, null} !14 = metadata !{i32 4, i32 2, metadata !10, null} !15 = metadata !{i32 5, i32 2, metadata !10, null} !16 = metadata !{i32 8, i32 2, metadata !17, null} -!17 = metadata !{i32 589835, metadata !6, i32 7, i32 12, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!17 = metadata !{i32 786443, metadata !2, metadata !6, i32 7, i32 12, i32 1} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/dbg-subrange.ll b/test/CodeGen/X86/dbg-subrange.ll index 788910c7fe724..6090185dc10ef 100644 --- a/test/CodeGen/X86/dbg-subrange.ll +++ b/test/CodeGen/X86/dbg-subrange.ll @@ -14,24 +14,21 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"small.c", metadata !"/private/tmp", metadata !"clang version 3.1 (trunk 144833)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11} ; [ DW_TAG_compile_unit ] -!1 = metadata !{metadata !2} -!2 = metadata !{i32 0} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !5} -!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 144833)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 0} +!3 = metadata !{metadata !5} +!5 = metadata !{i32 720942, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ] !6 = metadata !{i32 720937, metadata !"small.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ] !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{null} !9 = metadata !{metadata !10} !10 = metadata !{i32 720932} ; [ DW_TAG_base_type ] -!11 = metadata !{metadata !12} -!12 = metadata !{metadata !13} -!13 = metadata !{i32 720948, i32 0, null, metadata !"s", metadata !"s", metadata !"", metadata !6, i32 2, metadata !14, i32 0, i32 1, [4294967296 x i8]* @s} ; [ DW_TAG_variable ] +!11 = metadata !{metadata !13} +!13 = metadata !{i32 720948, i32 0, null, metadata !"s", metadata !"s", metadata !"", metadata !6, i32 2, metadata !14, i32 0, i32 1, [4294967296 x i8]* @s, null} ; [ DW_TAG_variable ] !14 = metadata !{i32 720897, null, metadata !"", null, i32 0, i64 34359738368, i64 8, i32 0, i32 0, metadata !15, metadata !16, i32 0, i32 0} ; [ DW_TAG_array_type ] !15 = metadata !{i32 720932, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] !16 = metadata !{metadata !17} -!17 = metadata !{i32 720929, i64 0, i64 4294967295} ; [ DW_TAG_subrange_type ] +!17 = metadata !{i32 720929, i64 0, i64 4294967296} ; [ DW_TAG_subrange_type ] !18 = metadata !{i32 5, i32 3, metadata !19, null} -!19 = metadata !{i32 720907, metadata !5, i32 4, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] +!19 = metadata !{i32 786443, metadata !5, i32 4, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] !20 = metadata !{i32 6, i32 1, metadata !19, null} diff --git a/test/CodeGen/X86/dbg-value-dag-combine.ll b/test/CodeGen/X86/dbg-value-dag-combine.ll index b115bf475c42a..fcbf64f42378f 100644 --- a/test/CodeGen/X86/dbg-value-dag-combine.ll +++ b/test/CodeGen/X86/dbg-value-dag-combine.ll @@ -23,26 +23,25 @@ entry: store i32 %tmp3, i32 addrspace(1)* %arrayidx, align 4, !dbg !16 ret void, !dbg !17 } -!llvm.dbg.sp = !{!0} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata -!"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata -!"__OpenCL_test_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp", metadata !"clc", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null, metadata !5} -!5 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] -!6 = metadata !{i32 589860, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 590081, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!5 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] +!6 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786689, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !8 = metadata !{i32 1, i32 42, metadata !0, null} -!9 = metadata !{i32 590080, metadata !10, metadata !"gid", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] -!10 = metadata !{i32 589835, metadata !0, i32 2, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 786688, metadata !10, metadata !"gid", metadata !1, i32 3, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] +!10 = metadata !{i32 786443, metadata !0, i32 2, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] !11 = metadata !{i32 3, i32 41, metadata !10, null} !12 = metadata !{i32 0} -!13 = metadata !{i32 590080, metadata !10, metadata !"idx", metadata !1, i32 4, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!13 = metadata !{i32 786688, metadata !10, metadata !"idx", metadata !1, i32 4, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] !14 = metadata !{i32 4, i32 20, metadata !10, null} !15 = metadata !{i32 5, i32 15, metadata !10, null} !16 = metadata !{i32 6, i32 18, metadata !10, null} !17 = metadata !{i32 7, i32 1, metadata !0, null} - +!18 = metadata !{metadata !0} +!19 = metadata !{metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp"} diff --git a/test/CodeGen/X86/dbg-value-inlined-parameter.ll b/test/CodeGen/X86/dbg-value-inlined-parameter.ll deleted file mode 100644 index d248a41303556..0000000000000 --- a/test/CodeGen/X86/dbg-value-inlined-parameter.ll +++ /dev/null @@ -1,87 +0,0 @@ -; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s -; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s - -;CHECK: DW_TAG_inlined_subroutine -;CHECK-NEXT: DW_AT_abstract_origin -;CHECK-NEXT: DW_AT_low_pc -;CHECK-NEXT: DW_AT_high_pc -;CHECK-NEXT: DW_AT_call_file -;CHECK-NEXT: DW_AT_call_line -;CHECK-NEXT: DW_TAG_formal_parameter -;CHECK-NEXT: Lstring11-Lsection_str ## DW_AT_name - -%struct.S1 = type { float*, i32 } - -@p = common global %struct.S1 zeroinitializer, align 8 - -define i32 @foo(%struct.S1* nocapture %sp, i32 %nums) nounwind optsize ssp { -entry: - tail call void @llvm.dbg.value(metadata !{%struct.S1* %sp}, i64 0, metadata !9), !dbg !20 - tail call void @llvm.dbg.value(metadata !{i32 %nums}, i64 0, metadata !18), !dbg !21 - %tmp2 = getelementptr inbounds %struct.S1* %sp, i64 0, i32 1, !dbg !22 - store i32 %nums, i32* %tmp2, align 4, !dbg !22, !tbaa !24 - %call = tail call float* @bar(i32 %nums) nounwind optsize, !dbg !27 - %tmp5 = getelementptr inbounds %struct.S1* %sp, i64 0, i32 0, !dbg !27 - store float* %call, float** %tmp5, align 8, !dbg !27, !tbaa !28 - %cmp = icmp ne float* %call, null, !dbg !29 - %cond = zext i1 %cmp to i32, !dbg !29 - ret i32 %cond, !dbg !29 -} - -declare float* @bar(i32) optsize - -define void @foobar() nounwind optsize ssp { -entry: - tail call void @llvm.dbg.value(metadata !30, i64 0, metadata !9) nounwind, !dbg !31 - tail call void @llvm.dbg.value(metadata !34, i64 0, metadata !18) nounwind, !dbg !35 - store i32 1, i32* getelementptr inbounds (%struct.S1* @p, i64 0, i32 1), align 8, !dbg !36, !tbaa !24 - %call.i = tail call float* @bar(i32 1) nounwind optsize, !dbg !37 - store float* %call.i, float** getelementptr inbounds (%struct.S1* @p, i64 0, i32 0), align 8, !dbg !37, !tbaa !28 - ret void, !dbg !38 -} - -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone - -!llvm.dbg.sp = !{!0, !6} -!llvm.dbg.lv.foo = !{!9, !18} -!llvm.dbg.gv = !{!19} - -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.S1*, i32)* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"nm2.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"nm2.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 125693)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"", metadata !1, i32 15, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, void ()* @foobar} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] -!8 = metadata !{null} -!9 = metadata !{i32 590081, metadata !0, metadata !"sp", metadata !1, i32 7, metadata !10, i32 0} ; [ DW_TAG_arg_variable ] -!10 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] -!11 = metadata !{i32 589846, metadata !2, metadata !"S1", metadata !1, i32 4, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ] -!12 = metadata !{i32 589843, metadata !2, metadata !"S1", metadata !1, i32 1, i64 128, i64 64, i32 0, i32 0, i32 0, metadata !13, i32 0, i32 0} ; [ DW_TAG_structure_type ] -!13 = metadata !{metadata !14, metadata !17} -!14 = metadata !{i32 589837, metadata !1, metadata !"m", metadata !1, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !15} ; [ DW_TAG_member ] -!15 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !16} ; [ DW_TAG_pointer_type ] -!16 = metadata !{i32 589860, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!17 = metadata !{i32 589837, metadata !1, metadata !"nums", metadata !1, i32 3, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!18 = metadata !{i32 590081, metadata !0, metadata !"nums", metadata !1, i32 7, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] -!19 = metadata !{i32 589876, i32 0, metadata !2, metadata !"p", metadata !"p", metadata !"", metadata !1, i32 14, metadata !11, i32 0, i32 1, %struct.S1* @p} ; [ DW_TAG_variable ] -!20 = metadata !{i32 7, i32 13, metadata !0, null} -!21 = metadata !{i32 7, i32 21, metadata !0, null} -!22 = metadata !{i32 9, i32 3, metadata !23, null} -!23 = metadata !{i32 589835, metadata !0, i32 8, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!24 = metadata !{metadata !"int", metadata !25} -!25 = metadata !{metadata !"omnipotent char", metadata !26} -!26 = metadata !{metadata !"Simple C/C++ TBAA", null} -!27 = metadata !{i32 10, i32 3, metadata !23, null} -!28 = metadata !{metadata !"any pointer", metadata !25} -!29 = metadata !{i32 11, i32 3, metadata !23, null} -!30 = metadata !{%struct.S1* @p} -!31 = metadata !{i32 7, i32 13, metadata !0, metadata !32} -!32 = metadata !{i32 16, i32 3, metadata !33, null} -!33 = metadata !{i32 589835, metadata !6, i32 15, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!34 = metadata !{i32 1} -!35 = metadata !{i32 7, i32 21, metadata !0, metadata !32} -!36 = metadata !{i32 9, i32 3, metadata !23, metadata !32} -!37 = metadata !{i32 10, i32 3, metadata !23, metadata !32} -!38 = metadata !{i32 17, i32 1, metadata !33, null} diff --git a/test/CodeGen/X86/dbg-value-isel.ll b/test/CodeGen/X86/dbg-value-isel.ll index f1101e61f0fef..55be3b1f222bf 100644 --- a/test/CodeGen/X86/dbg-value-isel.ll +++ b/test/CodeGen/X86/dbg-value-isel.ll @@ -78,25 +78,26 @@ declare <4 x i32> @__amdil_get_global_id_int() nounwind declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.sp = !{!0} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"OCLlLwTXZ.cl", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"OCLlLwTXZ.cl", metadata !"/tmp", metadata !"clc", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !20, i32 1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !19, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !20, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null, metadata !5} -!5 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] -!6 = metadata !{i32 589846, metadata !2, metadata !"uint", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] -!7 = metadata !{i32 589860, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!8 = metadata !{i32 590081, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!5 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] +!6 = metadata !{i32 589846, metadata !20, metadata !2, metadata !"uint", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 786689, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !9 = metadata !{i32 1, i32 32, metadata !0, null} -!10 = metadata !{i32 590080, metadata !11, metadata !"tid", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] -!11 = metadata !{i32 589835, metadata !0, i32 2, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 786688, metadata !11, metadata !"tid", metadata !1, i32 3, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] +!11 = metadata !{i32 786443, metadata !0, i32 2, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] !12 = metadata !{i32 5, i32 24, metadata !11, null} -!13 = metadata !{i32 590080, metadata !11, metadata !"gid", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!13 = metadata !{i32 786688, metadata !11, metadata !"gid", metadata !1, i32 3, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] !14 = metadata !{i32 6, i32 25, metadata !11, null} -!15 = metadata !{i32 590080, metadata !11, metadata !"lsz", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!15 = metadata !{i32 786688, metadata !11, metadata !"lsz", metadata !1, i32 3, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] !16 = metadata !{i32 7, i32 26, metadata !11, null} !17 = metadata !{i32 9, i32 24, metadata !11, null} !18 = metadata !{i32 10, i32 1, metadata !0, null} - +!19 = metadata !{metadata !0} +!20 = metadata !{metadata !"OCLlLwTXZ.cl", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-value-location.ll b/test/CodeGen/X86/dbg-value-location.ll index 05e29ecff03f4..2a1916f26c97c 100644 --- a/test/CodeGen/X86/dbg-value-location.ll +++ b/test/CodeGen/X86/dbg-value-location.ll @@ -45,26 +45,30 @@ declare hidden fastcc i32 @bar2(i32) nounwind optsize ssp declare hidden fastcc i32 @bar3(i32) nounwind optsize ssp declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.sp = !{!0, !6, !7, !8} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 19510, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i64, i8*, i32)* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"/tmp/f.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"f.i", metadata !"/tmp", metadata !"clang version 2.9 (trunk 124753)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 19510, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i64, i8*, i32)* @foo, null, null, null, i32 19510} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !27, i32 12, metadata !"clang version 2.9 (trunk 124753)", i1 true, metadata !"", i32 0, null, null, metadata !24, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"bar3", metadata !"bar3", metadata !"", metadata !1, i32 14827, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar3} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 589870, i32 0, metadata !1, metadata !"bar2", metadata !"bar2", metadata !"", metadata !1, i32 15397, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar2} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 589870, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 12382, metadata !9, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @bar} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar3", metadata !"bar3", metadata !"", i32 14827, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar3} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar2", metadata !"bar2", metadata !"", i32 15397, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar2} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar", metadata !"bar", metadata !"", i32 12382, metadata !9, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @bar} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !10 = metadata !{metadata !11} -!11 = metadata !{i32 589860, metadata !2, metadata !"unsigned char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] -!12 = metadata !{i32 590081, metadata !0, metadata !"var", metadata !1, i32 19509, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 786468, metadata !2, metadata !"unsigned char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!12 = metadata !{i32 786689, metadata !0, metadata !"var", metadata !1, i32 19509, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !13 = metadata !{i32 19509, i32 20, metadata !0, null} !14 = metadata !{i32 18091, i32 2, metadata !15, metadata !17} -!15 = metadata !{i32 589835, metadata !16, i32 18086, i32 1, metadata !1, i32 748} ; [ DW_TAG_lexical_block ] -!16 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo_bar", metadata !"foo_bar", metadata !"", metadata !1, i32 18086, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 786443, metadata !1, metadata !16, i32 18086, i32 1, i32 748} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo_bar", metadata !"foo_bar", metadata !"", i32 18086, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null} ; [ DW_TAG_subprogram ] !17 = metadata !{i32 19514, i32 2, metadata !18, null} -!18 = metadata !{i32 589835, metadata !0, i32 19510, i32 1, metadata !1, i32 99} ; [ DW_TAG_lexical_block ] +!18 = metadata !{i32 786443, metadata !1, metadata !0, i32 19510, i32 1, i32 99} ; [ DW_TAG_lexical_block ] !22 = metadata !{i32 18094, i32 2, metadata !15, metadata !17} !23 = metadata !{i32 19524, i32 1, metadata !18, null} +!24 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8} +!25 = metadata !{i32 786473, metadata !27} ; [ DW_TAG_file_type ] +!26 = metadata !{metadata !"/tmp/f.c", metadata !"/tmp"} +!27 = metadata !{metadata !"f.i", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-value-range.ll b/test/CodeGen/X86/dbg-value-range.ll index 6b16865ba9eeb..6766dbe9edb09 100644 --- a/test/CodeGen/X86/dbg-value-range.ll +++ b/test/CodeGen/X86/dbg-value-range.ll @@ -17,22 +17,21 @@ declare i32 @foo(...) declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.sp = !{!0} -!llvm.dbg.lv.bar = !{!6, !11} +!llvm.dbg.cu = !{!2} -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.a*)* @bar} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"bar.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"bar.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 122997)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.a*)* @bar, null, null, metadata !21, i32 0} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !22} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !22, i32 12, metadata !"clang version 2.9 (trunk 122997)", i1 true, metadata !"", i32 0, null, null, metadata !20, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 590081, metadata !0, metadata !"b", metadata !1, i32 5, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] -!7 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] -!8 = metadata !{i32 589843, metadata !2, metadata !"a", metadata !1, i32 1, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !9, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786689, metadata !0, metadata !"b", metadata !1, i32 5, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] +!7 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] +!8 = metadata !{i32 786451, metadata !2, metadata !"a", metadata !1, i32 1, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !9, i32 0, i32 0} ; [ DW_TAG_structure_type ] !9 = metadata !{metadata !10} -!10 = metadata !{i32 589837, metadata !1, metadata !"c", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!11 = metadata !{i32 590080, metadata !12, metadata !"x", metadata !1, i32 6, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!12 = metadata !{i32 589835, metadata !0, i32 5, i32 22, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 786445, metadata !1, metadata !"c", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!11 = metadata !{i32 786688, metadata !12, metadata !"x", metadata !1, i32 6, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] +!12 = metadata !{i32 786443, metadata !22, metadata !0, i32 5, i32 22, i32 0} ; [ DW_TAG_lexical_block ] !13 = metadata !{i32 5, i32 19, metadata !0, null} !14 = metadata !{i32 6, i32 14, metadata !12, null} !15 = metadata !{metadata !"int", metadata !16} @@ -40,6 +39,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !17 = metadata !{metadata !"Simple C/C++ TBAA", null} !18 = metadata !{i32 7, i32 2, metadata !12, null} !19 = metadata !{i32 8, i32 2, metadata !12, null} +!20 = metadata !{metadata !0} +!21 = metadata !{metadata !6, metadata !11} +!22 = metadata !{metadata !"bar.c", metadata !"/private/tmp"} ; Check that variable bar:b value range is appropriately trucated in debug info. ; The variable is in %rdi which is clobbered by 'movl %ebx, %edi' diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll index 8e7c13d8efa9c..9669d97cb7fa2 100644 --- a/test/CodeGen/X86/divide-by-constant.ll +++ b/test/CodeGen/X86/divide-by-constant.ll @@ -56,9 +56,9 @@ entry: %div = sdiv i16 %x, 10 ret i16 %div ; CHECK: test6: -; CHECK: imull $26215, %eax, %eax -; CHECK: shrl $31, %ecx -; CHECK: sarl $18, %eax +; CHECK: imull $26215, %eax, %ecx +; CHECK: sarl $18, %ecx +; CHECK: shrl $15, %eax } define i32 @test7(i32 %x) nounwind { diff --git a/test/CodeGen/X86/dwarf-comp-dir.ll b/test/CodeGen/X86/dwarf-comp-dir.ll index c64752c9522bd..3bc2957963ebd 100644 --- a/test/CodeGen/X86/dwarf-comp-dir.ll +++ b/test/CodeGen/X86/dwarf-comp-dir.ll @@ -1,14 +1,16 @@ ; RUN: llc %s -o %t -filetype=obj -; RUN: llvm-dwarfdump %t | FileCheck %s +; RUN: llvm-dwarfdump -debug-dump=line %t | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"empty.c", metadata !"/home/nlewycky", metadata !"clang version 3.1 (trunk 143523)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !1} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 720913, metadata !4, i32 12, metadata !"clang version 3.1 (trunk 143523)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !1} ; [ DW_TAG_compile_unit ] !1 = metadata !{metadata !2} !2 = metadata !{i32 0} +!3 = metadata !{i32 786473, metadata !4} ; [ DW_TAG_file_type ] +!4 = metadata !{metadata !"empty.c", metadata !"/home/nlewycky"} ; The important part of the following check is that dir = #0. ; Dir Mod Time File Len File Name diff --git a/test/CodeGen/X86/dynamic-allocas-VLAs.ll b/test/CodeGen/X86/dynamic-allocas-VLAs.ll index c5e47facf3468..9405f76cbed03 100644 --- a/test/CodeGen/X86/dynamic-allocas-VLAs.ll +++ b/test/CodeGen/X86/dynamic-allocas-VLAs.ll @@ -103,7 +103,7 @@ entry: declare void @t4_helper(i32*, i32*, <8 x float>*) -; Dynamic realignment + Spill +; Spilling an AVX register shouldn't cause dynamic realignment define i32 @t5(float* nocapture %f) nounwind uwtable ssp { entry: %a = alloca i32, align 4 @@ -116,21 +116,15 @@ entry: ret i32 %add ; CHECK: _t5 -; CHECK: pushq %rbp -; CHECK: movq %rsp, %rbp -; CHECK: andq $-32, %rsp ; CHECK: subq ${{[0-9]+}}, %rsp ; ; CHECK: vmovaps (%rdi), [[AVXREG:%ymm[0-9]+]] -; CHECK: vmovaps [[AVXREG]], (%rsp) +; CHECK: vmovups [[AVXREG]], (%rsp) ; CHECK: leaq {{[0-9]+}}(%rsp), %rdi ; CHECK: callq _t5_helper1 -; CHECK: vmovaps (%rsp), %ymm0 +; CHECK: vmovups (%rsp), %ymm0 ; CHECK: callq _t5_helper2 ; CHECK: movl {{[0-9]+}}(%rsp), %eax -; -; CHECK: movq %rbp, %rsp -; CHECK: popq %rbp } declare void @t5_helper1(i32*) diff --git a/test/CodeGen/X86/early-ifcvt-crash.ll b/test/CodeGen/X86/early-ifcvt-crash.ll index c8280269689d7..d9580503e91e3 100644 --- a/test/CodeGen/X86/early-ifcvt-crash.ll +++ b/test/CodeGen/X86/early-ifcvt-crash.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -x86-early-ifcvt -verify-machineinstrs ; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt -verify-machineinstrs +; CPU without a scheduling model: +; RUN: llc < %s -x86-early-ifcvt -mcpu=pentium3 -verify-machineinstrs ; ; Run these tests with and without -stress-early-ifcvt to exercise heuristics. ; diff --git a/test/CodeGen/X86/early-ifcvt.ll b/test/CodeGen/X86/early-ifcvt.ll index 2e1852d3e3aef..2606bd28d5fc4 100644 --- a/test/CodeGen/X86/early-ifcvt.ll +++ b/test/CodeGen/X86/early-ifcvt.ll @@ -142,3 +142,34 @@ save_state_and_return: } declare void @BZ2_bz__AssertH__fail() + +; Make sure we don't speculate on div/idiv instructions +; CHECK: test_idiv +; CHECK-NOT: cmov +define i32 @test_idiv(i32 %a, i32 %b) nounwind uwtable readnone ssp { + %1 = icmp eq i32 %b, 0 + br i1 %1, label %4, label %2 + +; <label>:2 ; preds = %0 + %3 = sdiv i32 %a, %b + br label %4 + +; <label>:4 ; preds = %0, %2 + %5 = phi i32 [ %3, %2 ], [ %a, %0 ] + ret i32 %5 +} + +; CHECK: test_div +; CHECK-NOT: cmov +define i32 @test_div(i32 %a, i32 %b) nounwind uwtable readnone ssp { + %1 = icmp eq i32 %b, 0 + br i1 %1, label %4, label %2 + +; <label>:2 ; preds = %0 + %3 = udiv i32 %a, %b + br label %4 + +; <label>:4 ; preds = %0, %2 + %5 = phi i32 [ %3, %2 ], [ %a, %0 ] + ret i32 %5 +} diff --git a/test/CodeGen/X86/fast-isel-args-fail.ll b/test/CodeGen/X86/fast-isel-args-fail.ll new file mode 100644 index 0000000000000..e748e1cad1fd4 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-args-fail.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-apple-darwin10 +; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=WIN32 +; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-pc-win64 | FileCheck %s -check-prefix=WIN64 +; Requires: Asserts + +; Previously, this would cause an assert. +define i31 @t1(i31 %a, i31 %b, i31 %c) { +entry: + %add = add nsw i31 %b, %a + %add1 = add nsw i31 %add, %c + ret i31 %add1 +} + +; We don't handle the Windows CC, yet. +define i32 @foo(i32* %p) { +entry: +; WIN32: foo +; WIN32: movl (%rcx), %eax +; WIN64: foo +; WIN64: movl (%rdi), %eax + %0 = load i32* %p, align 4 + ret i32 %0 +} diff --git a/test/CodeGen/X86/fast-isel-args.ll b/test/CodeGen/X86/fast-isel-args.ll new file mode 100644 index 0000000000000..0f3626565e7d1 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-args.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -fast-isel -fast-isel-abort -fast-isel-abort-args -verify-machineinstrs -mtriple=x86_64-apple-darwin10 + +; Just make sure these don't abort when lowering the arguments. +define i32 @t1(i32 %a, i32 %b, i32 %c) { +entry: + %add = add nsw i32 %b, %a + %add1 = add nsw i32 %add, %c + ret i32 %add1 +} + +define i64 @t2(i64 %a, i64 %b, i64 %c) { +entry: + %add = add nsw i64 %b, %a + %add1 = add nsw i64 %add, %c + ret i64 %add1 +} + +define i64 @t3(i32 %a, i64 %b, i32 %c) { +entry: + %conv = sext i32 %a to i64 + %add = add nsw i64 %conv, %b + %conv1 = sext i32 %c to i64 + %add2 = add nsw i64 %add, %conv1 + ret i64 %add2 +} diff --git a/test/CodeGen/X86/fast-isel-constant.ll b/test/CodeGen/X86/fast-isel-constant.ll new file mode 100644 index 0000000000000..6f9240ac47005 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-constant.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s +; Make sure fast-isel doesn't reset the materialised constant map +; across an intrinsic call. + +; CHECK: movl $100000 +; CHECK-NOT: movl $100000 +define i1 @test1(i32 %v1, i32 %v2, i32* %X) nounwind { +entry: + %a = shl i32 100000, %v1 + %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %v2) + %ext = extractvalue {i32, i1} %t, 0 + %sum = shl i32 100000, %ext + %obit = extractvalue {i32, i1} %t, 1 + br i1 %obit, label %overflow, label %normal + +normal: + store i32 %sum, i32* %X + br label %overflow + +overflow: + ret i1 false +} + +declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) diff --git a/test/CodeGen/X86/fast-isel-expect.ll b/test/CodeGen/X86/fast-isel-expect.ll new file mode 100644 index 0000000000000..c4be7f364f305 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-expect.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -O0 -march=x86 | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@glbl = extern_weak constant i8 + +declare i64 @llvm.expect.i64(i64, i64) + +define void @test() { +; CHECK: movl $glbl + %tmp = call i64 @llvm.expect.i64(i64 zext (i1 icmp eq (i8* @glbl, i8* null) to i64), i64 0) + %tmp2 = icmp ne i64 %tmp, 0 + br i1 %tmp2, label %bb1, label %bb2 + +bb1: + unreachable + +bb2: + unreachable +} diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll index cdfaf7f4c1348..ad1520ef81943 100644 --- a/test/CodeGen/X86/fast-isel-x86-64.ll +++ b/test/CodeGen/X86/fast-isel-x86-64.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mattr=-avx -fast-isel -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s -; RUN: llc < %s -mattr=+avx -fast-isel -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s --check-prefix=AVX +; RUN: llc < %s -mattr=-avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s +; RUN: llc < %s -mattr=+avx -fast-isel -mcpu=core2 -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s --check-prefix=AVX target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" diff --git a/test/CodeGen/X86/float-asmprint.ll b/test/CodeGen/X86/float-asmprint.ll new file mode 100644 index 0000000000000..4aeae7fe0469b --- /dev/null +++ b/test/CodeGen/X86/float-asmprint.ll @@ -0,0 +1,40 @@ +; RUN: llc -mtriple=x86_64-none-linux < %s | FileCheck %s + +; Check that all current floating-point types are correctly emitted to assembly +; on a little-endian target. + +@var128 = global fp128 0xL00000000000000008000000000000000, align 16 +@varppc128 = global ppc_fp128 0xM80000000000000000000000000000000, align 16 +@var80 = global x86_fp80 0xK80000000000000000000, align 16 +@var64 = global double -0.0, align 8 +@var32 = global float -0.0, align 4 +@var16 = global half -0.0, align 2 + +; CHECK: var128: +; CHECK-NEXT: .quad 0 # fp128 -0 +; CHECK-NEXT: .quad -9223372036854775808 +; CHECK-NEXT: .size + +; CHECK: varppc128: +; CHECK-NEXT: .quad 0 # ppc_fp128 -0 +; CHECK-NEXT: .quad -9223372036854775808 +; CHECK-NEXT: .size + +; CHECK: var80: +; CHECK-NEXT: .quad 0 # x86_fp80 -0 +; CHECK-NEXT: .short 32768 +; CHECK-NEXT: .zero 6 +; CHECK-NEXT: .size + +; CHECK: var64: +; CHECK-NEXT: .quad -9223372036854775808 # double -0 +; CHECK-NEXT: .size + +; CHECK: var32: +; CHECK-NEXT: .long 2147483648 # float -0 +; CHECK-NEXT: .size + +; CHECK: var16: +; CHECK-NEXT: .short 32768 # half -0 +; CHECK-NEXT: .size + diff --git a/test/CodeGen/X86/fma4-intrinsics-x86_64.ll b/test/CodeGen/X86/fma4-intrinsics-x86_64.ll index 2fe1ecd40e0cc..7a1a9ae46147a 100644 --- a/test/CodeGen/X86/fma4-intrinsics-x86_64.ll +++ b/test/CodeGen/X86/fma4-intrinsics-x86_64.ll @@ -63,6 +63,16 @@ define < 4 x float > @test_x86_fma_vfmadd_ps_load2(< 4 x float > %a0, < 4 x floa } declare < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float >, < 4 x float >, < 4 x float >) nounwind readnone +; To test execution dependency +define < 4 x float > @test_x86_fma_vfmadd_ps_load3(< 4 x float >* %a0, < 4 x float >* %a1, < 4 x float > %a2) { + ; CHECK: vmovaps + ; CHECK: vfmaddps %{{.*}}, (%{{.*}}) + %x = load <4 x float>* %a0 + %y = load <4 x float>* %a1 + %res = call < 4 x float > @llvm.x86.fma.vfmadd.ps(< 4 x float > %x, < 4 x float > %y, < 4 x float > %a2) ; <i64> [#uses=1] + ret < 4 x float > %res +} + define < 2 x double > @test_x86_fma_vfmadd_pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) { ; CHECK: vfmaddpd %res = call < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double > %a0, < 2 x double > %a1, < 2 x double > %a2) ; <i64> [#uses=1] @@ -82,6 +92,16 @@ define < 2 x double > @test_x86_fma_vfmadd_pd_load2(< 2 x double > %a0, < 2 x do } declare < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double >, < 2 x double >, < 2 x double >) nounwind readnone +; To test execution dependency +define < 2 x double > @test_x86_fma_vfmadd_pd_load3(< 2 x double >* %a0, < 2 x double >* %a1, < 2 x double > %a2) { + ; CHECK: vmovapd + ; CHECK: vfmaddpd %{{.*}}, (%{{.*}}) + %x = load <2 x double>* %a0 + %y = load <2 x double>* %a1 + %res = call < 2 x double > @llvm.x86.fma.vfmadd.pd(< 2 x double > %x, < 2 x double > %y, < 2 x double > %a2) ; <i64> [#uses=1] + ret < 2 x double > %res +} + define < 8 x float > @test_x86_fma_vfmadd_ps_256(< 8 x float > %a0, < 8 x float > %a1, < 8 x float > %a2) { ; CHECK: vfmaddps ; CHECK: ymm diff --git a/test/CodeGen/X86/fold-call.ll b/test/CodeGen/X86/fold-call.ll index 603e9ad66caaf..35327faa64868 100644 --- a/test/CodeGen/X86/fold-call.ll +++ b/test/CodeGen/X86/fold-call.ll @@ -1,10 +1,27 @@ -; RUN: llc < %s -march=x86 | not grep mov -; RUN: llc < %s -march=x86-64 | not grep mov +; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86-64 | FileCheck %s -declare void @bar() +; CHECK: test1 +; CHECK-NOT: mov -define void @foo(i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, void()* %arg) nounwind { +declare void @bar() +define void @test1(i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, void()* %arg) nounwind { call void @bar() call void %arg() ret void } + +; PR14739 +; CHECK: test2 +; CHECK: mov{{.*}} $0, ([[REGISTER:%[a-z]+]]) +; CHECK-NOT: jmp{{.*}} *([[REGISTER]]) + +%struct.X = type { void ()* } +define void @test2(%struct.X* nocapture %x) { +entry: + %f = getelementptr inbounds %struct.X* %x, i64 0, i32 0 + %0 = load void ()** %f + store void ()* null, void ()** %f + tail call void %0() + ret void +} diff --git a/test/CodeGen/X86/fold-load-vec.ll b/test/CodeGen/X86/fold-load-vec.ll new file mode 100644 index 0000000000000..c1756d5e2e1ad --- /dev/null +++ b/test/CodeGen/X86/fold-load-vec.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse41 | FileCheck %s + +; rdar://12721174 +; We should not fold movss into pshufd since pshufd expects m128 while movss +; loads from m32. +define void @sample_test(<4 x float>* %source, <2 x float>* %dest) nounwind { +; CHECK: sample_test +; CHECK: movss +; CHECK: pshufd +entry: + %source.addr = alloca <4 x float>*, align 8 + %dest.addr = alloca <2 x float>*, align 8 + %tmp = alloca <2 x float>, align 8 + store <4 x float>* %source, <4 x float>** %source.addr, align 8 + store <2 x float>* %dest, <2 x float>** %dest.addr, align 8 + store <2 x float> zeroinitializer, <2 x float>* %tmp, align 8 + %0 = load <4 x float>** %source.addr, align 8 + %arrayidx = getelementptr inbounds <4 x float>* %0, i64 0 + %1 = load <4 x float>* %arrayidx, align 16 + %2 = extractelement <4 x float> %1, i32 0 + %3 = load <2 x float>* %tmp, align 8 + %4 = insertelement <2 x float> %3, float %2, i32 1 + store <2 x float> %4, <2 x float>* %tmp, align 8 + %5 = load <2 x float>* %tmp, align 8 + %6 = load <2 x float>** %dest.addr, align 8 + %arrayidx1 = getelementptr inbounds <2 x float>* %6, i64 0 + store <2 x float> %5, <2 x float>* %arrayidx1, align 8 + %7 = load <2 x float>** %dest.addr, align 8 + %arrayidx2 = getelementptr inbounds <2 x float>* %7, i64 0 + %8 = load <2 x float>* %arrayidx2, align 8 + %vecext = extractelement <2 x float> %8, i32 0 + %9 = load <2 x float>** %dest.addr, align 8 + %arrayidx3 = getelementptr inbounds <2 x float>* %9, i64 0 + %10 = load <2 x float>* %arrayidx3, align 8 + %vecext4 = extractelement <2 x float> %10, i32 1 + call void @ext(float %vecext, float %vecext4) + ret void +} +declare void @ext(float, float) diff --git a/test/CodeGen/X86/fold-pcmpeqd-2.ll b/test/CodeGen/X86/fold-pcmpeqd-2.ll index 9cf4607cf5b23..2bde76efd2ae7 100644 --- a/test/CodeGen/X86/fold-pcmpeqd-2.ll +++ b/test/CodeGen/X86/fold-pcmpeqd-2.ll @@ -43,21 +43,21 @@ forbody: ; preds = %forcond %mul171.i = fmul <4 x float> %add167.i, %sub140.i ; <<4 x float>> [#uses=1] %add172.i = fadd <4 x float> %mul171.i, < float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000 > ; <<4 x float>> [#uses=1] %bitcast176.i = bitcast <4 x float> %add172.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %andnps178.i = and <4 x i32> %bitcast176.i, zeroinitializer ; <<4 x i32>> [#uses=1] + %andnps178.i = add <4 x i32> %bitcast176.i, <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1] %bitcast179.i = bitcast <4 x i32> %andnps178.i to <4 x float> ; <<4 x float>> [#uses=1] %mul186.i = fmul <4 x float> %bitcast179.i, zeroinitializer ; <<4 x float>> [#uses=1] %bitcast190.i = bitcast <4 x float> %mul186.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %andnps192.i = and <4 x i32> %bitcast190.i, zeroinitializer ; <<4 x i32>> [#uses=1] + %andnps192.i = add <4 x i32> %bitcast190.i, <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1] %xorps.i = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %orps203.i = or <4 x i32> %andnps192.i, %xorps.i ; <<4 x i32>> [#uses=1] + %orps203.i = add <4 x i32> %andnps192.i, %xorps.i ; <<4 x i32>> [#uses=1] %bitcast204.i = bitcast <4 x i32> %orps203.i to <4 x float> ; <<4 x float>> [#uses=1] %mul310 = fmul <4 x float> %bitcast204.i104, zeroinitializer ; <<4 x float>> [#uses=2] %mul313 = fmul <4 x float> %bitcast204.i, zeroinitializer ; <<4 x float>> [#uses=1] %cmpunord.i11 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> zeroinitializer, <4 x float> zeroinitializer, i8 3) nounwind ; <<4 x float>> [#uses=1] %bitcast6.i13 = bitcast <4 x float> %cmpunord.i11 to <4 x i32> ; <<4 x i32>> [#uses=2] - %andps.i14 = and <4 x i32> zeroinitializer, %bitcast6.i13 ; <<4 x i32>> [#uses=1] + %andps.i14 = add <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %bitcast6.i13 ; <<4 x i32>> [#uses=1] %not.i16 = xor <4 x i32> %bitcast6.i13, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %andnps.i17 = and <4 x i32> zeroinitializer, %not.i16 ; <<4 x i32>> [#uses=1] + %andnps.i17 = add <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %not.i16 ; <<4 x i32>> [#uses=1] %orps.i18 = or <4 x i32> %andnps.i17, %andps.i14 ; <<4 x i32>> [#uses=1] %bitcast17.i19 = bitcast <4 x i32> %orps.i18 to <4 x float> ; <<4 x float>> [#uses=1] %tmp83 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul310, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/X86/fold-vex.ll b/test/CodeGen/X86/fold-vex.ll new file mode 100644 index 0000000000000..2bb5b441c7c00 --- /dev/null +++ b/test/CodeGen/X86/fold-vex.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s + +;CHECK: @test +; No need to load from memory. The operand will be loaded as part of th AND instr. +;CHECK-NOT: vmovaps +;CHECK: vandps +;CHECK: ret + +define void @test1(<8 x i32>* %p0, <8 x i32> %in1) nounwind { +entry: + %in0 = load <8 x i32>* %p0, align 2 + %a = and <8 x i32> %in0, %in1 + store <8 x i32> %a, <8 x i32>* undef + ret void +} + diff --git a/test/CodeGen/X86/fp-fast.ll b/test/CodeGen/X86/fp-fast.ll index d70aa7d79f009..287504801d04f 100644 --- a/test/CodeGen/X86/fp-fast.ll +++ b/test/CodeGen/X86/fp-fast.ll @@ -38,7 +38,7 @@ define float @test3(float %a) { ; CHECK: test4 define float @test4(float %a) { ; CHECK-NOT: fma -; CHECK-NOT mul +; CHECK-NOT: mul ; CHECK-NOT: add ; CHECK: ret %t1 = fmul float %a, 0.0 diff --git a/test/CodeGen/X86/fp-load-trunc.ll b/test/CodeGen/X86/fp-load-trunc.ll index 2ae65c97d97ac..a973befdafe7d 100644 --- a/test/CodeGen/X86/fp-load-trunc.ll +++ b/test/CodeGen/X86/fp-load-trunc.ll @@ -49,8 +49,8 @@ define <8 x float> @test4(<8 x double>* %p) nounwind { ; CHECK: movlhps ; CHECK: ret ; AVX: test4 -; AVX: vcvtpd2psy {{[0-9]*}}(%{{.*}}) -; AVX: vcvtpd2psy {{[0-9]*}}(%{{.*}}) +; AVX: vcvtpd2psy +; AVX: vcvtpd2psy ; AVX: vinsertf128 ; AVX: ret %x = load <8 x double>* %p diff --git a/test/CodeGen/X86/handle-move.ll b/test/CodeGen/X86/handle-move.ll index e9f7a962e20d1..ba96275569b38 100644 --- a/test/CodeGen/X86/handle-move.ll +++ b/test/CodeGen/X86/handle-move.ll @@ -16,7 +16,7 @@ ; DL: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r ; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r ; -define i32 @f1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp { +define i32 @f1(i32 %a, i32 %b, i32 %c) nounwind uwtable readnone ssp { entry: %y = add i32 %c, 1 %x = udiv i32 %b, %a @@ -50,7 +50,7 @@ entry: ; %vreg5: [16r,112r:0) 0@16r ; --> [16r,120r:0) 0@16r ; -define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp { +define i32 @f3(i32 %a, i32 %b) nounwind uwtable readnone ssp { entry: %y = sub i32 %a, %b %x = add i32 %a, %b diff --git a/test/CodeGen/X86/hipe-cc.ll b/test/CodeGen/X86/hipe-cc.ll new file mode 100644 index 0000000000000..76d17a09d54e6 --- /dev/null +++ b/test/CodeGen/X86/hipe-cc.ll @@ -0,0 +1,77 @@ +; RUN: llc < %s -tailcallopt -code-model=medium -stack-alignment=4 -mtriple=i686-linux-gnu -mcpu=pentium | FileCheck %s + +; Check the HiPE calling convention works (x86-32) + +define void @zap(i32 %a, i32 %b) nounwind { +entry: + ; CHECK: movl 40(%esp), %eax + ; CHECK-NEXT: movl 44(%esp), %edx + ; CHECK-NEXT: movl $8, %ecx + ; CHECK-NEXT: calll addfour + %0 = call cc 11 {i32, i32, i32} @addfour(i32 undef, i32 undef, i32 %a, i32 %b, i32 8) + %res = extractvalue {i32, i32, i32} %0, 2 + + ; CHECK: movl %eax, 16(%esp) + ; CHECK-NEXT: movl $2, 12(%esp) + ; CHECK-NEXT: movl $1, 8(%esp) + ; CHECK: calll foo + tail call void @foo(i32 undef, i32 undef, i32 1, i32 2, i32 %res) nounwind + ret void +} + +define cc 11 {i32, i32, i32} @addfour(i32 %hp, i32 %p, i32 %x, i32 %y, i32 %z) nounwind { +entry: + ; CHECK: addl %edx, %eax + ; CHECK-NEXT: addl %ecx, %eax + %0 = add i32 %x, %y + %1 = add i32 %0, %z + + ; CHECK: ret + %res = insertvalue {i32, i32, i32} undef, i32 %1, 2 + ret {i32, i32, i32} %res +} + +define cc 11 void @foo(i32 %hp, i32 %p, i32 %arg0, i32 %arg1, i32 %arg2) nounwind { +entry: + ; CHECK: movl %esi, 16(%esp) + ; CHECK-NEXT: movl %ebp, 12(%esp) + ; CHECK-NEXT: movl %eax, 8(%esp) + ; CHECK-NEXT: movl %edx, 4(%esp) + ; CHECK-NEXT: movl %ecx, (%esp) + %hp_var = alloca i32 + %p_var = alloca i32 + %arg0_var = alloca i32 + %arg1_var = alloca i32 + %arg2_var = alloca i32 + store i32 %hp, i32* %hp_var + store i32 %p, i32* %p_var + store i32 %arg0, i32* %arg0_var + store i32 %arg1, i32* %arg1_var + store i32 %arg2, i32* %arg2_var + + ; CHECK: movl 4(%esp), %edx + ; CHECK-NEXT: movl 8(%esp), %eax + ; CHECK-NEXT: movl 12(%esp), %ebp + ; CHECK-NEXT: movl 16(%esp), %esi + %0 = load i32* %hp_var + %1 = load i32* %p_var + %2 = load i32* %arg0_var + %3 = load i32* %arg1_var + %4 = load i32* %arg2_var + ; CHECK: jmp bar + tail call cc 11 void @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) nounwind + ret void +} + +define cc 11 void @baz() nounwind { + %tmp_clos = load i32* @clos + %tmp_clos2 = inttoptr i32 %tmp_clos to i32* + %indirect_call = bitcast i32* %tmp_clos2 to void (i32, i32, i32)* + ; CHECK: movl $42, %eax + ; CHECK-NEXT: jmpl *clos + tail call cc 11 void %indirect_call(i32 undef, i32 undef, i32 42) nounwind + ret void +} + +@clos = external constant i32 +declare cc 11 void @bar(i32, i32, i32, i32, i32) diff --git a/test/CodeGen/X86/hipe-cc64.ll b/test/CodeGen/X86/hipe-cc64.ll new file mode 100644 index 0000000000000..5dbb5a25cbeb0 --- /dev/null +++ b/test/CodeGen/X86/hipe-cc64.ll @@ -0,0 +1,87 @@ +; RUN: llc < %s -tailcallopt -code-model=medium -stack-alignment=8 -mtriple=x86_64-linux-gnu -mcpu=opteron | FileCheck %s + +; Check the HiPE calling convention works (x86-64) + +define void @zap(i64 %a, i64 %b) nounwind { +entry: + ; CHECK: movq %rsi, %rax + ; CHECK-NEXT: movq %rdi, %rsi + ; CHECK-NEXT: movq %rax, %rdx + ; CHECK-NEXT: movl $8, %ecx + ; CHECK-NEXT: movl $9, %r8d + ; CHECK-NEXT: callq addfour + %0 = call cc 11 {i64, i64, i64} @addfour(i64 undef, i64 undef, i64 %a, i64 %b, i64 8, i64 9) + %res = extractvalue {i64, i64, i64} %0, 2 + + ; CHECK: movl $1, %edx + ; CHECK-NEXT: movl $2, %ecx + ; CHECK-NEXT: movl $3, %r8d + ; CHECK-NEXT: movq %rax, %r9 + ; CHECK: callq foo + tail call void @foo(i64 undef, i64 undef, i64 1, i64 2, i64 3, i64 %res) nounwind + ret void +} + +define cc 11 {i64, i64, i64} @addfour(i64 %hp, i64 %p, i64 %x, i64 %y, i64 %z, i64 %w) nounwind { +entry: + ; CHECK: leaq (%rsi,%rdx), %rax + ; CHECK-NEXT: addq %rcx, %rax + ; CHECK-NEXT: addq %r8, %rax + %0 = add i64 %x, %y + %1 = add i64 %0, %z + %2 = add i64 %1, %w + + ; CHECK: ret + %res = insertvalue {i64, i64, i64} undef, i64 %2, 2 + ret {i64, i64, i64} %res +} + +define cc 11 void @foo(i64 %hp, i64 %p, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) nounwind { +entry: + ; CHECK: movq %r15, 40(%rsp) + ; CHECK-NEXT: movq %rbp, 32(%rsp) + ; CHECK-NEXT: movq %rsi, 24(%rsp) + ; CHECK-NEXT: movq %rdx, 16(%rsp) + ; CHECK-NEXT: movq %rcx, 8(%rsp) + ; CHECK-NEXT: movq %r8, (%rsp) + %hp_var = alloca i64 + %p_var = alloca i64 + %arg0_var = alloca i64 + %arg1_var = alloca i64 + %arg2_var = alloca i64 + %arg3_var = alloca i64 + store i64 %hp, i64* %hp_var + store i64 %p, i64* %p_var + store i64 %arg0, i64* %arg0_var + store i64 %arg1, i64* %arg1_var + store i64 %arg2, i64* %arg2_var + store i64 %arg3, i64* %arg3_var + + ; CHECK: movq 8(%rsp), %rcx + ; CHECK-NEXT: movq 16(%rsp), %rdx + ; CHECK-NEXT: movq 24(%rsp), %rsi + ; CHECK-NEXT: movq 32(%rsp), %rbp + ; CHECK-NEXT: movq 40(%rsp), %r15 + %0 = load i64* %hp_var + %1 = load i64* %p_var + %2 = load i64* %arg0_var + %3 = load i64* %arg1_var + %4 = load i64* %arg2_var + %5 = load i64* %arg3_var + ; CHECK: jmp bar + tail call cc 11 void @bar(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) nounwind + ret void +} + +define cc 11 void @baz() nounwind { + %tmp_clos = load i64* @clos + %tmp_clos2 = inttoptr i64 %tmp_clos to i64* + %indirect_call = bitcast i64* %tmp_clos2 to void (i64, i64, i64)* + ; CHECK: movl $42, %esi + ; CHECK-NEXT: jmpq *(%rax) + tail call cc 11 void %indirect_call(i64 undef, i64 undef, i64 42) nounwind + ret void +} + +@clos = external constant i64 +declare cc 11 void @bar(i64, i64, i64, i64, i64, i64) diff --git a/test/CodeGen/X86/hipe-prologue.ll b/test/CodeGen/X86/hipe-prologue.ll new file mode 100644 index 0000000000000..ff3c5c803c907 --- /dev/null +++ b/test/CodeGen/X86/hipe-prologue.ll @@ -0,0 +1,67 @@ +; RUN: llc < %s -mcpu=generic -mtriple=i686-linux -verify-machineinstrs | FileCheck %s -check-prefix=X32-Linux +; RUN: llc < %s -mtriple=x86_64-linux-gnu -verify-machineinstrs | FileCheck %s -check-prefix=X64-Linux + +; The HiPE compiler (i.e., the native code compiler of the Erlang/OTP system) +; adds a custom assembly prologue in order to efficiently manipulate the stack +; at runtime. + +; Just to prevent the alloca from being optimized away. +declare void @dummy_use(i32*, i32) + +define {i32, i32} @test_basic(i32 %hp, i32 %p) { + ; X32-Linux: test_basic: + ; X32-Linux-NOT: calll inc_stack_0 + + ; X64-Linux: test_basic: + ; X64-Linux-NOT: callq inc_stack_0 + + %mem = alloca i32, i32 10 + call void @dummy_use (i32* %mem, i32 10) + %1 = insertvalue {i32, i32} undef, i32 %hp, 0 + %2 = insertvalue {i32, i32} %1, i32 %p, 1 + ret {i32, i32} %1 +} + +define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) { + ; X32-Linux: test_basic_hipecc: + ; X32-Linux: leal -156(%esp), %ebx + ; X32-Linux-NEXT: cmpl 76(%ebp), %ebx + ; X32-Linux-NEXT: jb .LBB1_1 + + ; X32-Linux: ret + + ; X32-Linux: .LBB1_1: + ; X32-Linux-NEXT: calll inc_stack_0 + + ; X64-Linux: test_basic_hipecc: + ; X64-Linux: leaq -232(%rsp), %r14 + ; X64-Linux-NEXT: cmpq 144(%rbp), %r14 + ; X64-Linux-NEXT: jb .LBB1_1 + + ; X64-Linux: ret + + ; X64-Linux: .LBB1_1: + ; X64-Linux-NEXT: callq inc_stack_0 + + %mem = alloca i32, i32 10 + call void @dummy_use (i32* %mem, i32 10) + %1 = insertvalue {i32, i32} undef, i32 %hp, 0 + %2 = insertvalue {i32, i32} %1, i32 %p, 1 + ret {i32, i32} %2 +} + +define cc 11 {i32,i32,i32} @test_nocall_hipecc(i32 %hp,i32 %p,i32 %x,i32 %y) { + ; X32-Linux: test_nocall_hipecc: + ; X32-Linux-NOT: calll inc_stack_0 + + ; X64-Linux: test_nocall_hipecc: + ; X64-Linux-NOT: callq inc_stack_0 + + %1 = add i32 %x, %y + %2 = mul i32 42, %1 + %3 = sub i32 24, %2 + %4 = insertvalue {i32, i32, i32} undef, i32 %hp, 0 + %5 = insertvalue {i32, i32, i32} %4, i32 %p, 1 + %6 = insertvalue {i32, i32, i32} %5, i32 %p, 2 + ret {i32, i32, i32} %6 +} diff --git a/test/CodeGen/X86/hoist-invariant-load.ll b/test/CodeGen/X86/hoist-invariant-load.ll index 74ecd045b3d53..34191e3f9a31a 100644 --- a/test/CodeGen/X86/hoist-invariant-load.ll +++ b/test/CodeGen/X86/hoist-invariant-load.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -stats -O2 2>&1 | grep "1 machine-licm" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" diff --git a/test/CodeGen/X86/imul-lea-2.ll b/test/CodeGen/X86/imul-lea-2.ll index 1cb54b37b0e1a..7b79d0678bee3 100644 --- a/test/CodeGen/X86/imul-lea-2.ll +++ b/test/CodeGen/X86/imul-lea-2.ll @@ -1,15 +1,19 @@ -; RUN: llc < %s -march=x86-64 | grep lea | count 3 -; RUN: llc < %s -march=x86-64 | grep shl | count 1 -; RUN: llc < %s -march=x86-64 | not grep imul +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK-NOT: imul define i64 @t1(i64 %a) nounwind readnone { entry: - %0 = mul i64 %a, 81 ; <i64> [#uses=1] - ret i64 %0 + %0 = mul i64 %a, 81 +; CHECK: lea +; CHECK: lea + ret i64 %0 } define i64 @t2(i64 %a) nounwind readnone { entry: - %0 = mul i64 %a, 40 ; <i64> [#uses=1] - ret i64 %0 + %0 = mul i64 %a, 40 +; CHECK: shl +; CHECK: lea + ret i64 %0 } diff --git a/test/CodeGen/X86/imul-lea.ll b/test/CodeGen/X86/imul-lea.ll index 4e8e2af0f2fec..d55ece7996edf 100644 --- a/test/CodeGen/X86/imul-lea.ll +++ b/test/CodeGen/X86/imul-lea.ll @@ -1,10 +1,12 @@ -; RUN: llc < %s -march=x86 | grep lea +; RUN: llc < %s -march=x86 | FileCheck %s declare i32 @foo() define i32 @test() { - %tmp.0 = tail call i32 @foo( ) ; <i32> [#uses=1] - %tmp.1 = mul i32 %tmp.0, 9 ; <i32> [#uses=1] - ret i32 %tmp.1 + %tmp.0 = tail call i32 @foo( ) + %tmp.1 = mul i32 %tmp.0, 9 +; CHECK-NOT: mul +; CHECK: lea + ret i32 %tmp.1 } diff --git a/test/CodeGen/X86/imul64-lea.ll b/test/CodeGen/X86/imul64-lea.ll new file mode 100644 index 0000000000000..047c129ddb33f --- /dev/null +++ b/test/CodeGen/X86/imul64-lea.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 | FileCheck %s + +; Test that 64-bit LEAs are generated for both LP64 and ILP32 in 64-bit mode. +declare i64 @foo64() + +define i64 @test64() { + %tmp.0 = tail call i64 @foo64( ) + %tmp.1 = mul i64 %tmp.0, 9 +; CHECK-NOT: mul +; CHECK: leaq + ret i64 %tmp.1 +} + +; Test that 32-bit LEAs are generated for both LP64 and ILP32 in 64-bit mode. +declare i32 @foo32() + +define i32 @test32() { + %tmp.0 = tail call i32 @foo32( ) + %tmp.1 = mul i32 %tmp.0, 9 +; CHECK-NOT: mul +; CHECK: leal + ret i32 %tmp.1 +} + diff --git a/test/CodeGen/X86/insertelement-copytoregs.ll b/test/CodeGen/X86/insertelement-copytoregs.ll index 34a29ca7d939c..88ff4dafad7d1 100644 --- a/test/CodeGen/X86/insertelement-copytoregs.ll +++ b/test/CodeGen/X86/insertelement-copytoregs.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 | grep -v IMPLICIT_DEF +; RUN: llc < %s -march=x86-64 | FileCheck %s +; CHECK-NOT: IMPLICIT_DEF define void @foo(<2 x float>* %p) { %t = insertelement <2 x float> undef, float 0.0, i32 0 diff --git a/test/CodeGen/X86/lea-2.ll b/test/CodeGen/X86/lea-2.ll index 43f69b0c6e93c..21128096e6e75 100644 --- a/test/CodeGen/X86/lea-2.ll +++ b/test/CodeGen/X86/lea-2.ll @@ -1,13 +1,15 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \ -; RUN: grep "lea EAX, DWORD PTR \[... + 4\*... - 5\]" -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \ -; RUN: not grep add +; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | FileCheck %s define i32 @test1(i32 %A, i32 %B) { - %tmp1 = shl i32 %A, 2 ; <i32> [#uses=1] - %tmp3 = add i32 %B, -5 ; <i32> [#uses=1] - %tmp4 = add i32 %tmp3, %tmp1 ; <i32> [#uses=1] - ret i32 %tmp4 + %tmp1 = shl i32 %A, 2 + %tmp3 = add i32 %B, -5 + %tmp4 = add i32 %tmp3, %tmp1 +; The above computation of %tmp4 should match a single lea, without using +; actual add instructions. +; CHECK-NOT: add +; CHECK: lea {{[A-Z]+}}, DWORD PTR [{{[A-Z]+}} + 4*{{[A-Z]+}} - 5] + + ret i32 %tmp4 } diff --git a/test/CodeGen/X86/lea-4.ll b/test/CodeGen/X86/lea-4.ll index 2171204c01d12..cef47264a5839 100644 --- a/test/CodeGen/X86/lea-4.ll +++ b/test/CodeGen/X86/lea-4.ll @@ -1,19 +1,21 @@ -; RUN: llc < %s -march=x86-64 | grep lea | count 2 +; RUN: llc < %s -march=x86-64 | FileCheck %s define zeroext i16 @t1(i32 %on_off) nounwind { entry: - %0 = sub i32 %on_off, 1 - %1 = mul i32 %0, 2 - %2 = trunc i32 %1 to i16 - %3 = zext i16 %2 to i32 - %4 = trunc i32 %3 to i16 - ret i16 %4 + %0 = sub i32 %on_off, 1 + %1 = mul i32 %0, 2 + %2 = trunc i32 %1 to i16 + %3 = zext i16 %2 to i32 + %4 = trunc i32 %3 to i16 +; CHECK: lea + ret i16 %4 } define i32 @t2(i32 %on_off) nounwind { entry: - %0 = sub i32 %on_off, 1 - %1 = mul i32 %0, 2 - %2 = and i32 %1, 65535 - ret i32 %2 + %0 = sub i32 %on_off, 1 + %1 = mul i32 %0, 2 + %2 = and i32 %1, 65535 +; CHECK: lea + ret i32 %2 } diff --git a/test/CodeGen/X86/legalize-shift-64.ll b/test/CodeGen/X86/legalize-shift-64.ll index c9f2fc27dbffc..71ef2d3152f8d 100644 --- a/test/CodeGen/X86/legalize-shift-64.ll +++ b/test/CodeGen/X86/legalize-shift-64.ll @@ -54,3 +54,14 @@ define i64 @test4(i64 %xx, i32 %test) nounwind { ; CHECK: orl %esi, %eax ; CHECK: sarl %cl, %edx } + +; PR14668 +define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) { + %shl = shl <2 x i64> %A, %B + ret <2 x i64> %shl +; CHECK: test5 +; CHECK: shl +; CHECK: shldl +; CHECK: shl +; CHECK: shldl +} diff --git a/test/CodeGen/X86/licm-nested.ll b/test/CodeGen/X86/licm-nested.ll index c3f991d7a9b03..66074fb3682c6 100644 --- a/test/CodeGen/X86/licm-nested.ll +++ b/test/CodeGen/X86/licm-nested.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 3 ; MachineLICM should be able to hoist the symbolic addresses out of diff --git a/test/CodeGen/X86/lit.local.cfg b/test/CodeGen/X86/lit.local.cfg index a8ad0f1a28b23..9d285bf4e238d 100644 --- a/test/CodeGen/X86/lit.local.cfg +++ b/test/CodeGen/X86/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll index eae2e708349cd..630c0ed1a33c3 100644 --- a/test/CodeGen/X86/memcpy-2.ll +++ b/test/CodeGen/X86/memcpy-2.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2 +; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Darwin +; RUN: llc < %s -mattr=+sse2 -mtriple=i686-pc-mingw32 -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Mingw32 ; RUN: llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1 ; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64 @@ -8,19 +9,26 @@ define void @t1(i32 %argc, i8** %argv) nounwind { entry: -; SSE2: t1: -; SSE2: movaps _.str, %xmm0 -; SSE2: movaps %xmm0 -; SSE2: movb $0 -; SSE2: movl $0 -; SSE2: movl $0 +; SSE2-Darwin: t1: +; SSE2-Darwin: movsd _.str+16, %xmm0 +; SSE2-Darwin: movsd %xmm0, 16(%esp) +; SSE2-Darwin: movaps _.str, %xmm0 +; SSE2-Darwin: movaps %xmm0 +; SSE2-Darwin: movb $0, 24(%esp) + +; SSE2-Mingw32: t1: +; SSE2-Mingw32: movsd _.str+16, %xmm0 +; SSE2-Mingw32: movsd %xmm0, 16(%esp) +; SSE2-Mingw32: movaps _.str, %xmm0 +; SSE2-Mingw32: movups %xmm0 +; SSE2-Mingw32: movb $0, 24(%esp) ; SSE1: t1: ; SSE1: movaps _.str, %xmm0 ; SSE1: movaps %xmm0 -; SSE1: movb $0 -; SSE1: movl $0 -; SSE1: movl $0 +; SSE1: movb $0, 24(%esp) +; SSE1: movl $0, 20(%esp) +; SSE1: movl $0, 16(%esp) ; NOSSE: t1: ; NOSSE: movb $0 @@ -47,9 +55,13 @@ entry: define void @t2(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp { entry: -; SSE2: t2: -; SSE2: movaps (%eax), %xmm0 -; SSE2: movaps %xmm0, (%eax) +; SSE2-Darwin: t2: +; SSE2-Darwin: movaps (%eax), %xmm0 +; SSE2-Darwin: movaps %xmm0, (%eax) + +; SSE2-Mingw32: t2: +; SSE2-Mingw32: movaps (%eax), %xmm0 +; SSE2-Mingw32: movaps %xmm0, (%eax) ; SSE1: t2: ; SSE1: movaps (%eax), %xmm0 @@ -78,11 +90,17 @@ entry: define void @t3(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp { entry: -; SSE2: t3: -; SSE2: movsd (%eax), %xmm0 -; SSE2: movsd 8(%eax), %xmm1 -; SSE2: movsd %xmm1, 8(%eax) -; SSE2: movsd %xmm0, (%eax) +; SSE2-Darwin: t3: +; SSE2-Darwin: movsd (%eax), %xmm0 +; SSE2-Darwin: movsd 8(%eax), %xmm1 +; SSE2-Darwin: movsd %xmm1, 8(%eax) +; SSE2-Darwin: movsd %xmm0, (%eax) + +; SSE2-Mingw32: t3: +; SSE2-Mingw32: movsd (%eax), %xmm0 +; SSE2-Mingw32: movsd 8(%eax), %xmm1 +; SSE2-Mingw32: movsd %xmm1, 8(%eax) +; SSE2-Mingw32: movsd %xmm0, (%eax) ; SSE1: t3: ; SSE1: movl @@ -121,15 +139,25 @@ entry: define void @t4() nounwind { entry: -; SSE2: t4: -; SSE2: movw $120 -; SSE2: movl $2021161080 -; SSE2: movl $2021161080 -; SSE2: movl $2021161080 -; SSE2: movl $2021161080 -; SSE2: movl $2021161080 -; SSE2: movl $2021161080 -; SSE2: movl $2021161080 +; SSE2-Darwin: t4: +; SSE2-Darwin: movw $120 +; SSE2-Darwin: movl $2021161080 +; SSE2-Darwin: movl $2021161080 +; SSE2-Darwin: movl $2021161080 +; SSE2-Darwin: movl $2021161080 +; SSE2-Darwin: movl $2021161080 +; SSE2-Darwin: movl $2021161080 +; SSE2-Darwin: movl $2021161080 + +; SSE2-Mingw32: t4: +; SSE2-Mingw32: movw $120 +; SSE2-Mingw32: movl $2021161080 +; SSE2-Mingw32: movl $2021161080 +; SSE2-Mingw32: movl $2021161080 +; SSE2-Mingw32: movl $2021161080 +; SSE2-Mingw32: movl $2021161080 +; SSE2-Mingw32: movl $2021161080 +; SSE2-Mingw32: movl $2021161080 ; SSE1: t4: ; SSE1: movw $120 diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll index 39c7fbafd4c7b..3372a4adc5eeb 100644 --- a/test/CodeGen/X86/memcpy.ll +++ b/test/CodeGen/X86/memcpy.ll @@ -87,8 +87,34 @@ entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([30 x i8]* @.str, i64 0, i64 0), i64 16, i32 1, i1 false) ret void +; DARWIN: test5: ; DARWIN: movabsq $7016996765293437281 ; DARWIN: movabsq $7016996765293437184 } +; PR14896 +@.str2 = private unnamed_addr constant [2 x i8] c"x\00", align 1 + +define void @test6() nounwind uwtable { +entry: +; DARWIN: test6 +; DARWIN: movw $0, 8 +; DARWIN: movq $120, 0 + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* null, i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0), i64 10, i32 1, i1 false) + ret void +} + +define void @PR15348(i8* %a, i8* %b) { +; Ensure that alignment of '0' in an @llvm.memcpy intrinsic results in +; unaligned loads and stores. +; LINUX: PR15348 +; LINUX: movb +; LINUX: movb +; LINUX: movq +; LINUX: movq +; LINUX: movq +; LINUX: movq + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 17, i32 0, i1 false) + ret void +} diff --git a/test/CodeGen/X86/memset-sse-stack-realignment.ll b/test/CodeGen/X86/memset-sse-stack-realignment.ll new file mode 100644 index 0000000000000..df9de5dfaf22b --- /dev/null +++ b/test/CodeGen/X86/memset-sse-stack-realignment.ll @@ -0,0 +1,77 @@ +; Make sure that we realign the stack. Mingw32 uses 4 byte stack alignment, we +; need 16 bytes for SSE and 32 bytes for AVX. + +; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium2 | FileCheck %s -check-prefix=NOSSE +; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s -check-prefix=SSE1 +; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=yonah | FileCheck %s -check-prefix=SSE2 +; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX1 +; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2 + +define void @test1(i32 %t) nounwind { + %tmp1210 = alloca i8, i32 32, align 4 + call void @llvm.memset.p0i8.i64(i8* %tmp1210, i8 0, i64 32, i32 4, i1 false) + %x = alloca i8, i32 %t + call void @dummy(i8* %x) + ret void + +; NOSSE: test1: +; NOSSE-NOT: and +; NOSSE: movl $0 + +; SSE1: test1: +; SSE1: andl $-16 +; SSE1: movl %esp, %esi +; SSE1: movaps + +; SSE2: test1: +; SSE2: andl $-16 +; SSE2: movl %esp, %esi +; SSE2: movaps + +; AVX1: test1: +; AVX1: andl $-32 +; AVX1: movl %esp, %esi +; AVX1: vmovaps %ymm + +; AVX2: test1: +; AVX2: andl $-32 +; AVX2: movl %esp, %esi +; AVX2: vmovaps %ymm + +} + +define void @test2(i32 %t) nounwind { + %tmp1210 = alloca i8, i32 16, align 4 + call void @llvm.memset.p0i8.i64(i8* %tmp1210, i8 0, i64 16, i32 4, i1 false) + %x = alloca i8, i32 %t + call void @dummy(i8* %x) + ret void + +; NOSSE: test2: +; NOSSE-NOT: and +; NOSSE: movl $0 + +; SSE1: test2: +; SSE1: andl $-16 +; SSE1: movl %esp, %esi +; SSE1: movaps + +; SSE2: test2: +; SSE2: andl $-16 +; SSE2: movl %esp, %esi +; SSE2: movaps + +; AVX1: test2: +; AVX1: andl $-16 +; AVX1: movl %esp, %esi +; AVX1: vmovaps %xmm + +; AVX2: test2: +; AVX2: andl $-16 +; AVX2: movl %esp, %esi +; AVX2: vmovaps %xmm +} + +declare void @dummy(i8*) + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/memset.ll b/test/CodeGen/X86/memset.ll index 72b3e0fa3d513..0d479f0abe7b9 100644 --- a/test/CodeGen/X86/memset.ll +++ b/test/CodeGen/X86/memset.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 9 -; RUN: llc < %s -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 3 +; RUN: llc < %s -march=x86 -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -march=x86 -mcpu=pentium3 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=XMM +; RUN: llc < %s -march=x86 -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM %struct.x = type { i16, i16 } @@ -8,7 +9,30 @@ entry: %up_mvd = alloca [8 x %struct.x] ; <[8 x %struct.x]*> [#uses=2] %up_mvd116 = getelementptr [8 x %struct.x]* %up_mvd, i32 0, i32 0 ; <%struct.x*> [#uses=1] %tmp110117 = bitcast [8 x %struct.x]* %up_mvd to i8* ; <i8*> [#uses=1] + call void @llvm.memset.p0i8.i64(i8* %tmp110117, i8 0, i64 32, i32 8, i1 false) +; X86: movl $0, +; X86: movl $0, +; X86: movl $0, +; X86: movl $0, +; X86: movl $0, +; X86: movl $0, +; X86: movl $0, +; X86: movl $0, +; X86-NOT: movl $0, +; X86: ret + +; XMM: xorps %xmm{{[0-9]+}}, [[Z:%xmm[0-9]+]] +; XMM: movaps [[Z]], +; XMM: movaps [[Z]], +; XMM-NOT: movaps +; XMM: ret + +; YMM: vxorps %ymm{{[0-9]+}}, %ymm{{[0-9]+}}, [[Z:%ymm[0-9]+]] +; YMM: vmovaps [[Z]], +; YMM-NOT: movaps +; YMM: ret + call void @foo( %struct.x* %up_mvd116 ) nounwind ret void } @@ -16,3 +40,16 @@ entry: declare void @foo(%struct.x*) declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind + +define void @PR15348(i8* %a) { +; Ensure that alignment of '0' in an @llvm.memset intrinsic results in +; unaligned loads and stores. +; XMM: PR15348 +; XMM: movb $0, +; XMM: movl $0, +; XMM: movl $0, +; XMM: movl $0, +; XMM: movl $0, + call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 17, i32 0, i1 false) + ret void +} diff --git a/test/CodeGen/X86/memset64-on-x86-32.ll b/test/CodeGen/X86/memset64-on-x86-32.ll index e20fce172f273..8cfa032797f70 100644 --- a/test/CodeGen/X86/memset64-on-x86-32.ll +++ b/test/CodeGen/X86/memset64-on-x86-32.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=nehalem | grep movups | count 5 ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 | grep movl | count 20 +; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=core2 | grep movl | count 20 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | grep movq | count 10 define void @bork() nounwind { diff --git a/test/CodeGen/X86/misched-crash.ll b/test/CodeGen/X86/misched-crash.ll new file mode 100644 index 0000000000000..7644ee0708780 --- /dev/null +++ b/test/CodeGen/X86/misched-crash.ll @@ -0,0 +1,40 @@ +; RUN: llc < %s -enable-misched -verify-misched +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10" + +; This function contains a cmp instruction with two users. +; Hoisting the last use requires trimming the EFLAGS live range to the second. +define void @rdar13353090(i8* %plane, i64 %_x1, i64 %_x2) { +entry: + %cmp = icmp ult i64 %_x1, %_x2 + %cond = select i1 %cmp, i64 %_x1, i64 %_x2 + %cond10 = select i1 %cmp, i64 %_x2, i64 %_x1 + %0 = load i64* null, align 8 + %cmp16 = icmp ult i64 %cond, %0 + %cmp23 = icmp ugt i64 %cond10, 0 + br i1 %cmp16, label %land.lhs.true21, label %return + +land.lhs.true21: ; preds = %entry + %sub = add i64 %0, -1 + br i1 %cmp23, label %if.then24, label %return + +if.then24: ; preds = %land.lhs.true21 + %cmp16.i = icmp ult i64 %cond, %sub + %cond20.i = select i1 %cmp16.i, i64 %cond, i64 %sub + %add21.i = add i64 0, %cond20.i + br label %for.body34.i + +for.body34.i: ; preds = %for.inc39.i, %if.then24 + %index.178.i = phi i64 [ %add21.i, %if.then24 ], [ %inc41.i, %for.inc39.i ] + %arrayidx35.i = getelementptr inbounds i8* %plane, i64 %index.178.i + %1 = load i8* %arrayidx35.i, align 1 + %tobool36.i = icmp eq i8 %1, 0 + br i1 %tobool36.i, label %for.inc39.i, label %return + +for.inc39.i: ; preds = %for.body34.i + %inc41.i = add i64 %index.178.i, 1 + br i1 undef, label %return, label %for.body34.i + +return: ; preds = %for.inc39.i, %for.body34.i, %land.lhs.true21, %entry + ret void +} diff --git a/test/CodeGen/X86/misched-ilp.ll b/test/CodeGen/X86/misched-ilp.ll index c6cedb7be8714..4ca296ca92e5f 100644 --- a/test/CodeGen/X86/misched-ilp.ll +++ b/test/CodeGen/X86/misched-ilp.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=core2 -enable-misched -misched=ilpmax | FileCheck -check-prefix=MAX %s -; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=core2 -enable-misched -misched=ilpmin | FileCheck -check-prefix=MIN %s +; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmax | FileCheck -check-prefix=MAX %s +; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmin | FileCheck -check-prefix=MIN %s ; ; Basic verification of the ScheduleDAGILP metric. ; diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll new file mode 100644 index 0000000000000..0f6e442b1a8d4 --- /dev/null +++ b/test/CodeGen/X86/misched-matmul.ll @@ -0,0 +1,228 @@ +; REQUIRES: asserts +; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -stats 2>&1 | FileCheck %s +; +; Verify that register pressure heuristics are working in MachineScheduler. +; +; When we enable subtree scheduling heuristics on X86, we may need a +; flag to disable it for this test case. +; +; CHECK: @wrap_mul4 +; CHECK: 30 regalloc - Number of spills inserted + +define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 { +entry: + %arrayidx1.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 0 + %0 = load double* %arrayidx1.i, align 8, !tbaa !0 + %arrayidx3.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 0 + %1 = load double* %arrayidx3.i, align 8, !tbaa !0 + %mul.i = fmul double %0, %1 + %arrayidx5.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 1 + %2 = load double* %arrayidx5.i, align 8, !tbaa !0 + %arrayidx7.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 0 + %3 = load double* %arrayidx7.i, align 8, !tbaa !0 + %mul8.i = fmul double %2, %3 + %add.i = fadd double %mul.i, %mul8.i + %arrayidx10.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 2 + %4 = load double* %arrayidx10.i, align 8, !tbaa !0 + %arrayidx12.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 0 + %5 = load double* %arrayidx12.i, align 8, !tbaa !0 + %mul13.i = fmul double %4, %5 + %add14.i = fadd double %add.i, %mul13.i + %arrayidx16.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 3 + %6 = load double* %arrayidx16.i, align 8, !tbaa !0 + %arrayidx18.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 0 + %7 = load double* %arrayidx18.i, align 8, !tbaa !0 + %mul19.i = fmul double %6, %7 + %add20.i = fadd double %add14.i, %mul19.i + %arrayidx25.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 1 + %8 = load double* %arrayidx25.i, align 8, !tbaa !0 + %mul26.i = fmul double %0, %8 + %arrayidx30.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 1 + %9 = load double* %arrayidx30.i, align 8, !tbaa !0 + %mul31.i = fmul double %2, %9 + %add32.i = fadd double %mul26.i, %mul31.i + %arrayidx36.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 1 + %10 = load double* %arrayidx36.i, align 8, !tbaa !0 + %mul37.i = fmul double %4, %10 + %add38.i = fadd double %add32.i, %mul37.i + %arrayidx42.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 1 + %11 = load double* %arrayidx42.i, align 8, !tbaa !0 + %mul43.i = fmul double %6, %11 + %add44.i = fadd double %add38.i, %mul43.i + %arrayidx49.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 2 + %12 = load double* %arrayidx49.i, align 8, !tbaa !0 + %mul50.i = fmul double %0, %12 + %arrayidx54.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 2 + %13 = load double* %arrayidx54.i, align 8, !tbaa !0 + %mul55.i = fmul double %2, %13 + %add56.i = fadd double %mul50.i, %mul55.i + %arrayidx60.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 2 + %14 = load double* %arrayidx60.i, align 8, !tbaa !0 + %mul61.i = fmul double %4, %14 + %add62.i = fadd double %add56.i, %mul61.i + %arrayidx66.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 2 + %15 = load double* %arrayidx66.i, align 8, !tbaa !0 + %mul67.i = fmul double %6, %15 + %add68.i = fadd double %add62.i, %mul67.i + %arrayidx73.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 3 + %16 = load double* %arrayidx73.i, align 8, !tbaa !0 + %mul74.i = fmul double %0, %16 + %arrayidx78.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 3 + %17 = load double* %arrayidx78.i, align 8, !tbaa !0 + %mul79.i = fmul double %2, %17 + %add80.i = fadd double %mul74.i, %mul79.i + %arrayidx84.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 3 + %18 = load double* %arrayidx84.i, align 8, !tbaa !0 + %mul85.i = fmul double %4, %18 + %add86.i = fadd double %add80.i, %mul85.i + %arrayidx90.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 3 + %19 = load double* %arrayidx90.i, align 8, !tbaa !0 + %mul91.i = fmul double %6, %19 + %add92.i = fadd double %add86.i, %mul91.i + %arrayidx95.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 0 + %20 = load double* %arrayidx95.i, align 8, !tbaa !0 + %mul98.i = fmul double %1, %20 + %arrayidx100.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 1 + %21 = load double* %arrayidx100.i, align 8, !tbaa !0 + %mul103.i = fmul double %3, %21 + %add104.i = fadd double %mul98.i, %mul103.i + %arrayidx106.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 2 + %22 = load double* %arrayidx106.i, align 8, !tbaa !0 + %mul109.i = fmul double %5, %22 + %add110.i = fadd double %add104.i, %mul109.i + %arrayidx112.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 3 + %23 = load double* %arrayidx112.i, align 8, !tbaa !0 + %mul115.i = fmul double %7, %23 + %add116.i = fadd double %add110.i, %mul115.i + %mul122.i = fmul double %8, %20 + %mul127.i = fmul double %9, %21 + %add128.i = fadd double %mul122.i, %mul127.i + %mul133.i = fmul double %10, %22 + %add134.i = fadd double %add128.i, %mul133.i + %mul139.i = fmul double %11, %23 + %add140.i = fadd double %add134.i, %mul139.i + %mul146.i = fmul double %12, %20 + %mul151.i = fmul double %13, %21 + %add152.i = fadd double %mul146.i, %mul151.i + %mul157.i = fmul double %14, %22 + %add158.i = fadd double %add152.i, %mul157.i + %mul163.i = fmul double %15, %23 + %add164.i = fadd double %add158.i, %mul163.i + %mul170.i = fmul double %16, %20 + %mul175.i = fmul double %17, %21 + %add176.i = fadd double %mul170.i, %mul175.i + %mul181.i = fmul double %18, %22 + %add182.i = fadd double %add176.i, %mul181.i + %mul187.i = fmul double %19, %23 + %add188.i = fadd double %add182.i, %mul187.i + %arrayidx191.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 0 + %24 = load double* %arrayidx191.i, align 8, !tbaa !0 + %mul194.i = fmul double %1, %24 + %arrayidx196.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 1 + %25 = load double* %arrayidx196.i, align 8, !tbaa !0 + %mul199.i = fmul double %3, %25 + %add200.i = fadd double %mul194.i, %mul199.i + %arrayidx202.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 2 + %26 = load double* %arrayidx202.i, align 8, !tbaa !0 + %mul205.i = fmul double %5, %26 + %add206.i = fadd double %add200.i, %mul205.i + %arrayidx208.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 3 + %27 = load double* %arrayidx208.i, align 8, !tbaa !0 + %mul211.i = fmul double %7, %27 + %add212.i = fadd double %add206.i, %mul211.i + %mul218.i = fmul double %8, %24 + %mul223.i = fmul double %9, %25 + %add224.i = fadd double %mul218.i, %mul223.i + %mul229.i = fmul double %10, %26 + %add230.i = fadd double %add224.i, %mul229.i + %mul235.i = fmul double %11, %27 + %add236.i = fadd double %add230.i, %mul235.i + %mul242.i = fmul double %12, %24 + %mul247.i = fmul double %13, %25 + %add248.i = fadd double %mul242.i, %mul247.i + %mul253.i = fmul double %14, %26 + %add254.i = fadd double %add248.i, %mul253.i + %mul259.i = fmul double %15, %27 + %add260.i = fadd double %add254.i, %mul259.i + %mul266.i = fmul double %16, %24 + %mul271.i = fmul double %17, %25 + %add272.i = fadd double %mul266.i, %mul271.i + %mul277.i = fmul double %18, %26 + %add278.i = fadd double %add272.i, %mul277.i + %mul283.i = fmul double %19, %27 + %add284.i = fadd double %add278.i, %mul283.i + %arrayidx287.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 0 + %28 = load double* %arrayidx287.i, align 8, !tbaa !0 + %mul290.i = fmul double %1, %28 + %arrayidx292.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 1 + %29 = load double* %arrayidx292.i, align 8, !tbaa !0 + %mul295.i = fmul double %3, %29 + %add296.i = fadd double %mul290.i, %mul295.i + %arrayidx298.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 2 + %30 = load double* %arrayidx298.i, align 8, !tbaa !0 + %mul301.i = fmul double %5, %30 + %add302.i = fadd double %add296.i, %mul301.i + %arrayidx304.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 3 + %31 = load double* %arrayidx304.i, align 8, !tbaa !0 + %mul307.i = fmul double %7, %31 + %add308.i = fadd double %add302.i, %mul307.i + %mul314.i = fmul double %8, %28 + %mul319.i = fmul double %9, %29 + %add320.i = fadd double %mul314.i, %mul319.i + %mul325.i = fmul double %10, %30 + %add326.i = fadd double %add320.i, %mul325.i + %mul331.i = fmul double %11, %31 + %add332.i = fadd double %add326.i, %mul331.i + %mul338.i = fmul double %12, %28 + %mul343.i = fmul double %13, %29 + %add344.i = fadd double %mul338.i, %mul343.i + %mul349.i = fmul double %14, %30 + %add350.i = fadd double %add344.i, %mul349.i + %mul355.i = fmul double %15, %31 + %add356.i = fadd double %add350.i, %mul355.i + %mul362.i = fmul double %16, %28 + %mul367.i = fmul double %17, %29 + %add368.i = fadd double %mul362.i, %mul367.i + %mul373.i = fmul double %18, %30 + %add374.i = fadd double %add368.i, %mul373.i + %mul379.i = fmul double %19, %31 + %add380.i = fadd double %add374.i, %mul379.i + store double %add20.i, double* %Out, align 8 + %Res.i.sroa.1.8.idx2 = getelementptr inbounds double* %Out, i64 1 + store double %add44.i, double* %Res.i.sroa.1.8.idx2, align 8 + %Res.i.sroa.2.16.idx4 = getelementptr inbounds double* %Out, i64 2 + store double %add68.i, double* %Res.i.sroa.2.16.idx4, align 8 + %Res.i.sroa.3.24.idx6 = getelementptr inbounds double* %Out, i64 3 + store double %add92.i, double* %Res.i.sroa.3.24.idx6, align 8 + %Res.i.sroa.4.32.idx8 = getelementptr inbounds double* %Out, i64 4 + store double %add116.i, double* %Res.i.sroa.4.32.idx8, align 8 + %Res.i.sroa.5.40.idx10 = getelementptr inbounds double* %Out, i64 5 + store double %add140.i, double* %Res.i.sroa.5.40.idx10, align 8 + %Res.i.sroa.6.48.idx12 = getelementptr inbounds double* %Out, i64 6 + store double %add164.i, double* %Res.i.sroa.6.48.idx12, align 8 + %Res.i.sroa.7.56.idx14 = getelementptr inbounds double* %Out, i64 7 + store double %add188.i, double* %Res.i.sroa.7.56.idx14, align 8 + %Res.i.sroa.8.64.idx16 = getelementptr inbounds double* %Out, i64 8 + store double %add212.i, double* %Res.i.sroa.8.64.idx16, align 8 + %Res.i.sroa.9.72.idx18 = getelementptr inbounds double* %Out, i64 9 + store double %add236.i, double* %Res.i.sroa.9.72.idx18, align 8 + %Res.i.sroa.10.80.idx20 = getelementptr inbounds double* %Out, i64 10 + store double %add260.i, double* %Res.i.sroa.10.80.idx20, align 8 + %Res.i.sroa.11.88.idx22 = getelementptr inbounds double* %Out, i64 11 + store double %add284.i, double* %Res.i.sroa.11.88.idx22, align 8 + %Res.i.sroa.12.96.idx24 = getelementptr inbounds double* %Out, i64 12 + store double %add308.i, double* %Res.i.sroa.12.96.idx24, align 8 + %Res.i.sroa.13.104.idx26 = getelementptr inbounds double* %Out, i64 13 + store double %add332.i, double* %Res.i.sroa.13.104.idx26, align 8 + %Res.i.sroa.14.112.idx28 = getelementptr inbounds double* %Out, i64 14 + store double %add356.i, double* %Res.i.sroa.14.112.idx28, align 8 + %Res.i.sroa.15.120.idx30 = getelementptr inbounds double* %Out, i64 15 + store double %add380.i, double* %Res.i.sroa.15.120.idx30, align 8 + ret void +} + +attributes #0 = { noinline nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!0 = metadata !{metadata !"double", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/misched-matrix.ll b/test/CodeGen/X86/misched-matrix.ll new file mode 100644 index 0000000000000..f5566e5e5de97 --- /dev/null +++ b/test/CodeGen/X86/misched-matrix.ll @@ -0,0 +1,195 @@ +; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ +; RUN: -misched-topdown -verify-machineinstrs \ +; RUN: | FileCheck %s -check-prefix=TOPDOWN +; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ +; RUN: -misched=ilpmin -verify-machineinstrs \ +; RUN: | FileCheck %s -check-prefix=ILPMIN +; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \ +; RUN: -misched=ilpmax -verify-machineinstrs \ +; RUN: | FileCheck %s -check-prefix=ILPMAX +; +; Verify that the MI scheduler minimizes register pressure for a +; uniform set of bottom-up subtrees (unrolled matrix multiply). +; +; For current top-down heuristics, ensure that some folded imulls have +; been reordered with the stores. This tests the scheduler's cheap +; alias analysis ability (that doesn't require any AliasAnalysis pass). +; +; TOPDOWN: %for.body +; TOPDOWN: movl %{{.*}}, ( +; TOPDOWN: imull {{[0-9]*}}( +; TOPDOWN: movl %{{.*}}, 4( +; TOPDOWN: imull {{[0-9]*}}( +; TOPDOWN: movl %{{.*}}, 8( +; TOPDOWN: movl %{{.*}}, 12( +; TOPDOWN: %for.end +; +; For -misched=ilpmin, verify that each expression subtree is +; scheduled independently, and that the imull/adds are interleaved. +; +; ILPMIN: %for.body +; ILPMIN: movl %{{.*}}, ( +; ILPMIN: imull +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: movl %{{.*}}, 4( +; ILPMIN: imull +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: movl %{{.*}}, 8( +; ILPMIN: imull +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: imull +; ILPMIN: addl +; ILPMIN: movl %{{.*}}, 12( +; ILPMIN: %for.end +; +; For -misched=ilpmax, verify that each expression subtree is +; scheduled independently, and that the imull/adds are clustered. +; +; ILPMAX: %for.body +; ILPMAX: movl %{{.*}}, ( +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: addl +; ILPMAX: addl +; ILPMAX: addl +; ILPMAX: movl %{{.*}}, 4( +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: addl +; ILPMAX: addl +; ILPMAX: addl +; ILPMAX: movl %{{.*}}, 8( +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: imull +; ILPMAX: addl +; ILPMAX: addl +; ILPMAX: addl +; ILPMAX: movl %{{.*}}, 12( +; ILPMAX: %for.end + +define void @mmult([4 x i32]* noalias nocapture %m1, [4 x i32]* noalias nocapture %m2, +[4 x i32]* noalias nocapture %m3) nounwind uwtable ssp { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx8 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 0 + %tmp = load i32* %arrayidx8, align 4, !tbaa !0 + %arrayidx12 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 0 + %tmp1 = load i32* %arrayidx12, align 4, !tbaa !0 + %arrayidx8.1 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 1 + %tmp2 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %arrayidx12.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 0 + %tmp3 = load i32* %arrayidx12.1, align 4, !tbaa !0 + %arrayidx8.2 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 2 + %tmp4 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %arrayidx12.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 0 + %tmp5 = load i32* %arrayidx12.2, align 4, !tbaa !0 + %arrayidx8.3 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 3 + %tmp6 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %arrayidx12.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 0 + %tmp8 = load i32* %arrayidx8, align 4, !tbaa !0 + %arrayidx12.137 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 1 + %tmp9 = load i32* %arrayidx12.137, align 4, !tbaa !0 + %tmp10 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %arrayidx12.1.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 1 + %tmp11 = load i32* %arrayidx12.1.1, align 4, !tbaa !0 + %tmp12 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %arrayidx12.2.1 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 1 + %tmp13 = load i32* %arrayidx12.2.1, align 4, !tbaa !0 + %tmp14 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %arrayidx12.3.1 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 1 + %tmp15 = load i32* %arrayidx12.3.1, align 4, !tbaa !0 + %tmp16 = load i32* %arrayidx8, align 4, !tbaa !0 + %arrayidx12.239 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 2 + %tmp17 = load i32* %arrayidx12.239, align 4, !tbaa !0 + %tmp18 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %arrayidx12.1.2 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 2 + %tmp19 = load i32* %arrayidx12.1.2, align 4, !tbaa !0 + %tmp20 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %arrayidx12.2.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 2 + %tmp21 = load i32* %arrayidx12.2.2, align 4, !tbaa !0 + %tmp22 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %arrayidx12.3.2 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 2 + %tmp23 = load i32* %arrayidx12.3.2, align 4, !tbaa !0 + %tmp24 = load i32* %arrayidx8, align 4, !tbaa !0 + %arrayidx12.341 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 3 + %tmp25 = load i32* %arrayidx12.341, align 4, !tbaa !0 + %tmp26 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %arrayidx12.1.3 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 3 + %tmp27 = load i32* %arrayidx12.1.3, align 4, !tbaa !0 + %tmp28 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %arrayidx12.2.3 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 3 + %tmp29 = load i32* %arrayidx12.2.3, align 4, !tbaa !0 + %tmp30 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %arrayidx12.3.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 3 + %tmp31 = load i32* %arrayidx12.3.3, align 4, !tbaa !0 + %tmp7 = load i32* %arrayidx12.3, align 4, !tbaa !0 + %mul = mul nsw i32 %tmp1, %tmp + %mul.1 = mul nsw i32 %tmp3, %tmp2 + %mul.2 = mul nsw i32 %tmp5, %tmp4 + %mul.3 = mul nsw i32 %tmp7, %tmp6 + %mul.138 = mul nsw i32 %tmp9, %tmp8 + %mul.1.1 = mul nsw i32 %tmp11, %tmp10 + %mul.2.1 = mul nsw i32 %tmp13, %tmp12 + %mul.3.1 = mul nsw i32 %tmp15, %tmp14 + %mul.240 = mul nsw i32 %tmp17, %tmp16 + %mul.1.2 = mul nsw i32 %tmp19, %tmp18 + %mul.2.2 = mul nsw i32 %tmp21, %tmp20 + %mul.3.2 = mul nsw i32 %tmp23, %tmp22 + %mul.342 = mul nsw i32 %tmp25, %tmp24 + %mul.1.3 = mul nsw i32 %tmp27, %tmp26 + %mul.2.3 = mul nsw i32 %tmp29, %tmp28 + %mul.3.3 = mul nsw i32 %tmp31, %tmp30 + %add.1 = add nsw i32 %mul.1, %mul + %add.2 = add nsw i32 %mul.2, %add.1 + %add.3 = add nsw i32 %mul.3, %add.2 + %add.1.1 = add nsw i32 %mul.1.1, %mul.138 + %add.2.1 = add nsw i32 %mul.2.1, %add.1.1 + %add.3.1 = add nsw i32 %mul.3.1, %add.2.1 + %add.1.2 = add nsw i32 %mul.1.2, %mul.240 + %add.2.2 = add nsw i32 %mul.2.2, %add.1.2 + %add.3.2 = add nsw i32 %mul.3.2, %add.2.2 + %add.1.3 = add nsw i32 %mul.1.3, %mul.342 + %add.2.3 = add nsw i32 %mul.2.3, %add.1.3 + %add.3.3 = add nsw i32 %mul.3.3, %add.2.3 + %arrayidx16 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 0 + store i32 %add.3, i32* %arrayidx16, align 4, !tbaa !0 + %arrayidx16.1 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 1 + store i32 %add.3.1, i32* %arrayidx16.1, align 4, !tbaa !0 + %arrayidx16.2 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 2 + store i32 %add.3.2, i32* %arrayidx16.2, align 4, !tbaa !0 + %arrayidx16.3 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 3 + store i32 %add.3.3, i32* %arrayidx16.3, align 4, !tbaa !0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 4 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/misched-new.ll b/test/CodeGen/X86/misched-new.ll index cec04b534fba3..89e45b7cfc212 100644 --- a/test/CodeGen/X86/misched-new.ll +++ b/test/CodeGen/X86/misched-new.ll @@ -1,6 +1,9 @@ ; RUN: llc < %s -march=x86-64 -mcpu=core2 -x86-early-ifcvt -enable-misched \ ; RUN: -misched=shuffle -misched-bottomup -verify-machineinstrs \ ; RUN: | FileCheck %s +; RUN: llc < %s -march=x86-64 -mcpu=core2 -x86-early-ifcvt -enable-misched \ +; RUN: -misched=shuffle -misched-topdown -verify-machineinstrs \ +; RUN: | FileCheck %s --check-prefix TOPDOWN ; REQUIRES: asserts ; ; Interesting MachineScheduler cases. @@ -51,3 +54,56 @@ if.end: ; preds = %if.then, %entry } declare void @bar(i32,i32) + +; Test that the DAG builder can handle an undef vreg on ExitSU. +; CHECK: hasundef +; CHECK: call + +%t0 = type { i32, i32, i8 } +%t6 = type { i32 (...)**, %t7* } +%t7 = type { i32 (...)** } + +define void @hasundef() unnamed_addr uwtable ssp align 2 { + %1 = alloca %t0, align 8 + br i1 undef, label %3, label %2 + +; <label>:2 ; preds = %0 + unreachable + +; <label>:3 ; preds = %0 + br i1 undef, label %4, label %5 + +; <label>:4 ; preds = %3 + call void undef(%t6* undef, %t0* %1) + unreachable + +; <label>:5 ; preds = %3 + ret void +} + +; Test top-down subregister liveness tracking. Self-verification +; catches any pressure set underflow. +; rdar://12797931. +; +; TOPDOWN: @testSubregTracking +; TOPDOWN: divb +; TOPDOWN: movzbl %al +; TOPDOWN: ret +define void @testSubregTracking() nounwind uwtable ssp align 2 { + %tmp = load i8* undef, align 1 + %tmp6 = sub i8 0, %tmp + %tmp7 = load i8* undef, align 1 + %tmp8 = udiv i8 %tmp6, %tmp7 + %tmp9 = zext i8 %tmp8 to i64 + %tmp10 = load i8* undef, align 1 + %tmp11 = zext i8 %tmp10 to i64 + %tmp12 = mul i64 %tmp11, %tmp9 + %tmp13 = urem i8 %tmp6, %tmp7 + %tmp14 = zext i8 %tmp13 to i32 + %tmp15 = add nsw i32 %tmp14, 0 + %tmp16 = add i32 %tmp15, 0 + store i32 %tmp16, i32* undef, align 4 + %tmp17 = add i64 0, %tmp12 + store i64 %tmp17, i64* undef, align 8 + ret void +} diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll index 65ee7b1d8e002..bb42734833ddc 100644 --- a/test/CodeGen/X86/movgs.ll +++ b/test/CodeGen/X86/movgs.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=sse41 | FileCheck %s --check-prefix=X32 -; RUN: llc < %s -mtriple=x86_64-linux -mattr=sse41 | FileCheck %s --check-prefix=X64 -; RUN: llc < %s -mtriple=x86_64-win32 -mattr=sse41 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X64 define i32 @test1() nounwind readonly { entry: diff --git a/test/CodeGen/X86/ms-inline-asm.ll b/test/CodeGen/X86/ms-inline-asm.ll index 24d28adda8949..5048a93ad302a 100644 --- a/test/CodeGen/X86/ms-inline-asm.ll +++ b/test/CodeGen/X86/ms-inline-asm.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s define i32 @t1() nounwind { entry: %0 = tail call i32 asm sideeffect inteldialect "mov eax, $1\0A\09mov $0, eax", "=r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind ret i32 %0 ; CHECK: t1 +; CHECK: movl %esp, %ebp ; CHECK: {{## InlineAsm Start|#APP}} ; CHECK: .intel_syntax ; CHECK: mov eax, ecx @@ -18,6 +19,7 @@ entry: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind ret void ; CHECK: t2 +; CHECK: movl %esp, %ebp ; CHECK: {{## InlineAsm Start|#APP}} ; CHECK: .intel_syntax ; CHECK: mov eax, 1 @@ -32,6 +34,7 @@ entry: call void asm sideeffect inteldialect "mov eax, DWORD PTR [$0]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %V.addr) nounwind ret void ; CHECK: t3 +; CHECK: movl %esp, %ebp ; CHECK: {{## InlineAsm Start|#APP}} ; CHECK: .intel_syntax ; CHECK: mov eax, DWORD PTR {{[[esp]}} @@ -53,6 +56,7 @@ entry: %0 = load i32* %b1, align 4 ret i32 %0 ; CHECK: t18 +; CHECK: movl %esp, %ebp ; CHECK: {{## InlineAsm Start|#APP}} ; CHECK: .intel_syntax ; CHECK: lea ebx, foo @@ -61,3 +65,46 @@ entry: ; CHECK: .att_syntax ; CHECK: {{## InlineAsm End|#NO_APP}} } + +define void @t19_helper() nounwind { +entry: + ret void +} + +define void @t19() nounwind { +entry: + call void asm sideeffect inteldialect "call $0", "r,~{dirflag},~{fpsr},~{flags}"(void ()* @t19_helper) nounwind + ret void +; CHECK: t19: +; CHECK: movl %esp, %ebp +; CHECK: movl ${{_?}}t19_helper, %eax +; CHECK: {{## InlineAsm Start|#APP}} +; CHECK: .intel_syntax +; CHECK: call eax +; CHECK: .att_syntax +; CHECK: {{## InlineAsm End|#NO_APP}} +} + +@results = global [2 x i32] [i32 3, i32 2], align 4 + +define i32* @t30() nounwind ssp { +entry: + %res = alloca i32*, align 4 + call void asm sideeffect inteldialect "lea edi, dword ptr $0", "*m,~{edi},~{dirflag},~{fpsr},~{flags}"([2 x i32]* @results) nounwind + call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind + %0 = load i32** %res, align 4 + ret i32* %0 +; CHECK: t30: +; CHECK: movl %esp, %ebp +; CHECK: {{## InlineAsm Start|#APP}} +; CHECK: .intel_syntax +; CHECK: lea edi, dword ptr [{{_?}}results] +; CHECK: .att_syntax +; CHECK: {{## InlineAsm End|#NO_APP}} +; CHECK: {{## InlineAsm Start|#APP}} +; CHECK: .intel_syntax +; CHECK: mov dword ptr [esi], edi +; CHECK: .att_syntax +; CHECK: {{## InlineAsm End|#NO_APP}} +; CHECK: movl (%esi), %eax +} diff --git a/test/CodeGen/X86/multiple-loop-post-inc.ll b/test/CodeGen/X86/multiple-loop-post-inc.ll index 9f7d036cf141c..29b9f34464f0c 100644 --- a/test/CodeGen/X86/multiple-loop-post-inc.ll +++ b/test/CodeGen/X86/multiple-loop-post-inc.ll @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s +; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s ; rdar://7236213 ; ; The scheduler's 2-address hack has been disabled, so there is diff --git a/test/CodeGen/X86/no-cmov.ll b/test/CodeGen/X86/no-cmov.ll new file mode 100644 index 0000000000000..62d73b0732e7d --- /dev/null +++ b/test/CodeGen/X86/no-cmov.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=x86 -mcpu=i486 < %s | FileCheck %s + +define i32 @test1(i32 %g, i32* %j) { + %tobool = icmp eq i32 %g, 0 + %cmp = load i32* %j, align 4 + %retval.0 = select i1 %tobool, i32 1, i32 %cmp + ret i32 %retval.0 + +; CHECK: test1: +; CHECK-NOT: cmov +} diff --git a/test/CodeGen/X86/phi-immediate-factoring.ll b/test/CodeGen/X86/phi-immediate-factoring.ll index 476bb10998314..6425ef0e8376b 100644 --- a/test/CodeGen/X86/phi-immediate-factoring.ll +++ b/test/CodeGen/X86/phi-immediate-factoring.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | grep "Number of blocks eliminated" | grep 6 ; PR1296 diff --git a/test/CodeGen/X86/pmovsx-inreg.ll b/test/CodeGen/X86/pmovsx-inreg.ll new file mode 100644 index 0000000000000..d8c27f25043a6 --- /dev/null +++ b/test/CodeGen/X86/pmovsx-inreg.ll @@ -0,0 +1,176 @@ +; RUN: llc < %s -march=x86-64 -mcpu=penryn | FileCheck -check-prefix=SSE41 %s +; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck -check-prefix=AVX1 %s +; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck -check-prefix=AVX2 %s + +; PR14887 +; These tests inject a store into the chain to test the inreg versions of pmovsx + +define void @test1(<2 x i8>* %in, <2 x i64>* %out) nounwind { + %wide.load35 = load <2 x i8>* %in, align 1 + %sext = sext <2 x i8> %wide.load35 to <2 x i64> + store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8 + store <2 x i64> %sext, <2 x i64>* %out, align 8 + ret void + +; SSE41: test1: +; SSE41: pmovsxbq + +; AVX1: test1: +; AVX1: vpmovsxbq + +; AVX2: test1: +; AVX2: vpmovsxbq +} + +define void @test2(<4 x i8>* %in, <4 x i64>* %out) nounwind { + %wide.load35 = load <4 x i8>* %in, align 1 + %sext = sext <4 x i8> %wide.load35 to <4 x i64> + store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8 + store <4 x i64> %sext, <4 x i64>* %out, align 8 + ret void + +; AVX2: test2: +; AVX2: vpmovsxbq +} + +define void @test3(<4 x i8>* %in, <4 x i32>* %out) nounwind { + %wide.load35 = load <4 x i8>* %in, align 1 + %sext = sext <4 x i8> %wide.load35 to <4 x i32> + store <4 x i32> zeroinitializer, <4 x i32>* undef, align 8 + store <4 x i32> %sext, <4 x i32>* %out, align 8 + ret void + +; SSE41: test3: +; SSE41: pmovsxbd + +; AVX1: test3: +; AVX1: vpmovsxbd + +; AVX2: test3: +; AVX2: vpmovsxbd +} + +define void @test4(<8 x i8>* %in, <8 x i32>* %out) nounwind { + %wide.load35 = load <8 x i8>* %in, align 1 + %sext = sext <8 x i8> %wide.load35 to <8 x i32> + store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8 + store <8 x i32> %sext, <8 x i32>* %out, align 8 + ret void + +; AVX2: test4: +; AVX2: vpmovsxbd +} + +define void @test5(<8 x i8>* %in, <8 x i16>* %out) nounwind { + %wide.load35 = load <8 x i8>* %in, align 1 + %sext = sext <8 x i8> %wide.load35 to <8 x i16> + store <8 x i16> zeroinitializer, <8 x i16>* undef, align 8 + store <8 x i16> %sext, <8 x i16>* %out, align 8 + ret void + +; SSE41: test5: +; SSE41: pmovsxbw + +; AVX1: test5: +; AVX1: vpmovsxbw + +; AVX2: test5: +; AVX2: vpmovsxbw +} + +define void @test6(<16 x i8>* %in, <16 x i16>* %out) nounwind { + %wide.load35 = load <16 x i8>* %in, align 1 + %sext = sext <16 x i8> %wide.load35 to <16 x i16> + store <16 x i16> zeroinitializer, <16 x i16>* undef, align 8 + store <16 x i16> %sext, <16 x i16>* %out, align 8 + ret void + +; AVX2: test6: +; FIXME: v16i8 -> v16i16 is scalarized. +; AVX2-NOT: pmovsx +} + +define void @test7(<2 x i16>* %in, <2 x i64>* %out) nounwind { + %wide.load35 = load <2 x i16>* %in, align 1 + %sext = sext <2 x i16> %wide.load35 to <2 x i64> + store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8 + store <2 x i64> %sext, <2 x i64>* %out, align 8 + ret void + + +; SSE41: test7: +; SSE41: pmovsxwq + +; AVX1: test7: +; AVX1: vpmovsxwq + +; AVX2: test7: +; AVX2: vpmovsxwq +} + +define void @test8(<4 x i16>* %in, <4 x i64>* %out) nounwind { + %wide.load35 = load <4 x i16>* %in, align 1 + %sext = sext <4 x i16> %wide.load35 to <4 x i64> + store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8 + store <4 x i64> %sext, <4 x i64>* %out, align 8 + ret void + +; AVX2: test8: +; AVX2: vpmovsxwq +} + +define void @test9(<4 x i16>* %in, <4 x i32>* %out) nounwind { + %wide.load35 = load <4 x i16>* %in, align 1 + %sext = sext <4 x i16> %wide.load35 to <4 x i32> + store <4 x i32> zeroinitializer, <4 x i32>* undef, align 8 + store <4 x i32> %sext, <4 x i32>* %out, align 8 + ret void + +; SSE41: test9: +; SSE41: pmovsxwd + +; AVX1: test9: +; AVX1: vpmovsxwd + +; AVX2: test9: +; AVX2: vpmovsxwd +} + +define void @test10(<8 x i16>* %in, <8 x i32>* %out) nounwind { + %wide.load35 = load <8 x i16>* %in, align 1 + %sext = sext <8 x i16> %wide.load35 to <8 x i32> + store <8 x i32> zeroinitializer, <8 x i32>* undef, align 8 + store <8 x i32> %sext, <8 x i32>* %out, align 8 + ret void + +; AVX2: test10: +; AVX2: vpmovsxwd +} + +define void @test11(<2 x i32>* %in, <2 x i64>* %out) nounwind { + %wide.load35 = load <2 x i32>* %in, align 1 + %sext = sext <2 x i32> %wide.load35 to <2 x i64> + store <2 x i64> zeroinitializer, <2 x i64>* undef, align 8 + store <2 x i64> %sext, <2 x i64>* %out, align 8 + ret void + +; SSE41: test11: +; SSE41: pmovsxdq + +; AVX1: test11: +; AVX1: vpmovsxdq + +; AVX2: test11: +; AVX2: vpmovsxdq +} + +define void @test12(<4 x i32>* %in, <4 x i64>* %out) nounwind { + %wide.load35 = load <4 x i32>* %in, align 1 + %sext = sext <4 x i32> %wide.load35 to <4 x i64> + store <4 x i64> zeroinitializer, <4 x i64>* undef, align 8 + store <4 x i64> %sext, <4 x i64>* %out, align 8 + ret void + +; AVX2: test12: +; AVX2: vpmovsxdq +} diff --git a/test/CodeGen/X86/pointer-vector.ll b/test/CodeGen/X86/pointer-vector.ll index 58423d1959644..0ee99875264f2 100644 --- a/test/CodeGen/X86/pointer-vector.ll +++ b/test/CodeGen/X86/pointer-vector.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 | FileCheck %s -; RUN: opt -instsimplify %s -disable-output +; RUN: opt -instsimplify -disable-output < %s ;CHECK: SHUFF0 define <8 x i32*> @SHUFF0(<4 x i32*> %ptrv) nounwind { diff --git a/test/CodeGen/X86/pr10475.ll b/test/CodeGen/X86/pr10475.ll new file mode 100644 index 0000000000000..3efc39ee9f1ff --- /dev/null +++ b/test/CodeGen/X86/pr10475.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx + +; No check in a crash test + +define void @autogen_262380_1000() { +BB: + br label %CF79 + +CF79: ; preds = %CF79, %BB + br i1 undef, label %CF79, label %CF84.critedge.critedge + +CF84.critedge.critedge: ; preds = %CF79 + %L35 = load <8 x i32>* undef + br label %CF85 + +CF85: ; preds = %CF85, %CF84.critedge.critedge + br i1 undef, label %CF85, label %CF86 + +CF86: ; preds = %CF86, %CF85 + %B61 = sub <8 x i32> %L35, zeroinitializer + %S64 = icmp ne <8 x i32> %B61, zeroinitializer + %E73 = extractelement <8 x i1> %S64, i32 6 + br i1 %E73, label %CF86, label %CF87 + +CF87: ; preds = %CF87, %CF86 + br i1 undef, label %CF87, label %CF88 + +CF88: ; preds = %CF87 + ret void +} diff --git a/test/CodeGen/X86/pr10499.ll b/test/CodeGen/X86/pr10499.ll new file mode 100644 index 0000000000000..f9cc747e49a84 --- /dev/null +++ b/test/CodeGen/X86/pr10499.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx -mattr=-sse2 + +; No check as PR10499 is a crashing bug. + +define void @autogen_24438_500() { +BB: + %I = insertelement <8 x i32> undef, i32 -1, i32 4 + %BC = bitcast <8 x i32> %I to <8 x float> + br label %CF + +CF: ; preds = %CF, %BB + %ZE = fpext <8 x float> %BC to <8 x double> + br label %CF +} diff --git a/test/CodeGen/X86/pr10523.ll b/test/CodeGen/X86/pr10523.ll new file mode 100644 index 0000000000000..7191d6949c183 --- /dev/null +++ b/test/CodeGen/X86/pr10523.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse41 + +; No check in a crash test + +define void @autogen_129334_5000() { +BB: + %I74 = insertelement <32 x i32> undef, i32 undef, i32 15 + %I105 = insertelement <32 x i32> undef, i32 undef, i32 14 + %Shuff292 = shufflevector <32 x i32> %I74, <32 x i32> undef, <32 x i32> <i32 undef, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 undef, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 undef, i32 54, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 2, i32 4, i32 6, i32 8> + %Shuff302 = shufflevector <32 x i32> %Shuff292, <32 x i32> undef, <32 x i32> <i32 27, i32 29, i32 undef, i32 33, i32 undef, i32 37, i32 39, i32 undef, i32 undef, i32 undef, i32 47, i32 undef, i32 51, i32 53, i32 55, i32 57, i32 undef, i32 undef, i32 63, i32 1, i32 undef, i32 undef, i32 undef, i32 9, i32 11, i32 13, i32 undef, i32 17, i32 19, i32 21, i32 23, i32 undef> + %I326 = insertelement <32 x i32> undef, i32 undef, i32 15 + %B338 = sub <32 x i32> zeroinitializer, %I105 + %FC339 = sitofp <32 x i32> %I326 to <32 x double> + %S341 = icmp ne <32 x i32> %B338, undef + %E376 = extractelement <32 x i1> %S341, i32 0 + %Shuff419 = shufflevector <32 x i32> undef, <32 x i32> %Shuff302, <32 x i32> <i32 undef, i32 44, i32 46, i32 48, i32 50, i32 52, i32 undef, i32 56, i32 58, i32 60, i32 62, i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 12, i32 14, i32 undef, i32 undef, i32 20, i32 22, i32 undef, i32 26, i32 28, i32 undef, i32 32, i32 34, i32 36, i32 38, i32 40> + ret void +} diff --git a/test/CodeGen/X86/pr10524.ll b/test/CodeGen/X86/pr10524.ll new file mode 100644 index 0000000000000..ed3e7c5280520 --- /dev/null +++ b/test/CodeGen/X86/pr10524.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse41 + +; No check in a crash test + +define void @autogen_178513_5000() { +BB: + %Shuff22 = shufflevector <2 x i32> undef, <2 x i32> zeroinitializer, <2 x i32> <i32 3, i32 1> + %B26 = sub <2 x i32> %Shuff22, zeroinitializer + %S79 = icmp eq <2 x i32> %B26, zeroinitializer + %B269 = urem <2 x i1> zeroinitializer, %S79 + %Se335 = sext <2 x i1> %B269 to <2 x i8> + store <2 x i8> %Se335, <2 x i8>* undef + ret void +} diff --git a/test/CodeGen/X86/pr10525.ll b/test/CodeGen/X86/pr10525.ll new file mode 100644 index 0000000000000..342c1d63e192b --- /dev/null +++ b/test/CodeGen/X86/pr10525.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse41 + +; No check in a crash test + +define void @autogen_163411_5000() { +BB: + %L = load <2 x i64>* undef + %Shuff11 = shufflevector <2 x i64> %L, <2 x i64> %L, <2 x i32> <i32 2, i32 0> + %I51 = insertelement <2 x i64> undef, i64 undef, i32 0 + %Shuff152 = shufflevector <2 x i64> %I51, <2 x i64> %Shuff11, <2 x i32> <i32 1, i32 3> + store <2 x i64> %Shuff152, <2 x i64>* undef + ret void +} diff --git a/test/CodeGen/X86/pr10526.ll b/test/CodeGen/X86/pr10526.ll new file mode 100644 index 0000000000000..6963fe515898d --- /dev/null +++ b/test/CodeGen/X86/pr10526.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse41 + +; No check in a crash test + +define void @autogen_142660_5000() { +BB: + %Shuff49 = shufflevector <8 x i32> zeroinitializer, <8 x i32> undef, <8 x i32> <i32 2, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 0> + %B85 = sub <8 x i32> %Shuff49, zeroinitializer + %S242 = icmp eq <8 x i32> zeroinitializer, %B85 + %FC284 = uitofp <8 x i1> %S242 to <8 x float> + store <8 x float> %FC284, <8 x float>* undef + ret void +} diff --git a/test/CodeGen/X86/pr11998.ll b/test/CodeGen/X86/pr11998.ll new file mode 100644 index 0000000000000..1baf07924d392 --- /dev/null +++ b/test/CodeGen/X86/pr11998.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mcpu=corei7-avx -march=x86-64 -mattr=+avx + +define void @autogen_51367_5000(i8) { +BB: + %B = srem i8 55, %0 + %B9 = shl i8 %B, %B + br label %CF + +CF: ; preds = %CF, %BB + br i1 undef, label %CF, label %CF403 + +CF403: ; preds = %CF403, %CF + %S44 = icmp eq i8 %B9, %0 + br i1 %S44, label %CF403, label %CF405 + +CF405: ; preds = %CF405, %CF403 + br label %CF405 +} diff --git a/test/CodeGen/X86/pr14314.ll b/test/CodeGen/X86/pr14314.ll index 5388a4b01b656..0832702244e51 100644 --- a/test/CodeGen/X86/pr14314.ll +++ b/test/CodeGen/X86/pr14314.ll @@ -5,9 +5,9 @@ entry: %0 = atomicrmw sub i64* %a, i64 %b seq_cst ret i64 %0 ; CHECK: atomicSub -; movl %eax, %ebx -; subl {{%[a-z]+}}, %ebx -; movl %edx, %ecx -; sbbl {{%[a-z]+}}, %ecx +; CHECK: movl %eax, %ebx +; CHECK: subl {{%[a-z]+}}, %ebx +; CHECK: movl %edx, %ecx +; CHECK: sbbl {{%[a-z]+}}, %ecx ; CHECK: ret } diff --git a/test/CodeGen/X86/pr14562.ll b/test/CodeGen/X86/pr14562.ll new file mode 100644 index 0000000000000..e66f1752a30f8 --- /dev/null +++ b/test/CodeGen/X86/pr14562.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +@temp1 = global i64 -77129852189294865, align 8 + +define void @foo() nounwind { + %x = load i64* @temp1, align 8 + %s = shl i64 %x, 32 + %t = trunc i64 %s to i32 + %z = zext i32 %t to i64 + store i64 %z, i64* @temp1, align 8 +; CHECK: movl $0, {{_?}}temp1+4 +; CHECK: movl $0, {{_?}}temp1 + ret void +} + diff --git a/test/CodeGen/X86/pr15267.ll b/test/CodeGen/X86/pr15267.ll new file mode 100644 index 0000000000000..c8aaf327a7ddf --- /dev/null +++ b/test/CodeGen/X86/pr15267.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s + +define <4 x i3> @test1(<4 x i3>* %in) nounwind { + %ret = load <4 x i3>* %in, align 1 + ret <4 x i3> %ret +} + +; CHECK: test1 +; CHECK: movzwl +; CHECK: shrl $3 +; CHECK: andl $7 +; CHECK: andl $7 +; CHECK: vmovd +; CHECK: pinsrd $1 +; CHECK: shrl $6 +; CHECK: andl $7 +; CHECK: pinsrd $2 +; CHECK: shrl $9 +; CHECK: andl $7 +; CHECK: pinsrd $3 +; CHECK: ret + +define <4 x i1> @test2(<4 x i1>* %in) nounwind { + %ret = load <4 x i1>* %in, align 1 + ret <4 x i1> %ret +} + +; CHECK: test2 +; CHECK: movzbl +; CHECK: shrl +; CHECK: andl $1 +; CHECK: andl $1 +; CHECK: vmovd +; CHECK: pinsrd $1 +; CHECK: shrl $2 +; CHECK: andl $1 +; CHECK: pinsrd $2 +; CHECK: shrl $3 +; CHECK: andl $1 +; CHECK: pinsrd $3 +; CHECK: ret + +define <4 x i64> @test3(<4 x i1>* %in) nounwind { + %wide.load35 = load <4 x i1>* %in, align 1 + %sext = sext <4 x i1> %wide.load35 to <4 x i64> + ret <4 x i64> %sext +} + +; CHECK: test3 +; CHECK: movzbl +; CHECK: shrl +; CHECK: andl $1 +; CHECK: andl $1 +; CHECK: vmovd +; CHECK: pinsrd $1 +; CHECK: shrl $2 +; CHECK: andl $1 +; CHECK: pinsrd $2 +; CHECK: shrl $3 +; CHECK: andl $1 +; CHECK: pinsrd $3 +; CHECK: pslld +; CHECK: psrad +; CHECK: pmovsxdq +; CHECK: pmovsxdq +; CHECK: ret diff --git a/test/CodeGen/X86/pr15296.ll b/test/CodeGen/X86/pr15296.ll new file mode 100644 index 0000000000000..1187d80cdf75c --- /dev/null +++ b/test/CodeGen/X86/pr15296.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -mtriple=i686-pc-linux -mcpu=corei7-avx | FileCheck %s + +define <8 x i32> @shiftInput___vyuunu(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind { +allocas: + %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0 + %smear.1 = insertelement <8 x i32> %smear.0, i32 %shiftval, i32 1 + %smear.2 = insertelement <8 x i32> %smear.1, i32 %shiftval, i32 2 + %smear.3 = insertelement <8 x i32> %smear.2, i32 %shiftval, i32 3 + %smear.4 = insertelement <8 x i32> %smear.3, i32 %shiftval, i32 4 + %smear.5 = insertelement <8 x i32> %smear.4, i32 %shiftval, i32 5 + %smear.6 = insertelement <8 x i32> %smear.5, i32 %shiftval, i32 6 + %smear.7 = insertelement <8 x i32> %smear.6, i32 %shiftval, i32 7 + %bitop = lshr <8 x i32> %input, %smear.7 + ret <8 x i32> %bitop +} + +; CHECK: shiftInput___vyuunu +; CHECK: psrld +; CHECK: psrld +; CHECK: ret + +define <8 x i32> @shiftInput___canonical(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind { +allocas: + %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0 + %smear.7 = shufflevector <8 x i32> %smear.0, <8 x i32> undef, <8 x i32> zeroinitializer + %bitop = lshr <8 x i32> %input, %smear.7 + ret <8 x i32> %bitop +} + +; CHECK: shiftInput___canonical +; CHECK: psrld +; CHECK: psrld +; CHECK: ret + +define <4 x i64> @shiftInput___64in32bitmode(<4 x i64> %input, i64 %shiftval, <4 x i64> %__mask) nounwind { +allocas: + %smear.0 = insertelement <4 x i64> undef, i64 %shiftval, i32 0 + %smear.7 = shufflevector <4 x i64> %smear.0, <4 x i64> undef, <4 x i32> zeroinitializer + %bitop = lshr <4 x i64> %input, %smear.7 + ret <4 x i64> %bitop +} + +; CHECK: shiftInput___64in32bitmode +; CHECK: psrlq +; CHECK: psrlq +; CHECK: ret diff --git a/test/CodeGen/X86/pr15309.ll b/test/CodeGen/X86/pr15309.ll new file mode 100644 index 0000000000000..6dbbc72a7b7a0 --- /dev/null +++ b/test/CodeGen/X86/pr15309.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s + +define void @test_convert_float2_ulong2(<2 x i64>* nocapture %src, <2 x float>* nocapture %dest) noinline { +L.entry: + %0 = getelementptr <2 x i64>* %src, i32 10 + %1 = load <2 x i64>* %0, align 16 + %2 = uitofp <2 x i64> %1 to <2 x float> + %3 = getelementptr <2 x float>* %dest, i32 10 + store <2 x float> %2, <2 x float>* %3, align 8 + ret void +} + +; CHECK: test_convert_float2_ulong2 +; CHECK-NOT: cvtpd2ps +; CHECK: ret diff --git a/test/CodeGen/X86/pr3522.ll b/test/CodeGen/X86/pr3522.ll index d8f37781fc6e3..9f8dc03706687 100644 --- a/test/CodeGen/X86/pr3522.ll +++ b/test/CodeGen/X86/pr3522.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | not grep "instructions sunk" ; PR3522 diff --git a/test/CodeGen/X86/pre-ra-sched.ll b/test/CodeGen/X86/pre-ra-sched.ll new file mode 100644 index 0000000000000..b792ffa09fb94 --- /dev/null +++ b/test/CodeGen/X86/pre-ra-sched.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx -debug-only=pre-RA-sched \ +; RUN: 2>&1 | FileCheck %s +; REQUIRES: asserts +; +; rdar:13279013: pre-RA-sched should not check all interferences and +; repush them on the ready queue after scheduling each instruction. +; +; CHECK: *** List Scheduling +; CHECK: Interfering reg EFLAGS +; CHECK: Repushing +; CHECK: Repushing +; CHECK: Repushing +; CHECK-NOT: Repushing +; CHECK: *** Final schedule +define i32 @test(i8* %pin) #0 { + %g0 = getelementptr inbounds i8* %pin, i64 0 + %l0 = load i8* %g0, align 1 + + %g1a = getelementptr inbounds i8* %pin, i64 1 + %l1a = load i8* %g1a, align 1 + %z1a = zext i8 %l1a to i32 + %g1b = getelementptr inbounds i8* %pin, i64 2 + %l1b = load i8* %g1b, align 1 + %z1b = zext i8 %l1b to i32 + %c1 = icmp ne i8 %l0, 0 + %x1 = xor i32 %z1a, %z1b + %s1 = select i1 %c1, i32 %z1a, i32 %x1 + + %g2a = getelementptr inbounds i8* %pin, i64 3 + %l2a = load i8* %g2a, align 1 + %z2a = zext i8 %l2a to i32 + %g2b = getelementptr inbounds i8* %pin, i64 4 + %l2b = load i8* %g2b, align 1 + %z2b = zext i8 %l2b to i32 + %x2 = xor i32 %z2a, %z2b + %s2 = select i1 %c1, i32 %z2a, i32 %x2 + + %g3a = getelementptr inbounds i8* %pin, i64 5 + %l3a = load i8* %g3a, align 1 + %z3a = zext i8 %l3a to i32 + %g3b = getelementptr inbounds i8* %pin, i64 6 + %l3b = load i8* %g3b, align 1 + %z3b = zext i8 %l3b to i32 + %x3 = xor i32 %z3a, %z3b + %s3 = select i1 %c1, i32 %z3a, i32 %x3 + + %c3 = icmp ne i8 %l1a, 0 + %c4 = icmp ne i8 %l2a, 0 + + %s4 = select i1 %c3, i32 %s1, i32 %s2 + %s5 = select i1 %c4, i32 %s4, i32 %s3 + + ret i32 %s5 +} + +attributes #0 = { nounwind ssp uwtable } diff --git a/test/CodeGen/X86/prefetch.ll b/test/CodeGen/X86/prefetch.ll index ec2f302b14993..efb51913c5c1f 100644 --- a/test/CodeGen/X86/prefetch.ll +++ b/test/CodeGen/X86/prefetch.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s ; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW ; rdar://10538297 @@ -9,10 +10,12 @@ entry: ; CHECK: prefetcht1 ; CHECK: prefetcht0 ; CHECK: prefetchnta +; PRFCHW: prefetchw tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 ) tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 ) tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 ) tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 ) + tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 ) ret void } diff --git a/test/CodeGen/X86/psubus.ll b/test/CodeGen/X86/psubus.ll new file mode 100644 index 0000000000000..aff4afbd2e35d --- /dev/null +++ b/test/CodeGen/X86/psubus.ll @@ -0,0 +1,340 @@ +; RUN: llc -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE2 +; RUN: llc -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1 +; RUN: llc -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +define void @test1(i16* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i16* %head, i64 %index + %1 = bitcast i16* %0 to <8 x i16>* + %2 = load <8 x i16>* %1, align 2 + %3 = icmp slt <8 x i16> %2, zeroinitializer + %4 = xor <8 x i16> %2, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768> + %5 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> zeroinitializer + store <8 x i16> %5, <8 x i16>* %1, align 2 + %index.next = add i64 %index, 8 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: @test1 +; SSE2: psubusw LCPI0_0(%rip), %xmm0 + +; AVX1: @test1 +; AVX1: vpsubusw LCPI0_0(%rip), %xmm0, %xmm0 + +; AVX2: @test1 +; AVX2: vpsubusw LCPI0_0(%rip), %xmm0, %xmm0 +} + +define void @test2(i16* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i16* %head, i64 %index + %1 = bitcast i16* %0 to <8 x i16>* + %2 = load <8 x i16>* %1, align 2 + %3 = icmp ugt <8 x i16> %2, <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766> + %4 = add <8 x i16> %2, <i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767> + %5 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> zeroinitializer + store <8 x i16> %5, <8 x i16>* %1, align 2 + %index.next = add i64 %index, 8 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: @test2 +; SSE2: psubusw LCPI1_0(%rip), %xmm0 + +; AVX1: @test2 +; AVX1: vpsubusw LCPI1_0(%rip), %xmm0, %xmm0 + +; AVX2: @test2 +; AVX2: vpsubusw LCPI1_0(%rip), %xmm0, %xmm0 +} + +define void @test3(i16* nocapture %head, i16 zeroext %w) nounwind { +vector.ph: + %0 = insertelement <8 x i16> undef, i16 %w, i32 0 + %broadcast15 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %1 = getelementptr inbounds i16* %head, i64 %index + %2 = bitcast i16* %1 to <8 x i16>* + %3 = load <8 x i16>* %2, align 2 + %4 = icmp ult <8 x i16> %3, %broadcast15 + %5 = sub <8 x i16> %3, %broadcast15 + %6 = select <8 x i1> %4, <8 x i16> zeroinitializer, <8 x i16> %5 + store <8 x i16> %6, <8 x i16>* %2, align 2 + %index.next = add i64 %index, 8 + %7 = icmp eq i64 %index.next, 16384 + br i1 %7, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: @test3 +; SSE2: psubusw %xmm0, %xmm1 + +; AVX1: @test3 +; AVX1: vpsubusw %xmm0, %xmm1, %xmm1 + +; AVX2: @test3 +; AVX2: vpsubusw %xmm0, %xmm1, %xmm1 +} + +define void @test4(i8* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i8* %head, i64 %index + %1 = bitcast i8* %0 to <16 x i8>* + %2 = load <16 x i8>* %1, align 1 + %3 = icmp slt <16 x i8> %2, zeroinitializer + %4 = xor <16 x i8> %2, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> + %5 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> zeroinitializer + store <16 x i8> %5, <16 x i8>* %1, align 1 + %index.next = add i64 %index, 16 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: @test4 +; SSE2: psubusb LCPI3_0(%rip), %xmm0 + +; AVX1: @test4 +; AVX1: vpsubusb LCPI3_0(%rip), %xmm0, %xmm0 + +; AVX2: @test4 +; AVX2: vpsubusb LCPI3_0(%rip), %xmm0, %xmm0 +} + +define void @test5(i8* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i8* %head, i64 %index + %1 = bitcast i8* %0 to <16 x i8>* + %2 = load <16 x i8>* %1, align 1 + %3 = icmp ugt <16 x i8> %2, <i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126> + %4 = add <16 x i8> %2, <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127> + %5 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> zeroinitializer + store <16 x i8> %5, <16 x i8>* %1, align 1 + %index.next = add i64 %index, 16 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: @test5 +; SSE2: psubusb LCPI4_0(%rip), %xmm0 + +; AVX1: @test5 +; AVX1: vpsubusb LCPI4_0(%rip), %xmm0, %xmm0 + +; AVX2: @test5 +; AVX2: vpsubusb LCPI4_0(%rip), %xmm0, %xmm0 +} + +define void @test6(i8* nocapture %head, i8 zeroext %w) nounwind { +vector.ph: + %0 = insertelement <16 x i8> undef, i8 %w, i32 0 + %broadcast15 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %1 = getelementptr inbounds i8* %head, i64 %index + %2 = bitcast i8* %1 to <16 x i8>* + %3 = load <16 x i8>* %2, align 1 + %4 = icmp ult <16 x i8> %3, %broadcast15 + %5 = sub <16 x i8> %3, %broadcast15 + %6 = select <16 x i1> %4, <16 x i8> zeroinitializer, <16 x i8> %5 + store <16 x i8> %6, <16 x i8>* %2, align 1 + %index.next = add i64 %index, 16 + %7 = icmp eq i64 %index.next, 16384 + br i1 %7, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: @test6 +; SSE2: psubusb %xmm0, %xmm1 + +; AVX1: @test6 +; AVX1: vpsubusb %xmm0, %xmm1, %xmm1 + +; AVX2: @test6 +; AVX2: vpsubusb %xmm0, %xmm1, %xmm1 +} + +define void @test7(i16* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i16* %head, i64 %index + %1 = bitcast i16* %0 to <16 x i16>* + %2 = load <16 x i16>* %1, align 2 + %3 = icmp slt <16 x i16> %2, zeroinitializer + %4 = xor <16 x i16> %2, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768> + %5 = select <16 x i1> %3, <16 x i16> %4, <16 x i16> zeroinitializer + store <16 x i16> %5, <16 x i16>* %1, align 2 + %index.next = add i64 %index, 8 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: @test7 +; AVX2: vpsubusw LCPI6_0(%rip), %ymm0, %ymm0 +} + +define void @test8(i16* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i16* %head, i64 %index + %1 = bitcast i16* %0 to <16 x i16>* + %2 = load <16 x i16>* %1, align 2 + %3 = icmp ugt <16 x i16> %2, <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766> + %4 = add <16 x i16> %2, <i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767, i16 -32767> + %5 = select <16 x i1> %3, <16 x i16> %4, <16 x i16> zeroinitializer + store <16 x i16> %5, <16 x i16>* %1, align 2 + %index.next = add i64 %index, 8 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: @test8 +; AVX2: vpsubusw LCPI7_0(%rip), %ymm0, %ymm0 +} + +define void @test9(i16* nocapture %head, i16 zeroext %w) nounwind { +vector.ph: + %0 = insertelement <16 x i16> undef, i16 %w, i32 0 + %broadcast15 = shufflevector <16 x i16> %0, <16 x i16> undef, <16 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %1 = getelementptr inbounds i16* %head, i64 %index + %2 = bitcast i16* %1 to <16 x i16>* + %3 = load <16 x i16>* %2, align 2 + %4 = icmp ult <16 x i16> %3, %broadcast15 + %5 = sub <16 x i16> %3, %broadcast15 + %6 = select <16 x i1> %4, <16 x i16> zeroinitializer, <16 x i16> %5 + store <16 x i16> %6, <16 x i16>* %2, align 2 + %index.next = add i64 %index, 8 + %7 = icmp eq i64 %index.next, 16384 + br i1 %7, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + + +; AVX2: @test9 +; AVX2: vpsubusw %ymm0, %ymm1, %ymm1 +} + +define void @test10(i8* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i8* %head, i64 %index + %1 = bitcast i8* %0 to <32 x i8>* + %2 = load <32 x i8>* %1, align 1 + %3 = icmp slt <32 x i8> %2, zeroinitializer + %4 = xor <32 x i8> %2, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> + %5 = select <32 x i1> %3, <32 x i8> %4, <32 x i8> zeroinitializer + store <32 x i8> %5, <32 x i8>* %1, align 1 + %index.next = add i64 %index, 16 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + + +; AVX2: @test10 +; AVX2: vpsubusb LCPI9_0(%rip), %ymm0, %ymm0 +} + +define void @test11(i8* nocapture %head) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i8* %head, i64 %index + %1 = bitcast i8* %0 to <32 x i8>* + %2 = load <32 x i8>* %1, align 1 + %3 = icmp ugt <32 x i8> %2, <i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126, i8 126> + %4 = add <32 x i8> %2, <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127> + %5 = select <32 x i1> %3, <32 x i8> %4, <32 x i8> zeroinitializer + store <32 x i8> %5, <32 x i8>* %1, align 1 + %index.next = add i64 %index, 16 + %6 = icmp eq i64 %index.next, 16384 + br i1 %6, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: @test11 +; AVX2: vpsubusb LCPI10_0(%rip), %ymm0, %ymm0 +} + +define void @test12(i8* nocapture %head, i8 zeroext %w) nounwind { +vector.ph: + %0 = insertelement <32 x i8> undef, i8 %w, i32 0 + %broadcast15 = shufflevector <32 x i8> %0, <32 x i8> undef, <32 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %1 = getelementptr inbounds i8* %head, i64 %index + %2 = bitcast i8* %1 to <32 x i8>* + %3 = load <32 x i8>* %2, align 1 + %4 = icmp ult <32 x i8> %3, %broadcast15 + %5 = sub <32 x i8> %3, %broadcast15 + %6 = select <32 x i1> %4, <32 x i8> zeroinitializer, <32 x i8> %5 + store <32 x i8> %6, <32 x i8>* %2, align 1 + %index.next = add i64 %index, 16 + %7 = icmp eq i64 %index.next, 16384 + br i1 %7, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: @test12 +; AVX2: vpsubusb %ymm0, %ymm1, %ymm1 +} diff --git a/test/CodeGen/X86/rdrand.ll b/test/CodeGen/X86/rdrand.ll index e2224a6196769..98f4077763816 100644 --- a/test/CodeGen/X86/rdrand.ll +++ b/test/CodeGen/X86/rdrand.ll @@ -39,7 +39,7 @@ define i32 @_rdrand64_step(i64* %random_val) { %isvalid = extractvalue {i64, i32} %call, 1 ret i32 %isvalid ; CHECK: _rdrand64_step: -; CHECK: rdrandq %r[[T1:[[a-z]+]] +; CHECK: rdrandq %r[[T1:[a-z]+]] ; CHECK: movq %r[[T1]], (%r[[A0]]) ; CHECK: movl $1, %eax ; CHECK: cmovael %e[[T1]], %eax diff --git a/test/CodeGen/X86/rdseed.ll b/test/CodeGen/X86/rdseed.ll new file mode 100644 index 0000000000000..35de7ebf74308 --- /dev/null +++ b/test/CodeGen/X86/rdseed.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=x86-64 -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s + +declare {i16, i32} @llvm.x86.rdseed.16() +declare {i32, i32} @llvm.x86.rdseed.32() +declare {i64, i32} @llvm.x86.rdseed.64() + +define i32 @_rdseed16_step(i16* %random_val) { + %call = call {i16, i32} @llvm.x86.rdseed.16() + %randval = extractvalue {i16, i32} %call, 0 + store i16 %randval, i16* %random_val + %isvalid = extractvalue {i16, i32} %call, 1 + ret i32 %isvalid +; CHECK: _rdseed16_step: +; CHECK: rdseedw %ax +; CHECK: movw %ax, (%r[[A0:di|cx]]) +; CHECK: movzwl %ax, %ecx +; CHECK: movl $1, %eax +; CHECK: cmovael %ecx, %eax +; CHECK: ret +} + +define i32 @_rdseed32_step(i32* %random_val) { + %call = call {i32, i32} @llvm.x86.rdseed.32() + %randval = extractvalue {i32, i32} %call, 0 + store i32 %randval, i32* %random_val + %isvalid = extractvalue {i32, i32} %call, 1 + ret i32 %isvalid +; CHECK: _rdseed32_step: +; CHECK: rdseedl %e[[T0:[a-z]+]] +; CHECK: movl %e[[T0]], (%r[[A0]]) +; CHECK: movl $1, %eax +; CHECK: cmovael %e[[T0]], %eax +; CHECK: ret +} + +define i32 @_rdseed64_step(i64* %random_val) { + %call = call {i64, i32} @llvm.x86.rdseed.64() + %randval = extractvalue {i64, i32} %call, 0 + store i64 %randval, i64* %random_val + %isvalid = extractvalue {i64, i32} %call, 1 + ret i32 %isvalid +; CHECK: _rdseed64_step: +; CHECK: rdseedq %r[[T1:[a-z]+]] +; CHECK: movq %r[[T1]], (%r[[A0]]) +; CHECK: movl $1, %eax +; CHECK: cmovael %e[[T1]], %eax +; CHECK: ret +} diff --git a/test/CodeGen/X86/regpressure.ll b/test/CodeGen/X86/regpressure.ll index 52d7b56f182ec..1f756bee8a9d9 100644 --- a/test/CodeGen/X86/regpressure.ll +++ b/test/CodeGen/X86/regpressure.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ;; Both functions in this testcase should codegen to the same function, and ;; neither of them should require spilling anything to the stack. diff --git a/test/CodeGen/X86/ret-mmx.ll b/test/CodeGen/X86/ret-mmx.ll index 865e147a4a243..778e4722cd953 100644 --- a/test/CodeGen/X86/ret-mmx.ll +++ b/test/CodeGen/X86/ret-mmx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mattr=+mmx,+sse2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mcpu=core2 -mattr=+mmx,+sse2 | FileCheck %s ; rdar://6602459 @g_v1di = external global <1 x i64> diff --git a/test/CodeGen/X86/rip-rel-lea.ll b/test/CodeGen/X86/rip-rel-lea.ll new file mode 100644 index 0000000000000..71dacf60caa1f --- /dev/null +++ b/test/CodeGen/X86/rip-rel-lea.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=PIC64 +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 -relocation-model=pic | FileCheck %s -check-prefix=PICX32 +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=PIC32 + +; Use %rip-relative addressing even in static mode on x86-64, because +; it has a smaller encoding. + +@a = internal global double 3.4 +define double* @foo() nounwind { + %a = getelementptr double* @a, i64 0 + ret double* %a + +; PIC64: leaq a(%rip) +; PICX32: leal a(%rip) +; PIC32: leal a@GOTOFF(%eax) +} diff --git a/test/CodeGen/X86/sandybridge-loads.ll b/test/CodeGen/X86/sandybridge-loads.ll new file mode 100644 index 0000000000000..5a23cf136d852 --- /dev/null +++ b/test/CodeGen/X86/sandybridge-loads.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s + +;CHECK: wideloads +;CHECK: vmovaps +;CHECK: vinsertf128 +;CHECK: vmovaps +;CHECK-NOT: vinsertf128 +;CHECK: ret + +define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp { + %v0 = load <8 x float>* %a, align 16 ; <---- unaligned! + %v1 = load <8 x float>* %b, align 32 ; <---- aligned! + %m0 = fcmp olt <8 x float> %v1, %v0 + %v2 = load <8 x float>* %c, align 32 ; <---- aligned! + %m1 = fcmp olt <8 x float> %v2, %v0 + %mand = and <8 x i1> %m1, %m0 + %r = zext <8 x i1> %mand to <8 x i32> + store <8 x i32> %r, <8 x i32>* undef, align 32 + ret void +} + +; CHECK: widestores +; loads: +; CHECK: vmovaps +; CHECK: vmovaps +; stores: +; CHECK: vmovaps +; CHECK: vextractf128 +; CHECK: vmovaps +;CHECK: ret + +define void @widestores(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp { + %v0 = load <8 x float>* %a, align 32 + %v1 = load <8 x float>* %b, align 32 + store <8 x float> %v0, <8 x float>* %b, align 32 ; <--- aligned + store <8 x float> %v1, <8 x float>* %a, align 16 ; <--- unaligned + ret void +} + diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll index 3bec3acdbf765..09ca07b31a108 100644 --- a/test/CodeGen/X86/select.ll +++ b/test/CodeGen/X86/select.ll @@ -282,7 +282,7 @@ define i32 @test13(i32 %a, i32 %b) nounwind { ; ATOM: test13: ; ATOM: cmpl ; ATOM-NEXT: sbbl -; ATOM-NEXT: ret +; ATOM: ret } define i32 @test14(i32 %a, i32 %b) nounwind { @@ -299,7 +299,7 @@ define i32 @test14(i32 %a, i32 %b) nounwind { ; ATOM: cmpl ; ATOM-NEXT: sbbl ; ATOM-NEXT: notl -; ATOM-NEXT: ret +; ATOM: ret } ; rdar://10961709 diff --git a/test/CodeGen/X86/sext-load.ll b/test/CodeGen/X86/sext-load.ll index c9b39d3a489e2..58c93229a2c0a 100644 --- a/test/CodeGen/X86/sext-load.ll +++ b/test/CodeGen/X86/sext-load.ll @@ -1,9 +1,30 @@ -; RUN: llc < %s -march=x86 | grep movsbl +; RUN: llc < %s -march=x86 | FileCheck %s -define i32 @foo(i32 %X) nounwind { +; When doing sign extension, use the sext-load lowering to take advantage of +; x86's sign extension during loads. +; +; CHECK: test1: +; CHECK: movsbl {{.*}}, %eax +; CHECK-NEXT: ret +define i32 @test1(i32 %X) nounwind { entry: %tmp12 = trunc i32 %X to i8 ; <i8> [#uses=1] %tmp123 = sext i8 %tmp12 to i32 ; <i32> [#uses=1] ret i32 %tmp123 } +; When using a sextload representation, ensure that the sign extension is +; preserved even when removing shifted-out low bits. +; +; CHECK: test2: +; CHECK: movswl {{.*}}, %eax +; CHECK-NEXT: ret +define i32 @test2({i16, [6 x i8]}* %this) { +entry: + %b48 = getelementptr inbounds { i16, [6 x i8] }* %this, i32 0, i32 1 + %cast = bitcast [6 x i8]* %b48 to i48* + %bf.load = load i48* %cast, align 2 + %bf.ashr = ashr i48 %bf.load, 32 + %bf.cast = trunc i48 %bf.ashr to i32 + ret i32 %bf.cast +} diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index 2af355905dc3f..ceb79ea927a1f 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32 -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64 +; RUN: llc < %s -mtriple=i686-linux -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32 +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64 define void @t1(i32 %x) nounwind ssp { entry: diff --git a/test/CodeGen/X86/sincos-opt.ll b/test/CodeGen/X86/sincos-opt.ll new file mode 100644 index 0000000000000..f364d1fc2dc8a --- /dev/null +++ b/test/CodeGen/X86/sincos-opt.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9.0 -mcpu=core2 | FileCheck %s --check-prefix=OSX_SINCOS +; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core2 | FileCheck %s --check-prefix=OSX_NOOPT +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -mcpu=core2 -enable-unsafe-fp-math | FileCheck %s --check-prefix=GNU_SINCOS + +; Combine sin / cos into a single call. +; rdar://13087969 + +define float @test1(float %x) nounwind { +entry: +; GNU_SINCOS: test1: +; GNU_SINCOS: callq sincosf +; GNU_SINCOS: movss 4(%rsp), %xmm0 +; GNU_SINCOS: addss (%rsp), %xmm0 + +; OSX_SINCOS: test1: +; OSX_SINCOS: callq ___sincosf_stret +; OSX_SINCOS: addss %xmm1, %xmm0 + +; OSX_NOOPT: test1 +; OSX_NOOPT: callq _cosf +; OSX_NOOPT: callq _sinf + %call = tail call float @sinf(float %x) nounwind readnone + %call1 = tail call float @cosf(float %x) nounwind readnone + %add = fadd float %call, %call1 + ret float %add +} + +define double @test2(double %x) nounwind { +entry: +; GNU_SINCOS: test2: +; GNU_SINCOS: callq sincos +; GNU_SINCOS: movsd 16(%rsp), %xmm0 +; GNU_SINCOS: addsd 8(%rsp), %xmm0 + +; OSX_SINCOS: test2: +; OSX_SINCOS: callq ___sincos_stret +; OSX_SINCOS: addsd %xmm1, %xmm0 + +; OSX_NOOPT: test2 +; OSX_NOOPT: callq _cos +; OSX_NOOPT: callq _sin + %call = tail call double @sin(double %x) nounwind readnone + %call1 = tail call double @cos(double %x) nounwind readnone + %add = fadd double %call, %call1 + ret double %add +} + +define x86_fp80 @test3(x86_fp80 %x) nounwind { +entry: +; GNU_SINCOS: test3: +; GNU_SINCOS: callq sinl +; GNU_SINCOS: callq cosl +; GNU_SINCOS: ret + %call = tail call x86_fp80 @sinl(x86_fp80 %x) nounwind + %call1 = tail call x86_fp80 @cosl(x86_fp80 %x) nounwind + %add = fadd x86_fp80 %call, %call1 + ret x86_fp80 %add +} + +declare float @sinf(float) readonly +declare double @sin(double) readonly +declare float @cosf(float) readonly +declare double @cos(double) readonly + +declare x86_fp80 @sinl(x86_fp80) +declare x86_fp80 @cosl(x86_fp80) diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 649cd61ab78c6..2aca5b897d357 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true -schedmodel=false | FileCheck %s ; Currently, floating-point selects are lowered to CFG triangles. ; This means that one side of the select is always unconditionally diff --git a/test/CodeGen/X86/sse-align-2.ll b/test/CodeGen/X86/sse-align-2.ll index 102c3fb06cd7e..22cd7723068cb 100644 --- a/test/CodeGen/X86/sse-align-2.ll +++ b/test/CodeGen/X86/sse-align-2.ll @@ -1,12 +1,21 @@ -; RUN: llc < %s -march=x86-64 | grep movup | count 2 +; RUN: llc < %s -march=x86-64 -mcpu=penryn | FileCheck %s define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind { %t = load <4 x float>* %p, align 4 %z = fmul <4 x float> %t, %x ret <4 x float> %z } + +; CHECK: foo: +; CHECK: movups +; CHECK: ret + define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind { %t = load <2 x double>* %p, align 8 %z = fmul <2 x double> %t, %x ret <2 x double> %z } + +; CHECK: bar: +; CHECK: movupd +; CHECK: ret diff --git a/test/CodeGen/X86/sse-domains.ll b/test/CodeGen/X86/sse-domains.ll index c99287bdfb9f5..168959a5d6533 100644 --- a/test/CodeGen/X86/sse-domains.ll +++ b/test/CodeGen/X86/sse-domains.ll @@ -55,10 +55,10 @@ while.end: ; instructions, they are still dependent on themselves. ; CHECK: xorps [[XMM1:%xmm[0-9]+]] ; CHECK: , [[XMM1]] -; CHECK: cvtsi2ss %{{.*}}, [[XMM1]] +; CHECK: cvtsi2ssl %{{.*}}, [[XMM1]] ; CHECK: xorps [[XMM2:%xmm[0-9]+]] ; CHECK: , [[XMM2]] -; CHECK: cvtsi2ss %{{.*}}, [[XMM2]] +; CHECK: cvtsi2ssl %{{.*}}, [[XMM2]] ; define float @f2(i32 %m) nounwind uwtable readnone ssp { entry: diff --git a/test/CodeGen/X86/sse2-blend.ll b/test/CodeGen/X86/sse2-blend.ll index 2f4317bf294c2..30a0fbe7d6deb 100644 --- a/test/CodeGen/X86/sse2-blend.ll +++ b/test/CodeGen/X86/sse2-blend.ll @@ -28,33 +28,29 @@ define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) { ; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_i64 -; CHECK: xorps -; CHECK: andps ; CHECK: andnps ; CHECK: orps ; CHECK: ret -define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) { - %A = load <4 x i64>* %v1 - %B = load <4 x i64>* %v2 - %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %A, <4 x i64> %B - store <4 x i64 > %vsel, <4 x i64>* %v1 +define void@vsel_i64(<2 x i64>* %v1, <2 x i64>* %v2) { + %A = load <2 x i64>* %v1 + %B = load <2 x i64>* %v2 + %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %A, <2 x i64> %B + store <2 x i64 > %vsel, <2 x i64>* %v1 ret void } ; Without forcing instructions, fall back to the preferred PS domain. ; CHECK: vsel_double -; CHECK: xorps -; CHECK: andps ; CHECK: andnps ; CHECK: orps ; CHECK: ret -define void@vsel_double(<4 x double>* %v1, <4 x double>* %v2) { - %A = load <4 x double>* %v1 - %B = load <4 x double>* %v2 - %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %A, <4 x double> %B - store <4 x double > %vsel, <4 x double>* %v1 +define void@vsel_double(<2 x double>* %v1, <2 x double>* %v2) { + %A = load <2 x double>* %v1 + %B = load <2 x double>* %v2 + %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %A, <2 x double> %B + store <2 x double > %vsel, <2 x double>* %v1 ret void } diff --git a/test/CodeGen/X86/sse2-mul.ll b/test/CodeGen/X86/sse2-mul.ll new file mode 100644 index 0000000000000..0466d60ec3015 --- /dev/null +++ b/test/CodeGen/X86/sse2-mul.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s + +define <4 x i32> @test1(<4 x i32> %x, <4 x i32> %y) { + %m = mul <4 x i32> %x, %y + ret <4 x i32> %m +; CHECK: test1: +; CHECK: pshufd $49 +; CHECK: pmuludq +; CHECK: pshufd $49 +; CHECK: pmuludq +; CHECK: shufps $-120 +; CHECK: pshufd $-40 +; CHECK: ret +} diff --git a/test/CodeGen/X86/stack-align-memcpy.ll b/test/CodeGen/X86/stack-align-memcpy.ll new file mode 100644 index 0000000000000..74945e5bb1bdf --- /dev/null +++ b/test/CodeGen/X86/stack-align-memcpy.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -force-align-stack -mtriple i386-apple-darwin -mcpu=i486 | FileCheck %s + +%struct.foo = type { [88 x i8] } + +; PR15249 +; We can't use rep;movsl here because it clobbers the base pointer in %esi. +define void @test1(%struct.foo* nocapture %x, i32 %y) nounwind { + %dynalloc = alloca i8, i32 %y, align 1 + call void @bar(i8* %dynalloc, %struct.foo* align 4 byval %x) + ret void + +; CHECK: test1: +; CHECK: andl $-16, %esp +; CHECK: movl %esp, %esi +; CHECK-NOT: rep;movsl +} + +declare void @bar(i8* nocapture, %struct.foo* align 4 byval) nounwind diff --git a/test/CodeGen/X86/stack-protector.ll b/test/CodeGen/X86/stack-protector.ll index c07511443bceb..1e9ca1d2c24d8 100644 --- a/test/CodeGen/X86/stack-protector.ll +++ b/test/CodeGen/X86/stack-protector.ll @@ -1,28 +1,3141 @@ -; RUN: llc -mtriple=i386-pc-linux-gnu < %s -o - | grep %gs: -; RUN: llc -mtriple=x86_64-pc-linux-gnu < %s -o - | grep %fs: -; RUN: llc -code-model=kernel -mtriple=x86_64-pc-linux-gnu < %s -o - | grep %gs: -; RUN: llc -mtriple=x86_64-apple-darwin < %s -o - | grep "__stack_chk_guard" -; RUN: llc -mtriple=x86_64-apple-darwin < %s -o - | grep "__stack_chk_fail" +; RUN: llc -mtriple=i386-pc-linux-gnu < %s -o - | FileCheck --check-prefix=LINUX-I386 %s +; RUN: llc -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck --check-prefix=LINUX-X64 %s +; RUN: llc -code-model=kernel -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck --check-prefix=LINUX-KERNEL-X64 %s +; RUN: llc -mtriple=x86_64-apple-darwin < %s -o - | FileCheck --check-prefix=DARWIN-X64 %s -@"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00" ; <[11 x i8]*> [#uses=1] +%struct.foo = type { [16 x i8] } +%struct.foo.0 = type { [4 x i8] } +%struct.pair = type { i32, i32 } +%struct.nest = type { %struct.pair, %struct.pair } +%struct.vec = type { <4 x i32> } +%class.A = type { [2 x i8] } +%struct.deep = type { %union.anon } +%union.anon = type { %struct.anon } +%struct.anon = type { %struct.anon.0 } +%struct.anon.0 = type { %union.anon.1 } +%union.anon.1 = type { [2 x i8] } +%struct.small = type { i8 } -define void @test(i8* %a) nounwind ssp { +@.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1 + +; test1a: array of [16 x i8] +; no ssp attribute +; Requires no protector. +define void @test1a(i8* %a) nounwind uwtable { +entry: +; LINUX-I386: test1a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test1a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test1a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test1a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + %buf = alloca [16 x i8], align 16 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test1b: array of [16 x i8] +; ssp attribute +; Requires protector. +define void @test1b(i8* %a) nounwind uwtable ssp { +entry: +; LINUX-I386: test1b: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test1b: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test1b: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test1b: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %buf = alloca [16 x i8], align 16 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test1c: array of [16 x i8] +; sspstrong attribute +; Requires protector. +define void @test1c(i8* %a) nounwind uwtable sspstrong { +entry: +; LINUX-I386: test1c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test1c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test1c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test1c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %buf = alloca [16 x i8], align 16 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test1d: array of [16 x i8] +; sspreq attribute +; Requires protector. +define void @test1d(i8* %a) nounwind uwtable sspreq { +entry: +; LINUX-I386: test1d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test1d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test1d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test1d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %buf = alloca [16 x i8], align 16 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test2a: struct { [16 x i8] } +; no ssp attribute +; Requires no protector. +define void @test2a(i8* %a) nounwind uwtable { +entry: +; LINUX-I386: test2a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test2a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test2a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test2a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test2b: struct { [16 x i8] } +; ssp attribute +; Requires protector. +define void @test2b(i8* %a) nounwind uwtable ssp { +entry: +; LINUX-I386: test2b: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test2b: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test2b: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test2b: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test2c: struct { [16 x i8] } +; sspstrong attribute +; Requires protector. +define void @test2c(i8* %a) nounwind uwtable sspstrong { +entry: +; LINUX-I386: test2c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test2c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test2c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test2c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test2d: struct { [16 x i8] } +; sspreq attribute +; Requires protector. +define void @test2d(i8* %a) nounwind uwtable sspreq { +entry: +; LINUX-I386: test2d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test2d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test2d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test2d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [16 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [16 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test3a: array of [4 x i8] +; no ssp attribute +; Requires no protector. +define void @test3a(i8* %a) nounwind uwtable { +entry: +; LINUX-I386: test3a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test3a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test3a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test3a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + %buf = alloca [4 x i8], align 1 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test3b: array [4 x i8] +; ssp attribute +; Requires no protector. +define void @test3b(i8* %a) nounwind uwtable ssp { +entry: +; LINUX-I386: test3b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test3b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test3b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test3b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + %buf = alloca [4 x i8], align 1 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test3c: array of [4 x i8] +; sspstrong attribute +; Requires protector. +define void @test3c(i8* %a) nounwind uwtable sspstrong { +entry: +; LINUX-I386: test3c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test3c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test3c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test3c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %buf = alloca [4 x i8], align 1 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test3d: array of [4 x i8] +; sspreq attribute +; Requires protector. +define void @test3d(i8* %a) nounwind uwtable sspreq { +entry: +; LINUX-I386: test3d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test3d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test3d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test3d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %buf = alloca [4 x i8], align 1 + store i8* %a, i8** %a.addr, align 8 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %arraydecay1 = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay1) + ret void +} + +; test4a: struct { [4 x i8] } +; no ssp attribute +; Requires no protector. +define void @test4a(i8* %a) nounwind uwtable { +entry: +; LINUX-I386: test4a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test4a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test4a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test4a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo.0, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test4b: struct { [4 x i8] } +; ssp attribute +; Requires no protector. +define void @test4b(i8* %a) nounwind uwtable ssp { +entry: +; LINUX-I386: test4b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test4b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test4b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test4b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo.0, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test4c: struct { [4 x i8] } +; sspstrong attribute +; Requires protector. +define void @test4c(i8* %a) nounwind uwtable sspstrong { +entry: +; LINUX-I386: test4c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test4c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test4c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test4c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo.0, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test4d: struct { [4 x i8] } +; sspreq attribute +; Requires protector. +define void @test4d(i8* %a) nounwind uwtable sspreq { +entry: +; LINUX-I386: test4d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test4d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test4d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test4d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + %b = alloca %struct.foo.0, align 1 + store i8* %a, i8** %a.addr, align 8 + %buf = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay = getelementptr inbounds [4 x i8]* %buf, i32 0, i32 0 + %0 = load i8** %a.addr, align 8 + %call = call i8* @strcpy(i8* %arraydecay, i8* %0) + %buf1 = getelementptr inbounds %struct.foo.0* %b, i32 0, i32 0 + %arraydecay2 = getelementptr inbounds [4 x i8]* %buf1, i32 0, i32 0 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %arraydecay2) + ret void +} + +; test5a: no arrays / no nested arrays +; no ssp attribute +; Requires no protector. +define void @test5a(i8* %a) nounwind uwtable { +entry: +; LINUX-I386: test5a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test5a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test5a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test5a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + store i8* %a, i8** %a.addr, align 8 + %0 = load i8** %a.addr, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0) + ret void +} + +; test5b: no arrays / no nested arrays +; ssp attribute +; Requires no protector. +define void @test5b(i8* %a) nounwind uwtable ssp { +entry: +; LINUX-I386: test5b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test5b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test5b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test5b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + store i8* %a, i8** %a.addr, align 8 + %0 = load i8** %a.addr, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0) + ret void +} + +; test5c: no arrays / no nested arrays +; sspstrong attribute +; Requires no protector. +define void @test5c(i8* %a) nounwind uwtable sspstrong { +entry: +; LINUX-I386: test5c: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test5c: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test5c: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test5c: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a.addr = alloca i8*, align 8 + store i8* %a, i8** %a.addr, align 8 + %0 = load i8** %a.addr, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0) + ret void +} + +; test5d: no arrays / no nested arrays +; sspreq attribute +; Requires protector. +define void @test5d(i8* %a) nounwind uwtable sspreq { +entry: +; LINUX-I386: test5d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test5d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test5d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test5d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a.addr = alloca i8*, align 8 + store i8* %a, i8** %a.addr, align 8 + %0 = load i8** %a.addr, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* %0) + ret void +} + +; test6a: Address-of local taken (j = &a) +; no ssp attribute +; Requires no protector. +define void @test6a() nounwind uwtable { +entry: +; LINUX-I386: test6a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test6a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test6a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test6a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %j = alloca i32*, align 8 + store i32 0, i32* %retval + %0 = load i32* %a, align 4 + %add = add nsw i32 %0, 1 + store i32 %add, i32* %a, align 4 + store i32* %a, i32** %j, align 8 + ret void +} + +; test6b: Address-of local taken (j = &a) +; ssp attribute +; Requires no protector. +define void @test6b() nounwind uwtable ssp { +entry: +; LINUX-I386: test6b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test6b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test6b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test6b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %j = alloca i32*, align 8 + store i32 0, i32* %retval + %0 = load i32* %a, align 4 + %add = add nsw i32 %0, 1 + store i32 %add, i32* %a, align 4 + store i32* %a, i32** %j, align 8 + ret void +} + +; test6c: Address-of local taken (j = &a) +; sspstrong attribute +; Requires protector. +define void @test6c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test6c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test6c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test6c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test6c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %j = alloca i32*, align 8 + store i32 0, i32* %retval + %0 = load i32* %a, align 4 + %add = add nsw i32 %0, 1 + store i32 %add, i32* %a, align 4 + store i32* %a, i32** %j, align 8 + ret void +} + +; test6d: Address-of local taken (j = &a) +; sspreq attribute +; Requires protector. +define void @test6d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test6d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test6d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test6d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test6d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %j = alloca i32*, align 8 + store i32 0, i32* %retval + %0 = load i32* %a, align 4 + %add = add nsw i32 %0, 1 + store i32 %add, i32* %a, align 4 + store i32* %a, i32** %j, align 8 + ret void +} + +; test7a: PtrToInt Cast +; no ssp attribute +; Requires no protector. +define void @test7a() nounwind uwtable readnone { +entry: +; LINUX-I386: test7a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test7a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test7a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test7a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %0 = ptrtoint i32* %a to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test7b: PtrToInt Cast +; ssp attribute +; Requires no protector. +define void @test7b() nounwind uwtable readnone ssp { +entry: +; LINUX-I386: test7b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test7b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test7b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test7b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %0 = ptrtoint i32* %a to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test7c: PtrToInt Cast +; sspstrong attribute +; Requires protector. +define void @test7c() nounwind uwtable readnone sspstrong { +entry: +; LINUX-I386: test7c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test7c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test7c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test7c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %0 = ptrtoint i32* %a to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test7d: PtrToInt Cast +; sspreq attribute +; Requires protector. +define void @test7d() nounwind uwtable readnone sspreq { +entry: +; LINUX-I386: test7d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test7d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test7d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test7d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %0 = ptrtoint i32* %a to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test8a: Passing addr-of to function call +; no ssp attribute +; Requires no protector. +define void @test8a() nounwind uwtable { +entry: +; LINUX-I386: test8a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test8a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test8a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test8a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %b = alloca i32, align 4 + call void @funcall(i32* %b) nounwind + ret void +} + +; test8b: Passing addr-of to function call +; ssp attribute +; Requires no protector. +define void @test8b() nounwind uwtable ssp { +entry: +; LINUX-I386: test8b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test8b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test8b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test8b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %b = alloca i32, align 4 + call void @funcall(i32* %b) nounwind + ret void +} + +; test8c: Passing addr-of to function call +; sspstrong attribute +; Requires protector. +define void @test8c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test8c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test8c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test8c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test8c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %b = alloca i32, align 4 + call void @funcall(i32* %b) nounwind + ret void +} + +; test8d: Passing addr-of to function call +; sspreq attribute +; Requires protector. +define void @test8d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test8d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test8d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test8d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test8d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %b = alloca i32, align 4 + call void @funcall(i32* %b) nounwind + ret void +} + +; test9a: Addr-of in select instruction +; no ssp attribute +; Requires no protector. +define void @test9a() nounwind uwtable { +entry: +; LINUX-I386: test9a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test9a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test9a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test9a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp2 = fcmp ogt double %call, 0.000000e+00 + %y.1 = select i1 %cmp2, double* %x, double* null + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1) + ret void +} + +; test9b: Addr-of in select instruction +; ssp attribute +; Requires no protector. +define void @test9b() nounwind uwtable ssp { +entry: +; LINUX-I386: test9b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test9b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test9b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test9b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp2 = fcmp ogt double %call, 0.000000e+00 + %y.1 = select i1 %cmp2, double* %x, double* null + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1) + ret void +} + +; test9c: Addr-of in select instruction +; sspstrong attribute +; Requires protector. +define void @test9c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test9c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test9c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test9c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test9c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp2 = fcmp ogt double %call, 0.000000e+00 + %y.1 = select i1 %cmp2, double* %x, double* null + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1) + ret void +} + +; test9d: Addr-of in select instruction +; sspreq attribute +; Requires protector. +define void @test9d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test9d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test9d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test9d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test9d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp2 = fcmp ogt double %call, 0.000000e+00 + %y.1 = select i1 %cmp2, double* %x, double* null + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), double* %y.1) + ret void +} + +; test10a: Addr-of in phi instruction +; no ssp attribute +; Requires no protector. +define void @test10a() nounwind uwtable { +entry: +; LINUX-I386: test10a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test10a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test10a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test10a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp = fcmp ogt double %call, 3.140000e+00 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + %call1 = call double @testi_aux() nounwind + store double %call1, double* %x, align 8 + br label %if.end4 + +if.else: ; preds = %entry + %cmp2 = fcmp ogt double %call, 1.000000e+00 + br i1 %cmp2, label %if.then3, label %if.end4 + +if.then3: ; preds = %if.else + br label %if.end4 + +if.end4: ; preds = %if.else, %if.then3, %if.then + %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ] + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0) nounwind + ret void +} + +; test10b: Addr-of in phi instruction +; ssp attribute +; Requires no protector. +define void @test10b() nounwind uwtable ssp { +entry: +; LINUX-I386: test10b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test10b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test10b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test10b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp = fcmp ogt double %call, 3.140000e+00 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + %call1 = call double @testi_aux() nounwind + store double %call1, double* %x, align 8 + br label %if.end4 + +if.else: ; preds = %entry + %cmp2 = fcmp ogt double %call, 1.000000e+00 + br i1 %cmp2, label %if.then3, label %if.end4 + +if.then3: ; preds = %if.else + br label %if.end4 + +if.end4: ; preds = %if.else, %if.then3, %if.then + %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ] + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0) nounwind + ret void +} + +; test10c: Addr-of in phi instruction +; sspstrong attribute +; Requires protector. +define void @test10c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test10c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test10c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test10c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test10c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp = fcmp ogt double %call, 3.140000e+00 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + %call1 = call double @testi_aux() nounwind + store double %call1, double* %x, align 8 + br label %if.end4 + +if.else: ; preds = %entry + %cmp2 = fcmp ogt double %call, 1.000000e+00 + br i1 %cmp2, label %if.then3, label %if.end4 + +if.then3: ; preds = %if.else + br label %if.end4 + +if.end4: ; preds = %if.else, %if.then3, %if.then + %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ] + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0) nounwind + ret void +} + +; test10d: Addr-of in phi instruction +; sspreq attribute +; Requires protector. +define void @test10d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test10d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test10d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test10d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test10d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %x = alloca double, align 8 + %call = call double @testi_aux() nounwind + store double %call, double* %x, align 8 + %cmp = fcmp ogt double %call, 3.140000e+00 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + %call1 = call double @testi_aux() nounwind + store double %call1, double* %x, align 8 + br label %if.end4 + +if.else: ; preds = %entry + %cmp2 = fcmp ogt double %call, 1.000000e+00 + br i1 %cmp2, label %if.then3, label %if.end4 + +if.then3: ; preds = %if.else + br label %if.end4 + +if.end4: ; preds = %if.else, %if.then3, %if.then + %y.0 = phi double* [ null, %if.then ], [ %x, %if.then3 ], [ null, %if.else ] + %call5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), double* %y.0) nounwind + ret void +} + +; test11a: Addr-of struct element. (GEP followed by store). +; no ssp attribute +; Requires no protector. +define void @test11a() nounwind uwtable { +entry: +; LINUX-I386: test11a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test11a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test11a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test11a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + store i32* %y, i32** %b, align 8 + %0 = load i32** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0) + ret void +} + +; test11b: Addr-of struct element. (GEP followed by store). +; ssp attribute +; Requires no protector. +define void @test11b() nounwind uwtable ssp { +entry: +; LINUX-I386: test11b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test11b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test11b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test11b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + store i32* %y, i32** %b, align 8 + %0 = load i32** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0) + ret void +} + +; test11c: Addr-of struct element. (GEP followed by store). +; sspstrong attribute +; Requires protector. +define void @test11c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test11c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test11c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test11c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test11c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + store i32* %y, i32** %b, align 8 + %0 = load i32** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0) + ret void +} + +; test11d: Addr-of struct element. (GEP followed by store). +; sspreq attribute +; Requires protector. +define void @test11d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test11d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test11d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test11d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test11d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + store i32* %y, i32** %b, align 8 + %0 = load i32** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32* %0) + ret void +} + +; test12a: Addr-of struct element, GEP followed by ptrtoint. +; no ssp attribute +; Requires no protector. +define void @test12a() nounwind uwtable { +entry: +; LINUX-I386: test12a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test12a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test12a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test12a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + %0 = ptrtoint i32* %y to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test12b: Addr-of struct element, GEP followed by ptrtoint. +; ssp attribute +; Requires no protector. +define void @test12b() nounwind uwtable ssp { +entry: +; LINUX-I386: test12b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test12b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test12b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test12b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + %0 = ptrtoint i32* %y to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test12c: Addr-of struct element, GEP followed by ptrtoint. +; sspstrong attribute +; Requires protector. +define void @test12c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test12c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test12c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test12c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test12c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + %0 = ptrtoint i32* %y to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test12d: Addr-of struct element, GEP followed by ptrtoint. +; sspreq attribute +; Requires protector. +define void @test12d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test12d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test12d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test12d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test12d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %b = alloca i32*, align 8 + %y = getelementptr inbounds %struct.pair* %c, i32 0, i32 1 + %0 = ptrtoint i32* %y to i64 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i64 %0) + ret void +} + +; test13a: Addr-of struct element, GEP followed by callinst. +; no ssp attribute +; Requires no protector. +define void @test13a() nounwind uwtable { +entry: +; LINUX-I386: test13a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test13a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test13a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test13a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y) nounwind + ret void +} + +; test13b: Addr-of struct element, GEP followed by callinst. +; ssp attribute +; Requires no protector. +define void @test13b() nounwind uwtable ssp { +entry: +; LINUX-I386: test13b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test13b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test13b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test13b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y) nounwind + ret void +} + +; test13c: Addr-of struct element, GEP followed by callinst. +; sspstrong attribute +; Requires protector. +define void @test13c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test13c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test13c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test13c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test13c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y) nounwind + ret void +} + +; test13d: Addr-of struct element, GEP followed by callinst. +; sspreq attribute +; Requires protector. +define void @test13d() nounwind uwtable sspreq { entry: - %a_addr = alloca i8* ; <i8**> [#uses=2] - %buf = alloca [8 x i8] ; <[8 x i8]*> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i8* %a, i8** %a_addr - %buf1 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] - %0 = load i8** %a_addr, align 4 ; <i8*> [#uses=1] - %1 = call i8* @strcpy(i8* %buf1, i8* %0) nounwind ; <i8*> [#uses=0] - %buf2 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1] - %2 = call i32 (i8*, ...)* @printf(i8* getelementptr ([11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind ; <i32> [#uses=0] - br label %return +; LINUX-I386: test13d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test13d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail -return: ; preds = %entry - ret void +; LINUX-KERNEL-X64: test13d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test13d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %y = getelementptr inbounds %struct.pair* %c, i64 0, i32 1 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %y) nounwind + ret void } -declare i8* @strcpy(i8*, i8*) nounwind +; test14a: Addr-of a local, optimized into a GEP (e.g., &a - 12) +; no ssp attribute +; Requires no protector. +define void @test14a() nounwind uwtable { +entry: +; LINUX-I386: test14a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test14a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test14a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test14a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %add.ptr5 = getelementptr inbounds i32* %a, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5) nounwind + ret void +} + +; test14b: Addr-of a local, optimized into a GEP (e.g., &a - 12) +; ssp attribute +; Requires no protector. +define void @test14b() nounwind uwtable ssp { +entry: +; LINUX-I386: test14b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test14b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test14b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test14b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %add.ptr5 = getelementptr inbounds i32* %a, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5) nounwind + ret void +} + +; test14c: Addr-of a local, optimized into a GEP (e.g., &a - 12) +; sspstrong attribute +; Requires protector. +define void @test14c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test14c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test14c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test14c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test14c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %add.ptr5 = getelementptr inbounds i32* %a, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5) nounwind + ret void +} + +; test14d: Addr-of a local, optimized into a GEP (e.g., &a - 12) +; sspreq attribute +; Requires protector. +define void @test14d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test14d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test14d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test14d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test14d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %add.ptr5 = getelementptr inbounds i32* %a, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32* %add.ptr5) nounwind + ret void +} + +; test15a: Addr-of a local cast to a ptr of a different type +; (e.g., int a; ... ; float *b = &a;) +; no ssp attribute +; Requires no protector. +define void @test15a() nounwind uwtable { +entry: +; LINUX-I386: test15a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test15a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test15a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test15a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %b = alloca float*, align 8 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + store float* %0, float** %b, align 8 + %1 = load float** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1) + ret void +} + +; test15b: Addr-of a local cast to a ptr of a different type +; (e.g., int a; ... ; float *b = &a;) +; ssp attribute +; Requires no protector. +define void @test15b() nounwind uwtable ssp { +entry: +; LINUX-I386: test15b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test15b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test15b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test15b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %b = alloca float*, align 8 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + store float* %0, float** %b, align 8 + %1 = load float** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1) + ret void +} + +; test15c: Addr-of a local cast to a ptr of a different type +; (e.g., int a; ... ; float *b = &a;) +; sspstrong attribute +; Requires protector. +define void @test15c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test15c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test15c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test15c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test15c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %b = alloca float*, align 8 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + store float* %0, float** %b, align 8 + %1 = load float** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1) + ret void +} + +; test15d: Addr-of a local cast to a ptr of a different type +; (e.g., int a; ... ; float *b = &a;) +; sspreq attribute +; Requires protector. +define void @test15d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test15d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test15d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test15d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test15d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %b = alloca float*, align 8 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + store float* %0, float** %b, align 8 + %1 = load float** %b, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), float* %1) + ret void +} + +; test16a: Addr-of a local cast to a ptr of a different type (optimized) +; (e.g., int a; ... ; float *b = &a;) +; no ssp attribute +; Requires no protector. +define void @test16a() nounwind uwtable { +entry: +; LINUX-I386: test16a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test16a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test16a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test16a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + call void @funfloat(float* %0) nounwind + ret void +} + +; test16b: Addr-of a local cast to a ptr of a different type (optimized) +; (e.g., int a; ... ; float *b = &a;) +; ssp attribute +; Requires no protector. +define void @test16b() nounwind uwtable ssp { +entry: +; LINUX-I386: test16b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test16b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test16b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test16b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + call void @funfloat(float* %0) nounwind + ret void +} + +; test16c: Addr-of a local cast to a ptr of a different type (optimized) +; (e.g., int a; ... ; float *b = &a;) +; sspstrong attribute +; Requires protector. +define void @test16c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test16c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test16c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test16c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test16c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + call void @funfloat(float* %0) nounwind + ret void +} + +; test16d: Addr-of a local cast to a ptr of a different type (optimized) +; (e.g., int a; ... ; float *b = &a;) +; sspreq attribute +; Requires protector. +define void @test16d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test16d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test16d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test16d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test16d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + store i32 0, i32* %a, align 4 + %0 = bitcast i32* %a to float* + call void @funfloat(float* %0) nounwind + ret void +} + +; test17a: Addr-of a vector nested in a struct +; no ssp attribute +; Requires no protector. +define void @test17a() nounwind uwtable { +entry: +; LINUX-I386: test17a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test17a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test17a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test17a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.vec, align 16 + %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0 + %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr) nounwind + ret void +} + +; test17b: Addr-of a vector nested in a struct +; ssp attribute +; Requires no protector. +define void @test17b() nounwind uwtable ssp { +entry: +; LINUX-I386: test17b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test17b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test17b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test17b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.vec, align 16 + %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0 + %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr) nounwind + ret void +} + +; test17c: Addr-of a vector nested in a struct +; sspstrong attribute +; Requires protector. +define void @test17c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test17c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test17c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test17c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test17c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.vec, align 16 + %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0 + %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr) nounwind + ret void +} + +; test17d: Addr-of a vector nested in a struct +; sspreq attribute +; Requires protector. +define void @test17d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test17d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test17d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test17d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test17d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.vec, align 16 + %y = getelementptr inbounds %struct.vec* %c, i64 0, i32 0 + %add.ptr = getelementptr inbounds <4 x i32>* %y, i64 -12 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), <4 x i32>* %add.ptr) nounwind + ret void +} + +; test18a: Addr-of a variable passed into an invoke instruction. +; no ssp attribute +; Requires no protector. +define i32 @test18a() uwtable { +entry: +; LINUX-I386: test18a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test18a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test18a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test18a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + store i32 0, i32* %a, align 4 + invoke void @_Z3exceptPi(i32* %a) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test18b: Addr-of a variable passed into an invoke instruction. +; ssp attribute +; Requires no protector. +define i32 @test18b() uwtable ssp { +entry: +; LINUX-I386: test18b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test18b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test18b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test18b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + store i32 0, i32* %a, align 4 + invoke void @_Z3exceptPi(i32* %a) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test18c: Addr-of a variable passed into an invoke instruction. +; sspstrong attribute +; Requires protector. +define i32 @test18c() uwtable sspstrong { +entry: +; LINUX-I386: test18c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test18c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test18c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test18c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + store i32 0, i32* %a, align 4 + invoke void @_Z3exceptPi(i32* %a) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test18d: Addr-of a variable passed into an invoke instruction. +; sspreq attribute +; Requires protector. +define i32 @test18d() uwtable sspreq { +entry: +; LINUX-I386: test18d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test18d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test18d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test18d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + store i32 0, i32* %a, align 4 + invoke void @_Z3exceptPi(i32* %a) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test19a: Addr-of a struct element passed into an invoke instruction. +; (GEP followed by an invoke) +; no ssp attribute +; Requires no protector. +define i32 @test19a() uwtable { +entry: +; LINUX-I386: test19a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test19a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test19a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test19a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + store i32 0, i32* %a, align 4 + %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + invoke void @_Z3exceptPi(i32* %a1) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test19b: Addr-of a struct element passed into an invoke instruction. +; (GEP followed by an invoke) +; ssp attribute +; Requires no protector. +define i32 @test19b() uwtable ssp { +entry: +; LINUX-I386: test19b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test19b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test19b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test19b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.pair, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + store i32 0, i32* %a, align 4 + %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + invoke void @_Z3exceptPi(i32* %a1) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test19c: Addr-of a struct element passed into an invoke instruction. +; (GEP followed by an invoke) +; sspstrong attribute +; Requires protector. +define i32 @test19c() uwtable sspstrong { +entry: +; LINUX-I386: test19c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test19c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test19c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test19c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + store i32 0, i32* %a, align 4 + %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + invoke void @_Z3exceptPi(i32* %a1) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test19d: Addr-of a struct element passed into an invoke instruction. +; (GEP followed by an invoke) +; sspreq attribute +; Requires protector. +define i32 @test19d() uwtable sspreq { +entry: +; LINUX-I386: test19d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test19d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test19d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test19d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %c = alloca %struct.pair, align 4 + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %a = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + store i32 0, i32* %a, align 4 + %a1 = getelementptr inbounds %struct.pair* %c, i32 0, i32 0 + invoke void @_Z3exceptPi(i32* %a1) + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret i32 0 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* null + ret i32 0 +} + +; test20a: Addr-of a pointer +; no ssp attribute +; Requires no protector. +define void @test20a() nounwind uwtable { +entry: +; LINUX-I386: test20a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test20a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test20a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test20a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32*, align 8 + %b = alloca i32**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + store i32** %a, i32*** %b, align 8 + %0 = load i32*** %b, align 8 + call void @funcall2(i32** %0) + ret void +} + +; test20b: Addr-of a pointer +; ssp attribute +; Requires no protector. +define void @test20b() nounwind uwtable ssp { +entry: +; LINUX-I386: test20b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test20b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test20b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test20b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32*, align 8 + %b = alloca i32**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + store i32** %a, i32*** %b, align 8 + %0 = load i32*** %b, align 8 + call void @funcall2(i32** %0) + ret void +} + +; test20c: Addr-of a pointer +; sspstrong attribute +; Requires protector. +define void @test20c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test20c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test20c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test20c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test20c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32*, align 8 + %b = alloca i32**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + store i32** %a, i32*** %b, align 8 + %0 = load i32*** %b, align 8 + call void @funcall2(i32** %0) + ret void +} + +; test20d: Addr-of a pointer +; sspreq attribute +; Requires protector. +define void @test20d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test20d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test20d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test20d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test20d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32*, align 8 + %b = alloca i32**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + store i32** %a, i32*** %b, align 8 + %0 = load i32*** %b, align 8 + call void @funcall2(i32** %0) + ret void +} + +; test21a: Addr-of a casted pointer +; no ssp attribute +; Requires no protector. +define void @test21a() nounwind uwtable { +entry: +; LINUX-I386: test21a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test21a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test21a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test21a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32*, align 8 + %b = alloca float**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + %0 = bitcast i32** %a to float** + store float** %0, float*** %b, align 8 + %1 = load float*** %b, align 8 + call void @funfloat2(float** %1) + ret void +} + +; test21b: Addr-of a casted pointer +; ssp attribute +; Requires no protector. +define void @test21b() nounwind uwtable ssp { +entry: +; LINUX-I386: test21b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test21b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test21b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test21b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca i32*, align 8 + %b = alloca float**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + %0 = bitcast i32** %a to float** + store float** %0, float*** %b, align 8 + %1 = load float*** %b, align 8 + call void @funfloat2(float** %1) + ret void +} + +; test21c: Addr-of a casted pointer +; sspstrong attribute +; Requires protector. +define void @test21c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test21c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test21c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test21c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test21c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32*, align 8 + %b = alloca float**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + %0 = bitcast i32** %a to float** + store float** %0, float*** %b, align 8 + %1 = load float*** %b, align 8 + call void @funfloat2(float** %1) + ret void +} + +; test21d: Addr-of a casted pointer +; sspreq attribute +; Requires protector. +define void @test21d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test21d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test21d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test21d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test21d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca i32*, align 8 + %b = alloca float**, align 8 + %call = call i32* @getp() + store i32* %call, i32** %a, align 8 + %0 = bitcast i32** %a to float** + store float** %0, float*** %b, align 8 + %1 = load float*** %b, align 8 + call void @funfloat2(float** %1) + ret void +} + +; test22a: [2 x i8] in a class +; no ssp attribute +; Requires no protector. +define signext i8 @test22a() nounwind uwtable { +entry: +; LINUX-I386: test22a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test22a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test22a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test22a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca %class.A, align 1 + %array = getelementptr inbounds %class.A* %a, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test22b: [2 x i8] in a class +; ssp attribute +; Requires no protector. +define signext i8 @test22b() nounwind uwtable ssp { +entry: +; LINUX-I386: test22b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test22b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test22b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test22b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca %class.A, align 1 + %array = getelementptr inbounds %class.A* %a, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test22c: [2 x i8] in a class +; sspstrong attribute +; Requires protector. +define signext i8 @test22c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test22c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test22c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test22c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test22c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca %class.A, align 1 + %array = getelementptr inbounds %class.A* %a, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test22d: [2 x i8] in a class +; sspreq attribute +; Requires protector. +define signext i8 @test22d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test22d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test22d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test22d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test22d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca %class.A, align 1 + %array = getelementptr inbounds %class.A* %a, i32 0, i32 0 + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test23a: [2 x i8] nested in several layers of structs and unions +; no ssp attribute +; Requires no protector. +define signext i8 @test23a() nounwind uwtable { +entry: +; LINUX-I386: test23a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test23a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test23a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test23a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %x = alloca %struct.deep, align 1 + %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0 + %c = bitcast %union.anon* %b to %struct.anon* + %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0 + %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0 + %array = bitcast %union.anon.1* %e to [2 x i8]* + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test23b: [2 x i8] nested in several layers of structs and unions +; ssp attribute +; Requires no protector. +define signext i8 @test23b() nounwind uwtable ssp { +entry: +; LINUX-I386: test23b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test23b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test23b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test23b: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %x = alloca %struct.deep, align 1 + %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0 + %c = bitcast %union.anon* %b to %struct.anon* + %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0 + %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0 + %array = bitcast %union.anon.1* %e to [2 x i8]* + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test23c: [2 x i8] nested in several layers of structs and unions +; sspstrong attribute +; Requires protector. +define signext i8 @test23c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test23c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test23c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test23c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test23c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %x = alloca %struct.deep, align 1 + %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0 + %c = bitcast %union.anon* %b to %struct.anon* + %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0 + %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0 + %array = bitcast %union.anon.1* %e to [2 x i8]* + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test23d: [2 x i8] nested in several layers of structs and unions +; sspreq attribute +; Requires protector. +define signext i8 @test23d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test23d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test23d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test23d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test23d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %x = alloca %struct.deep, align 1 + %b = getelementptr inbounds %struct.deep* %x, i32 0, i32 0 + %c = bitcast %union.anon* %b to %struct.anon* + %d = getelementptr inbounds %struct.anon* %c, i32 0, i32 0 + %e = getelementptr inbounds %struct.anon.0* %d, i32 0, i32 0 + %array = bitcast %union.anon.1* %e to [2 x i8]* + %arrayidx = getelementptr inbounds [2 x i8]* %array, i32 0, i64 0 + %0 = load i8* %arrayidx, align 1 + ret i8 %0 +} + +; test24a: Variable sized alloca +; no ssp attribute +; Requires no protector. +define void @test24a(i32 %n) nounwind uwtable { +entry: +; LINUX-I386: test24a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test24a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test24a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test24a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %n.addr = alloca i32, align 4 + %a = alloca i32*, align 8 + store i32 %n, i32* %n.addr, align 4 + %0 = load i32* %n.addr, align 4 + %conv = sext i32 %0 to i64 + %1 = alloca i8, i64 %conv + %2 = bitcast i8* %1 to i32* + store i32* %2, i32** %a, align 8 + ret void +} + +; test24b: Variable sized alloca +; ssp attribute +; Requires protector. +define void @test24b(i32 %n) nounwind uwtable ssp { +entry: +; LINUX-I386: test24b: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test24b: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test24b: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test24b: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %n.addr = alloca i32, align 4 + %a = alloca i32*, align 8 + store i32 %n, i32* %n.addr, align 4 + %0 = load i32* %n.addr, align 4 + %conv = sext i32 %0 to i64 + %1 = alloca i8, i64 %conv + %2 = bitcast i8* %1 to i32* + store i32* %2, i32** %a, align 8 + ret void +} + +; test24c: Variable sized alloca +; sspstrong attribute +; Requires protector. +define void @test24c(i32 %n) nounwind uwtable sspstrong { +entry: +; LINUX-I386: test24c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test24c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test24c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test24c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %n.addr = alloca i32, align 4 + %a = alloca i32*, align 8 + store i32 %n, i32* %n.addr, align 4 + %0 = load i32* %n.addr, align 4 + %conv = sext i32 %0 to i64 + %1 = alloca i8, i64 %conv + %2 = bitcast i8* %1 to i32* + store i32* %2, i32** %a, align 8 + ret void +} + +; test24d: Variable sized alloca +; sspreq attribute +; Requires protector. +define void @test24d(i32 %n) nounwind uwtable sspreq { +entry: +; LINUX-I386: test24d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test24d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test24d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test24d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %n.addr = alloca i32, align 4 + %a = alloca i32*, align 8 + store i32 %n, i32* %n.addr, align 4 + %0 = load i32* %n.addr, align 4 + %conv = sext i32 %0 to i64 + %1 = alloca i8, i64 %conv + %2 = bitcast i8* %1 to i32* + store i32* %2, i32** %a, align 8 + ret void +} + +; test25a: array of [4 x i32] +; no ssp attribute +; Requires no protector. +define i32 @test25a() nounwind uwtable { +entry: +; LINUX-I386: test25a: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test25a: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test25a: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test25a: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %a = alloca [4 x i32], align 16 + %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0 + %0 = load i32* %arrayidx, align 4 + ret i32 %0 +} + +; test25b: array of [4 x i32] +; ssp attribute +; Requires no protector, except for Darwin which _does_ require a protector. +define i32 @test25b() nounwind uwtable ssp { +entry: +; LINUX-I386: test25b: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test25b: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test25b: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test25b: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca [4 x i32], align 16 + %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0 + %0 = load i32* %arrayidx, align 4 + ret i32 %0 +} + +; test25c: array of [4 x i32] +; sspstrong attribute +; Requires protector. +define i32 @test25c() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test25c: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test25c: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test25c: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test25c: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca [4 x i32], align 16 + %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0 + %0 = load i32* %arrayidx, align 4 + ret i32 %0 +} + +; test25d: array of [4 x i32] +; sspreq attribute +; Requires protector. +define i32 @test25d() nounwind uwtable sspreq { +entry: +; LINUX-I386: test25d: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test25d: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test25d: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test25d: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %a = alloca [4 x i32], align 16 + %arrayidx = getelementptr inbounds [4 x i32]* %a, i32 0, i64 0 + %0 = load i32* %arrayidx, align 4 + ret i32 %0 +} + +; test26: Nested structure, no arrays, no address-of expressions. +; Verify that the resulting gep-of-gep does not incorrectly trigger +; a stack protector. +; ssptrong attribute +; Requires no protector. +define void @test26() nounwind uwtable sspstrong { +entry: +; LINUX-I386: test26: +; LINUX-I386-NOT: calll __stack_chk_fail +; LINUX-I386: .cfi_endproc + +; LINUX-X64: test26: +; LINUX-X64-NOT: callq __stack_chk_fail +; LINUX-X64: .cfi_endproc + +; LINUX-KERNEL-X64: test26: +; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail +; LINUX-KERNEL-X64: .cfi_endproc + +; DARWIN-X64: test26: +; DARWIN-X64-NOT: callq ___stack_chk_fail +; DARWIN-X64: .cfi_endproc + %c = alloca %struct.nest, align 4 + %b = getelementptr inbounds %struct.nest* %c, i32 0, i32 1 + %_a = getelementptr inbounds %struct.pair* %b, i32 0, i32 0 + %0 = load i32* %_a, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %0) + ret void +} + +; test27: Address-of a structure taken in a function with a loop where +; the alloca is an incoming value to a PHI node and a use of that PHI +; node is also an incoming value. +; Verify that the address-of analysis does not get stuck in infinite +; recursion when chasing the alloca through the PHI nodes. +; Requires protector. +define i32 @test27(i32 %arg) nounwind uwtable sspstrong { +bb: +; LINUX-I386: test27: +; LINUX-I386: mov{{l|q}} %gs: +; LINUX-I386: calll __stack_chk_fail + +; LINUX-X64: test27: +; LINUX-X64: mov{{l|q}} %fs: +; LINUX-X64: callq __stack_chk_fail + +; LINUX-KERNEL-X64: test27: +; LINUX-KERNEL-X64: mov{{l|q}} %gs: +; LINUX-KERNEL-X64: callq __stack_chk_fail + +; DARWIN-X64: test27: +; DARWIN-X64: mov{{l|q}} ___stack_chk_guard +; DARWIN-X64: callq ___stack_chk_fail + %tmp = alloca %struct.small*, align 8 + %tmp1 = call i32 (...)* @dummy(%struct.small** %tmp) nounwind + %tmp2 = load %struct.small** %tmp, align 8 + %tmp3 = ptrtoint %struct.small* %tmp2 to i64 + %tmp4 = trunc i64 %tmp3 to i32 + %tmp5 = icmp sgt i32 %tmp4, 0 + br i1 %tmp5, label %bb6, label %bb21 + +bb6: ; preds = %bb17, %bb + %tmp7 = phi %struct.small* [ %tmp19, %bb17 ], [ %tmp2, %bb ] + %tmp8 = phi i64 [ %tmp20, %bb17 ], [ 1, %bb ] + %tmp9 = phi i32 [ %tmp14, %bb17 ], [ %tmp1, %bb ] + %tmp10 = getelementptr inbounds %struct.small* %tmp7, i64 0, i32 0 + %tmp11 = load i8* %tmp10, align 1 + %tmp12 = icmp eq i8 %tmp11, 1 + %tmp13 = add nsw i32 %tmp9, 8 + %tmp14 = select i1 %tmp12, i32 %tmp13, i32 %tmp9 + %tmp15 = trunc i64 %tmp8 to i32 + %tmp16 = icmp eq i32 %tmp15, %tmp4 + br i1 %tmp16, label %bb21, label %bb17 + +bb17: ; preds = %bb6 + %tmp18 = getelementptr inbounds %struct.small** %tmp, i64 %tmp8 + %tmp19 = load %struct.small** %tmp18, align 8 + %tmp20 = add i64 %tmp8, 1 + br label %bb6 + +bb21: ; preds = %bb6, %bb + %tmp22 = phi i32 [ %tmp1, %bb ], [ %tmp14, %bb6 ] + %tmp23 = call i32 (...)* @dummy(i32 %tmp22) nounwind + ret i32 undef +} -declare i32 @printf(i8*, ...) nounwind +declare double @testi_aux() +declare i8* @strcpy(i8*, i8*) +declare i32 @printf(i8*, ...) +declare void @funcall(i32*) +declare void @funcall2(i32**) +declare void @funfloat(float*) +declare void @funfloat2(float**) +declare void @_Z3exceptPi(i32*) +declare i32 @__gxx_personality_v0(...) +declare i32* @getp() +declare i32 @dummy(...) diff --git a/test/CodeGen/X86/stack-update-frame-opcode.ll b/test/CodeGen/X86/stack-update-frame-opcode.ll new file mode 100644 index 0000000000000..9a5a2421233d7 --- /dev/null +++ b/test/CodeGen/X86/stack-update-frame-opcode.ll @@ -0,0 +1,31 @@ +; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7 < %s | FileCheck -check-prefix=CORE_LP64 %s +; RUN: llc -mtriple=x86_64-pc-linux -mcpu=atom < %s | FileCheck -check-prefix=ATOM_LP64 %s +; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -mcpu=corei7 < %s | FileCheck -check-prefix=CORE_ILP32 %s +; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -mcpu=atom < %s | FileCheck -check-prefix=ATOM_ILP32 %s + +define i32 @bar(i32 %a) nounwind { +entry: + %arr = alloca [400 x i32], align 16 + +; There is a 2x2 variation matrix here: +; Atoms use LEA to update the SP. Opcode bitness depends on data model. +; Cores use sub/add to update the SP. Opcode bitness depends on data model. + +; CORE_LP64: subq $1608 +; CORE_ILP32: subl $1608 +; ATOM_LP64: leaq -1608 +; ATOM_ILP32: leal -1608 + + %arraydecay = getelementptr inbounds [400 x i32]* %arr, i64 0, i64 0 + %call = call i32 @foo(i32 %a, i32* %arraydecay) nounwind + ret i32 %call + +; CORE_LP64: addq $1608 +; CORE_ILP32: addl $1608 +; ATOM_LP64: leaq 1608 +; ATOM_ILP32: leal 1608 + +} + +declare i32 @foo(i32, i32*) + diff --git a/test/CodeGen/X86/store_op_load_fold.ll b/test/CodeGen/X86/store_op_load_fold.ll index 6e47eb397d1df..070cccdb87dda 100644 --- a/test/CodeGen/X86/store_op_load_fold.ll +++ b/test/CodeGen/X86/store_op_load_fold.ll @@ -1,13 +1,30 @@ -; RUN: llc < %s -march=x86 | not grep mov +; RUN: llc < %s -mtriple=i686-darwin | FileCheck %s ; ; Test the add and load are folded into the store instruction. @X = internal global i16 0 ; <i16*> [#uses=2] define void @foo() nounwind { +; CHECK: foo: +; CHECK-NOT: mov +; CHECK: add +; CHECK-NEXT: ret %tmp.0 = load i16* @X ; <i16> [#uses=1] %tmp.3 = add i16 %tmp.0, 329 ; <i16> [#uses=1] store i16 %tmp.3, i16* @X ret void } +; rdar://12838504 +%struct.S2 = type { i64, i16, [2 x i8], i8, [3 x i8], [7 x i8], i8, [8 x i8] } +@s2 = external global %struct.S2, align 16 +define void @test2() nounwind uwtable ssp { +; CHECK: test2: +; CHECK: mov +; CHECK-NEXT: and +; CHECK-NEXT: ret + %bf.load35 = load i56* bitcast ([7 x i8]* getelementptr inbounds (%struct.S2* @s2, i32 0, i32 5) to i56*), align 16 + %bf.clear36 = and i56 %bf.load35, -1125895611875329 + store i56 %bf.clear36, i56* bitcast ([7 x i8]* getelementptr inbounds (%struct.S2* @s2, i32 0, i32 5) to i56*), align 16 + ret void +} diff --git a/test/CodeGen/X86/subtarget-feature-change.ll b/test/CodeGen/X86/subtarget-feature-change.ll new file mode 100644 index 0000000000000..cd677294c6696 --- /dev/null +++ b/test/CodeGen/X86/subtarget-feature-change.ll @@ -0,0 +1,66 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; This should not generate SSE instructions: +; +; CHECK: without.sse: +; CHECK: flds +; CHECK: fmuls +; CHECK: fstps +define void @without.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #0 { +entry: + %cmp9 = icmp sgt i32 %n, 0 + br i1 %cmp9, label %for.body, label %for.end + +for.body: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv + %1 = load float* %arrayidx2, align 4, !tbaa !0 + %mul = fmul float %0, %1 + %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv + store float %mul, float* %arrayidx4, align 4, !tbaa !0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} + +; This should generate SSE instructions: +; +; CHECK: with.sse +; CHECK: movss +; CHECK: mulss +; CHECK: movss +define void @with.sse(float* nocapture %a, float* nocapture %b, float* nocapture %c, i32 %n) #1 { +entry: + %cmp9 = icmp sgt i32 %n, 0 + br i1 %cmp9, label %for.body, label %for.end + +for.body: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv + %1 = load float* %arrayidx2, align 4, !tbaa !0 + %mul = fmul float %0, %1 + %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv + store float %mul, float* %arrayidx4, align 4, !tbaa !0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} + +attributes #0 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,-sse,-avx,-sse41,-ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,-sse2,-sse3" } +attributes #1 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,+sse,-avx,-sse41,+ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,+sse2,+sse3" } + +!0 = metadata !{metadata !"float", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/tailcall-fastisel.ll b/test/CodeGen/X86/tailcall-fastisel.ll index 7f92af4dca9f3..842ed25439f84 100644 --- a/test/CodeGen/X86/tailcall-fastisel.ll +++ b/test/CodeGen/X86/tailcall-fastisel.ll @@ -1,12 +1,11 @@ -; RUN: llc < %s -march=x86-64 -tailcallopt -fast-isel | not grep TAILCALL - -; Fast-isel shouldn't attempt to cope with tail calls. +; RUN: llc < %s -mtriple=x86_64-apple-darwin -tailcallopt -fast-isel -fast-isel-abort | FileCheck %s %0 = type { i64, i32, i8* } define fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 %arg1) nounwind { fail: ; preds = %entry %tmp20 = tail call fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 undef) ; <i8*> [#uses=1] +; CHECK: jmp "_visit_array_aux<`Reference>" ## TAILCALL ret i8* %tmp20 } diff --git a/test/CodeGen/X86/tailcall-structret.ll b/test/CodeGen/X86/tailcall-structret.ll index d8be4b2e2dfd8..dcfefe86704ef 100644 --- a/test/CodeGen/X86/tailcall-structret.ll +++ b/test/CodeGen/X86/tailcall-structret.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL +; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | FileCheck %s define fastcc { { i8*, i8* }*, i8*} @init({ { i8*, i8* }*, i8*}, i32) { entry: %2 = tail call fastcc { { i8*, i8* }*, i8* } @init({ { i8*, i8*}*, i8*} %0, i32 %1) ret { { i8*, i8* }*, i8*} %2 +; CHECK: jmp init } diff --git a/test/CodeGen/X86/tailcallbyval.ll b/test/CodeGen/X86/tailcallbyval.ll index 118eee6ba6cd1..9a0b57c138c25 100644 --- a/test/CodeGen/X86/tailcallbyval.ll +++ b/test/CodeGen/X86/tailcallbyval.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL -; RUN: llc < %s -march=x86 -tailcallopt | grep "movl[[:space:]]*4(%esp), %eax" | count 1 +; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | FileCheck %s %struct.s = type {i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } @@ -9,10 +8,14 @@ entry: %tmp2 = getelementptr %struct.s* %a, i32 0, i32 0 %tmp3 = load i32* %tmp2 ret i32 %tmp3 +; CHECK: tailcallee +; CHECK: movl 4(%esp), %eax } define fastcc i32 @tailcaller(%struct.s* byval %a) nounwind { entry: %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* byval %a ) ret i32 %tmp4 +; CHECK: tailcaller +; CHECK: jmp tailcallee } diff --git a/test/CodeGen/X86/tailcallfp.ll b/test/CodeGen/X86/tailcallfp.ll index c0b609ac956ec..22a7930ba8770 100644 --- a/test/CodeGen/X86/tailcallfp.ll +++ b/test/CodeGen/X86/tailcallfp.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -tailcallopt | not grep call +; RUN: llc < %s -march=x86 -tailcallopt | FileCheck %s define fastcc i32 @bar(i32 %X, i32(double, i32) *%FP) { %Y = tail call fastcc i32 %FP(double 0.0, i32 %X) ret i32 %Y +; CHECK: jmpl } diff --git a/test/CodeGen/X86/tailcallpic1.ll b/test/CodeGen/X86/tailcallpic1.ll index 60e3be5c50fda..ff590a1fd3e98 100644 --- a/test/CodeGen/X86/tailcallpic1.ll +++ b/test/CodeGen/X86/tailcallpic1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep TAILCALL +; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | FileCheck %s define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { entry: @@ -9,4 +9,5 @@ define fastcc i32 @tailcaller(i32 %in1, i32 %in2) { entry: %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1] ret i32 %tmp11 +; CHECK: jmp tailcallee } diff --git a/test/CodeGen/X86/tailcallpic2.ll b/test/CodeGen/X86/tailcallpic2.ll index eaa76312396c6..1b6bdb769861d 100644 --- a/test/CodeGen/X86/tailcallpic2.ll +++ b/test/CodeGen/X86/tailcallpic2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep -v TAILCALL +; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | FileCheck %s define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { entry: @@ -9,4 +9,7 @@ define fastcc i32 @tailcaller(i32 %in1, i32 %in2) { entry: %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1] ret i32 %tmp11 +; CHECK: movl tailcallee@GOT +; CHECK: jmpl } + diff --git a/test/CodeGen/X86/thiscall-struct-return.ll b/test/CodeGen/X86/thiscall-struct-return.ll deleted file mode 100644 index 0507cb890cd23..0000000000000 --- a/test/CodeGen/X86/thiscall-struct-return.ll +++ /dev/null @@ -1,47 +0,0 @@ -; RUN: llc < %s -mtriple=i386-PC-Win32 | FileCheck %s - -%class.C = type { i8 } -%struct.S = type { i32 } -%struct.M = type { i32, i32 } - -declare void @_ZN1CC1Ev(%class.C* %this) unnamed_addr nounwind align 2 -declare x86_thiscallcc void @_ZNK1C5SmallEv(%struct.S* noalias sret %agg.result, %class.C* %this) nounwind align 2 -declare x86_thiscallcc void @_ZNK1C6MediumEv(%struct.M* noalias sret %agg.result, %class.C* %this) nounwind align 2 - -define void @testv() nounwind { -; CHECK: testv: -; CHECK: leal 16(%esp), %esi -; CHECK-NEXT: movl %esi, (%esp) -; CHECK-NEXT: calll _ZN1CC1Ev -; CHECK: leal 8(%esp), %eax -; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: calll _ZNK1C5SmallEv -entry: - %c = alloca %class.C, align 1 - %tmp = alloca %struct.S, align 4 - call void @_ZN1CC1Ev(%class.C* %c) - ; This call should put the return structure as a pointer - ; into EAX instead of returning directly in EAX. The this - ; pointer should go into ECX - call x86_thiscallcc void @_ZNK1C5SmallEv(%struct.S* sret %tmp, %class.C* %c) - ret void -} - -define void @test2v() nounwind { -; CHECK: test2v: -; CHECK: leal 16(%esp), %esi -; CHECK-NEXT: movl %esi, (%esp) -; CHECK-NEXT: calll _ZN1CC1Ev -; CHECK: leal 8(%esp), %eax -; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: calll _ZNK1C6MediumEv -entry: - %c = alloca %class.C, align 1 - %tmp = alloca %struct.M, align 4 - call void @_ZN1CC1Ev(%class.C* %c) - ; This call should put the return structure as a pointer - ; into EAX instead of returning directly in EAX/EDX. The this - ; pointer should go into ECX - call x86_thiscallcc void @_ZNK1C6MediumEv(%struct.M* sret %tmp, %class.C* %c) - ret void -} diff --git a/test/CodeGen/X86/tls.ll b/test/CodeGen/X86/tls.ll index e8a79bfa6ee32..8cdecd81bff51 100644 --- a/test/CodeGen/X86/tls.ll +++ b/test/CodeGen/X86/tls.ll @@ -22,13 +22,13 @@ define i32 @f1() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movl _i1@SECREL(%eax), %eax +; X32_WIN-NEXT: movl _i1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f1: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movl i1@SECREL(%rax), %eax +; X64_WIN-NEXT: movl i1@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -49,13 +49,13 @@ define i32* @f2() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: leal _i1@SECREL(%eax), %eax +; X32_WIN-NEXT: leal _i1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f2: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: leaq i1@SECREL(%rax), %rax +; X64_WIN-NEXT: leaq i1@SECREL32(%rax), %rax ; X64_WIN-NEXT: ret entry: @@ -75,13 +75,13 @@ define i32 @f3() nounwind { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movl _i2@SECREL(%eax), %eax +; X32_WIN-NEXT: movl _i2@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f3: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movl i2@SECREL(%rax), %eax +; X64_WIN-NEXT: movl i2@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -102,13 +102,13 @@ define i32* @f4() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: leal _i2@SECREL(%eax), %eax +; X32_WIN-NEXT: leal _i2@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f4: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: leaq i2@SECREL(%rax), %rax +; X64_WIN-NEXT: leaq i2@SECREL32(%rax), %rax ; X64_WIN-NEXT: ret entry: @@ -126,13 +126,13 @@ define i32 @f5() nounwind { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movl _i3@SECREL(%eax), %eax +; X32_WIN-NEXT: movl _i3@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f5: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movl i3@SECREL(%rax), %eax +; X64_WIN-NEXT: movl i3@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -153,13 +153,13 @@ define i32* @f6() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: leal _i3@SECREL(%eax), %eax +; X32_WIN-NEXT: leal _i3@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f6: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: leaq i3@SECREL(%rax), %rax +; X64_WIN-NEXT: leaq i3@SECREL32(%rax), %rax ; X64_WIN-NEXT: ret entry: @@ -234,14 +234,14 @@ define i16 @f11() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movzwl _s1@SECREL(%eax), %eax +; X32_WIN-NEXT: movzwl _s1@SECREL32(%eax), %eax ; X32_WIN-NEXT: # kill ; X32_WIN-NEXT: ret ; X64_WIN: f11: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movzwl s1@SECREL(%rax), %eax +; X64_WIN-NEXT: movzwl s1@SECREL32(%rax), %eax ; X64_WIN-NEXT: # kill ; X64_WIN-NEXT: ret @@ -261,13 +261,13 @@ define i32 @f12() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movswl _s1@SECREL(%eax), %eax +; X32_WIN-NEXT: movswl _s1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f12: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movswl s1@SECREL(%rax), %eax +; X64_WIN-NEXT: movswl s1@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -287,13 +287,13 @@ define i8 @f13() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movb _b1@SECREL(%eax), %al +; X32_WIN-NEXT: movb _b1@SECREL32(%eax), %al ; X32_WIN-NEXT: ret ; X64_WIN: f13: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movb b1@SECREL(%rax), %al +; X64_WIN-NEXT: movb b1@SECREL32(%rax), %al ; X64_WIN-NEXT: ret entry: @@ -312,13 +312,13 @@ define i32 @f14() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movsbl _b1@SECREL(%eax), %eax +; X32_WIN-NEXT: movsbl _b1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f14: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movsbl b1@SECREL(%rax), %eax +; X64_WIN-NEXT: movsbl b1@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: diff --git a/test/CodeGen/X86/twoaddr-coalesce-2.ll b/test/CodeGen/X86/twoaddr-coalesce-2.ll index af6d47af7a0fb..cbcde06555971 100644 --- a/test/CodeGen/X86/twoaddr-coalesce-2.ll +++ b/test/CodeGen/X86/twoaddr-coalesce-2.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -stats 2>&1 | \ ; RUN: grep "twoaddrinstr" | grep "Number of instructions aggressively commuted" ; rdar://6480363 diff --git a/test/CodeGen/X86/twoaddr-pass-sink.ll b/test/CodeGen/X86/twoaddr-pass-sink.ll index 513c304e3bf84..9ca280627afeb 100644 --- a/test/CodeGen/X86/twoaddr-pass-sink.ll +++ b/test/CodeGen/X86/twoaddr-pass-sink.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -stats 2>&1 | grep "Number of 3-address instructions sunk" define void @t2(<2 x i64>* %vDct, <2 x i64>* %vYp, i8* %skiplist, <2 x i64> %a1) nounwind { diff --git a/test/CodeGen/X86/unknown-location.ll b/test/CodeGen/X86/unknown-location.ll index b89c4738af125..e02e3b54752ba 100644 --- a/test/CodeGen/X86/unknown-location.ll +++ b/test/CodeGen/X86/unknown-location.ll @@ -18,12 +18,16 @@ entry: ret i32 %c, !dbg !8 } -!0 = metadata !{i32 524545, metadata !1, metadata !"x", metadata !2, i32 1, metadata !6} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 524329, metadata !"test.c", metadata !"/dir", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 524305, i32 0, i32 12, metadata !"test.c", metadata !".", metadata !"producer", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!llvm.dbg.cu = !{!3} + +!0 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !2, i32 1, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, i32, i32, i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, metadata !10, i32 12, metadata !"producer", i1 false, metadata !"", i32 0, null, null, metadata !9, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6} -!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 524299, metadata !1, i32 1, i32 30} ; [ DW_TAG_lexical_block ] +!6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786443, metadata !1, i32 1, i32 30} ; [ DW_TAG_lexical_block ] !8 = metadata !{i32 4, i32 3, metadata !7, null} +!9 = metadata !{metadata !1} +!10 = metadata !{metadata !"test.c", metadata !"/dir"} diff --git a/test/CodeGen/X86/v8i1-masks.ll b/test/CodeGen/X86/v8i1-masks.ll new file mode 100644 index 0000000000000..8cbfb5d7243af --- /dev/null +++ b/test/CodeGen/X86/v8i1-masks.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s + +;CHECK: and_masks +;CHECK: vmovaps +;CHECK: vcmpltp +;CHECK: vcmpltp +;CHECK: vandps +;CHECK: vandps +;CHECK: vmovaps +;CHECK: ret + +define void @and_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp { + %v0 = load <8 x float>* %a, align 16 + %v1 = load <8 x float>* %b, align 16 + %m0 = fcmp olt <8 x float> %v1, %v0 + %v2 = load <8 x float>* %c, align 16 + %m1 = fcmp olt <8 x float> %v2, %v0 + %mand = and <8 x i1> %m1, %m0 + %r = zext <8 x i1> %mand to <8 x i32> + store <8 x i32> %r, <8 x i32>* undef, align 32 + ret void +} + +;CHECK: neg_mask +;CHECK: vcmpltps +;CHECK: vxorps +;CHECK: vandps +;CHECK: vmovaps +;CHECK: ret +define void @neg_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp { + %v0 = load <8 x float>* %a, align 16 + %v1 = load <8 x float>* %b, align 16 + %m0 = fcmp olt <8 x float> %v1, %v0 + %mand = xor <8 x i1> %m0, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1> + %r = zext <8 x i1> %mand to <8 x i32> + store <8 x i32> %r, <8 x i32>* undef, align 32 + ret void +} + diff --git a/test/CodeGen/X86/vec_align_i256.ll b/test/CodeGen/X86/vec_align_i256.ll new file mode 100644 index 0000000000000..078bcb1544d3a --- /dev/null +++ b/test/CodeGen/X86/vec_align_i256.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" + +; Make sure that we are not generating a movaps because the vector is aligned to 1. +;CHECK: @foo +;CHECK: xor +;CHECK-NEXT: vmovups +;CHECK-NEXT: ret +define void @foo() { + store <16 x i16> zeroinitializer, <16 x i16>* undef, align 1 + ret void +} diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll index 367dd27f30769..b6d91a3f770ef 100644 --- a/test/CodeGen/X86/vec_compare.ll +++ b/test/CodeGen/X86/vec_compare.ll @@ -41,3 +41,27 @@ define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { %D = sext <4 x i1> %C to <4 x i32> ret <4 x i32> %D } + +define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test5: +; CHECK: pcmpeqd +; CHECK: pshufd $-79 +; CHECK: pand +; CHECK: ret + %C = icmp eq <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test6: +; CHECK: pcmpeqd +; CHECK: pshufd $-79 +; CHECK: pand +; CHECK: pcmpeqd +; CHECK: pxor +; CHECK: ret + %C = icmp ne <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} diff --git a/test/CodeGen/X86/vec_floor.ll b/test/CodeGen/X86/vec_floor.ll index 5e0160bd2856c..4db68bd18223a 100644 --- a/test/CodeGen/X86/vec_floor.ll +++ b/test/CodeGen/X86/vec_floor.ll @@ -36,3 +36,147 @@ define <8 x float> @floor_v8f32(<8 x float> %p) ret <8 x float> %t } declare <8 x float> @llvm.floor.v8f32(<8 x float> %p) + +define <2 x double> @ceil_v2f64(<2 x double> %p) +{ + ; CHECK: ceil_v2f64 + ; CHECK: vroundpd + %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p) + ret <2 x double> %t +} +declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p) + +define <4 x float> @ceil_v4f32(<4 x float> %p) +{ + ; CHECK: ceil_v4f32 + ; CHECK: vroundps + %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p) + ret <4 x float> %t +} +declare <4 x float> @llvm.ceil.v4f32(<4 x float> %p) + +define <4 x double> @ceil_v4f64(<4 x double> %p) +{ + ; CHECK: ceil_v4f64 + ; CHECK: vroundpd + %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p) + ret <4 x double> %t +} +declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p) + +define <8 x float> @ceil_v8f32(<8 x float> %p) +{ + ; CHECK: ceil_v8f32 + ; CHECK: vroundps + %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p) + ret <8 x float> %t +} +declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p) + +define <2 x double> @trunc_v2f64(<2 x double> %p) +{ + ; CHECK: trunc_v2f64 + ; CHECK: vroundpd + %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p) + ret <2 x double> %t +} +declare <2 x double> @llvm.trunc.v2f64(<2 x double> %p) + +define <4 x float> @trunc_v4f32(<4 x float> %p) +{ + ; CHECK: trunc_v4f32 + ; CHECK: vroundps + %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p) + ret <4 x float> %t +} +declare <4 x float> @llvm.trunc.v4f32(<4 x float> %p) + +define <4 x double> @trunc_v4f64(<4 x double> %p) +{ + ; CHECK: trunc_v4f64 + ; CHECK: vroundpd + %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p) + ret <4 x double> %t +} +declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p) + +define <8 x float> @trunc_v8f32(<8 x float> %p) +{ + ; CHECK: trunc_v8f32 + ; CHECK: vroundps + %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p) + ret <8 x float> %t +} +declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p) + +define <2 x double> @rint_v2f64(<2 x double> %p) +{ + ; CHECK: rint_v2f64 + ; CHECK: vroundpd + %t = call <2 x double> @llvm.rint.v2f64(<2 x double> %p) + ret <2 x double> %t +} +declare <2 x double> @llvm.rint.v2f64(<2 x double> %p) + +define <4 x float> @rint_v4f32(<4 x float> %p) +{ + ; CHECK: rint_v4f32 + ; CHECK: vroundps + %t = call <4 x float> @llvm.rint.v4f32(<4 x float> %p) + ret <4 x float> %t +} +declare <4 x float> @llvm.rint.v4f32(<4 x float> %p) + +define <4 x double> @rint_v4f64(<4 x double> %p) +{ + ; CHECK: rint_v4f64 + ; CHECK: vroundpd + %t = call <4 x double> @llvm.rint.v4f64(<4 x double> %p) + ret <4 x double> %t +} +declare <4 x double> @llvm.rint.v4f64(<4 x double> %p) + +define <8 x float> @rint_v8f32(<8 x float> %p) +{ + ; CHECK: rint_v8f32 + ; CHECK: vroundps + %t = call <8 x float> @llvm.rint.v8f32(<8 x float> %p) + ret <8 x float> %t +} +declare <8 x float> @llvm.rint.v8f32(<8 x float> %p) + +define <2 x double> @nearbyint_v2f64(<2 x double> %p) +{ + ; CHECK: nearbyint_v2f64 + ; CHECK: vroundpd + %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) + ret <2 x double> %t +} +declare <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) + +define <4 x float> @nearbyint_v4f32(<4 x float> %p) +{ + ; CHECK: nearbyint_v4f32 + ; CHECK: vroundps + %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p) + ret <4 x float> %t +} +declare <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p) + +define <4 x double> @nearbyint_v4f64(<4 x double> %p) +{ + ; CHECK: nearbyint_v4f64 + ; CHECK: vroundpd + %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p) + ret <4 x double> %t +} +declare <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p) + +define <8 x float> @nearbyint_v8f32(<8 x float> %p) +{ + ; CHECK: nearbyint_v8f32 + ; CHECK: vroundps + %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p) + ret <8 x float> %t +} +declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p) diff --git a/test/CodeGen/X86/vec_fpext.ll b/test/CodeGen/X86/vec_fpext.ll index dc0464ff9e0f5..863712ff48b3d 100644 --- a/test/CodeGen/X86/vec_fpext.ll +++ b/test/CodeGen/X86/vec_fpext.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse41,-avx | FileCheck %s -; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck --check-prefix=AVX %s +; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck --check-prefix=AVX %s ; PR11674 define void @fpext_frommem(<2 x float>* %in, <2 x double>* %out) { @@ -29,8 +29,8 @@ entry: ; CHECK: cvtps2pd 8(%{{.+}}), %xmm{{[0-9]+}} ; CHECK: cvtps2pd 16(%{{.+}}), %xmm{{[0-9]+}} ; CHECK: cvtps2pd 24(%{{.+}}), %xmm{{[0-9]+}} -; AVX: vcvtps2pd (%{{.+}}), %ymm{{[0-9]+}} ; AVX: vcvtps2pd 16(%{{.+}}), %ymm{{[0-9]+}} +; AVX: vcvtps2pd (%{{.+}}), %ymm{{[0-9]+}} %0 = load <8 x float>* %in %1 = fpext <8 x float> %0 to <8 x double> store <8 x double> %1, <8 x double>* %out, align 1 diff --git a/test/CodeGen/X86/vec_insert-6.ll b/test/CodeGen/X86/vec_insert-6.ll index 2a4864a48a257..4583e1925e59d 100644 --- a/test/CodeGen/X86/vec_insert-6.ll +++ b/test/CodeGen/X86/vec_insert-6.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn | grep pslldq ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -mtriple=i686-apple-darwin9 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 6 diff --git a/test/CodeGen/X86/vec_sdiv_to_shift.ll b/test/CodeGen/X86/vec_sdiv_to_shift.ll new file mode 100644 index 0000000000000..349868a87f532 --- /dev/null +++ b/test/CodeGen/X86/vec_sdiv_to_shift.ll @@ -0,0 +1,72 @@ +; RUN: llc < %s -march=x86-64 -mcpu=penryn -mattr=+avx2 | FileCheck %s + + +define <8 x i16> @sdiv_vec8x16(<8 x i16> %var) { +entry: +; CHECK: sdiv_vec8x16 +; CHECK: psraw $15 +; CHECK: vpsrlw $11 +; CHECK: vpaddw +; CHECK: vpsraw $5 +; CHECK: ret + %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32> + ret <8 x i16> %0 +} + +define <4 x i32> @sdiv_zero(<4 x i32> %var) { +entry: +; CHECK: sdiv_zero +; CHECK-NOT: sra +; CHECK: ret + %0 = sdiv <4 x i32> %var, <i32 0, i32 0, i32 0, i32 0> + ret <4 x i32> %0 +} + +define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) { +entry: +; CHECK: sdiv_vec4x32 +; CHECK: vpsrad $31 +; CHECK: vpsrld $28 +; CHECK: vpaddd +; CHECK: vpsrad $4 +; CHECK: ret +%0 = sdiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16> +ret <4 x i32> %0 +} + +define <4 x i32> @sdiv_negative(<4 x i32> %var) { +entry: +; CHECK: sdiv_negative +; CHECK: vpsrad $31 +; CHECK: vpsrld $28 +; CHECK: vpaddd +; CHECK: vpsrad $4 +; CHECK: vpsubd +; CHECK: ret +%0 = sdiv <4 x i32> %var, <i32 -16, i32 -16, i32 -16, i32 -16> +ret <4 x i32> %0 +} + +define <8 x i32> @sdiv8x32(<8 x i32> %var) { +entry: +; CHECK: sdiv8x32 +; CHECK: vpsrad $31 +; CHECK: vpsrld $26 +; CHECK: vpaddd +; CHECK: vpsrad $6 +; CHECK: ret +%0 = sdiv <8 x i32> %var, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64> +ret <8 x i32> %0 +} + +define <16 x i16> @sdiv16x16(<16 x i16> %var) { +entry: +; CHECK: sdiv16x16 +; CHECK: vpsraw $15 +; CHECK: vpsrlw $14 +; CHECK: vpaddw +; CHECK: vpsraw $2 +; CHECK: ret + %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> + ret <16 x i16> %a0 +} diff --git a/test/CodeGen/X86/vec_shuffle-19.ll b/test/CodeGen/X86/vec_shuffle-19.ll index b26f920e5e230..48db8de0d936d 100644 --- a/test/CodeGen/X86/vec_shuffle-19.ll +++ b/test/CodeGen/X86/vec_shuffle-19.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -o /dev/null -march=x86 -mcpu=penryn -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 4 ; PR2485 diff --git a/test/CodeGen/X86/vec_shuffle-20.ll b/test/CodeGen/X86/vec_shuffle-20.ll index 976cd1835b40d..5a2c4449456be 100644 --- a/test/CodeGen/X86/vec_shuffle-20.ll +++ b/test/CodeGen/X86/vec_shuffle-20.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3 +; REQUIRES: asserts +; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2 define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind { entry: diff --git a/test/CodeGen/X86/vec_splat-2.ll b/test/CodeGen/X86/vec_splat-2.ll index f105de4d977d5..5c668b7e5a5b7 100644 --- a/test/CodeGen/X86/vec_splat-2.ll +++ b/test/CodeGen/X86/vec_splat-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 | grep pshufd | count 1 +; RUN: llc < %s -march=x86 -mcpu=pentium4 -mattr=+sse2 | FileCheck %s define void @test(<2 x i64>* %P, i8 %x) nounwind { %tmp = insertelement <16 x i8> zeroinitializer, i8 %x, i32 0 ; <<16 x i8>> [#uses=1] @@ -23,4 +23,11 @@ define void @test(<2 x i64>* %P, i8 %x) nounwind { %tmp73.upgrd.1 = bitcast <16 x i8> %tmp73 to <2 x i64> ; <<2 x i64>> [#uses=1] store <2 x i64> %tmp73.upgrd.1, <2 x i64>* %P ret void + +; CHECK: test: +; CHECK-NOT: pshufd +; CHECK: punpcklbw +; CHECK: punpcklbw +; CHECK: pshufd $0 +; CHECK-NOT: pshufd } diff --git a/test/CodeGen/X86/vec_splat-3.ll b/test/CodeGen/X86/vec_splat-3.ll index feacc42406df7..cf0ecf40554d6 100644 --- a/test/CodeGen/X86/vec_splat-3.ll +++ b/test/CodeGen/X86/vec_splat-3.ll @@ -1,55 +1,230 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=sse41 -o %t -; RUN: grep punpcklwd %t | count 4 -; RUN: grep punpckhwd %t | count 4 -; RUN: grep "pshufd" %t | count 8 +; RUN: llc <%s -march=x86 -mcpu=penryn -mattr=sse41 | FileCheck %s ; Splat test for v8i16 -; Should generate with pshufd with masks $0, $85, $170, $255 (each mask is used twice) define <8 x i16> @shuf_8i16_0(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x i16> %tmp6 + +; CHECK: shuf_8i16_0: +; CHECK: pshuflw $0 } define <8 x i16> @shuf_8i16_1(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x i16> %tmp6 + +; CHECK: shuf_8i16_1: +; CHECK: pshuflw $5 } define <8 x i16> @shuf_8i16_2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef, i32 undef> ret <8 x i16> %tmp6 + +; CHECK: shuf_8i16_2: +; CHECK: punpcklwd +; CHECK-NEXT: pshufd $-86 } define <8 x i16> @shuf_8i16_3(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x i16> %tmp6 + +; CHECK: shuf_8i16_3: +; CHECK: pshuflw $15 } define <8 x i16> @shuf_8i16_4(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef> ret <8 x i16> %tmp6 + +; CHECK: shuf_8i16_4: +; CHECK: movhlps } define <8 x i16> @shuf_8i16_5(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 undef, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x i16> %tmp6 + +; CHECK: shuf_8i16_5: +; CHECK: punpckhwd +; CHECK-NEXT: pshufd $85 } define <8 x i16> @shuf_8i16_6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 6, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 6, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x i16> %tmp6 -} +; CHECK: shuf_8i16_6: +; CHECK: punpckhwd +; CHECK-NEXT: pshufd $-86 +} define <8 x i16> @shuf_8i16_7(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef , i32 undef > + %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x i16> %tmp6 + +; CHECK: shuf_8i16_7: +; CHECK: punpckhwd +; CHECK-NEXT: pshufd $-1 +} + +; Splat test for v16i8 +define <16 x i8> @shuf_16i8_8(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_8: +; CHECK: punpcklbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $0 +} + +define <16 x i8> @shuf_16i8_9(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef > + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_9: +; CHECK: punpcklbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $85 +} + +define <16 x i8> @shuf_16i8_10(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_10: +; CHECK: punpcklbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $-86 +} + +define <16 x i8> @shuf_16i8_11(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 3, i32 undef, i32 undef, i32 3, i32 undef, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_11: +; CHECK: punpcklbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $-1 +} + + +define <16 x i8> @shuf_16i8_12(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef > + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_12: +; CHECK: pshufd $5 +} + +define <16 x i8> @shuf_16i8_13(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_13: +; CHECK: punpcklbw +; CHECK-NEXT: punpckhbw +; CHECK-NEXT: pshufd $85 +} + +define <16 x i8> @shuf_16i8_14(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 6, i32 undef, i32 undef, i32 6, i32 undef, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_14: +; CHECK: punpcklbw +; CHECK-NEXT: punpckhbw +; CHECK-NEXT: pshufd $-86 +} + +define <16 x i8> @shuf_16i8_15(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef > + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_15: +; CHECK: punpcklbw +; CHECK-NEXT: punpckhbw +; CHECK-NEXT: pshufd $-1 +} + +define <16 x i8> @shuf_16i8_16(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 8, i32 undef, i32 undef, i32 8, i32 undef, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_16: +; CHECK: punpckhbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $0 +} + +define <16 x i8> @shuf_16i8_17(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 9, i32 undef, i32 undef, i32 9, i32 undef, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_17: +; CHECK: punpckhbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $85 +} + +define <16 x i8> @shuf_16i8_18(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 10, i32 undef, i32 undef, i32 10, i32 undef, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_18: +; CHECK: punpckhbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $-86 +} + +define <16 x i8> @shuf_16i8_19(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 11, i32 undef, i32 undef, i32 11, i32 undef, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_19: +; CHECK: punpckhbw +; CHECK-NEXT: punpcklbw +; CHECK-NEXT: pshufd $-1 +} + +define <16 x i8> @shuf_16i8_20(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 12, i32 undef, i32 undef, i32 12, i32 undef, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_20: +; CHECK: punpckhbw +; CHECK-NEXT: punpckhbw +; CHECK-NEXT: pshufd $0 +} + +define <16 x i8> @shuf_16i8_21(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 13, i32 undef, i32 undef, i32 13, i32 undef, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_21: +; CHECK: punpckhbw +; CHECK-NEXT: punpckhbw +; CHECK-NEXT: pshufd $85 +} + +define <16 x i8> @shuf_16i8_22(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 14, i32 undef, i32 undef, i32 14, i32 undef, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_22: +; CHECK: punpckhbw +; CHECK-NEXT: punpckhbw +; CHECK-NEXT: pshufd $-86 +} + +define <16 x i8> @shuf_16i8_23(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone { + %tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 15, i32 undef, i32 undef, i32 15, i32 undef, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15> + ret <16 x i8> %tmp6 + +; CHECK: shuf_16i8_23: +; CHECK: punpckhbw +; CHECK-NEXT: punpckhbw +; CHECK-NEXT: pshufd $-1 } diff --git a/test/CodeGen/X86/vec_splat-4.ll b/test/CodeGen/X86/vec_splat-4.ll deleted file mode 100644 index 374acfa4e094c..0000000000000 --- a/test/CodeGen/X86/vec_splat-4.ll +++ /dev/null @@ -1,104 +0,0 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=sse41 -o %t -; RUN: grep punpcklbw %t | count 16 -; RUN: grep punpckhbw %t | count 16 -; RUN: grep "pshufd" %t | count 16 - -; Should generate with pshufd with masks $0, $85, $170, $255 (each mask is used 4 times) - -; Splat test for v16i8 -define <16 x i8 > @shuf_16i8_0(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 0, i32 0 , i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_1(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_2(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 2 , i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_3(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 3, i32 undef, i32 undef, i32 3, i32 undef, i32 3, i32 3 , i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3 > - ret <16 x i8 > %tmp6 -} - - -define <16 x i8 > @shuf_16i8_4(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_5(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 5, i32 5 , i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_6(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 6, i32 undef, i32 undef, i32 6, i32 undef, i32 6, i32 6 , i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_7(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef , i32 undef , i32 undef, i32 undef, i32 undef , i32 undef > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_8(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 8, i32 undef, i32 undef, i32 8, i32 undef, i32 8, i32 8 , i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_9(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 9, i32 undef, i32 undef, i32 9, i32 undef, i32 9, i32 9 , i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_10(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 10, i32 undef, i32 undef, i32 10, i32 undef, i32 10, i32 10 , i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_11(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 11, i32 undef, i32 undef, i32 11, i32 undef, i32 11, i32 11 , i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_12(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 12, i32 undef, i32 undef, i32 12, i32 undef, i32 12, i32 12 , i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_13(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 13, i32 undef, i32 undef, i32 13, i32 undef, i32 13, i32 13 , i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_14(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 14, i32 undef, i32 undef, i32 14, i32 undef, i32 14, i32 14 , i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14 > - ret <16 x i8 > %tmp6 -} - -define <16 x i8 > @shuf_16i8_15(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone { -entry: - %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 15, i32 undef, i32 undef, i32 15, i32 undef, i32 15, i32 15 , i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15 > - ret <16 x i8 > %tmp6 -} diff --git a/test/CodeGen/X86/vec_splat.ll b/test/CodeGen/X86/vec_splat.ll index 24d8487f17bd4..deedee8019676 100644 --- a/test/CodeGen/X86/vec_splat.ll +++ b/test/CodeGen/X86/vec_splat.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 | grep pshufd -; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse3 | grep movddup +; RUN: llc < %s -march=x86 -mcpu=pentium4 -mattr=+sse2 | FileCheck %s -check-prefix=SSE2 +; RUN: llc < %s -march=x86 -mcpu=pentium4 -mattr=+sse3 | FileCheck %s -check-prefix=SSE3 define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind { %tmp = insertelement <4 x float> zeroinitializer, float %X, i32 0 ; <<4 x float>> [#uses=1] @@ -10,6 +10,12 @@ define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind { %tmp10 = fmul <4 x float> %tmp8, %tmp6 ; <<4 x float>> [#uses=1] store <4 x float> %tmp10, <4 x float>* %P ret void + +; SSE2: test_v4sf: +; SSE2: pshufd $0 + +; SSE3: test_v4sf: +; SSE3: pshufd $0 } define void @test_v2sd(<2 x double>* %P, <2 x double>* %Q, double %X) nounwind { @@ -19,4 +25,10 @@ define void @test_v2sd(<2 x double>* %P, <2 x double>* %Q, double %X) nounwind { %tmp6 = fmul <2 x double> %tmp4, %tmp2 ; <<2 x double>> [#uses=1] store <2 x double> %tmp6, <2 x double>* %P ret void + +; SSE2: test_v2sd: +; SSE2: shufpd $0 + +; SSE3: test_v2sd: +; SSE3: movddup } diff --git a/test/CodeGen/X86/vec_zero.ll b/test/CodeGen/X86/vec_zero.ll index 682a0dfca806f..c3ea0ad2023f7 100644 --- a/test/CodeGen/X86/vec_zero.ll +++ b/test/CodeGen/X86/vec_zero.ll @@ -13,7 +13,7 @@ define void @foo(<4 x float>* %P) { ; CHECK: pxor define void @bar(<4 x i32>* %P) { %T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1] - %S = add <4 x i32> zeroinitializer, %T ; <<4 x i32>> [#uses=1] + %S = sub <4 x i32> zeroinitializer, %T ; <<4 x i32>> [#uses=1] store <4 x i32> %S, <4 x i32>* %P ret void } diff --git a/test/CodeGen/X86/vector-gep.ll b/test/CodeGen/X86/vector-gep.ll index 3476e36c646fd..ec93ce0761cc2 100644 --- a/test/CodeGen/X86/vector-gep.ll +++ b/test/CodeGen/X86/vector-gep.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s -; RUN: opt -instsimplify %s -disable-output +; RUN: opt -instsimplify -disable-output < %s ;CHECK: AGEP0: define <4 x i32*> @AGEP0(i32* %ptr) nounwind { @@ -8,10 +8,8 @@ entry: %vecinit2.i = insertelement <4 x i32*> %vecinit.i, i32* %ptr, i32 1 %vecinit4.i = insertelement <4 x i32*> %vecinit2.i, i32* %ptr, i32 2 %vecinit6.i = insertelement <4 x i32*> %vecinit4.i, i32* %ptr, i32 3 -;CHECK: pslld $2 ;CHECK: padd %A2 = getelementptr <4 x i32*> %vecinit6.i, <4 x i32> <i32 1, i32 2, i32 3, i32 4> -;CHECK: pslld $2 ;CHECK: padd %A3 = getelementptr <4 x i32*> %A2, <4 x i32> <i32 10, i32 14, i32 19, i32 233> ret <4 x i32*> %A3 @@ -21,7 +19,6 @@ entry: ;CHECK: AGEP1: define i32 @AGEP1(<4 x i32*> %param) nounwind { entry: -;CHECK: pslld $2 ;CHECK: padd %A2 = getelementptr <4 x i32*> %param, <4 x i32> <i32 1, i32 2, i32 3, i32 4> %k = extractelement <4 x i32*> %A2, i32 3 diff --git a/test/CodeGen/X86/vselect-minmax.ll b/test/CodeGen/X86/vselect-minmax.ll new file mode 100644 index 0000000000000..cf654b6f20599 --- /dev/null +++ b/test/CodeGen/X86/vselect-minmax.ll @@ -0,0 +1,2788 @@ +; RUN: llc -march=x86-64 -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE2 +; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE4 +; RUN: llc -march=x86-64 -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1 +; RUN: llc -march=x86-64 -mcpu=core-avx2 -mattr=+avx2 < %s | FileCheck %s -check-prefix=AVX2 + +define void @test1(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp slt <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test1: +; SSE4: pminsb + +; AVX1: test1: +; AVX1: vpminsb + +; AVX2: test1: +; AVX2: vpminsb +} + +define void @test2(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp sle <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test2: +; SSE4: pminsb + +; AVX1: test2: +; AVX1: vpminsb + +; AVX2: test2: +; AVX2: vpminsb +} + +define void @test3(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp sgt <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test3: +; SSE4: pmaxsb + +; AVX1: test3: +; AVX1: vpmaxsb + +; AVX2: test3: +; AVX2: vpmaxsb +} + +define void @test4(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp sge <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test4: +; SSE4: pmaxsb + +; AVX1: test4: +; AVX1: vpmaxsb + +; AVX2: test4: +; AVX2: vpmaxsb +} + +define void @test5(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp ult <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test5: +; SSE2: pminub + +; AVX1: test5: +; AVX1: vpminub + +; AVX2: test5: +; AVX2: vpminub +} + +define void @test6(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp ule <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test6: +; SSE2: pminub + +; AVX1: test6: +; AVX1: vpminub + +; AVX2: test6: +; AVX2: vpminub +} + +define void @test7(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp ugt <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test7: +; SSE2: pmaxub + +; AVX1: test7: +; AVX1: vpmaxub + +; AVX2: test7: +; AVX2: vpmaxub +} + +define void @test8(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp uge <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.a, <16 x i8> %load.b + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test8: +; SSE2: pmaxub + +; AVX1: test8: +; AVX1: vpmaxub + +; AVX2: test8: +; AVX2: vpmaxub +} + +define void @test9(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp slt <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test9: +; SSE2: pminsw + +; AVX1: test9: +; AVX1: vpminsw + +; AVX2: test9: +; AVX2: vpminsw +} + +define void @test10(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp sle <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test10: +; SSE2: pminsw + +; AVX1: test10: +; AVX1: vpminsw + +; AVX2: test10: +; AVX2: vpminsw +} + +define void @test11(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp sgt <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test11: +; SSE2: pmaxsw + +; AVX1: test11: +; AVX1: vpmaxsw + +; AVX2: test11: +; AVX2: vpmaxsw +} + +define void @test12(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp sge <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test12: +; SSE2: pmaxsw + +; AVX1: test12: +; AVX1: vpmaxsw + +; AVX2: test12: +; AVX2: vpmaxsw +} + +define void @test13(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp ult <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test13: +; SSE4: pminuw + +; AVX1: test13: +; AVX1: vpminuw + +; AVX2: test13: +; AVX2: vpminuw +} + +define void @test14(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp ule <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test14: +; SSE4: pminuw + +; AVX1: test14: +; AVX1: vpminuw + +; AVX2: test14: +; AVX2: vpminuw +} + +define void @test15(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp ugt <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test15: +; SSE4: pmaxuw + +; AVX1: test15: +; AVX1: vpmaxuw + +; AVX2: test15: +; AVX2: vpmaxuw +} + +define void @test16(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp uge <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.a, <8 x i16> %load.b + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test16: +; SSE4: pmaxuw + +; AVX1: test16: +; AVX1: vpmaxuw + +; AVX2: test16: +; AVX2: vpmaxuw +} + +define void @test17(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp slt <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test17: +; SSE4: pminsd + +; AVX1: test17: +; AVX1: vpminsd + +; AVX2: test17: +; AVX2: vpminsd +} + +define void @test18(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp sle <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test18: +; SSE4: pminsd + +; AVX1: test18: +; AVX1: vpminsd + +; AVX2: test18: +; AVX2: vpminsd +} + +define void @test19(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp sgt <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test19: +; SSE4: pmaxsd + +; AVX1: test19: +; AVX1: vpmaxsd + +; AVX2: test19: +; AVX2: vpmaxsd +} + +define void @test20(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp sge <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test20: +; SSE4: pmaxsd + +; AVX1: test20: +; AVX1: vpmaxsd + +; AVX2: test20: +; AVX2: vpmaxsd +} + +define void @test21(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp ult <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test21: +; SSE4: pminud + +; AVX1: test21: +; AVX1: vpminud + +; AVX2: test21: +; AVX2: vpminud +} + +define void @test22(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp ule <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test22: +; SSE4: pminud + +; AVX1: test22: +; AVX1: vpminud + +; AVX2: test22: +; AVX2: vpminud +} + +define void @test23(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp ugt <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test23: +; SSE4: pmaxud + +; AVX1: test23: +; AVX1: vpmaxud + +; AVX2: test23: +; AVX2: vpmaxud +} + +define void @test24(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp uge <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.a, <4 x i32> %load.b + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test24: +; SSE4: pmaxud + +; AVX1: test24: +; AVX1: vpmaxud + +; AVX2: test24: +; AVX2: vpmaxud +} + +define void @test25(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp slt <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test25: +; AVX2: vpminsb +} + +define void @test26(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp sle <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test26: +; AVX2: vpminsb +} + +define void @test27(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp sgt <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test27: +; AVX2: vpmaxsb +} + +define void @test28(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp sge <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test28: +; AVX2: vpmaxsb +} + +define void @test29(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp ult <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test29: +; AVX2: vpminub +} + +define void @test30(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp ule <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test30: +; AVX2: vpminub +} + +define void @test31(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp ugt <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test31: +; AVX2: vpmaxub +} + +define void @test32(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp uge <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.a, <32 x i8> %load.b + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test32: +; AVX2: vpmaxub +} + +define void @test33(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp slt <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test33: +; AVX2: vpminsw +} + +define void @test34(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp sle <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test34: +; AVX2: vpminsw +} + +define void @test35(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp sgt <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test35: +; AVX2: vpmaxsw +} + +define void @test36(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp sge <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test36: +; AVX2: vpmaxsw +} + +define void @test37(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp ult <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test37: +; AVX2: vpminuw +} + +define void @test38(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp ule <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test38: +; AVX2: vpminuw +} + +define void @test39(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp ugt <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test39: +; AVX2: vpmaxuw +} + +define void @test40(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp uge <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.a, <16 x i16> %load.b + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test40: +; AVX2: vpmaxuw +} + +define void @test41(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp slt <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test41: +; AVX2: vpminsd +} + +define void @test42(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp sle <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test42: +; AVX2: vpminsd +} + +define void @test43(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp sgt <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test43: +; AVX2: vpmaxsd +} + +define void @test44(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp sge <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test44: +; AVX2: vpmaxsd +} + +define void @test45(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp ult <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test45: +; AVX2: vpminud +} + +define void @test46(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp ule <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test46: +; AVX2: vpminud +} + +define void @test47(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp ugt <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test47: +; AVX2: vpmaxud +} + +define void @test48(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp uge <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.a, <8 x i32> %load.b + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test48: +; AVX2: vpmaxud +} + +define void @test49(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp slt <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test49: +; SSE4: pmaxsb + +; AVX1: test49: +; AVX1: vpmaxsb + +; AVX2: test49: +; AVX2: vpmaxsb +} + +define void @test50(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp sle <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test50: +; SSE4: pmaxsb + +; AVX1: test50: +; AVX1: vpmaxsb + +; AVX2: test50: +; AVX2: vpmaxsb +} + +define void @test51(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp sgt <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test51: +; SSE4: pminsb + +; AVX1: test51: +; AVX1: vpminsb + +; AVX2: test51: +; AVX2: vpminsb +} + +define void @test52(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp sge <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test52: +; SSE4: pminsb + +; AVX1: test52: +; AVX1: vpminsb + +; AVX2: test52: +; AVX2: vpminsb +} + +define void @test53(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp ult <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test53: +; SSE2: pmaxub + +; AVX1: test53: +; AVX1: vpmaxub + +; AVX2: test53: +; AVX2: vpmaxub +} + +define void @test54(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp ule <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test54: +; SSE2: pmaxub + +; AVX1: test54: +; AVX1: vpmaxub + +; AVX2: test54: +; AVX2: vpmaxub +} + +define void @test55(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp ugt <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test55: +; SSE2: pminub + +; AVX1: test55: +; AVX1: vpminub + +; AVX2: test55: +; AVX2: vpminub +} + +define void @test56(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <16 x i8>* + %ptr.b = bitcast i8* %gep.b to <16 x i8>* + %load.a = load <16 x i8>* %ptr.a, align 2 + %load.b = load <16 x i8>* %ptr.b, align 2 + %cmp = icmp uge <16 x i8> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i8> %load.b, <16 x i8> %load.a + store <16 x i8> %sel, <16 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test56: +; SSE2: pminub + +; AVX1: test56: +; AVX1: vpminub + +; AVX2: test56: +; AVX2: vpminub +} + +define void @test57(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp slt <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test57: +; SSE2: pmaxsw + +; AVX1: test57: +; AVX1: vpmaxsw + +; AVX2: test57: +; AVX2: vpmaxsw +} + +define void @test58(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp sle <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test58: +; SSE2: pmaxsw + +; AVX1: test58: +; AVX1: vpmaxsw + +; AVX2: test58: +; AVX2: vpmaxsw +} + +define void @test59(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp sgt <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test59: +; SSE2: pminsw + +; AVX1: test59: +; AVX1: vpminsw + +; AVX2: test59: +; AVX2: vpminsw +} + +define void @test60(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp sge <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE2: test60: +; SSE2: pminsw + +; AVX1: test60: +; AVX1: vpminsw + +; AVX2: test60: +; AVX2: vpminsw +} + +define void @test61(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp ult <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test61: +; SSE4: pmaxuw + +; AVX1: test61: +; AVX1: vpmaxuw + +; AVX2: test61: +; AVX2: vpmaxuw +} + +define void @test62(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp ule <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test62: +; SSE4: pmaxuw + +; AVX1: test62: +; AVX1: vpmaxuw + +; AVX2: test62: +; AVX2: vpmaxuw +} + +define void @test63(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp ugt <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test63: +; SSE4: pminuw + +; AVX1: test63: +; AVX1: vpminuw + +; AVX2: test63: +; AVX2: vpminuw +} + +define void @test64(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <8 x i16>* + %ptr.b = bitcast i16* %gep.b to <8 x i16>* + %load.a = load <8 x i16>* %ptr.a, align 2 + %load.b = load <8 x i16>* %ptr.b, align 2 + %cmp = icmp uge <8 x i16> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i16> %load.b, <8 x i16> %load.a + store <8 x i16> %sel, <8 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test64: +; SSE4: pminuw + +; AVX1: test64: +; AVX1: vpminuw + +; AVX2: test64: +; AVX2: vpminuw +} + +define void @test65(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp slt <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test65: +; SSE4: pmaxsd + +; AVX1: test65: +; AVX1: vpmaxsd + +; AVX2: test65: +; AVX2: vpmaxsd +} + +define void @test66(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp sle <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test66: +; SSE4: pmaxsd + +; AVX1: test66: +; AVX1: vpmaxsd + +; AVX2: test66: +; AVX2: vpmaxsd +} + +define void @test67(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp sgt <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test67: +; SSE4: pminsd + +; AVX1: test67: +; AVX1: vpminsd + +; AVX2: test67: +; AVX2: vpminsd +} + +define void @test68(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp sge <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test68: +; SSE4: pminsd + +; AVX1: test68: +; AVX1: vpminsd + +; AVX2: test68: +; AVX2: vpminsd +} + +define void @test69(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp ult <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test69: +; SSE4: pmaxud + +; AVX1: test69: +; AVX1: vpmaxud + +; AVX2: test69: +; AVX2: vpmaxud +} + +define void @test70(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp ule <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test70: +; SSE4: pmaxud + +; AVX1: test70: +; AVX1: vpmaxud + +; AVX2: test70: +; AVX2: vpmaxud +} + +define void @test71(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp ugt <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test71: +; SSE4: pminud + +; AVX1: test71: +; AVX1: vpminud + +; AVX2: test71: +; AVX2: vpminud +} + +define void @test72(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <4 x i32>* + %ptr.b = bitcast i32* %gep.b to <4 x i32>* + %load.a = load <4 x i32>* %ptr.a, align 2 + %load.b = load <4 x i32>* %ptr.b, align 2 + %cmp = icmp uge <4 x i32> %load.a, %load.b + %sel = select <4 x i1> %cmp, <4 x i32> %load.b, <4 x i32> %load.a + store <4 x i32> %sel, <4 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 4 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; SSE4: test72: +; SSE4: pminud + +; AVX1: test72: +; AVX1: vpminud + +; AVX2: test72: +; AVX2: vpminud +} + +define void @test73(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp slt <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test73: +; AVX2: vpmaxsb +} + +define void @test74(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp sle <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test74: +; AVX2: vpmaxsb +} + +define void @test75(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp sgt <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test75: +; AVX2: vpminsb +} + +define void @test76(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp sge <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test76: +; AVX2: vpminsb +} + +define void @test77(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp ult <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test77: +; AVX2: vpmaxub +} + +define void @test78(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp ule <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test78: +; AVX2: vpmaxub +} + +define void @test79(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp ugt <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test79: +; AVX2: vpminub +} + +define void @test80(i8* nocapture %a, i8* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i8* %a, i64 %index + %gep.b = getelementptr inbounds i8* %b, i64 %index + %ptr.a = bitcast i8* %gep.a to <32 x i8>* + %ptr.b = bitcast i8* %gep.b to <32 x i8>* + %load.a = load <32 x i8>* %ptr.a, align 2 + %load.b = load <32 x i8>* %ptr.b, align 2 + %cmp = icmp uge <32 x i8> %load.a, %load.b + %sel = select <32 x i1> %cmp, <32 x i8> %load.b, <32 x i8> %load.a + store <32 x i8> %sel, <32 x i8>* %ptr.a, align 2 + %index.next = add i64 %index, 32 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test80: +; AVX2: vpminub +} + +define void @test81(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp slt <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test81: +; AVX2: vpmaxsw +} + +define void @test82(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp sle <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test82: +; AVX2: vpmaxsw +} + +define void @test83(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp sgt <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test83: +; AVX2: vpminsw +} + +define void @test84(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp sge <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test84: +; AVX2: vpminsw +} + +define void @test85(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp ult <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test85: +; AVX2: vpmaxuw +} + +define void @test86(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp ule <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test86: +; AVX2: vpmaxuw +} + +define void @test87(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp ugt <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test87: +; AVX2: vpminuw +} + +define void @test88(i16* nocapture %a, i16* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i16* %a, i64 %index + %gep.b = getelementptr inbounds i16* %b, i64 %index + %ptr.a = bitcast i16* %gep.a to <16 x i16>* + %ptr.b = bitcast i16* %gep.b to <16 x i16>* + %load.a = load <16 x i16>* %ptr.a, align 2 + %load.b = load <16 x i16>* %ptr.b, align 2 + %cmp = icmp uge <16 x i16> %load.a, %load.b + %sel = select <16 x i1> %cmp, <16 x i16> %load.b, <16 x i16> %load.a + store <16 x i16> %sel, <16 x i16>* %ptr.a, align 2 + %index.next = add i64 %index, 16 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test88: +; AVX2: vpminuw +} + +define void @test89(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp slt <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test89: +; AVX2: vpmaxsd +} + +define void @test90(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp sle <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test90: +; AVX2: vpmaxsd +} + +define void @test91(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp sgt <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test91: +; AVX2: vpminsd +} + +define void @test92(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp sge <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test92: +; AVX2: vpminsd +} + +define void @test93(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp ult <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test93: +; AVX2: vpmaxud +} + +define void @test94(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp ule <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test94: +; AVX2: vpmaxud +} + +define void @test95(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp ugt <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test95: +; AVX2: vpminud +} + +define void @test96(i32* nocapture %a, i32* nocapture %b) nounwind { +vector.ph: + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %gep.a = getelementptr inbounds i32* %a, i64 %index + %gep.b = getelementptr inbounds i32* %b, i64 %index + %ptr.a = bitcast i32* %gep.a to <8 x i32>* + %ptr.b = bitcast i32* %gep.b to <8 x i32>* + %load.a = load <8 x i32>* %ptr.a, align 2 + %load.b = load <8 x i32>* %ptr.b, align 2 + %cmp = icmp uge <8 x i32> %load.a, %load.b + %sel = select <8 x i1> %cmp, <8 x i32> %load.b, <8 x i32> %load.a + store <8 x i32> %sel, <8 x i32>* %ptr.a, align 2 + %index.next = add i64 %index, 8 + %loop = icmp eq i64 %index.next, 16384 + br i1 %loop, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void + +; AVX2: test96: +; AVX2: vpminud +} diff --git a/test/CodeGen/X86/vsplit-and.ll b/test/CodeGen/X86/vsplit-and.ll index ee98806c0f8b1..3b7fdff84e3c2 100644 --- a/test/CodeGen/X86/vsplit-and.ll +++ b/test/CodeGen/X86/vsplit-and.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn | FileCheck %s define void @t0(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly { ; CHECK: t0 diff --git a/test/CodeGen/X86/wide-fma-contraction.ll b/test/CodeGen/X86/wide-fma-contraction.ll new file mode 100644 index 0000000000000..d93f33ba0e581 --- /dev/null +++ b/test/CodeGen/X86/wide-fma-contraction.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s + +; CHECK: fmafunc +define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) { +; CHECK-NOT: vmulps +; CHECK-NOT: vaddps +; CHECK: vfmaddps +; CHECK-NOT: vmulps +; CHECK-NOT: vaddps +; CHECK: vfmaddps +; CHECK-NOT: vmulps +; CHECK-NOT: vaddps + %ret = tail call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c) + ret <16 x float> %ret +} + +declare <16 x float> @llvm.fmuladd.v16f32(<16 x float>, <16 x float>, <16 x float>) nounwind readnone + + + diff --git a/test/CodeGen/X86/win32_sret.ll b/test/CodeGen/X86/win32_sret.ll index 878c6db99286f..52b987e2be659 100644 --- a/test/CodeGen/X86/win32_sret.ll +++ b/test/CodeGen/X86/win32_sret.ll @@ -1,28 +1,127 @@ -; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN_X32 -; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X32 +; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 +; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X86 ; RUN: llc < %s -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX -; RUN: llc < %s -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN_X32 -; RUN: llc < %s -O0 -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X32 +; RUN: llc < %s -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 +; RUN: llc < %s -O0 -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X86 ; RUN: llc < %s -O0 -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX ; The SysV ABI used by most Unixes and Mingw on x86 specifies that an sret pointer ; is callee-cleanup. However, in MSVC's cdecl calling convention, sret pointer ; arguments are caller-cleanup like normal arguments. -define void @sret1(i8* sret) nounwind { +define void @sret1(i8* sret %x) nounwind { entry: -; WIN_X32: {{ret$}} -; MINGW_X32: ret $4 +; WIN32: sret1 +; WIN32: movb $42, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret1 +; MINGW_X86: ret $4 + +; LINUX: sret1 ; LINUX: ret $4 + + store i8 42, i8* %x, align 4 ret void } -define void @sret2(i32* sret %x, i32 %y) nounwind { +define void @sret2(i8* sret %x, i8 %y) nounwind { entry: -; WIN_X32: {{ret$}} -; MINGW_X32: ret $4 +; WIN32: sret2 +; WIN32: movb {{.*}}, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret2 +; MINGW_X86: ret $4 + +; LINUX: sret2 ; LINUX: ret $4 - store i32 %y, i32* %x + + store i8 %y, i8* %x + ret void +} + +define void @sret3(i8* sret %x, i8* %y) nounwind { +entry: +; WIN32: sret3 +; WIN32: movb $42, (%eax) +; WIN32-NOT: movb $13, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret3 +; MINGW_X86: ret $4 + +; LINUX: sret3 +; LINUX: ret $4 + + store i8 42, i8* %x + store i8 13, i8* %y + ret void +} + +; PR15556 +%struct.S4 = type { i32, i32, i32 } + +define void @sret4(%struct.S4* noalias sret %agg.result) { +entry: +; WIN32: sret4 +; WIN32: movl $42, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret4 +; MINGW_X86: ret $4 + +; LINUX: sret4 +; LINUX: ret $4 + + %x = getelementptr inbounds %struct.S4* %agg.result, i32 0, i32 0 + store i32 42, i32* %x, align 4 ret void } +%struct.S5 = type { i32 } +%class.C5 = type { i8 } + +define x86_thiscallcc void @"\01?foo@C5@@QAE?AUS5@@XZ"(%struct.S5* noalias sret %agg.result, %class.C5* %this) { +entry: + %this.addr = alloca %class.C5*, align 4 + store %class.C5* %this, %class.C5** %this.addr, align 4 + %this1 = load %class.C5** %this.addr + %x = getelementptr inbounds %struct.S5* %agg.result, i32 0, i32 0 + store i32 42, i32* %x, align 4 + ret void +; WIN32: {{^}}"?foo@C5@@QAE?AUS5@@XZ": + +; The address of the return structure is passed as an implicit parameter. +; In the -O0 build, %eax is spilled at the beginning of the function, hence we +; should match both 4(%esp) and 8(%esp). +; WIN32: {{[48]}}(%esp), %eax +; WIN32: movl $42, (%eax) +; WIN32: ret $4 +} + +define void @call_foo5() { +entry: + %c = alloca %class.C5, align 1 + %s = alloca %struct.S5, align 4 + call x86_thiscallcc void @"\01?foo@C5@@QAE?AUS5@@XZ"(%struct.S5* sret %s, %class.C5* %c) +; WIN32: {{^}}_call_foo5: + +; Load the address of the result and put it onto stack +; (through %ecx in the -O0 build). +; WIN32: leal {{[0-9]+}}(%esp), %eax +; WIN32: movl %eax, (%e{{[sc][px]}}) + +; The this pointer goes to ECX. +; FIXME: for some reason, the below checks fail on the Ubuntu Atom D2700 bot. +; FIXME-NEXT: leal {{[0-9]+}}(%esp), %ecx +; FIXME-NEXT: calll "?foo@C5@@QAE?AUS5@@XZ" + +; WIN32: calll "?foo@C5@@QAE?AUS5@@XZ" +; WIN32: ret + ret void +} diff --git a/test/CodeGen/X86/win_ftol2.ll b/test/CodeGen/X86/win_ftol2.ll index 596b4262e6b09..14591248f354e 100644 --- a/test/CodeGen/X86/win_ftol2.ll +++ b/test/CodeGen/X86/win_ftol2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=FTOL +; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=generic | FileCheck %s -check-prefix=FTOL ; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=COMPILERRT ; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s -check-prefix=COMPILERRT ; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=COMPILERRT @@ -63,9 +63,9 @@ define i64 @double_ui64_2(double %x, double %y, double %z) nounwind { %1 = fdiv double %x, %y %2 = fsub double %x, %z - %3 = fptoui double %1 to i64 - %4 = fptoui double %2 to i64 - %5 = sub i64 %3, %4 + %3 = fptoui double %2 to i64 + %4 = fptoui double %1 to i64 + %5 = sub i64 %4, %3 ret i64 %5 } @@ -121,9 +121,9 @@ define {double, i64} @double_ui64_4(double %x, double %y) nounwind { ; FTOL_2: calll __ftol2 ;; stack is %x - %1 = fptoui double %x to i64 - %2 = fptoui double %y to i64 - %3 = sub i64 %1, %2 + %1 = fptoui double %y to i64 + %2 = fptoui double %x to i64 + %3 = sub i64 %2, %1 %4 = insertvalue {double, i64} undef, double %x, 0 %5 = insertvalue {double, i64} %4, i64 %3, 1 ret {double, i64} %5 diff --git a/test/CodeGen/X86/x86-64-dead-stack-adjust.ll b/test/CodeGen/X86/x86-64-dead-stack-adjust.ll index 902c9d5ae081d..9c01f16f24f54 100644 --- a/test/CodeGen/X86/x86-64-dead-stack-adjust.ll +++ b/test/CodeGen/X86/x86-64-dead-stack-adjust.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mcpu=nehalem | not grep rsp -; RUN: llc < %s -mcpu=nehalem | grep cvttsd2siq +; RUN: llc < %s -mcpu=nehalem | grep cvttsd2si target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin8" diff --git a/test/CodeGen/X86/x86-64-ptr-arg-simple.ll b/test/CodeGen/X86/x86-64-ptr-arg-simple.ll new file mode 100644 index 0000000000000..6d466639890b4 --- /dev/null +++ b/test/CodeGen/X86/x86-64-ptr-arg-simple.ll @@ -0,0 +1,29 @@ +; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s + +; %in is kept in %esi for both ABIs. But the pointer will be passed in %edi +; for x32, not %rdi + +; CHECK: movl %esi, (%rdi) +; X32ABI: movl %esi, (%edi) + +define void @foo(i32* nocapture %out, i32 %in) nounwind { +entry: + store i32 %in, i32* %out, align 4 + ret void +} + +; CHECK: bar +; CHECK: movl (%rsi), %eax + +; Similarly here, but for loading +; X32ABI: bar +; X32ABI: movl (%esi), %eax + +define void @bar(i32* nocapture %pOut, i32* nocapture %pIn) nounwind { +entry: + %0 = load i32* %pIn, align 4 + store i32 %0, i32* %pOut, align 4 + ret void +} + diff --git a/test/CodeGen/X86/x86-64-sret-return.ll b/test/CodeGen/X86/x86-64-sret-return.ll index 7b5f189faa0fa..bc8a543465808 100644 --- a/test/CodeGen/X86/x86-64-sret-return.ll +++ b/test/CodeGen/X86/x86-64-sret-return.ll @@ -1,11 +1,16 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin8 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-apple-darwin8" - %struct.foo = type { [4 x i64] } +%struct.foo = type { [4 x i64] } ; CHECK: bar: ; CHECK: movq %rdi, %rax + +; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used +; X32ABI: bar: +; X32ABI: movl %edi, %eax + define void @bar(%struct.foo* noalias sret %agg.result, %struct.foo* %d) nounwind { entry: %d_addr = alloca %struct.foo* ; <%struct.foo**> [#uses=2] @@ -57,6 +62,11 @@ return: ; preds = %entry ; CHECK: foo: ; CHECK: movq %rdi, %rax + +; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used +; X32ABI: foo: +; X32ABI: movl %edi, %eax + define void @foo({ i64 }* noalias nocapture sret %agg.result) nounwind { store { i64 } { i64 0 }, { i64 }* %agg.result ret void diff --git a/test/CodeGen/X86/xtest.ll b/test/CodeGen/X86/xtest.ll new file mode 100644 index 0000000000000..e85565edcd551 --- /dev/null +++ b/test/CodeGen/X86/xtest.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86-64 -mattr=+rtm | FileCheck %s + +declare i32 @llvm.x86.xtest() nounwind + +define i32 @test_xtest() nounwind uwtable { +entry: + %0 = tail call i32 @llvm.x86.xtest() nounwind + ret i32 %0 +; CHECK: test_xtest +; CHECK: xtest +} diff --git a/test/CodeGen/X86/zero-remat.ll b/test/CodeGen/X86/zero-remat.ll index 4242530f7731f..5d25a2d749719 100644 --- a/test/CodeGen/X86/zero-remat.ll +++ b/test/CodeGen/X86/zero-remat.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64 ; RUN: llc < %s -march=x86-64 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 12 ; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32 |