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-rw-r--r--test/CodeGen/builtins-arm.c125
1 files changed, 104 insertions, 21 deletions
diff --git a/test/CodeGen/builtins-arm.c b/test/CodeGen/builtins-arm.c
index 4cec84c33728d..a385bd27546a4 100644
--- a/test/CodeGen/builtins-arm.c
+++ b/test/CodeGen/builtins-arm.c
@@ -1,5 +1,6 @@
-// REQUIRES: arm-registered-target
-// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -O3 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+#include <stdint.h>
void *f0()
{
@@ -85,16 +86,86 @@ void prefetch(int i) {
// CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 0)
}
+void ldc(const void *i) {
+ // CHECK: define void @ldc(i8* %i)
+ // CHECK: call void @llvm.arm.ldc(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_ldc(1, 2, i);
+}
+
+void ldcl(const void *i) {
+ // CHECK: define void @ldcl(i8* %i)
+ // CHECK: call void @llvm.arm.ldcl(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_ldcl(1, 2, i);
+}
+
+void ldc2(const void *i) {
+ // CHECK: define void @ldc2(i8* %i)
+ // CHECK: call void @llvm.arm.ldc2(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_ldc2(1, 2, i);
+}
+
+void ldc2l(const void *i) {
+ // CHECK: define void @ldc2l(i8* %i)
+ // CHECK: call void @llvm.arm.ldc2l(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_ldc2l(1, 2, i);
+}
+
+void stc(void *i) {
+ // CHECK: define void @stc(i8* %i)
+ // CHECK: call void @llvm.arm.stc(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_stc(1, 2, i);
+}
+
+void stcl(void *i) {
+ // CHECK: define void @stcl(i8* %i)
+ // CHECK: call void @llvm.arm.stcl(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_stcl(1, 2, i);
+}
+
+void stc2(void *i) {
+ // CHECK: define void @stc2(i8* %i)
+ // CHECK: call void @llvm.arm.stc2(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_stc2(1, 2, i);
+}
+
+void stc2l(void *i) {
+ // CHECK: define void @stc2l(i8* %i)
+ // CHECK: call void @llvm.arm.stc2l(i32 1, i32 2, i8* %i)
+ // CHECK-NEXT: ret void
+ __builtin_arm_stc2l(1, 2, i);
+}
+
+void cdp() {
+ // CHECK: define void @cdp()
+ // CHECK: call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
+ // CHECK-NEXT: ret void
+ __builtin_arm_cdp(1, 2, 3, 4, 5, 6);
+}
+
+void cdp2() {
+ // CHECK: define void @cdp2()
+ // CHECK: call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
+ // CHECK-NEXT: ret void
+ __builtin_arm_cdp2(1, 2, 3, 4, 5, 6);
+}
+
unsigned mrc() {
// CHECK: define i32 @mrc()
- // CHECK: [[R:%.*]] = {{.*}} call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
+ // CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3)
// CHECK-NEXT: ret i32 [[R]]
return __builtin_arm_mrc(15, 0, 13, 0, 3);
}
unsigned mrc2() {
// CHECK: define i32 @mrc2()
- // CHECK: [[R:%.*]] = {{.*}} call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
+ // CHECK: [[R:%.*]] = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3)
// CHECK-NEXT: ret i32 [[R]]
return __builtin_arm_mrc2(15, 0, 13, 0, 3);
}
@@ -111,53 +182,65 @@ void mcr2(unsigned a) {
__builtin_arm_mcr2(15, 0, a, 13, 0, 3);
}
-void mcrr(unsigned a, unsigned b) {
- // CHECK: define void @mcrr(i32 [[A:%.*]], i32 [[B:%.*]])
- // CHECK: call void @llvm.arm.mcrr(i32 15, i32 0, i32 [[A]], i32 [[B]], i32 0)
- __builtin_arm_mcrr(15, 0, a, b, 0);
+void mcrr(uint64_t a) {
+ // CHECK: define void @mcrr(i64 %{{.*}})
+ // CHECK: call void @llvm.arm.mcrr(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0)
+ __builtin_arm_mcrr(15, 0, a, 0);
+}
+
+void mcrr2(uint64_t a) {
+ // CHECK: define void @mcrr2(i64 %{{.*}})
+ // CHECK: call void @llvm.arm.mcrr2(i32 15, i32 0, i32 %{{[0-9]+}}, i32 %{{[0-9]+}}, i32 0)
+ __builtin_arm_mcrr2(15, 0, a, 0);
+}
+
+uint64_t mrrc() {
+ // CHECK: define i64 @mrrc()
+ // CHECK: call { i32, i32 } @llvm.arm.mrrc(i32 15, i32 0, i32 0)
+ return __builtin_arm_mrrc(15, 0, 0);
}
-void mcrr2(unsigned a, unsigned b) {
- // CHECK: define void @mcrr2(i32 [[A:%.*]], i32 [[B:%.*]])
- // CHECK: call void @llvm.arm.mcrr2(i32 15, i32 0, i32 [[A]], i32 [[B]], i32 0)
- __builtin_arm_mcrr2(15, 0, a, b, 0);
+uint64_t mrrc2() {
+ // CHECK: define i64 @mrrc2()
+ // CHECK: call { i32, i32 } @llvm.arm.mrrc2(i32 15, i32 0, i32 0)
+ return __builtin_arm_mrrc2(15, 0, 0);
}
unsigned rsr() {
- // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i32 @llvm.read_register.i32(metadata !7)
+ // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M0:.*]])
// CHECK-NEXT: ret i32 [[V0]]
return __builtin_arm_rsr("cp1:2:c3:c4:5");
}
unsigned long long rsr64() {
- // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata !8)
+ // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M1:.*]])
// CHECK-NEXT: ret i64 [[V0]]
return __builtin_arm_rsr64("cp1:2:c3");
}
void *rsrp() {
- // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i32 @llvm.read_register.i32(metadata !9)
+ // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M2:.*]])
// CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to i8*
// CHECK-NEXT: ret i8* [[V1]]
return __builtin_arm_rsrp("sysreg");
}
void wsr(unsigned v) {
- // CHECK: call void @llvm.write_register.i32(metadata !7, i32 %v)
+ // CHECK: call void @llvm.write_register.i32(metadata ![[M0]], i32 %v)
__builtin_arm_wsr("cp1:2:c3:c4:5", v);
}
void wsr64(unsigned long long v) {
- // CHECK: call void @llvm.write_register.i64(metadata !8, i64 %v)
+ // CHECK: call void @llvm.write_register.i64(metadata ![[M1]], i64 %v)
__builtin_arm_wsr64("cp1:2:c3", v);
}
void wsrp(void *v) {
// CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i32
- // CHECK-NEXT: call void @llvm.write_register.i32(metadata !9, i32 [[V0]])
+ // CHECK-NEXT: call void @llvm.write_register.i32(metadata ![[M2]], i32 [[V0]])
__builtin_arm_wsrp("sysreg", v);
}
-// CHECK: !7 = !{!"cp1:2:c3:c4:5"}
-// CHECK: !8 = !{!"cp1:2:c3"}
-// CHECK: !9 = !{!"sysreg"}
+// CHECK: ![[M0]] = !{!"cp1:2:c3:c4:5"}
+// CHECK: ![[M1]] = !{!"cp1:2:c3"}
+// CHECK: ![[M2]] = !{!"sysreg"}
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