diff options
Diffstat (limited to 'test/CodeGen')
50 files changed, 335 insertions, 89 deletions
diff --git a/test/CodeGen/64bit-swiftcall.c b/test/CodeGen/64bit-swiftcall.c index c1f098172371e..06c3145015529 100644 --- a/test/CodeGen/64bit-swiftcall.c +++ b/test/CodeGen/64bit-swiftcall.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64 // REQUIRES: aarch64-registered-target,x86-registered-target @@ -60,6 +61,7 @@ SWIFTCALL void context_error_2(short s, CONTEXT int *self, ERROR float **error) /********************************** LOWERING *********************************/ /*****************************************************************************/ +typedef float float3 __attribute__((ext_vector_type(3))); typedef float float4 __attribute__((ext_vector_type(4))); typedef float float8 __attribute__((ext_vector_type(8))); typedef double double2 __attribute__((ext_vector_type(2))); @@ -1005,3 +1007,10 @@ struct { TEST(union_het_vecint) // CHECK: define swiftcc void @return_union_het_vecint([[UNION:%.*]]* noalias sret // CHECK: define swiftcc void @take_union_het_vecint([[UNION]]* + +typedef struct { + float3 f3; +} struct_v1f3; +TEST(struct_v1f3) +// ARM64-LABEL: define swiftcc { <2 x float>, float } @return_struct_v1f3() +// ARM64-LABEL: define swiftcc void @take_struct_v1f3(<2 x float>, float) diff --git a/test/CodeGen/aarch64-neon-2velem.c b/test/CodeGen/aarch64-neon-2velem.c index 2937d7e5b1509..3867b01afb7a8 100644 --- a/test/CodeGen/aarch64-neon-2velem.c +++ b/test/CodeGen/aarch64-neon-2velem.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-3v.c b/test/CodeGen/aarch64-neon-3v.c index 3581f780ffc68..de38e95c44ea2 100644 --- a/test/CodeGen/aarch64-neon-3v.c +++ b/test/CodeGen/aarch64-neon-3v.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-across.c b/test/CodeGen/aarch64-neon-across.c index 6d7a0d5bcde42..767825461b4c3 100644 --- a/test/CodeGen/aarch64-neon-across.c +++ b/test/CodeGen/aarch64-neon-across.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-extract.c b/test/CodeGen/aarch64-neon-extract.c index c84c861b8742e..6b62d9f1cff7f 100644 --- a/test/CodeGen/aarch64-neon-extract.c +++ b/test/CodeGen/aarch64-neon-extract.c @@ -1,6 +1,6 @@ // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-fcvt-intrinsics.c b/test/CodeGen/aarch64-neon-fcvt-intrinsics.c index f2c238ebeb351..929a6501df77f 100644 --- a/test/CodeGen/aarch64-neon-fcvt-intrinsics.c +++ b/test/CodeGen/aarch64-neon-fcvt-intrinsics.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-fma.c b/test/CodeGen/aarch64-neon-fma.c index 6ada533c66ee4..3a84834e11765 100644 --- a/test/CodeGen/aarch64-neon-fma.c +++ b/test/CodeGen/aarch64-neon-fma.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-intrinsics.c b/test/CodeGen/aarch64-neon-intrinsics.c index 935e762d8c639..bcb680c4b518e 100644 --- a/test/CodeGen/aarch64-neon-intrinsics.c +++ b/test/CodeGen/aarch64-neon-intrinsics.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -fallow-half-arguments-and-returns -S -emit-llvm -o - %s \ +// RUN: -fallow-half-arguments-and-returns -S -disable-O0-optnone -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg \ // RUN: | FileCheck %s diff --git a/test/CodeGen/aarch64-neon-ldst-one.c b/test/CodeGen/aarch64-neon-ldst-one.c index 25bd797b92768..9bd9ab1cb61bf 100644 --- a/test/CodeGen/aarch64-neon-ldst-one.c +++ b/test/CodeGen/aarch64-neon-ldst-one.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/aarch64-neon-misc.c b/test/CodeGen/aarch64-neon-misc.c index 28fc1fe1e3f89..0772d4fc677d5 100644 --- a/test/CodeGen/aarch64-neon-misc.c +++ b/test/CodeGen/aarch64-neon-misc.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-perm.c b/test/CodeGen/aarch64-neon-perm.c index 5b8a99c993fe0..471017a99bbdb 100644 --- a/test/CodeGen/aarch64-neon-perm.c +++ b/test/CodeGen/aarch64-neon-perm.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types #include <arm_neon.h> diff --git a/test/CodeGen/aarch64-neon-scalar-copy.c b/test/CodeGen/aarch64-neon-scalar-copy.c index 90fceb44ed908..28cff5fbf3b97 100644 --- a/test/CodeGen/aarch64-neon-scalar-copy.c +++ b/test/CodeGen/aarch64-neon-scalar-copy.c @@ -1,6 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s - +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c b/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c index 01296c9359331..e85b918d5ace3 100644 --- a/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c +++ b/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-shifts.c b/test/CodeGen/aarch64-neon-shifts.c index 66449f7fef4ca..e9a679bc69a44 100644 --- a/test/CodeGen/aarch64-neon-shifts.c +++ b/test/CodeGen/aarch64-neon-shifts.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/aarch64-neon-tbl.c b/test/CodeGen/aarch64-neon-tbl.c index 0cc66453ac2b7..28881830bfb37 100644 --- a/test/CodeGen/aarch64-neon-tbl.c +++ b/test/CodeGen/aarch64-neon-tbl.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-vcombine.c b/test/CodeGen/aarch64-neon-vcombine.c index 482463cacfe0d..f27017404dc60 100644 --- a/test/CodeGen/aarch64-neon-vcombine.c +++ b/test/CodeGen/aarch64-neon-vcombine.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -fallow-half-arguments-and-returns -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-vget-hilo.c b/test/CodeGen/aarch64-neon-vget-hilo.c index f66bac6a6a3a5..cc4d46dd69b33 100644 --- a/test/CodeGen/aarch64-neon-vget-hilo.c +++ b/test/CodeGen/aarch64-neon-vget-hilo.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \ +// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s // Test new aarch64 intrinsics and types diff --git a/test/CodeGen/aarch64-neon-vget.c b/test/CodeGen/aarch64-neon-vget.c index 87afcee9c8401..ac7bc2d68a436 100644 --- a/test/CodeGen/aarch64-neon-vget.c +++ b/test/CodeGen/aarch64-neon-vget.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon \ -// RUN: -fallow-half-arguments-and-returns -emit-llvm -o - %s \ +// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/aarch64-poly128.c b/test/CodeGen/aarch64-poly128.c index 01c509035f5c7..d33d936717dcf 100644 --- a/test/CodeGen/aarch64-poly128.c +++ b/test/CodeGen/aarch64-poly128.c @@ -1,6 +1,6 @@ // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -ffp-contract=fast -emit-llvm -o - %s | opt -S -mem2reg \ +// RUN: -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - %s | opt -S -mem2reg \ // RUN: | FileCheck %s // Test new aarch64 intrinsics with poly128 diff --git a/test/CodeGen/aarch64-poly64.c b/test/CodeGen/aarch64-poly64.c index eadeda640434a..3fb8048fb39e4 100644 --- a/test/CodeGen/aarch64-poly64.c +++ b/test/CodeGen/aarch64-poly64.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -ffp-contract=fast -emit-llvm -o - %s | opt -S -mem2reg \ +// RUN: -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \ // RUN: | FileCheck %s // Test new aarch64 intrinsics with poly64 diff --git a/test/CodeGen/address-safety-attr-kasan.cpp b/test/CodeGen/address-safety-attr-kasan.cpp index 4d8333d2ffea4..603134db69fbc 100644 --- a/test/CodeGen/address-safety-attr-kasan.cpp +++ b/test/CodeGen/address-safety-attr-kasan.cpp @@ -1,9 +1,9 @@ // Make sure the sanitize_address attribute is emitted when using both ASan and KASan. // Also document that __attribute__((no_sanitize_address)) doesn't disable KASan instrumentation. -/// RUN: %clang_cc1 -triple i386-unknown-linux -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-NOASAN %s -/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=address -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-ASAN %s -/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=kernel-address -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-KASAN %s +/// RUN: %clang_cc1 -triple i386-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-NOASAN %s +/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=address -disable-O0-optnone -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-ASAN %s +/// RUN: %clang_cc1 -triple i386-unknown-linux -fsanitize=kernel-address -disable-O0-optnone -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-KASAN %s int HasSanitizeAddress() { return 1; diff --git a/test/CodeGen/address-safety-attr.cpp b/test/CodeGen/address-safety-attr.cpp index 60faeddbd4ce4..986224092922f 100644 --- a/test/CodeGen/address-safety-attr.cpp +++ b/test/CodeGen/address-safety-attr.cpp @@ -3,16 +3,16 @@ int DefinedInDifferentFile(int *a); // RUN: echo "struct S { S(){} ~S(){} };" >> %t.extra-source.cpp // RUN: echo "S glob_array[5];" >> %t.extra-source.cpp -// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp | FileCheck -check-prefix=WITHOUT %s -// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address | FileCheck -check-prefix=ASAN %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp | FileCheck -check-prefix=WITHOUT %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address | FileCheck -check-prefix=ASAN %s // RUN: echo "fun:*BlacklistedFunction*" > %t.func.blacklist -// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.func.blacklist | FileCheck -check-prefix=BLFUNC %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.func.blacklist | FileCheck -check-prefix=BLFUNC %s // The blacklist file uses regexps, so escape backslashes, which are common in // Windows paths. // RUN: echo "src:%s" | sed -e 's/\\/\\\\/g' > %t.file.blacklist -// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.file.blacklist | FileCheck -check-prefix=BLFILE %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin -disable-O0-optnone -emit-llvm -o - %s -include %t.extra-source.cpp -fsanitize=address -fsanitize-blacklist=%t.file.blacklist | FileCheck -check-prefix=BLFILE %s // The sanitize_address attribute should be attached to functions // when AddressSanitizer is enabled, unless no_sanitize_address attribute diff --git a/test/CodeGen/arm-crc32.c b/test/CodeGen/arm-crc32.c index 8a70d8c78a958..c9aa549cbb3ba 100644 --- a/test/CodeGen/arm-crc32.c +++ b/test/CodeGen/arm-crc32.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s int crc32b(int a, char b) { diff --git a/test/CodeGen/arm-neon-directed-rounding.c b/test/CodeGen/arm-neon-directed-rounding.c index 7471b1c230c9a..b06808a77cd11 100644 --- a/test/CodeGen/arm-neon-directed-rounding.c +++ b/test/CodeGen/arm-neon-directed-rounding.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/arm-neon-fma.c b/test/CodeGen/arm-neon-fma.c index 9311f6be68346..b5184c195e403 100644 --- a/test/CodeGen/arm-neon-fma.c +++ b/test/CodeGen/arm-neon-fma.c @@ -3,7 +3,7 @@ // RUN: -target-cpu cortex-a7 \ // RUN: -mfloat-abi hard \ // RUN: -ffreestanding \ -// RUN: -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/arm-neon-numeric-maxmin.c b/test/CodeGen/arm-neon-numeric-maxmin.c index 38f020a756df3..d4f5674cd9326 100644 --- a/test/CodeGen/arm-neon-numeric-maxmin.c +++ b/test/CodeGen/arm-neon-numeric-maxmin.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/arm-neon-shifts.c b/test/CodeGen/arm-neon-shifts.c index ebaa97fe38843..ec059738ec197 100644 --- a/test/CodeGen/arm-neon-shifts.c +++ b/test/CodeGen/arm-neon-shifts.c @@ -1,5 +1,6 @@ // REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple thumbv7-apple-darwin \ +// RUN: -disable-O0-optnone \ // RUN: -target-cpu cortex-a8 \ // RUN: -ffreestanding \ // RUN: -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s diff --git a/test/CodeGen/arm-neon-vcvtX.c b/test/CodeGen/arm-neon-vcvtX.c index 4ea8fa874e48f..43d48a0a4f184 100644 --- a/test/CodeGen/arm-neon-vcvtX.c +++ b/test/CodeGen/arm-neon-vcvtX.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/arm-neon-vget.c b/test/CodeGen/arm-neon-vget.c index 3bf8905f395f1..841cf0396d461 100644 --- a/test/CodeGen/arm-neon-vget.c +++ b/test/CodeGen/arm-neon-vget.c @@ -4,7 +4,7 @@ // RUN: -mfloat-abi soft \ // RUN: -target-feature +soft-float-abi \ // RUN: -ffreestanding \ -// RUN: -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/arm-swiftcall.c b/test/CodeGen/arm-swiftcall.c index 5a7e17068b7c7..f5c33845e2f4a 100644 --- a/test/CodeGen/arm-swiftcall.c +++ b/test/CodeGen/arm-swiftcall.c @@ -57,6 +57,7 @@ SWIFTCALL void context_error_2(short s, CONTEXT int *self, ERROR float **error) /********************************** LOWERING *********************************/ /*****************************************************************************/ +typedef float float3 __attribute__((ext_vector_type(3))); typedef float float4 __attribute__((ext_vector_type(4))); typedef float float8 __attribute__((ext_vector_type(8))); typedef double double2 __attribute__((ext_vector_type(2))); @@ -1013,3 +1014,10 @@ typedef struct { TEST(struct_vf81) // CHECK-LABEL: define swiftcc { <4 x float>, <4 x float> } @return_struct_vf81() // CHECK-LABEL: define swiftcc void @take_struct_vf81(<4 x float>, <4 x float>) + +typedef struct { + float3 f3; +} struct_v1f3; +TEST(struct_v1f3) +// CHECK-LABEL: define swiftcc { <2 x float>, float } @return_struct_v1f3() +// CHECK-LABEL: define swiftcc void @take_struct_v1f3(<2 x float>, float) diff --git a/test/CodeGen/arm64-crc32.c b/test/CodeGen/arm64-crc32.c index efb51ed407f8b..2d913fb123b7c 100644 --- a/test/CodeGen/arm64-crc32.c +++ b/test/CodeGen/arm64-crc32.c @@ -1,6 +1,6 @@ // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple arm64-none-linux-gnu \ -// RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s int crc32b(int a, char b) { diff --git a/test/CodeGen/arm64-lanes.c b/test/CodeGen/arm64-lanes.c index ea47bae69f470..fde5f848b9ee2 100644 --- a/test/CodeGen/arm64-lanes.c +++ b/test/CodeGen/arm64-lanes.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -target-feature +neon -ffreestanding -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix CHECK-BE +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix CHECK-BE #include <arm_neon.h> diff --git a/test/CodeGen/arm64_vcopy.c b/test/CodeGen/arm64_vcopy.c index 4c0143016fbe8..fc2ad3746ba95 100644 --- a/test/CodeGen/arm64_vcopy.c +++ b/test/CodeGen/arm64_vcopy.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -emit-llvm %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -disable-O0-optnone -emit-llvm %s | opt -S -mem2reg | FileCheck %s // Test ARM64 SIMD copy vector element to vector element: vcopyq_lane* diff --git a/test/CodeGen/arm64_vdupq_n_f64.c b/test/CodeGen/arm64_vdupq_n_f64.c index 58cc7f020e916..e9e814e92a05b 100644 --- a/test/CodeGen/arm64_vdupq_n_f64.c +++ b/test/CodeGen/arm64_vdupq_n_f64.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -fallow-half-arguments-and-returns -S -o - -emit-llvm %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -fallow-half-arguments-and-returns -S -o - -disable-O0-optnone -emit-llvm %s | opt -S -mem2reg | FileCheck %s #include <arm_neon.h> diff --git a/test/CodeGen/attr-coldhot.c b/test/CodeGen/attr-coldhot.c index ec54edde9d777..24e1feb77b4e9 100644 --- a/test/CodeGen/attr-coldhot.c +++ b/test/CodeGen/attr-coldhot.c @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s -check-prefixes=CHECK,O0 +// RUN: %clang_cc1 -emit-llvm %s -o - -O1 -disable-llvm-passes | FileCheck %s -check-prefixes=CHECK,O1 int test1() __attribute__((__cold__)) { return 42; @@ -8,4 +9,5 @@ int test1() __attribute__((__cold__)) { // CHECK: ret } -// CHECK: attributes [[ATTR]] = { {{.*}}cold{{.*}}optsize{{.*}} } +// O0: attributes [[ATTR]] = { {{.*}}cold{{.*}}optnone{{.*}} } +// O1: attributes [[ATTR]] = { {{.*}}cold{{.*}}optsize{{.*}} } diff --git a/test/CodeGen/attr-naked.c b/test/CodeGen/attr-naked.c index 270fc7959f443..34e745b3740a4 100644 --- a/test/CodeGen/attr-naked.c +++ b/test/CodeGen/attr-naked.c @@ -4,14 +4,14 @@ void t1() __attribute__((naked)); // Basic functionality check // (Note that naked needs to imply noinline to work properly.) -// CHECK: define void @t1() [[NAKED:#[0-9]+]] { +// CHECK: define void @t1() [[NAKED_OPTNONE:#[0-9]+]] { void t1() { } // Make sure this doesn't explode in the verifier. // (It doesn't really make sense, but it isn't invalid.) -// CHECK: define void @t2() [[NAKED]] { +// CHECK: define void @t2() [[NAKED:#[0-9]+]] { __attribute((naked, always_inline)) void t2() { } @@ -23,4 +23,5 @@ __attribute((naked)) void t3(int x) { // CHECK: unreachable } +// CHECK: attributes [[NAKED_OPTNONE]] = { naked noinline nounwind optnone{{.*}} } // CHECK: attributes [[NAKED]] = { naked noinline nounwind{{.*}} } diff --git a/test/CodeGen/attr-target-x86.c b/test/CodeGen/attr-target-x86.c index 7557ec7acdd50..f2777679aec13 100644 --- a/test/CodeGen/attr-target-x86.c +++ b/test/CodeGen/attr-target-x86.c @@ -36,7 +36,7 @@ int __attribute__((target("arch=lakemont"))) lake(int a) { return 4; } // CHECK: lake{{.*}} #6 // CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" // CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" -// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt" +// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt" // CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" // CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes" // CHECK: #5 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+sse,+sse2,+x87,-3dnow,-3dnowa,-mmx" diff --git a/test/CodeGen/avx512vpopcntdqintrin.c b/test/CodeGen/avx512vpopcntdqintrin.c new file mode 100644 index 0000000000000..e7c797c195499 --- /dev/null +++ b/test/CodeGen/avx512vpopcntdqintrin.c @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512vpopcntdq -emit-llvm -o - -Wall -Werror | FileCheck %s + +#include <immintrin.h> + +__m512i test_mm512_popcnt_epi64(__m512i __A) { + // CHECK-LABEL: @test_mm512_popcnt_epi64 + // CHECK: @llvm.ctpop.v8i64 + return _mm512_popcnt_epi64(__A); +} +__m512i test_mm512_mask_popcnt_epi64(__m512i __W, __mmask8 __U, __m512i __A) { + // CHECK-LABEL: @test_mm512_mask_popcnt_epi64 + // CHECK: @llvm.ctpop.v8i64 + // CHECK: select <8 x i1> %{{[0-9]+}}, <8 x i64> %{{[0-9]+}}, <8 x i64> {{.*}} + return _mm512_mask_popcnt_epi64(__W, __U, __A); +} +__m512i test_mm512_maskz_popcnt_epi64(__mmask8 __U, __m512i __A) { + // CHECK-LABEL: @test_mm512_maskz_popcnt_epi64 + // CHECK: @llvm.ctpop.v8i64 + // CHECK: select <8 x i1> %{{[0-9]+}}, <8 x i64> %{{[0-9]+}}, <8 x i64> {{.*}} + return _mm512_maskz_popcnt_epi64(__U, __A); +} +__m512i test_mm512_popcnt_epi32(__m512i __A) { + // CHECK-LABEL: @test_mm512_popcnt_epi32 + // CHECK: @llvm.ctpop.v16i32 + return _mm512_popcnt_epi32(__A); +} +__m512i test_mm512_mask_popcnt_epi32(__m512i __W, __mmask16 __U, __m512i __A) { + // CHECK-LABEL: @test_mm512_mask_popcnt_epi32 + // CHECK: @llvm.ctpop.v16i32 + // CHECK: select <16 x i1> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}}, <16 x i32> {{.*}} + return _mm512_mask_popcnt_epi32(__W, __U, __A); +} +__m512i test_mm512_maskz_popcnt_epi32(__mmask16 __U, __m512i __A) { + // CHECK-LABEL: @test_mm512_maskz_popcnt_epi32 + // CHECK: @llvm.ctpop.v16i32 + // CHECK: select <16 x i1> %{{[0-9]+}}, <16 x i32> %{{[0-9]+}}, <16 x i32> {{.*}} + return _mm512_maskz_popcnt_epi32(__U, __A); +} diff --git a/test/CodeGen/builtins-arm-exclusive.c b/test/CodeGen/builtins-arm-exclusive.c index b0bc2b82d316b..56d7798a5e898 100644 --- a/test/CodeGen/builtins-arm-exclusive.c +++ b/test/CodeGen/builtins-arm-exclusive.c @@ -1,6 +1,5 @@ -// RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK-ARM64 - +// RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK-ARM64 struct Simple { char a, b; diff --git a/test/CodeGen/builtins-arm.c b/test/CodeGen/builtins-arm.c index 0dc4c7dd77906..e04349f1a38aa 100644 --- a/test/CodeGen/builtins-arm.c +++ b/test/CodeGen/builtins-arm.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include <stdint.h> diff --git a/test/CodeGen/builtins-arm64.c b/test/CodeGen/builtins-arm64.c index dc5fb6f31cffe..7027a6e220f3d 100644 --- a/test/CodeGen/builtins-arm64.c +++ b/test/CodeGen/builtins-arm64.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-unknown-linux -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s void f0(void *a, void *b) { __clear_cache(a,b); diff --git a/test/CodeGen/builtins-ppc-error.c b/test/CodeGen/builtins-ppc-error.c index e8d2a37a21eda..c3d6e639d8280 100644 --- a/test/CodeGen/builtins-ppc-error.c +++ b/test/CodeGen/builtins-ppc-error.c @@ -13,8 +13,24 @@ extern vector signed int vsi; extern vector unsigned char vuc; -void testInsertWord1(void) { +void testInsertWord(void) { int index = 5; vector unsigned char v1 = vec_insert4b(vsi, vuc, index); // expected-error {{argument to '__builtin_vsx_insertword' must be a constant integer}} vector unsigned long long v2 = vec_extract4b(vuc, index); // expected-error {{argument to '__builtin_vsx_extractuword' must be a constant integer}} } + +void testXXPERMDI(int index) { + vec_xxpermdi(vsi); //expected-error {{too few arguments to function call, expected at least 3, have 1}} + vec_xxpermdi(vsi, vsi, 2, 4); //expected-error {{too many arguments to function call, expected at most 3, have 4}} + vec_xxpermdi(vsi, vsi, index); //expected-error {{argument 3 to '__builtin_vsx_xxpermdi' must be a 2-bit unsigned literal (i.e. 0, 1, 2 or 3)}} + vec_xxpermdi(1, 2, 3); //expected-error {{first two arguments to '__builtin_vsx_xxpermdi' must be vectors}} + vec_xxpermdi(vsi, vuc, 2); //expected-error {{first two arguments to '__builtin_vsx_xxpermdi' must have the same type}} +} + +void testXXSLDWI(int index) { + vec_xxsldwi(vsi); //expected-error {{too few arguments to function call, expected at least 3, have 1}} + vec_xxsldwi(vsi, vsi, 2, 4); //expected-error {{too many arguments to function call, expected at most 3, have 4}} + vec_xxsldwi(vsi, vsi, index); //expected-error {{argument 3 to '__builtin_vsx_xxsldwi' must be a 2-bit unsigned literal (i.e. 0, 1, 2 or 3)}} + vec_xxsldwi(1, 2, 3); //expected-error {{first two arguments to '__builtin_vsx_xxsldwi' must be vectors}} + vec_xxsldwi(vsi, vuc, 2); //expected-error {{first two arguments to '__builtin_vsx_xxsldwi' must have the same type}} +} diff --git a/test/CodeGen/builtins-ppc-vsx.c b/test/CodeGen/builtins-ppc-vsx.c index 9e0052630ef7f..6dda19d5d9f33 100644 --- a/test/CodeGen/builtins-ppc-vsx.c +++ b/test/CodeGen/builtins-ppc-vsx.c @@ -1691,4 +1691,115 @@ vec_xst_be(vd, sll, ad); res_vd = vec_neg(vd); // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, {{%[0-9]+}} // CHECK-LE: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, {{%[0-9]+}} + +res_vd = vec_xxpermdi(vd, vd, 0); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 3, i32 1> + +res_vf = vec_xxpermdi(vf, vf, 1); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 2, i32 1> + +res_vsll = vec_xxpermdi(vsll, vsll, 2); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 3, i32 0> + +res_vull = vec_xxpermdi(vull, vull, 3); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 2, i32 0> + +res_vsi = vec_xxpermdi(vsi, vsi, 0); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 3, i32 1> + +res_vui = vec_xxpermdi(vui, vui, 1); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 2, i32 1> + +res_vss = vec_xxpermdi(vss, vss, 2); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 3, i32 0> + +res_vus = vec_xxpermdi(vus, vus, 3); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 2, i32 0> + +res_vsc = vec_xxpermdi(vsc, vsc, 0); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 3, i32 1> + +res_vuc = vec_xxpermdi(vuc, vuc, 1); +// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3> +// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 2, i32 1> + +res_vd = vec_xxsldwi(vd, vd, 0); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + +res_vf = vec_xxsldwi(vf, vf, 1); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2> + +res_vsll = vec_xxsldwi(vsll, vsll, 2); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1> + +res_vull = vec_xxsldwi(vull, vull, 3); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0> + +res_vsi = vec_xxsldwi(vsi, vsi, 0); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + +res_vui = vec_xxsldwi(vui, vui, 1); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2> + +res_vss = vec_xxsldwi(vss, vss, 2); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1> + + +res_vus = vec_xxsldwi(vus, vus, 3); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0> + +res_vsc = vec_xxsldwi(vsc, vsc, 0); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + +res_vuc = vec_xxsldwi(vuc, vuc, 1); +// CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4> +// CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2> +} + +// The return type of the call expression may be different from the return type of the shufflevector. +// Wrong implementation could crash the compiler, add this test case to check that and avoid ICE. +vector int xxpermdi_should_not_assert(vector int a, vector int b) { + return vec_xxpermdi(a, b, 0); +// CHECK-LABEL: xxpermdi_should_not_assert +// CHECK: bitcast <4 x i32> %{{[0-9]+}} to <2 x i64> +// CHECK-NEXT: bitcast <4 x i32> %{{[0-9]+}} to <2 x i64> +// CHECK-NEXT: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2> +// CHECK-NEXT: bitcast <2 x i64> %{{[0-9]+}} to <4 x i32> + +// CHECK-LE: bitcast <4 x i32> %{{[0-9]+}} to <2 x i64> +// CHECK-LE-NEXT: bitcast <4 x i32> %{{[0-9]+}} to <2 x i64> +// CHECK-LE-NEXT: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 3, i32 1> +// CHECK-LE-NEXT: bitcast <2 x i64> %{{[0-9]+}} to <4 x i32> +} + +vector double xxsldwi_should_not_assert(vector double a, vector double b) { + return vec_xxsldwi(a, b, 0); +// CHECK-LABEL: xxsldwi_should_not_assert +// CHECK: bitcast <2 x double> %{{[0-9]+}} to <4 x i32> +// CHECK-NEXT: bitcast <2 x double> %{{[0-9]+}} to <4 x i32> +// CHECK-NEXT: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +// CHECK-NEXT: bitcast <4 x i32> %{{[0-9]+}} to <2 x double> + +// CHECK-LE: bitcast <2 x double> %{{[0-9]+}} to <4 x i32> +// CHECK-NEXT-LE: bitcast <2 x double> %{{[0-9]+}} to <4 x i32> +// CHECK-NEXT-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> +// CHECK-NEXT-LE: bitcast <4 x i32> %{{[0-9]+}} to <2 x double> } diff --git a/test/CodeGen/mips-varargs.c b/test/CodeGen/mips-varargs.c index 0d656dcfba9df..343914ad8df1a 100644 --- a/test/CodeGen/mips-varargs.c +++ b/test/CodeGen/mips-varargs.c @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -triple mips-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -// RUN: %clang_cc1 -triple mipsel-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -emit-llvm -target-abi n32 %s | FileCheck %s -check-prefix=ALL -check-prefix=N32 -check-prefix=NEW -// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -emit-llvm -target-abi n32 %s | FileCheck %s -check-prefix=ALL -check-prefix=N32 -check-prefix=NEW -// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NEW -// RUN: %clang_cc1 -triple mips64el-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NEW +// RUN: %clang_cc1 -triple mips-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefixes=ALL,O32 -enable-var-scope +// RUN: %clang_cc1 -triple mipsel-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefixes=ALL,O32 -enable-var-scope +// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -emit-llvm -target-abi n32 %s | FileCheck %s -check-prefixes=ALL,N32,NEW -enable-var-scope +// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -emit-llvm -target-abi n32 %s | FileCheck %s -check-prefixes=ALL,N32,NEW -enable-var-scope +// RUN: %clang_cc1 -triple mips64-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefixes=ALL,N64,NEW -enable-var-scope +// RUN: %clang_cc1 -triple mips64el-unknown-linux -o - -emit-llvm %s | FileCheck %s -check-prefixes=ALL,N64,NEW -enable-var-scope #include <stdarg.h> @@ -21,19 +21,19 @@ int test_i32(char *fmt, ...) { // ALL-LABEL: define i32 @test_i32(i8*{{.*}} %fmt, ...) // -// O32: %va = alloca i8*, align [[PTRALIGN:4]] -// N32: %va = alloca i8*, align [[PTRALIGN:4]] -// N64: %va = alloca i8*, align [[PTRALIGN:8]] +// O32: %va = alloca i8*, align [[$PTRALIGN:4]] +// N32: %va = alloca i8*, align [[$PTRALIGN:4]] +// N64: %va = alloca i8*, align [[$PTRALIGN:8]] // ALL: [[V:%.*]] = alloca i32, align 4 // NEW: [[PROMOTION_TEMP:%.*]] = alloca i32, align 4 // // ALL: [[VA:%.+]] = bitcast i8** %va to i8* // ALL: call void @llvm.va_start(i8* [[VA]]) -// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]] -// O32: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[INTPTR_T:i32]] [[CHUNKSIZE:4]] -// NEW: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[INTPTR_T:i32|i64]] [[CHUNKSIZE:8]] +// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[$PTRALIGN]] +// O32: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[$INTPTR_T:i32]] [[$CHUNKSIZE:4]] +// NEW: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[$INTPTR_T:i32|i64]] [[$CHUNKSIZE:8]] // -// ALL: store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]] +// ALL: store i8* [[AP_NEXT]], i8** %va, align [[$PTRALIGN]] // // O32: [[AP_CAST:%.+]] = bitcast i8* [[AP_CUR]] to [[CHUNK_T:i32]]* // O32: [[ARG:%.+]] = load i32, i32* [[AP_CAST]], align [[CHUNKALIGN:4]] @@ -63,10 +63,10 @@ long long test_i64(char *fmt, ...) { // ALL-LABEL: define i64 @test_i64(i8*{{.*}} %fmt, ...) // -// ALL: %va = alloca i8*, align [[PTRALIGN]] +// ALL: %va = alloca i8*, align [[$PTRALIGN]] // ALL: [[VA:%.+]] = bitcast i8** %va to i8* // ALL: call void @llvm.va_start(i8* [[VA]]) -// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]] +// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[$PTRALIGN]] // // i64 is 8-byte aligned, while this is within O32's stack alignment there's no // guarantee that the offset is still 8-byte aligned after earlier reads. @@ -75,8 +75,8 @@ long long test_i64(char *fmt, ...) { // O32: [[TMP3:%.+]] = and i32 [[TMP2]], -8 // O32: [[AP_CUR:%.+]] = inttoptr i32 [[TMP3]] to i8* // -// ALL: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[INTPTR_T]] 8 -// ALL: store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]] +// ALL: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[$INTPTR_T]] 8 +// ALL: store i8* [[AP_NEXT]], i8** %va, align [[$PTRALIGN]] // // ALL: [[AP_CAST:%.*]] = bitcast i8* [[AP_CUR]] to i64* // ALL: [[ARG:%.+]] = load i64, i64* [[AP_CAST]], align 8 @@ -97,14 +97,14 @@ char *test_ptr(char *fmt, ...) { // ALL-LABEL: define i8* @test_ptr(i8*{{.*}} %fmt, ...) // -// ALL: %va = alloca i8*, align [[PTRALIGN]] -// ALL: [[V:%.*]] = alloca i8*, align [[PTRALIGN]] +// ALL: %va = alloca i8*, align [[$PTRALIGN]] +// ALL: [[V:%.*]] = alloca i8*, align [[$PTRALIGN]] // N32: [[AP_CAST:%.+]] = alloca i8*, align 4 // ALL: [[VA:%.+]] = bitcast i8** %va to i8* // ALL: call void @llvm.va_start(i8* [[VA]]) -// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]] -// ALL: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[INTPTR_T]] [[CHUNKSIZE]] -// ALL: store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]] +// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[$PTRALIGN]] +// ALL: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[$INTPTR_T]] [[$CHUNKSIZE]] +// ALL: store i8* [[AP_NEXT]], i8** %va, align [[$PTRALIGN]] // // When the chunk size matches the pointer size, this is easy. // O32: [[AP_CAST:%.+]] = bitcast i8* [[AP_CUR]] to i8** @@ -116,8 +116,8 @@ char *test_ptr(char *fmt, ...) { // N32: [[PTR:%.+]] = inttoptr i32 [[TMP3]] to i8* // N32: store i8* [[PTR]], i8** [[AP_CAST]], align 4 // -// ALL: [[ARG:%.+]] = load i8*, i8** [[AP_CAST]], align [[PTRALIGN]] -// ALL: store i8* [[ARG]], i8** [[V]], align [[PTRALIGN]] +// ALL: [[ARG:%.+]] = load i8*, i8** [[AP_CAST]], align [[$PTRALIGN]] +// ALL: store i8* [[ARG]], i8** [[V]], align [[$PTRALIGN]] // // ALL: [[VA1:%.+]] = bitcast i8** %va to i8* // ALL: call void @llvm.va_end(i8* [[VA1]]) @@ -135,11 +135,11 @@ int test_v4i32(char *fmt, ...) { // ALL-LABEL: define i32 @test_v4i32(i8*{{.*}} %fmt, ...) // -// ALL: %va = alloca i8*, align [[PTRALIGN]] -// ALL: [[V]] = alloca <4 x i32>, align 16 +// ALL: %va = alloca i8*, align [[$PTRALIGN]] +// ALL: [[V:%.+]] = alloca <4 x i32>, align 16 // ALL: [[VA1:%.+]] = bitcast i8** %va to i8* // ALL: call void @llvm.va_start(i8* [[VA1]]) -// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]] +// ALL: [[AP_CUR:%.+]] = load i8*, i8** %va, align [[$PTRALIGN]] // // Vectors are 16-byte aligned, however the O32 ABI has a maximum alignment of // 8-bytes since the base of the stack is 8-byte aligned. @@ -148,17 +148,18 @@ int test_v4i32(char *fmt, ...) { // O32: [[TMP3:%.+]] = and i32 [[TMP2]], -8 // O32: [[AP_CUR:%.+]] = inttoptr i32 [[TMP3]] to i8* // -// NEW: [[TMP1:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T]] -// NEW: [[TMP2:%.+]] = add [[INTPTR_T]] [[TMP1]], 15 -// NEW: [[TMP3:%.+]] = and [[INTPTR_T]] [[TMP2]], -16 -// NEW: [[AP_CUR:%.+]] = inttoptr [[INTPTR_T]] [[TMP3]] to i8* +// NEW: [[TMP1:%.+]] = ptrtoint i8* [[AP_CUR]] to [[$INTPTR_T]] +// NEW: [[TMP2:%.+]] = add [[$INTPTR_T]] [[TMP1]], 15 +// NEW: [[TMP3:%.+]] = and [[$INTPTR_T]] [[TMP2]], -16 +// NEW: [[AP_CUR:%.+]] = inttoptr [[$INTPTR_T]] [[TMP3]] to i8* // -// ALL: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[INTPTR_T]] 16 -// ALL: store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]] +// ALL: [[AP_NEXT:%.+]] = getelementptr inbounds i8, i8* [[AP_CUR]], [[$INTPTR_T]] 16 +// ALL: store i8* [[AP_NEXT]], i8** %va, align [[$PTRALIGN]] // // ALL: [[AP_CAST:%.+]] = bitcast i8* [[AP_CUR]] to <4 x i32>* // O32: [[ARG:%.+]] = load <4 x i32>, <4 x i32>* [[AP_CAST]], align 8 // N64: [[ARG:%.+]] = load <4 x i32>, <4 x i32>* [[AP_CAST]], align 16 +// N32: [[ARG:%.+]] = load <4 x i32>, <4 x i32>* [[AP_CAST]], align 16 // ALL: store <4 x i32> [[ARG]], <4 x i32>* [[V]], align 16 // // ALL: [[VA1:%.+]] = bitcast i8** %va to i8* diff --git a/test/CodeGen/noduplicate-cxx11-test.cpp b/test/CodeGen/noduplicate-cxx11-test.cpp index 01278632bffb3..bcec05f72a62c 100644 --- a/test/CodeGen/noduplicate-cxx11-test.cpp +++ b/test/CodeGen/noduplicate-cxx11-test.cpp @@ -17,4 +17,4 @@ int main() { } -// CHECK: attributes [[NI]] = { noduplicate nounwind{{.*}} } +// CHECK: attributes [[NI]] = { noduplicate {{.*}}nounwind{{.*}} } diff --git a/test/CodeGen/piclevels.c b/test/CodeGen/piclevels.c index 54744e2efa7d3..f050af96ff453 100644 --- a/test/CodeGen/piclevels.c +++ b/test/CodeGen/piclevels.c @@ -1,7 +1,12 @@ -// RUN: %clang_cc1 -emit-llvm -pic-level 2 %s -o - | FileCheck %s -check-prefix=CHECK-BIGPIC -// RUN: %clang_cc1 -emit-llvm -pic-level 1 %s -o - | FileCheck %s -check-prefix=CHECK-SMALLPIC +// RUN: %clang_cc1 -emit-llvm -pic-level 2 %s -o - | FileCheck %s -check-prefix=CHECK-BIGPIC -check-prefix=CHECK-NOPIE +// RUN: %clang_cc1 -emit-llvm -pic-level 1 %s -o - | FileCheck %s -check-prefix=CHECK-SMALLPIC -check-prefix=CHECK-NOPIE +// RUN: %clang_cc1 -emit-llvm -pic-level 2 -pic-is-pie %s -o - | FileCheck %s -check-prefix=CHECK-BIGPIC -check-prefix=CHECK-BIGPIE +// RUN: %clang_cc1 -emit-llvm -pic-level 1 -pic-is-pie %s -o - | FileCheck %s -check-prefix=CHECK-SMALLPIC -check-prefix=CHECK-SMALLPIE // CHECK-BIGPIC: !llvm.module.flags = !{{{.*}}} -// CHECK-BIGPIC: !{{[0-9]+}} = !{i32 1, !"PIC Level", i32 2} +// CHECK-BIGPIC: !{{[0-9]+}} = !{i32 7, !"PIC Level", i32 2} // CHECK-SMALLPIC: !llvm.module.flags = !{{{.*}}} -// CHECK-SMALLPIC: !{{[0-9]+}} = !{i32 1, !"PIC Level", i32 1} +// CHECK-SMALLPIC: !{{[0-9]+}} = !{i32 7, !"PIC Level", i32 1} +// CHECK-NOPIE-NOT: PIE Level +// CHECK-BIGPIE: !{{[0-9]+}} = !{i32 7, !"PIE Level", i32 2} +// CHECK-SMALLPIE: !{{[0-9]+}} = !{i32 7, !"PIE Level", i32 1} diff --git a/test/CodeGen/pragma-weak.c b/test/CodeGen/pragma-weak.c index 36abca5de32bb..d1f7ab6c3ebee 100644 --- a/test/CodeGen/pragma-weak.c +++ b/test/CodeGen/pragma-weak.c @@ -189,4 +189,4 @@ void zzz(void){} int correct_linkage; // CHECK: attributes [[NI]] = { noinline nounwind{{.*}} } -// CHECK: attributes [[RN]] = { noinline nounwind readnone{{.*}} } +// CHECK: attributes [[RN]] = { noinline nounwind optnone readnone{{.*}} } diff --git a/test/CodeGen/union-tbaa1.c b/test/CodeGen/union-tbaa1.c new file mode 100644 index 0000000000000..07f5fcfeb4215 --- /dev/null +++ b/test/CodeGen/union-tbaa1.c @@ -0,0 +1,44 @@ +// RUN: %clang_cc1 %s -triple hexagon-unknown-elf -O2 -emit-llvm -o - | FileCheck %s + +typedef union __attribute__((aligned(4))) { + unsigned short uh[2]; + unsigned uw; +} vect32; + +void bar(vect32 p[][2]); + +// CHECK-LABEL: define void @fred +void fred(unsigned Num, int Vec[2], int *Index, int Arr[4][2]) { + vect32 Tmp[4][2]; +// Generate tbaa for the load of Index: +// CHECK: load i32, i32* %Index{{.*}}tbaa +// But no tbaa for the two stores: +// CHECK: %uw[[UW1:[0-9]*]] = getelementptr +// CHECK: store{{.*}}%uw[[UW1]] +// CHECK: tbaa ![[OCPATH:[0-9]+]] +// There will be a load after the store, and it will use tbaa. Make sure +// the check-not above doesn't find it: +// CHECK: load + Tmp[*Index][0].uw = Arr[*Index][0] * Num; +// CHECK: %uw[[UW2:[0-9]*]] = getelementptr +// CHECK: store{{.*}}%uw[[UW2]] +// CHECK: tbaa ![[OCPATH]] + Tmp[*Index][1].uw = Arr[*Index][1] * Num; +// Same here, don't generate tbaa for the loads: +// CHECK: %uh[[UH1:[0-9]*]] = bitcast %union.vect32 +// CHECK: %arrayidx[[AX1:[0-9]*]] = getelementptr{{.*}}%uh[[UH1]] +// CHECK: load i16, i16* %arrayidx[[AX1]] +// CHECK: tbaa ![[OCPATH]] +// CHECK: store + Vec[0] = Tmp[*Index][0].uh[1]; +// CHECK: %uh[[UH2:[0-9]*]] = bitcast %union.vect32 +// CHECK: %arrayidx[[AX2:[0-9]*]] = getelementptr{{.*}}%uh[[UH2]] +// CHECK: load i16, i16* %arrayidx[[AX2]] +// CHECK: tbaa ![[OCPATH]] +// CHECK: store + Vec[1] = Tmp[*Index][1].uh[1]; + bar(Tmp); +} + +// CHECK-DAG: ![[CHAR:[0-9]+]] = !{!"omnipotent char" +// CHECK-DAG: ![[OCPATH]] = !{![[CHAR]], ![[CHAR]], i64 0} diff --git a/test/CodeGen/unwind-attr.c b/test/CodeGen/unwind-attr.c index 2065653e0de4c..9979235003691 100644 --- a/test/CodeGen/unwind-attr.c +++ b/test/CodeGen/unwind-attr.c @@ -23,7 +23,7 @@ __attribute__((weak)) int test2(void) { return 0; } -// CHECK: attributes [[TF]] = { noinline "{{.*}} } +// CHECK: attributes [[TF]] = { noinline optnone "{{.*}} } // CHECK: attributes [[NUW]] = { noinline nounwind{{.*}} } // CHECK-NOEXC: attributes [[NUW]] = { noinline nounwind{{.*}} } diff --git a/test/CodeGen/xray-imbue-arg1.cpp b/test/CodeGen/xray-imbue-arg1.cpp new file mode 100644 index 0000000000000..eb272b97eafb6 --- /dev/null +++ b/test/CodeGen/xray-imbue-arg1.cpp @@ -0,0 +1,12 @@ +// RUN: echo "fun:*arg1*=arg1" >> %t.always-instrument +// RUN: %clang_cc1 -fxray-instrument -x c++ -std=c++11 -fxray-always-instrument=%t.always-instrument -emit-llvm -o - %s -triple x86_64-unknown-linux-gnu | FileCheck %s + +void foo() {} + +void arg1(void*) {} + +// CHECK: define void @_Z3foov() #[[FOO:[0-9]+]] { +// CHECK: define void {{.*}}arg1{{.*}} #[[ALWAYSARG1:[0-9]+]] { + +// CHECK: attributes #[[FOO]] = {{.*}} +// CHECK: attributes #[[ALWAYSARG1]] = {{.*}} "function-instrument"="xray-always" {{.*}} "xray-log-args"="1" |