diff options
Diffstat (limited to 'test/CodeGen')
58 files changed, 1231 insertions, 136 deletions
diff --git a/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll new file mode 100644 index 0000000000000..465368b0ba8dc --- /dev/null +++ b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll @@ -0,0 +1,63 @@ +; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s +; PR5367 + +define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(i8* nocapture %pBuffer, i32 %numItems) nounwind { +entry: + br i1 undef, label %return, label %bb + +bb: ; preds = %bb, %entry + %0 = load float* undef, align 4 ; <float> [#uses=1] + %1 = load float* null, align 4 ; <float> [#uses=1] + %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1] + %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2] + %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] + %5 = insertelement <4 x float> %4, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=4] + %6 = fsub <4 x float> zeroinitializer, %3 ; <<4 x float>> [#uses=1] + %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=2] + %8 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1] + %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=2] + %10 = fmul <4 x float> %7, %9 ; <<4 x float>> [#uses=1] + %11 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %12 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=2] + %13 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %14 = fmul <4 x float> %11, %13 ; <<4 x float>> [#uses=1] + %15 = fadd <4 x float> %10, %14 ; <<4 x float>> [#uses=1] + %16 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1] + %17 = fadd <4 x float> %15, zeroinitializer ; <<4 x float>> [#uses=1] + %18 = shufflevector <4 x float> %17, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] + %19 = fmul <4 x float> %7, %16 ; <<4 x float>> [#uses=1] + %20 = fadd <4 x float> %19, zeroinitializer ; <<4 x float>> [#uses=1] + %21 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] + %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %23 = fmul <4 x float> %22, %9 ; <<4 x float>> [#uses=1] + %24 = fadd <4 x float> %20, %23 ; <<4 x float>> [#uses=1] + %25 = shufflevector <4 x float> %18, <4 x float> %24, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> ; <<4 x float>> [#uses=1] + %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1] + %27 = fmul <4 x float> %26, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1] + %28 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %5 ; <<4 x float>> [#uses=1] + %29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1] + %30 = fmul <4 x float> zeroinitializer, %29 ; <<4 x float>> [#uses=1] + %31 = fmul <4 x float> %30, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1] + %32 = shufflevector <4 x float> %27, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %33 = shufflevector <4 x float> %28, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1] + %34 = shufflevector <2 x float> %33, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1] + %35 = fmul <4 x float> %32, %34 ; <<4 x float>> [#uses=1] + %36 = fadd <4 x float> %35, zeroinitializer ; <<4 x float>> [#uses=1] + %37 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1] + %38 = shufflevector <4 x float> %37, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] + %39 = fmul <4 x float> zeroinitializer, %38 ; <<4 x float>> [#uses=1] + %40 = fadd <4 x float> %36, %39 ; <<4 x float>> [#uses=1] + %41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1] + %42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1] + %43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1] + store float undef, float* undef, align 4 + store float 0.000000e+00, float* null, align 4 + %44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1] + store float %44, float* undef, align 4 + br i1 undef, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} + +declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll new file mode 100644 index 0000000000000..a4e76859d16de --- /dev/null +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s + +@.str = private constant [1 x i8] zeroinitializer, align 1 + +define arm_aapcscc void @g() { +entry: +;CHECK: [sp, #+8] +;CHECK: [sp, #+12] +;CHECK: [sp] + tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + ret void +} + +declare arm_aapcscc void @f(i8*, ...) diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll new file mode 100644 index 0000000000000..82563869bd968 --- /dev/null +++ b/test/CodeGen/ARM/2009-10-30.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; This test checks that the address of the varg arguments is correctly +; computed when there are 5 or more regular arguments. + +define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) { +entry: +;CHECK: sub sp, sp, #4 +;CHECK: add r0, sp, #8 +;CHECK: str r0, [sp], #+4 +;CHECK: bx lr + %ap = alloca i8*, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret void +} + +declare void @llvm.va_start(i8*) nounwind diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll new file mode 100644 index 0000000000000..c260b973b5a0b --- /dev/null +++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -0,0 +1,37 @@ +; RUN: llc -mcpu=cortex-a8 < %s | grep vmov | count 1 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv7-eabi" + +%foo = type { <4 x float> } + +define arm_aapcs_vfpcc void @bar(%foo* noalias sret %agg.result, <4 x float> %quat.0) nounwind { +entry: + %quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2] + %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] + store <4 x float> %quat.0, <4 x float>* %0 + %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3] + %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2] + %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1] + %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1] + %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2] + %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2] + %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2] + %8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses=3] + %9 = fmul <4 x float> %8, %8 ; <<4 x float>> [#uses=1] + %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1] + %11 = fmul <4 x float> %10, %8 ; <<4 x float>> [#uses=1] + %12 = fmul <4 x float> %11, %1 ; <<4 x float>> [#uses=1] + %13 = call arm_aapcs_vfpcc %foo* @baz(%foo* %agg.result, <4 x float> %12) nounwind ; <%foo*> [#uses=0] + ret void +} + +declare arm_aapcs_vfpcc %foo* @baz(%foo*, <4 x float>) nounwind + +declare arm_aapcs_vfpcc <4 x float> @quux(%foo* nocapture) nounwind readonly + +declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone + +declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll new file mode 100644 index 0000000000000..f2288c3710e16 --- /dev/null +++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -0,0 +1,20 @@ +; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.32 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv7-eabi" + +define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind { +entry: + br i1 undef, label %return, label %bb + +bb: ; preds = %bb, %entry + %0 = load float* undef, align 4 ; <float> [#uses=1] + %1 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] + %2 = insertelement <4 x float> %1, float undef, i32 3 ; <<4 x float>> [#uses=1] + %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1] + %4 = extractelement <4 x float> %3, i32 1 ; <float> [#uses=1] + store float %4, float* undef, align 4 + br i1 undef, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/ARM/alloca.ll b/test/CodeGen/ARM/alloca.ll index 15cf67734cb2d..82a8c98599c21 100644 --- a/test/CodeGen/ARM/alloca.ll +++ b/test/CodeGen/ARM/alloca.ll @@ -1,13 +1,12 @@ -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \ -; RUN: grep {mov r11, sp} -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | \ -; RUN: grep {mov sp, r11} +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s define void @f(i32 %a) { entry: +; CHECK: mov r11, sp %tmp = alloca i8, i32 %a ; <i8*> [#uses=1] call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 ) ret void +; CHECK: mov sp, r11 } declare void @g(i8*, i32, i32, i32, i32) diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll index ad5b2d69fab92..cc718399ea96e 100644 --- a/test/CodeGen/ARM/arguments.ll +++ b/test/CodeGen/ARM/arguments.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | \ -; RUN: grep {mov r0, r2} | count 1 -; RUN: llc < %s -mtriple=arm-apple-darwin | \ -; RUN: grep {mov r0, r1} | count 1 +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN define i32 @f(i32 %a, i64 %b) { +; ELF: mov r0, r2 +; DARWIN: mov r0, r1 %tmp = call i32 @g(i64 %b) ret i32 %tmp } diff --git a/test/CodeGen/ARM/arguments_f64_backfill.ll b/test/CodeGen/ARM/arguments_f64_backfill.ll index 690f488d8483d..d8019a07fabf1 100644 --- a/test/CodeGen/ARM/arguments_f64_backfill.ll +++ b/test/CodeGen/ARM/arguments_f64_backfill.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 -float-abi=hard | grep {fcpys s0, s1} +; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 -float-abi=hard | FileCheck %s define float @f(float %z, double %a, float %b) { +; CHECK: fcpys s0, s1 %tmp = call float @g(float %b) ret float %tmp } diff --git a/test/CodeGen/ARM/arm-negative-stride.ll b/test/CodeGen/ARM/arm-negative-stride.ll index c4b4ec613ee55..72ec8efcc4459 100644 --- a/test/CodeGen/ARM/arm-negative-stride.ll +++ b/test/CodeGen/ARM/arm-negative-stride.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=arm | grep {str r1, \\\[r.*, -r.*, lsl #2\} +; RUN: llc < %s -march=arm | FileCheck %s define void @test(i32* %P, i32 %A, i32 %i) nounwind { entry: +; CHECK: str r1, [{{r.*}}, -{{r.*}}, lsl #2] icmp eq i32 %i, 0 ; <i1>:0 [#uses=1] br i1 %0, label %return, label %bb diff --git a/test/CodeGen/ARM/bfc.ll b/test/CodeGen/ARM/bfc.ll index 53392de73fcf8..c4a44b4472d1e 100644 --- a/test/CodeGen/ARM/bfc.ll +++ b/test/CodeGen/ARM/bfc.ll @@ -1,19 +1,25 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | grep "bfc " | count 3 +; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s ; 4278190095 = 0xff00000f define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: bfc %tmp = and i32 %a, 4278190095 ret i32 %tmp } ; 4286578688 = 0xff800000 define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: bfc %tmp = and i32 %a, 4286578688 ret i32 %tmp } ; 4095 = 0x00000fff define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: bfc %tmp = and i32 %a, 4095 ret i32 %tmp } diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index 52246c3f0cd77..3dd66ae71df86 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -1,13 +1,16 @@ -; RUN: llc < %s -march=arm | grep {mov lr, pc} -; RUN: llc < %s -march=arm -mattr=+v5t | grep blx +; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ -; RUN: -relocation-model=pic | grep {PLT} +; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF @t = weak global i32 ()* null ; <i32 ()**> [#uses=1] declare void @g(i32, i32, i32, i32) define void @f() { +; CHECKV4: mov lr, pc +; CHECKV5: blx +; CHECKELF: PLT call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll index 294de5ff72780..a6a7ed6af1840 100644 --- a/test/CodeGen/ARM/carry.ll +++ b/test/CodeGen/ARM/carry.ll @@ -1,14 +1,19 @@ -; RUN: llc < %s -march=arm | grep "subs r" | count 2 -; RUN: llc < %s -march=arm | grep "adc r" -; RUN: llc < %s -march=arm | grep "sbc r" | count 2 +; RUN: llc < %s -march=arm | FileCheck %s define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: subs r +; CHECK: sbc r entry: %tmp = sub i64 %a, %b ret i64 %tmp } define i64 @f2(i64 %a, i64 %b) { +; CHECK: f2: +; CHECK: adc r +; CHECK: subs r +; CHECK: sbc r entry: %tmp1 = shl i64 %a, 1 %tmp2 = sub i64 %tmp1, %b diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll index e2d8ddc63fcf4..ce919361619a0 100644 --- a/test/CodeGen/ARM/constants.ll +++ b/test/CodeGen/ARM/constants.ll @@ -1,39 +1,44 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep {mov r0, #0} | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep {mov r0, #255$} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | \ -; RUN: grep {mov r0.*256} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | grep {orr.*256} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | grep {mov r0, .*-1073741761} | count 1 -; RUN: llc < %s -march=arm -asm-verbose | grep {mov r0, .*1008} | count 1 -; RUN: llc < %s -march=arm | grep {cmp r0, #1, 16} | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1() { +; CHECK: f1 +; CHECK: mov r0, #0 ret i32 0 } define i32 @f2() { +; CHECK: f2 +; CHECK: mov r0, #255 ret i32 255 } define i32 @f3() { +; CHECK: f3 +; CHECK: mov r0{{.*}}256 ret i32 256 } define i32 @f4() { +; CHECK: f4 +; CHECK: orr{{.*}}256 ret i32 257 } define i32 @f5() { +; CHECK: f5 +; CHECK: mov r0, {{.*}}-1073741761 ret i32 -1073741761 } define i32 @f6() { +; CHECK: f6 +; CHECK: mov r0, {{.*}}1008 ret i32 1008 } define void @f7(i32 %a) { +; CHECK: f7 +; CHECK: cmp r0, #1, 16 %b = icmp ugt i32 %a, 65536 ; <i1> [#uses=1] br i1 %b, label %r, label %r diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index 1a1cd0747b498..5c31ea641de49 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 ; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 define float @test(float %acc, float %a, float %b) { diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll index e57bbbba3b384..8fc13e78bc30c 100644 --- a/test/CodeGen/ARM/fnmacs.ll +++ b/test/CodeGen/ARM/fnmacs.ll @@ -1,11 +1,18 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEONFP define float @test(float %acc, float %a, float %b) { entry: +; VFP2: fnmacs +; NEON: fnmacs + +; NEONFP-NOT: vmls +; NEONFP-NOT: fcpys +; NEONFP: vmul.f32 +; NEONFP: vsub.f32 +; NEONFP: fmrs + %0 = fmul float %a, %b %1 = fsub float %acc, %0 ret float %1 diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll new file mode 100644 index 0000000000000..4de18bc3b456e --- /dev/null +++ b/test/CodeGen/ARM/fpconsts.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s + +define arm_apcscc float @t1(float %x) nounwind readnone optsize { +entry: +; CHECK: t1: +; CHECK: fconsts s1, #16 + %0 = fadd float %x, 4.000000e+00 + ret float %0 +} + +define arm_apcscc double @t2(double %x) nounwind readnone optsize { +entry: +; CHECK: t2: +; CHECK: fconstd d1, #8 + %0 = fadd double %x, 3.000000e+00 + ret double %0 +} + +define arm_apcscc double @t3(double %x) nounwind readnone optsize { +entry: +; CHECK: t3: +; CHECK: fconstd d1, #170 + %0 = fmul double %x, -1.300000e+01 + ret double %0 +} + +define arm_apcscc float @t4(float %x) nounwind readnone optsize { +entry: +; CHECK: t4: +; CHECK: fconsts s1, #184 + %0 = fmul float %x, -2.400000e+01 + ret float %0 +} diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll index fa897bf83f3a4..0822fbff653f6 100644 --- a/test/CodeGen/ARM/fpmem.ll +++ b/test/CodeGen/ARM/fpmem.ll @@ -1,21 +1,22 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep {mov r0, #0} | count 1 -; RUN: llc < %s -march=arm -mattr=+vfp2 | \ -; RUN: grep {flds.*\\\[} | count 1 -; RUN: llc < %s -march=arm -mattr=+vfp2 | \ -; RUN: grep {fsts.*\\\[} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s define float @f1(float %a) { +; CHECK: f1: +; CHECK: mov r0, #0 ret float 0.000000e+00 } define float @f2(float* %v, float %u) { +; CHECK: f2: +; CHECK: flds{{.*}}[ %tmp = load float* %v ; <float> [#uses=1] %tmp1 = fadd float %tmp, %u ; <float> [#uses=1] ret float %tmp1 } define void @f3(float %a, float %b, float* %v) { +; CHECK: f3: +; CHECK: fsts{{.*}}[ %tmp = fadd float %a, %b ; <float> [#uses=1] store float %tmp, float* %v ret void diff --git a/test/CodeGen/ARM/ispositive.ll b/test/CodeGen/ARM/ispositive.ll index 5116ac82862a4..245ed516f70bc 100644 --- a/test/CodeGen/ARM/ispositive.ll +++ b/test/CodeGen/ARM/ispositive.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=arm | grep {mov r0, r0, lsr #31} +; RUN: llc < %s -march=arm | FileCheck %s define i32 @test1(i32 %X) { +; CHECK: mov r0, r0, lsr #31 entry: icmp slt i32 %X, 0 ; <i1>:0 [#uses=1] zext i1 %0 to i32 ; <i32>:1 [#uses=1] diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 774b3c09bed42..1a016a0942d23 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -1,13 +1,10 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep ldmia | count 2 -; RUN: llc < %s -march=arm | \ -; RUN: grep ldmib | count 1 -; RUN: llc < %s -mtriple=arm-apple-darwin | \ -; RUN: grep {ldmfd sp\!} | count 3 +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s @X = external global [0 x i32] ; <[0 x i32]*> [#uses=5] define i32 @t1() { +; CHECK: t1: +; CHECK: ldmia %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1] @@ -15,6 +12,8 @@ define i32 @t1() { } define i32 @t2() { +; CHECK: t2: +; CHECK: ldmia %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1] @@ -23,6 +22,9 @@ define i32 @t2() { } define i32 @t3() { +; CHECK: t3: +; CHECK: ldmib +; CHECK: ldmfd sp! %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll index 954fb5b8ad311..011e61caea966 100644 --- a/test/CodeGen/ARM/ldr.ll +++ b/test/CodeGen/ARM/ldr.ll @@ -1,16 +1,16 @@ -; RUN: llc < %s -march=arm | grep {ldr r0} | count 7 -; RUN: llc < %s -march=arm | grep mov | grep 1 -; RUN: llc < %s -march=arm | not grep mvn -; RUN: llc < %s -march=arm | grep ldr | grep lsl -; RUN: llc < %s -march=arm | grep ldr | grep lsr +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1(i32* %v) { +; CHECK: f1: +; CHECK: ldr r0 entry: %tmp = load i32* %v ret i32 %tmp } define i32 @f2(i32* %v) { +; CHECK: f2: +; CHECK: ldr r0 entry: %tmp2 = getelementptr i32* %v, i32 1023 %tmp = load i32* %tmp2 @@ -18,6 +18,9 @@ entry: } define i32 @f3(i32* %v) { +; CHECK: f3: +; CHECK: mov +; CHECK: ldr r0 entry: %tmp2 = getelementptr i32* %v, i32 1024 %tmp = load i32* %tmp2 @@ -25,6 +28,9 @@ entry: } define i32 @f4(i32 %base) { +; CHECK: f4: +; CHECK-NOT: mvn +; CHECK: ldr r0 entry: %tmp1 = sub i32 %base, 128 %tmp2 = inttoptr i32 %tmp1 to i32* @@ -33,6 +39,8 @@ entry: } define i32 @f5(i32 %base, i32 %offset) { +; CHECK: f5: +; CHECK: ldr r0 entry: %tmp1 = add i32 %base, %offset %tmp2 = inttoptr i32 %tmp1 to i32* @@ -41,6 +49,8 @@ entry: } define i32 @f6(i32 %base, i32 %offset) { +; CHECK: f6: +; CHECK: ldr r0{{.*}}lsl{{.*}} entry: %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 @@ -50,6 +60,8 @@ entry: } define i32 @f7(i32 %base, i32 %offset) { +; CHECK: f7: +; CHECK: ldr r0{{.*}}lsr{{.*}} entry: %tmp1 = lshr i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index 2fcaac0d9c982..16ef7cc2cb6c7 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -1,47 +1,50 @@ -; RUN: llc < %s -march=arm -asm-verbose | \ -; RUN: grep -- {-2147483648} | count 3 -; RUN: llc < %s -march=arm | grep mvn | count 3 -; RUN: llc < %s -march=arm | grep adds | count 1 -; RUN: llc < %s -march=arm | grep adc | count 1 -; RUN: llc < %s -march=arm | grep {subs } | count 1 -; RUN: llc < %s -march=arm | grep sbc | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep smull | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep umull | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i64 @f1() { +; CHECK: f1: entry: ret i64 0 } define i64 @f2() { +; CHECK: f2: entry: ret i64 1 } define i64 @f3() { +; CHECK: f3: +; CHECK: mvn{{.*}}-2147483648 entry: ret i64 2147483647 } define i64 @f4() { +; CHECK: f4: +; CHECK: -2147483648 entry: ret i64 2147483648 } define i64 @f5() { +; CHECK: f5: +; CHECK: mvn +; CHECK: mvn{{.*}}-2147483648 entry: ret i64 9223372036854775807 } define i64 @f6(i64 %x, i64 %y) { +; CHECK: f6: +; CHECK: adds +; CHECK: adc entry: %tmp1 = add i64 %y, 1 ; <i64> [#uses=1] ret i64 %tmp1 } define void @f7() { +; CHECK: f7: entry: %tmp = call i64 @f8( ) ; <i64> [#uses=0] ret void @@ -50,12 +53,17 @@ entry: declare i64 @f8() define i64 @f9(i64 %a, i64 %b) { +; CHECK: f9: +; CHECK: subs r +; CHECK: sbc entry: %tmp = sub i64 %a, %b ; <i64> [#uses=1] ret i64 %tmp } define i64 @f(i32 %a, i32 %b) { +; CHECK: f: +; CHECK: smull entry: %tmp = sext i32 %a to i64 ; <i64> [#uses=1] %tmp1 = sext i32 %b to i64 ; <i64> [#uses=1] @@ -64,6 +72,8 @@ entry: } define i64 @g(i32 %a, i32 %b) { +; CHECK: g: +; CHECK: umull entry: %tmp = zext i32 %a to i64 ; <i64> [#uses=1] %tmp1 = zext i32 %b to i64 ; <i64> [#uses=1] @@ -72,9 +82,9 @@ entry: } define i64 @f10() { +; CHECK: f10: entry: %a = alloca i64, align 8 ; <i64*> [#uses=1] %retval = load i64* %a ; <i64> [#uses=1] ret i64 %retval } - diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 057b5f067f803..688b7bc312c7b 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep rrx %t | count 1 -; RUN: grep __ashldi3 %t -; RUN: grep __ashrdi3 %t -; RUN: grep __lshrdi3 %t +; RUN: llc < %s -march=arm | FileCheck %s define i64 @f0(i64 %A, i64 %B) { +; CHECK: f0 +; CHECK: movs r3, r3, lsr #1 +; CHECK-NEXT: mov r2, r2, rrx +; CHECK-NEXT: subs r0, r0, r2 +; CHECK-NEXT: sbc r1, r1, r3 %tmp = bitcast i64 %A to i64 %tmp2 = lshr i64 %B, 1 %tmp3 = sub i64 %tmp, %tmp2 @@ -12,18 +13,34 @@ define i64 @f0(i64 %A, i64 %B) { } define i32 @f1(i64 %x, i64 %y) { +; CHECK: f1 +; CHECK: mov r0, r0, lsl r2 %a = shl i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b } define i32 @f2(i64 %x, i64 %y) { +; CHECK: f2 +; CHECK: mov r0, r0, lsr r2 +; CHECK-NEXT: rsb r3, r2, #32 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 +; CHECK-NEXT: movge r0, r1, asr r2 %a = ashr i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b } define i32 @f3(i64 %x, i64 %y) { +; CHECK: f3 +; CHECK: mov r0, r0, lsr r2 +; CHECK-NEXT: rsb r3, r2, #32 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 +; CHECK-NEXT: movge r0, r1, lsr r2 %a = lshr i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll index ba9699efd5973..50da997ed468a 100644 --- a/test/CodeGen/ARM/remat.ll +++ b/test/CodeGen/ARM/remat.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 4 +; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 5 %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } %struct.LOCBOX = type { i32, i32, i32, i32 } diff --git a/test/CodeGen/ARM/str_post.ll b/test/CodeGen/ARM/str_post.ll index 801b9cee37d69..97916f169b0f4 100644 --- a/test/CodeGen/ARM/str_post.ll +++ b/test/CodeGen/ARM/str_post.ll @@ -1,9 +1,8 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep {strh .*\\\[.*\], #-4} | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep {str .*\\\[.*\],} | count 1 +; RUN: llc < %s -march=arm | FileCheck %s define i16 @test1(i32* %X, i16* %A) { +; CHECK: test1: +; CHECK: strh {{.*}}[{{.*}}], #-4 %Y = load i32* %X ; <i32> [#uses=1] %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1] store i16 %tmp1, i16* %A @@ -13,6 +12,8 @@ define i16 @test1(i32* %X, i16* %A) { } define i32 @test2(i32* %X, i32* %A) { +; CHECK: test2: +; CHECK: str {{.*}}[{{.*}}], %Y = load i32* %X ; <i32> [#uses=1] store i32 %Y, i32* %A %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll index 328472081e197..d932f90e4c10f 100644 --- a/test/CodeGen/ARM/tls2.ll +++ b/test/CodeGen/ARM/tls2.ll @@ -1,19 +1,27 @@ -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ -; RUN: grep {i(gottpoff)} -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ -; RUN: grep {ldr r., \[pc, r.\]} ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \ -; RUN: -relocation-model=pic | grep {__tls_get_addr} +; RUN: | FileCheck %s -check-prefix=CHECK-NONPIC +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \ +; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC @i = external thread_local global i32 ; <i32*> [#uses=2] define i32 @f() { +; CHECK-NONPIC: f: +; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: i(gottpoff) +; CHECK-PIC: f: +; CHECK-PIC: __tls_get_addr entry: %tmp1 = load i32* @i ; <i32> [#uses=1] ret i32 %tmp1 } define i32* @g() { +; CHECK-NONPIC: g: +; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}] +; CHECK-NONPIC: i(gottpoff) +; CHECK-PIC: g: +; CHECK-PIC: __tls_get_addr entry: ret i32* @i } diff --git a/test/CodeGen/CPP/llvm2cpp.ll b/test/CodeGen/CPP/llvm2cpp.ll index 447f332b269e0..d0ba0cfac3125 100644 --- a/test/CodeGen/CPP/llvm2cpp.ll +++ b/test/CodeGen/CPP/llvm2cpp.ll @@ -273,7 +273,7 @@ define i32 @foozball(i32) { @A = global i32* @B ; <i32**> [#uses=0] @B = global i32 7 ; <i32*> [#uses=1] -define void @X() { +define void @test12312() { ret void } ; ModuleID = 'global_section.ll' diff --git a/test/CodeGen/Generic/intrinsics.ll b/test/CodeGen/Generic/intrinsics.ll index 9a42c3ef32a1f..29bc499adfc59 100644 --- a/test/CodeGen/Generic/intrinsics.ll +++ b/test/CodeGen/Generic/intrinsics.ll @@ -14,9 +14,9 @@ define double @test_sqrt(float %F) { ; SIN -declare float @sinf(float) +declare float @sinf(float) readonly -declare double @sin(double) +declare double @sin(double) readonly define double @test_sin(float %F) { %G = call float @sinf( float %F ) ; <float> [#uses=1] @@ -27,9 +27,9 @@ define double @test_sin(float %F) { ; COS -declare float @cosf(float) +declare float @cosf(float) readonly -declare double @cos(double) +declare double @cos(double) readonly define double @test_cos(float %F) { %G = call float @cosf( float %F ) ; <float> [#uses=1] diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll index 3cbb212b628bc..76474746ee487 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | grep fcpys | count 1 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | not grep fcpys ; rdar://7117307 %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } diff --git a/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll new file mode 100644 index 0000000000000..216f3e3f9cc84 --- /dev/null +++ b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 + +define arm_apcscc void @get_initial_mb16x16_cost() nounwind { +entry: + br i1 undef, label %bb4, label %bb1 + +bb1: ; preds = %entry + br label %bb7 + +bb4: ; preds = %entry + br i1 undef, label %bb7.thread, label %bb5 + +bb5: ; preds = %bb4 + br label %bb7 + +bb7.thread: ; preds = %bb4 + br label %bb8 + +bb7: ; preds = %bb5, %bb1 + br i1 undef, label %bb8, label %bb10 + +bb8: ; preds = %bb7, %bb7.thread + %0 = phi double [ 5.120000e+02, %bb7.thread ], [ undef, %bb7 ] ; <double> [#uses=1] + %1 = fdiv double %0, undef ; <double> [#uses=0] + unreachable + +bb10: ; preds = %bb7 + ret void +} diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll new file mode 100644 index 0000000000000..572f1e8975a3a --- /dev/null +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 + +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } + +declare arm_apcscc i32 @fgetc(%struct.FILE* nocapture) nounwind + +define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + br i1 undef, label %bb, label %bb1 + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + br i1 undef, label %bb.i1, label %bb1.i2 + +bb.i1: ; preds = %bb1 + unreachable + +bb1.i2: ; preds = %bb1 + %0 = call arm_apcscc i32 @fgetc(%struct.FILE* undef) nounwind ; <i32> [#uses=0] + br i1 undef, label %bb2.i3, label %bb3.i4 + +bb2.i3: ; preds = %bb1.i2 + br i1 undef, label %bb4.i, label %bb3.i4 + +bb3.i4: ; preds = %bb2.i3, %bb1.i2 + unreachable + +bb4.i: ; preds = %bb2.i3 + br i1 undef, label %bb5.i, label %get_image.exit + +bb5.i: ; preds = %bb4.i + unreachable + +get_image.exit: ; preds = %bb4.i + br i1 undef, label %bb28, label %bb27 + +bb27: ; preds = %get_image.exit + br label %bb.i + +bb.i: ; preds = %bb.i, %bb27 + %1 = fptrunc double undef to float ; <float> [#uses=1] + %2 = fptoui float %1 to i8 ; <i8> [#uses=1] + store i8 %2, i8* undef, align 1 + br label %bb.i + +bb28: ; preds = %get_image.exit + unreachable +} diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll new file mode 100644 index 0000000000000..4320328e9c102 --- /dev/null +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -0,0 +1,67 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep fcpys | count 4 + +define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { +entry: + br label %bb5 + +bb5: ; preds = %bb5, %entry + br i1 undef, label %bb5, label %bb.nph + +bb.nph: ; preds = %bb5 + br label %bb7 + +bb7: ; preds = %bb9, %bb.nph + %s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3] + %tmp79 = add i32 undef, undef ; <i32> [#uses=1] + %tmp53 = sub i32 undef, undef ; <i32> [#uses=1] + %0 = fadd float 0.000000e+00, 1.000000e+00 ; <float> [#uses=2] + %1 = fmul float 0.000000e+00, 0.000000e+00 ; <float> [#uses=2] + br label %bb8 + +bb8: ; preds = %bb8, %bb7 + %tmp54 = add i32 0, %tmp53 ; <i32> [#uses=0] + %fi.1 = getelementptr float* %fz, i32 undef ; <float*> [#uses=2] + %tmp80 = add i32 0, %tmp79 ; <i32> [#uses=1] + %scevgep81 = getelementptr float* %fz, i32 %tmp80 ; <float*> [#uses=1] + %2 = load float* undef, align 4 ; <float> [#uses=1] + %3 = fmul float %2, %1 ; <float> [#uses=1] + %4 = load float* null, align 4 ; <float> [#uses=2] + %5 = fmul float %4, %0 ; <float> [#uses=1] + %6 = fsub float %3, %5 ; <float> [#uses=1] + %7 = fmul float %4, %1 ; <float> [#uses=1] + %8 = fadd float undef, %7 ; <float> [#uses=2] + %9 = load float* %fi.1, align 4 ; <float> [#uses=2] + %10 = fsub float %9, %8 ; <float> [#uses=1] + %11 = fadd float %9, %8 ; <float> [#uses=1] + %12 = fsub float 0.000000e+00, %6 ; <float> [#uses=1] + %13 = fsub float 0.000000e+00, undef ; <float> [#uses=2] + %14 = fmul float undef, %0 ; <float> [#uses=1] + %15 = fadd float %14, undef ; <float> [#uses=2] + %16 = load float* %scevgep81, align 4 ; <float> [#uses=2] + %17 = fsub float %16, %15 ; <float> [#uses=1] + %18 = fadd float %16, %15 ; <float> [#uses=2] + %19 = load float* undef, align 4 ; <float> [#uses=2] + %20 = fsub float %19, %13 ; <float> [#uses=2] + %21 = fadd float %19, %13 ; <float> [#uses=1] + %22 = fmul float %s1.02, %18 ; <float> [#uses=1] + %23 = fmul float 0.000000e+00, %20 ; <float> [#uses=1] + %24 = fsub float %22, %23 ; <float> [#uses=1] + %25 = fmul float 0.000000e+00, %18 ; <float> [#uses=1] + %26 = fmul float %s1.02, %20 ; <float> [#uses=1] + %27 = fadd float %25, %26 ; <float> [#uses=1] + %28 = fadd float %11, %27 ; <float> [#uses=1] + store float %28, float* %fi.1, align 4 + %29 = fadd float %12, %24 ; <float> [#uses=1] + store float %29, float* null, align 4 + %30 = fmul float 0.000000e+00, %21 ; <float> [#uses=1] + %31 = fmul float %s1.02, %17 ; <float> [#uses=1] + %32 = fsub float %30, %31 ; <float> [#uses=1] + %33 = fsub float %10, %32 ; <float> [#uses=1] + store float %33, float* undef, align 4 + %34 = icmp slt i32 undef, undef ; <i1> [#uses=1] + br i1 %34, label %bb8, label %bb9 + +bb9: ; preds = %bb8 + %35 = fadd float 0.000000e+00, undef ; <float> [#uses=1] + br label %bb7 +} diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll new file mode 100644 index 0000000000000..4c8ffe882896a --- /dev/null +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s +; rdar://7352504 +; Make sure we use "str r9, [sp, #+28]" instead of "sub.w r4, r7, #256" followed by "str r9, [r4, #-32]". + +%0 = type { i16, i8, i8 } +%1 = type { [2 x i32], [2 x i32] } +%2 = type { %union.rec* } +%struct.FILE_POS = type { i8, i8, i16, i32 } +%struct.GAP = type { i8, i8, i16 } +%struct.LIST = type { %union.rec*, %union.rec* } +%struct.STYLE = type { %union.anon, %union.anon, i16, i16, i32 } +%struct.head_type = type { [2 x %struct.LIST], %union.FIRST_UNION, %union.SECOND_UNION, %union.THIRD_UNION, %union.FOURTH_UNION, %union.rec*, %2, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, i32 } +%union.FIRST_UNION = type { %struct.FILE_POS } +%union.FOURTH_UNION = type { %struct.STYLE } +%union.SECOND_UNION = type { %0 } +%union.THIRD_UNION = type { %1 } +%union.anon = type { %struct.GAP } +%union.rec = type { %struct.head_type } + +@zz_hold = external global %union.rec* ; <%union.rec**> [#uses=2] +@zz_res = external global %union.rec* ; <%union.rec**> [#uses=1] + +define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { +entry: +; CHECK: ldr.w r9, [r7, #+32] +; CHECK-NEXT : str.w r9, [sp, #+28] + %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] + %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] + br i1 false, label %bb, label %bb20 + +bb: ; preds = %entry + unreachable + +bb20: ; preds = %entry + switch i32 undef, label %bb1287 [ + i32 11, label %bb119 + i32 12, label %bb119 + i32 21, label %bb420 + i32 23, label %bb420 + i32 45, label %bb438 + i32 46, label %bb438 + i32 55, label %bb533 + i32 56, label %bb569 + i32 64, label %bb745 + i32 78, label %bb1098 + ] + +bb119: ; preds = %bb20, %bb20 + unreachable + +bb420: ; preds = %bb20, %bb20 + store %union.rec* null, %union.rec** @zz_hold, align 4 + store %union.rec* null, %union.rec** @zz_res, align 4 + store %union.rec* %x, %union.rec** @zz_hold, align 4 + %0 = call arm_apcscc %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0] + unreachable + +bb438: ; preds = %bb20, %bb20 + unreachable + +bb533: ; preds = %bb20 + ret %union.rec* %x + +bb569: ; preds = %bb20 + unreachable + +bb745: ; preds = %bb20 + unreachable + +bb1098: ; preds = %bb20 + unreachable + +bb1287: ; preds = %bb20 + unreachable +} diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll new file mode 100644 index 0000000000000..64309c492dd8a --- /dev/null +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -0,0 +1,36 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s +; rdar://7353541 + +; The generated code is no where near ideal. It's not recognizing the two +; constantpool entries being loaded can be merged into one. + +@GV = external global i32 ; <i32*> [#uses=2] + +define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind { +entry: +; CHECK: t: +; CHECK: cbz + %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1] + br i1 %0, label %return, label %bb.nph + +bb.nph: ; preds = %entry +; CHECK: BB#1 +; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_0 +; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_1 + %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1] + %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2] + %scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1] + %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1] + %3 = add nsw i32 %1, %2 ; <i32> [#uses=2] + store i32 %3, i32* @GV, align 4 + %4 = add i32 %i.03, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll index e1f9cdbf8c643..aae9f5c0af714 100644 --- a/test/CodeGen/Thumb2/thumb2-bcc.ll +++ b/test/CodeGen/Thumb2/thumb2-bcc.ll @@ -2,8 +2,8 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it define i32 @t1(i32 %a, i32 %b, i32 %c) { -; CHECK: t1 -; CHECK: beq +; CHECK: t1: +; CHECK: cbz %tmp2 = icmp eq i32 %a, 0 br i1 %tmp2, label %cond_false, label %cond_true diff --git a/test/CodeGen/Thumb2/thumb2-bfc.ll b/test/CodeGen/Thumb2/thumb2-bfc.ll index d33cf7ebdb27f..b486045ab5015 100644 --- a/test/CodeGen/Thumb2/thumb2-bfc.ll +++ b/test/CodeGen/Thumb2/thumb2-bfc.ll @@ -1,25 +1,32 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "bfc " | count 3 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; 4278190095 = 0xff00000f define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: bfc r %tmp = and i32 %a, 4278190095 ret i32 %tmp } ; 4286578688 = 0xff800000 define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: bfc r %tmp = and i32 %a, 4286578688 ret i32 %tmp } ; 4095 = 0x00000fff define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: bfc r %tmp = and i32 %a, 4095 ret i32 %tmp } ; 2147483646 = 0x7ffffffe not implementable w/ BFC define i32 @f4(i32 %a) { +; CHECK: f4: %tmp = and i32 %a, 2147483646 ret i32 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll index b46cb5f7c70e9..129838457b261 100644 --- a/test/CodeGen/Thumb2/thumb2-branch.ll +++ b/test/CodeGen/Thumb2/thumb2-branch.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s define void @f1(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f1: -; CHECK bne LBB +; CHECK: bne LBB %tmp = icmp eq i32 %a, %b ; <i1> [#uses=1] br i1 %tmp, label %cond_true, label %return @@ -18,7 +18,7 @@ return: ; preds = %entry define void @f2(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f2: -; CHECK bge LBB +; CHECK: bge LBB %tmp = icmp slt i32 %a, %b ; <i1> [#uses=1] br i1 %tmp, label %cond_true, label %return @@ -33,7 +33,7 @@ return: ; preds = %entry define void @f3(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f3: -; CHECK bhs LBB +; CHECK: bhs LBB %tmp = icmp ult i32 %a, %b ; <i1> [#uses=1] br i1 %tmp, label %cond_true, label %return @@ -48,7 +48,7 @@ return: ; preds = %entry define void @f4(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f4: -; CHECK blo LBB +; CHECK: blo LBB %tmp = icmp ult i32 %a, %b ; <i1> [#uses=1] br i1 %tmp, label %return, label %cond_true diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll new file mode 100644 index 0000000000000..64587c13fdd11 --- /dev/null +++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; rdar://7354379 + +declare arm_apcscc double @floor(double) nounwind readnone + +define void @t(i1 %a, double %b) { +entry: + br i1 %a, label %bb3, label %bb1 + +bb1: ; preds = %entry + unreachable + +bb3: ; preds = %entry + br i1 %a, label %bb7, label %bb5 + +bb5: ; preds = %bb3 + unreachable + +bb7: ; preds = %bb3 + br i1 %a, label %bb11, label %bb9 + +bb9: ; preds = %bb7 +; CHECK: @ BB#2: +; CHECK-NEXT: cbnz + %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0] + br label %bb11 + +bb11: ; preds = %bb9, %bb7 + %1 = getelementptr i32* undef, i32 0 + store i32 0, i32* %1 + ret void +} diff --git a/test/CodeGen/Thumb2/thumb2-clz.ll b/test/CodeGen/Thumb2/thumb2-clz.ll index 0bed0585b5d16..74728bfcc5a99 100644 --- a/test/CodeGen/Thumb2/thumb2-clz.ll +++ b/test/CodeGen/Thumb2/thumb2-clz.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | grep "clz " | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: clz r %tmp = tail call i32 @llvm.ctlz.i32(i32 %a) ret i32 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-cmn2.ll b/test/CodeGen/Thumb2/thumb2-cmn2.ll index c1fcac00e643b..c0e19f63a3095 100644 --- a/test/CodeGen/Thumb2/thumb2-cmn2.ll +++ b/test/CodeGen/Thumb2/thumb2-cmn2.ll @@ -1,25 +1,33 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "cmn\\.w " | grep {#187\\|#11141290\\|#-872363008\\|#1114112} | count 4 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; -0x000000bb = 4294967109 define i1 @f1(i32 %a) { +; CHECK: f1: +; CHECK: cmn.w {{r.*}}, #187 %tmp = icmp ne i32 %a, 4294967109 ret i1 %tmp } ; -0x00aa00aa = 4283826006 define i1 @f2(i32 %a) { +; CHECK: f2: +; CHECK: cmn.w {{r.*}}, #11141290 %tmp = icmp eq i32 %a, 4283826006 ret i1 %tmp } ; -0xcc00cc00 = 872363008 define i1 @f3(i32 %a) { +; CHECK: f3: +; CHECK: cmn.w {{r.*}}, #-872363008 %tmp = icmp ne i32 %a, 872363008 ret i1 %tmp } ; -0x00110000 = 4293853184 define i1 @f4(i32 %a) { +; CHECK: f4: +; CHECK: cmn.w {{r.*}}, #1114112 %tmp = icmp eq i32 %a, 4293853184 ret i1 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-eor2.ll b/test/CodeGen/Thumb2/thumb2-eor2.ll index 185634cdd6fc9..6b2e9dcf3d1f8 100644 --- a/test/CodeGen/Thumb2/thumb2-eor2.ll +++ b/test/CodeGen/Thumb2/thumb2-eor2.ll @@ -1,31 +1,41 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep "eor " | grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 5 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; 0x000000bb = 187 define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: eor {{.*}}#187 %tmp = xor i32 %a, 187 ret i32 %tmp } ; 0x00aa00aa = 11141290 define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: eor {{.*}}#11141290 %tmp = xor i32 %a, 11141290 ret i32 %tmp } ; 0xcc00cc00 = 3422604288 define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: eor {{.*}}#-872363008 %tmp = xor i32 %a, 3422604288 ret i32 %tmp } ; 0xdddddddd = 3722304989 define i32 @f4(i32 %a) { +; CHECK: f4: +; CHECK: eor {{.*}}#-572662307 %tmp = xor i32 %a, 3722304989 ret i32 %tmp } ; 0x00110000 = 1114112 define i32 @f5(i32 %a) { +; CHECK: f5: +; CHECK: eor {{.*}}#1114112 %tmp = xor i32 %a, 1114112 ret i32 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll index 8606e327a637b..1dc3614993bd3 100644 --- a/test/CodeGen/Thumb2/thumb2-mov.ll +++ b/test/CodeGen/Thumb2/thumb2-mov.ll @@ -5,38 +5,40 @@ ; var 2.1 - 0x00ab00ab define i32 @t2_const_var2_1_ok_1(i32 %lhs) { ;CHECK: t2_const_var2_1_ok_1: -;CHECK: #11206827 +;CHECK: add.w r0, r0, #11206827 %ret = add i32 %lhs, 11206827 ; 0x00ab00ab ret i32 %ret } define i32 @t2_const_var2_1_ok_2(i32 %lhs) { ;CHECK: t2_const_var2_1_ok_2: -;CHECK: #11206656 -;CHECK: #187 +;CHECK: add.w r0, r0, #11206656 +;CHECK: adds r0, #187 %ret = add i32 %lhs, 11206843 ; 0x00ab00bb ret i32 %ret } define i32 @t2_const_var2_1_ok_3(i32 %lhs) { ;CHECK: t2_const_var2_1_ok_3: -;CHECK: #11206827 -;CHECK: #16777216 +;CHECK: add.w r0, r0, #11206827 +;CHECK: add.w r0, r0, #16777216 %ret = add i32 %lhs, 27984043 ; 0x01ab00ab ret i32 %ret } define i32 @t2_const_var2_1_ok_4(i32 %lhs) { ;CHECK: t2_const_var2_1_ok_4: -;CHECK: #16777472 -;CHECK: #11206827 +;CHECK: add.w r0, r0, #16777472 +;CHECK: add.w r0, r0, #11206827 %ret = add i32 %lhs, 27984299 ; 0x01ab01ab ret i32 %ret } define i32 @t2_const_var2_1_fail_1(i32 %lhs) { ;CHECK: t2_const_var2_1_fail_1: -;CHECK: movt +;CHECK: movw r1, #43777 +;CHECK: movt r1, #427 +;CHECK: add r0, r1 %ret = add i32 %lhs, 28027649 ; 0x01abab01 ret i32 %ret } @@ -44,37 +46,40 @@ define i32 @t2_const_var2_1_fail_1(i32 %lhs) { ; var 2.2 - 0xab00ab00 define i32 @t2_const_var2_2_ok_1(i32 %lhs) { ;CHECK: t2_const_var2_2_ok_1: -;CHECK: #-1426019584 +;CHECK: add.w r0, r0, #-1426019584 %ret = add i32 %lhs, 2868947712 ; 0xab00ab00 ret i32 %ret } define i32 @t2_const_var2_2_ok_2(i32 %lhs) { ;CHECK: t2_const_var2_2_ok_2: -;CHECK: #-1426063360 -;CHECK: #47616 +;CHECK: add.w r0, r0, #-1426063360 +;CHECK: add.w r0, r0, #47616 %ret = add i32 %lhs, 2868951552 ; 0xab00ba00 ret i32 %ret } define i32 @t2_const_var2_2_ok_3(i32 %lhs) { ;CHECK: t2_const_var2_2_ok_3: -;CHECK: #-1426019584 +;CHECK: add.w r0, r0, #-1426019584 +;CHECK: adds r0, #16 %ret = add i32 %lhs, 2868947728 ; 0xab00ab10 ret i32 %ret } define i32 @t2_const_var2_2_ok_4(i32 %lhs) { ;CHECK: t2_const_var2_2_ok_4: -;CHECK: #-1426019584 -;CHECK: #1048592 +;CHECK: add.w r0, r0, #-1426019584 +;CHECK: add.w r0, r0, #1048592 %ret = add i32 %lhs, 2869996304 ; 0xab10ab10 ret i32 %ret } define i32 @t2_const_var2_2_fail_1(i32 %lhs) { ;CHECK: t2_const_var2_2_fail_1: -;CHECK: movt +;CHECK: movw r1, #43792 +;CHECK: movt r1, #4267 +;CHECK: add r0, r1 %ret = add i32 %lhs, 279685904 ; 0x10abab10 ret i32 %ret } @@ -82,35 +87,43 @@ define i32 @t2_const_var2_2_fail_1(i32 %lhs) { ; var 2.3 - 0xabababab define i32 @t2_const_var2_3_ok_1(i32 %lhs) { ;CHECK: t2_const_var2_3_ok_1: -;CHECK: #-1414812757 +;CHECK: add.w r0, r0, #-1414812757 %ret = add i32 %lhs, 2880154539 ; 0xabababab ret i32 %ret } define i32 @t2_const_var2_3_fail_1(i32 %lhs) { ;CHECK: t2_const_var2_3_fail_1: -;CHECK: movt +;CHECK: movw r1, #43962 +;CHECK: movt r1, #43947 +;CHECK: add r0, r1 %ret = add i32 %lhs, 2880154554 ; 0xabababba ret i32 %ret } define i32 @t2_const_var2_3_fail_2(i32 %lhs) { ;CHECK: t2_const_var2_3_fail_2: -;CHECK: movt +;CHECK: movw r1, #47787 +;CHECK: movt r1, #43947 +;CHECK: add r0, r1 %ret = add i32 %lhs, 2880158379 ; 0xababbaab ret i32 %ret } define i32 @t2_const_var2_3_fail_3(i32 %lhs) { ;CHECK: t2_const_var2_3_fail_3: -;CHECK: movt +;CHECK: movw r1, #43947 +;CHECK: movt r1, #43962 +;CHECK: add r0, r1 %ret = add i32 %lhs, 2881137579 ; 0xabbaabab ret i32 %ret } define i32 @t2_const_var2_3_fail_4(i32 %lhs) { ;CHECK: t2_const_var2_3_fail_4: -;CHECK: movt +;CHECK: movw r1, #43947 +;CHECK: movt r1, #47787 +;CHECK: add r0, r1 %ret = add i32 %lhs, 3131812779 ; 0xbaababab ret i32 %ret } @@ -118,36 +131,136 @@ define i32 @t2_const_var2_3_fail_4(i32 %lhs) { ; var 3 - 0x0F000000 define i32 @t2_const_var3_1_ok_1(i32 %lhs) { ;CHECK: t2_const_var3_1_ok_1: -;CHECK: #251658240 +;CHECK: add.w r0, r0, #251658240 %ret = add i32 %lhs, 251658240 ; 0x0F000000 ret i32 %ret } define i32 @t2_const_var3_2_ok_1(i32 %lhs) { ;CHECK: t2_const_var3_2_ok_1: -;CHECK: #3948544 +;CHECK: add.w r0, r0, #3948544 %ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000 ret i32 %ret } define i32 @t2_const_var3_2_ok_2(i32 %lhs) { ;CHECK: t2_const_var3_2_ok_2: -;CHECK: #2097152 -;CHECK: #1843200 +;CHECK: add.w r0, r0, #2097152 +;CHECK: add.w r0, r0, #1843200 %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000 ret i32 %ret } define i32 @t2_const_var3_3_ok_1(i32 %lhs) { ;CHECK: t2_const_var3_3_ok_1: -;CHECK: #258 +;CHECK: add.w r0, r0, #258 %ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010 ret i32 %ret } define i32 @t2_const_var3_4_ok_1(i32 %lhs) { ;CHECK: t2_const_var3_4_ok_1: -;CHECK: #-268435456 +;CHECK: add.w r0, r0, #-268435456 %ret = add i32 %lhs, 4026531840 ; 0xF0000000 ret i32 %ret } + +define i32 @t2MOVTi16_ok_1(i32 %a) { +; CHECK: t2MOVTi16_ok_1: +; CHECK: movt r0, #1234 + %1 = and i32 %a, 65535 + %2 = shl i32 1234, 16 + %3 = or i32 %1, %2 + + ret i32 %3 +} + +define i32 @t2MOVTi16_test_1(i32 %a) { +; CHECK: t2MOVTi16_test_1: +; CHECK: movt r0, #1234 + %1 = shl i32 255, 8 + %2 = shl i32 1234, 8 + %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3 + %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4 + %5 = and i32 %a, %3 + %6 = or i32 %4, %5 + + ret i32 %6 +} + +define i32 @t2MOVTi16_test_2(i32 %a) { +; CHECK: t2MOVTi16_test_2: +; CHECK: movt r0, #1234 + %1 = shl i32 255, 8 + %2 = shl i32 1234, 8 + %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3 + %4 = shl i32 %2, 6 + %5 = and i32 %a, %3 + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 + %7 = or i32 %5, %6 + + ret i32 %7 +} + +define i32 @t2MOVTi16_test_3(i32 %a) { +; CHECK: t2MOVTi16_test_3: +; CHECK: movt r0, #1234 + %1 = shl i32 255, 8 + %2 = shl i32 1234, 8 + %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3 + %4 = shl i32 %2, 6 + %5 = and i32 %a, %3 + %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 + %7 = lshr i32 %6, 6 + %8 = shl i32 %7, 6 + %9 = or i32 %5, %8 + + ret i32 %8 +} + +; 171 = 0x000000ab +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: movs r0, #171 + %tmp = add i32 0, 171 + ret i32 %tmp +} + +; 1179666 = 0x00120012 +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: mov.w r0, #1179666 + %tmp = add i32 0, 1179666 + ret i32 %tmp +} + +; 872428544 = 0x34003400 +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: mov.w r0, #872428544 + %tmp = add i32 0, 872428544 + ret i32 %tmp +} + +; 1448498774 = 0x56565656 +define i32 @f4(i32 %a) { +; CHECK: f4: +; CHECK: mov.w r0, #1448498774 + %tmp = add i32 0, 1448498774 + ret i32 %tmp +} + +; 66846720 = 0x03fc0000 +define i32 @f5(i32 %a) { +; CHECK: f5: +; CHECK: mov.w r0, #66846720 + %tmp = add i32 0, 66846720 + ret i32 %tmp +} + +define i32 @f6(i32 %a) { +;CHECK: f6 +;CHECK: movw r0, #65535 + %tmp = add i32 0, 65535 + ret i32 %tmp +} diff --git a/test/CodeGen/Thumb2/thumb2-str_post.ll b/test/CodeGen/Thumb2/thumb2-str_post.ll index bee58105daebb..bbfb447ca3efd 100644 --- a/test/CodeGen/Thumb2/thumb2-str_post.ll +++ b/test/CodeGen/Thumb2/thumb2-str_post.ll @@ -1,9 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep {strh .*\\\[.*\], #-4} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ -; RUN: grep {str .*\\\[.*\],} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i16 @test1(i32* %X, i16* %A) { +; CHECK: test1: +; CHECK: strh {{.*}}[{{.*}}], #-4 %Y = load i32* %X ; <i32> [#uses=1] %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1] store i16 %tmp1, i16* %A @@ -13,6 +12,8 @@ define i16 @test1(i32* %X, i16* %A) { } define i32 @test2(i32* %X, i32* %A) { +; CHECK: test2: +; CHECK: str {{.*}}[{{.*}}], %Y = load i32* %X ; <i32> [#uses=1] store i32 %Y, i32* %A %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll index 0626d28eefee4..721d4c945b144 100644 --- a/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll +++ b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll @@ -1,6 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& \ -; RUN: grep {1 .*folded into instructions} -; Increment in loop bb.128.i adjusted to 2, to prevent loop reversal from +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; Increment in loop bb.i28.i adjusted to 2, to prevent loop reversal from ; kicking in. declare fastcc void @rdft(i32, i32, double*, i32*, double*) @@ -34,6 +33,9 @@ cond_next36.i: ; preds = %cond_next.i br label %bb.i28.i bb.i28.i: ; preds = %bb.i28.i, %cond_next36.i +; CHECK: %bb.i28.i +; CHECK: addl $2 +; CHECK: addl $2 %j.0.reg2mem.0.i16.i = phi i32 [ 0, %cond_next36.i ], [ %indvar.next39.i, %bb.i28.i ] ; <i32> [#uses=2] %din_addr.1.reg2mem.0.i17.i = phi double [ 0.000000e+00, %cond_next36.i ], [ %tmp16.i25.i, %bb.i28.i ] ; <double> [#uses=1] %tmp1.i18.i = fptosi double %din_addr.1.reg2mem.0.i17.i to i32 ; <i32> [#uses=2] diff --git a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll index 9b52c5c06990c..7463a0eebf340 100644 --- a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll +++ b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll @@ -3,7 +3,7 @@ @.str = internal constant [48 x i8] c"transformed bounds: (%.2f, %.2f), (%.2f, %.2f)\0A\00" ; <[48 x i8]*> [#uses=1] -define void @minmax(float* %result) nounwind { +define void @minmax(float* %result) nounwind optsize { entry: %tmp2 = load float* %result, align 4 ; <float> [#uses=6] %tmp4 = getelementptr float* %result, i32 2 ; <float*> [#uses=5] diff --git a/test/CodeGen/X86/2008-05-12-tailmerge-5.ll b/test/CodeGen/X86/2008-05-12-tailmerge-5.ll index 1f95a2409fe74..4852e89c4d991 100644 --- a/test/CodeGen/X86/2008-05-12-tailmerge-5.ll +++ b/test/CodeGen/X86/2008-05-12-tailmerge-5.ll @@ -6,7 +6,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin8" %struct.BoundaryAlignment = type { [3 x i8], i8, i16, i16, i8, [2 x i8] } -define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind { +define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind optsize { entry: %str_addr = alloca %struct.BoundaryAlignment ; <%struct.BoundaryAlignment*> [#uses=7] %s_addr = alloca i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/X86/2009-10-25-RewriterBug.ll b/test/CodeGen/X86/2009-10-25-RewriterBug.ll new file mode 100644 index 0000000000000..5b4e818359e90 --- /dev/null +++ b/test/CodeGen/X86/2009-10-25-RewriterBug.ll @@ -0,0 +1,171 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim + +%struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t* } +%struct.FrameStore = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.StorablePicture*, %struct.StorablePicture*, %struct.StorablePicture* } +%struct.StorablePicture = type { i32, i32, i32, i32, i32, [50 x [6 x [33 x i64]]], [50 x [6 x [33 x i64]]], [50 x [6 x [33 x i64]]], [50 x [6 x [33 x i64]]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16**, i16***, i8*, i16**, i8***, i64***, i64***, i16****, i8**, i8**, %struct.StorablePicture*, %struct.StorablePicture*, %struct.StorablePicture*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, %struct.DecRefPicMarking_t*, i32 } + +define fastcc void @insert_picture_in_dpb(%struct.FrameStore* nocapture %fs, %struct.StorablePicture* %p) nounwind ssp { +entry: + %0 = getelementptr inbounds %struct.FrameStore* %fs, i64 0, i32 12 ; <%struct.StorablePicture**> [#uses=1] + %1 = icmp eq i32 undef, 0 ; <i1> [#uses=1] + br i1 %1, label %bb.i, label %bb36.i + +bb.i: ; preds = %entry + br i1 undef, label %bb3.i, label %bb14.preheader.i + +bb3.i: ; preds = %bb.i + unreachable + +bb14.preheader.i: ; preds = %bb.i + br i1 undef, label %bb9.i, label %bb20.preheader.i + +bb9.i: ; preds = %bb9.i, %bb14.preheader.i + br i1 undef, label %bb9.i, label %bb20.preheader.i + +bb20.preheader.i: ; preds = %bb9.i, %bb14.preheader.i + br i1 undef, label %bb18.i, label %bb29.preheader.i + +bb18.i: ; preds = %bb20.preheader.i + unreachable + +bb29.preheader.i: ; preds = %bb20.preheader.i + br i1 undef, label %bb24.i, label %bb30.i + +bb24.i: ; preds = %bb29.preheader.i + unreachable + +bb30.i: ; preds = %bb29.preheader.i + store i32 undef, i32* undef, align 8 + br label %bb67.preheader.i + +bb36.i: ; preds = %entry + br label %bb67.preheader.i + +bb67.preheader.i: ; preds = %bb36.i, %bb30.i + %2 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=2] + %3 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=2] + %4 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=2] + %5 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + %6 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + %7 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + %8 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + %9 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + %10 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + %11 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + %12 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1] + br i1 undef, label %bb38.i, label %bb68.i + +bb38.i: ; preds = %bb66.i, %bb67.preheader.i + %13 = phi %struct.StorablePicture* [ %37, %bb66.i ], [ %2, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %14 = phi %struct.StorablePicture* [ %38, %bb66.i ], [ %3, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %15 = phi %struct.StorablePicture* [ %39, %bb66.i ], [ %4, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %16 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %5, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %17 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %6, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %18 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %7, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %19 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %8, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %20 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %9, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %21 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %10, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %22 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %11, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %23 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %12, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1] + %indvar248.i = phi i64 [ %indvar.next249.i, %bb66.i ], [ 0, %bb67.preheader.i ] ; <i64> [#uses=3] + %storemerge52.i = trunc i64 %indvar248.i to i32 ; <i32> [#uses=1] + %24 = getelementptr inbounds %struct.StorablePicture* %23, i64 0, i32 19 ; <i32*> [#uses=0] + br i1 undef, label %bb.nph51.i, label %bb66.i + +bb.nph51.i: ; preds = %bb38.i + %25 = sdiv i32 %storemerge52.i, 8 ; <i32> [#uses=0] + br label %bb39.i + +bb39.i: ; preds = %bb64.i, %bb.nph51.i + %26 = phi %struct.StorablePicture* [ %17, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=1] + %27 = phi %struct.StorablePicture* [ %18, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0] + %28 = phi %struct.StorablePicture* [ %19, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0] + %29 = phi %struct.StorablePicture* [ %20, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0] + %30 = phi %struct.StorablePicture* [ %21, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0] + %31 = phi %struct.StorablePicture* [ %22, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0] + br i1 undef, label %bb57.i, label %bb40.i + +bb40.i: ; preds = %bb39.i + br i1 undef, label %bb57.i, label %bb41.i + +bb41.i: ; preds = %bb40.i + %storemerge10.i = select i1 undef, i32 2, i32 4 ; <i32> [#uses=1] + %32 = zext i32 %storemerge10.i to i64 ; <i64> [#uses=1] + br i1 undef, label %bb45.i, label %bb47.i + +bb45.i: ; preds = %bb41.i + %33 = getelementptr inbounds %struct.StorablePicture* %26, i64 0, i32 5, i64 undef, i64 %32, i64 undef ; <i64*> [#uses=1] + %34 = load i64* %33, align 8 ; <i64> [#uses=1] + br label %bb47.i + +bb47.i: ; preds = %bb45.i, %bb41.i + %storemerge11.i = phi i64 [ %34, %bb45.i ], [ 0, %bb41.i ] ; <i64> [#uses=0] + %scevgep246.i = getelementptr i64* undef, i64 undef ; <i64*> [#uses=0] + br label %bb64.i + +bb57.i: ; preds = %bb40.i, %bb39.i + br i1 undef, label %bb58.i, label %bb60.i + +bb58.i: ; preds = %bb57.i + br label %bb60.i + +bb60.i: ; preds = %bb58.i, %bb57.i + %35 = load i64*** undef, align 8 ; <i64**> [#uses=1] + %scevgep256.i = getelementptr i64** %35, i64 %indvar248.i ; <i64**> [#uses=1] + %36 = load i64** %scevgep256.i, align 8 ; <i64*> [#uses=1] + %scevgep243.i = getelementptr i64* %36, i64 undef ; <i64*> [#uses=1] + store i64 -1, i64* %scevgep243.i, align 8 + br label %bb64.i + +bb64.i: ; preds = %bb60.i, %bb47.i + br i1 undef, label %bb39.i, label %bb66.i + +bb66.i: ; preds = %bb64.i, %bb38.i + %37 = phi %struct.StorablePicture* [ %13, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=2] + %38 = phi %struct.StorablePicture* [ %14, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=2] + %39 = phi %struct.StorablePicture* [ %15, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=2] + %40 = phi %struct.StorablePicture* [ %16, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=8] + %indvar.next249.i = add i64 %indvar248.i, 1 ; <i64> [#uses=1] + br i1 undef, label %bb38.i, label %bb68.i + +bb68.i: ; preds = %bb66.i, %bb67.preheader.i + %41 = phi %struct.StorablePicture* [ %2, %bb67.preheader.i ], [ %37, %bb66.i ] ; <%struct.StorablePicture*> [#uses=0] + %42 = phi %struct.StorablePicture* [ %3, %bb67.preheader.i ], [ %38, %bb66.i ] ; <%struct.StorablePicture*> [#uses=1] + %43 = phi %struct.StorablePicture* [ %4, %bb67.preheader.i ], [ %39, %bb66.i ] ; <%struct.StorablePicture*> [#uses=1] + br i1 undef, label %bb.nph48.i, label %bb108.i + +bb.nph48.i: ; preds = %bb68.i + br label %bb80.i + +bb80.i: ; preds = %bb104.i, %bb.nph48.i + %44 = phi %struct.StorablePicture* [ %42, %bb.nph48.i ], [ null, %bb104.i ] ; <%struct.StorablePicture*> [#uses=1] + %45 = phi %struct.StorablePicture* [ %43, %bb.nph48.i ], [ null, %bb104.i ] ; <%struct.StorablePicture*> [#uses=1] + br i1 undef, label %bb.nph39.i, label %bb104.i + +bb.nph39.i: ; preds = %bb80.i + br label %bb81.i + +bb81.i: ; preds = %bb102.i, %bb.nph39.i + %46 = phi %struct.StorablePicture* [ %44, %bb.nph39.i ], [ %48, %bb102.i ] ; <%struct.StorablePicture*> [#uses=0] + %47 = phi %struct.StorablePicture* [ %45, %bb.nph39.i ], [ %48, %bb102.i ] ; <%struct.StorablePicture*> [#uses=0] + br i1 undef, label %bb83.i, label %bb82.i + +bb82.i: ; preds = %bb81.i + br i1 undef, label %bb83.i, label %bb101.i + +bb83.i: ; preds = %bb82.i, %bb81.i + br label %bb102.i + +bb101.i: ; preds = %bb82.i + br label %bb102.i + +bb102.i: ; preds = %bb101.i, %bb83.i + %48 = load %struct.StorablePicture** %0, align 8 ; <%struct.StorablePicture*> [#uses=2] + br i1 undef, label %bb81.i, label %bb104.i + +bb104.i: ; preds = %bb102.i, %bb80.i + br label %bb80.i + +bb108.i: ; preds = %bb68.i + unreachable +} diff --git a/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll b/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll new file mode 100644 index 0000000000000..d84b63a21be3b --- /dev/null +++ b/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s +; rdar://7362871 + +define void @bar(i32 %b, i32 %a) nounwind optsize ssp { +entry: +; CHECK: leal 15(%rsi), %edi +; CHECK-NOT: movl +; CHECK: call _foo + %0 = add i32 %a, 15 ; <i32> [#uses=1] + %1 = zext i32 %0 to i64 ; <i64> [#uses=1] + tail call void @foo(i64 %1) nounwind + ret void +} + +declare void @foo(i64) diff --git a/test/CodeGen/X86/break-anti-dependencies.ll b/test/CodeGen/X86/break-anti-dependencies.ll index 6b245c103e204..972b3cd43cf65 100644 --- a/test/CodeGen/X86/break-anti-dependencies.ll +++ b/test/CodeGen/X86/break-anti-dependencies.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=false > %t +; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=none > %t ; RUN: grep {%xmm0} %t | count 14 ; RUN: not grep {%xmm1} %t -; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies > %t +; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=critical > %t ; RUN: grep {%xmm0} %t | count 7 ; RUN: grep {%xmm1} %t | count 7 diff --git a/test/CodeGen/X86/constant-pool-sharing.ll b/test/CodeGen/X86/constant-pool-sharing.ll new file mode 100644 index 0000000000000..c3e97adffb19c --- /dev/null +++ b/test/CodeGen/X86/constant-pool-sharing.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; llc should share constant pool entries between this integer vector +; and this floating-point vector since they have the same encoding. + +; CHECK: LCPI1_0(%rip), %xmm0 +; CHECK: movaps %xmm0, (%rdi) +; CHECK: movaps %xmm0, (%rsi) + +define void @foo(<4 x i32>* %p, <4 x float>* %q, i1 %t) nounwind { +entry: + br label %loop +loop: + store <4 x i32><i32 1073741824, i32 1073741824, i32 1073741824, i32 1073741824>, <4 x i32>* %p + store <4 x float><float 2.0, float 2.0, float 2.0, float 2.0>, <4 x float>* %q + br i1 %t, label %loop, label %ret +ret: + ret void +} diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll index 2b4b83259b82a..337f1b2a8e75f 100644 --- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll +++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll @@ -2,7 +2,7 @@ ; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 5 ; RUN: grep {leal 1(\%rsi),} %t -define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2) nounwind { +define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2) nounwind optsize { entry: %0 = add i32 %i2, 1 ; <i32> [#uses=1] %1 = sext i32 %0 to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/large-gep-scale.ll b/test/CodeGen/X86/large-gep-scale.ll new file mode 100644 index 0000000000000..143294e8b07f2 --- /dev/null +++ b/test/CodeGen/X86/large-gep-scale.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=x86 | FileCheck %s +; PR5281 + +; After scaling, this type doesn't fit in memory. Codegen should generate +; correct addressing still. + +; CHECK: shll $2, %edx + +define fastcc i32* @_ada_smkr([2147483647 x i32]* %u, i32 %t) nounwind { + %x = getelementptr [2147483647 x i32]* %u, i32 %t, i32 0 + ret i32* %x +} diff --git a/test/CodeGen/X86/negative-stride-fptosi-user.ll b/test/CodeGen/X86/negative-stride-fptosi-user.ll new file mode 100644 index 0000000000000..332e0b9cc6e15 --- /dev/null +++ b/test/CodeGen/X86/negative-stride-fptosi-user.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=x86-64 | grep cvtsi2sd + +; LSR previously eliminated the sitofp by introducing an induction +; variable which stepped by a bogus ((double)UINT32_C(-1)). It's theoretically +; possible to eliminate the sitofp using a proper -1.0 step though; this +; test should be changed if that is done. + +define void @foo(i32 %N) nounwind { +entry: + %0 = icmp slt i32 %N, 0 ; <i1> [#uses=1] + br i1 %0, label %bb, label %return + +bb: ; preds = %bb, %entry + %i.03 = phi i32 [ 0, %entry ], [ %2, %bb ] ; <i32> [#uses=2] + %1 = sitofp i32 %i.03 to double ; <double> [#uses=1] + tail call void @bar(double %1) nounwind + %2 = add nsw i32 %i.03, -1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %2, %N ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} + +declare void @bar(double) diff --git a/test/CodeGen/X86/palignr-2.ll b/test/CodeGen/X86/palignr-2.ll new file mode 100644 index 0000000000000..2936641e95d9f --- /dev/null +++ b/test/CodeGen/X86/palignr-2.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=x86 -mattr=+ssse3 | FileCheck %s +; rdar://7341330 + +@a = global [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 16 ; <[4 x i32]*> [#uses=1] +@c = common global [4 x i32] zeroinitializer, align 16 ; <[4 x i32]*> [#uses=1] +@b = global [4 x i32] [i32 0, i32 1, i32 2, i32 3], align 16 ; <[4 x i32]*> [#uses=1] + +define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp { +entry: +; CHECK: t1: +; palignr $3, %xmm1, %xmm0 + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i32 24) nounwind readnone + store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 + ret void +} + +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i32) nounwind readnone + +define void @t2() nounwind ssp { +entry: +; CHECK: t2: +; palignr $4, _b, %xmm0 + %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] + %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i32 32) nounwind readnone + store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 + ret void +} diff --git a/test/CodeGen/X86/pic-load-remat.ll b/test/CodeGen/X86/pic-load-remat.ll index 77297521cd0d8..d930f76a7747e 100644 --- a/test/CodeGen/X86/pic-load-remat.ll +++ b/test/CodeGen/X86/pic-load-remat.ll @@ -1,4 +1,10 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb +; XFAIL: * + +; This is XFAIL'd because MachineLICM is now hoisting all of the loads, and the pic +; base appears killed in the entry block when remat is making its decisions. Remat's +; simple heuristic decides against rematting because it doesn't want to extend the +; live-range of the pic base; this isn't necessarily optimal. define void @f() nounwind { entry: diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 4042a095c6c36..f8d542e525c61 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; Currently, floating-point selects are lowered to CFG triangles. ; This means that one side of the select is always unconditionally @@ -41,3 +41,108 @@ bb: return: ret void } + +; Sink instructions with dead EFLAGS defs. + +; CHECK: zzz: +; CHECK: je +; CHECK-NEXT: orb + +define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone { +entry: + %tmp = zext i8 %a to i32 ; <i32> [#uses=1] + %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1] + %tmp3 = or i8 %b, -128 ; <i8> [#uses=1] + %tmp4 = and i8 %b, 127 ; <i8> [#uses=1] + %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1] + ret i8 %b_addr.0 +} + +; Codegen should hoist and CSE these constants. + +; CHECK: vv: +; CHECK: LCPI4_0(%rip), %xmm0 +; CHECK: LCPI4_1(%rip), %xmm1 +; CHECK: LCPI4_2(%rip), %xmm2 +; CHECK: align +; CHECK-NOT: LCPI +; CHECK: ret + +@_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <<4 x float>*> [#uses=0] +@twoTo23.6008 = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <<4 x float>*> [#uses=0] + +define void @vv(float* %y, float* %x, i32* %n) nounwind ssp { +entry: + br label %bb60 + +bb: ; preds = %bb60 + %0 = bitcast float* %x_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1] + %1 = load <4 x float>* %0, align 16 ; <<4 x float>> [#uses=4] + %tmp20 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1] + %tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp25 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2] + %tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1] + %tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1] + %tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1] + %tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1] + %tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2] + %tmp45 = fadd <4 x float> %1, %tmp43 ; <<4 x float>> [#uses=1] + %tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2] + %tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %1, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1] + %2 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1] + %3 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %2) nounwind readnone ; <<4 x float>> [#uses=1] + %tmp53 = fadd <4 x float> %tmp47, %3 ; <<4 x float>> [#uses=1] + %tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1] + %tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1] + %4 = bitcast float* %y_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1] + store <4 x float> %tmp58, <4 x float>* %4, align 16 + %5 = getelementptr float* %x_addr.0, i64 4 ; <float*> [#uses=1] + %6 = getelementptr float* %y_addr.0, i64 4 ; <float*> [#uses=1] + %7 = add i32 %i.0, 4 ; <i32> [#uses=1] + br label %bb60 + +bb60: ; preds = %bb, %entry + %i.0 = phi i32 [ 0, %entry ], [ %7, %bb ] ; <i32> [#uses=2] + %x_addr.0 = phi float* [ %x, %entry ], [ %5, %bb ] ; <float*> [#uses=2] + %y_addr.0 = phi float* [ %y, %entry ], [ %6, %bb ] ; <float*> [#uses=2] + %8 = load i32* %n, align 4 ; <i32> [#uses=1] + %9 = icmp sgt i32 %8, %i.0 ; <i1> [#uses=1] + br i1 %9, label %bb, label %return + +return: ; preds = %bb60 + ret void +} + +declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone + +declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone + +; CodeGen should use the correct register class when extracting +; a load from a zero-extending load for hoisting. + +; CHECK: default_get_pch_validity: +; CHECK: movl cl_options_count(%rip), %ecx + +@cl_options_count = external constant i32 ; <i32*> [#uses=2] + +define void @default_get_pch_validity() nounwind { +entry: + %tmp4 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1] + %tmp5 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1] + br i1 %tmp5, label %bb6, label %bb2 + +bb2: ; preds = %bb2, %entry + %i.019 = phi i64 [ 0, %entry ], [ %tmp25, %bb2 ] ; <i64> [#uses=1] + %tmp25 = add i64 %i.019, 1 ; <i64> [#uses=2] + %tmp11 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1] + %tmp12 = zext i32 %tmp11 to i64 ; <i64> [#uses=1] + %tmp13 = icmp ugt i64 %tmp12, %tmp25 ; <i1> [#uses=1] + br i1 %tmp13, label %bb2, label %bb6 + +bb6: ; preds = %bb2, %entry + ret void +} diff --git a/test/CodeGen/X86/vec_ins_extract.ll b/test/CodeGen/X86/vec_ins_extract.ll index bf43deb1d19a6..daf222e395bf2 100644 --- a/test/CodeGen/X86/vec_ins_extract.ll +++ b/test/CodeGen/X86/vec_ins_extract.ll @@ -3,6 +3,7 @@ ; This checks that various insert/extract idiom work without going to the ; stack. +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" define void @test(<4 x float>* %F, float %f) { entry: diff --git a/test/CodeGen/X86/x86-64-jumps.ll b/test/CodeGen/X86/x86-64-jumps.ll new file mode 100644 index 0000000000000..5ed6a23ef876d --- /dev/null +++ b/test/CodeGen/X86/x86-64-jumps.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin10.0" + +define i8 @test1() nounwind ssp { +entry: + %0 = select i1 undef, i8* blockaddress(@test1, %bb), i8* blockaddress(@test1, %bb6) ; <i8*> [#uses=1] + indirectbr i8* %0, [label %bb, label %bb6] + +bb: ; preds = %entry + ret i8 1 + +bb6: ; preds = %entry + ret i8 2 +} + diff --git a/test/CodeGen/X86/x86-64-pic-10.ll b/test/CodeGen/X86/x86-64-pic-10.ll index 0f65e57449596..7baa7e59e1c3f 100644 --- a/test/CodeGen/X86/x86-64-pic-10.ll +++ b/test/CodeGen/X86/x86-64-pic-10.ll @@ -3,7 +3,7 @@ @g = alias weak i32 ()* @f -define void @g() { +define void @h() { entry: %tmp31 = call i32 @g() ret void |