9 files changed, 197 insertions, 93 deletions
diff --git a/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll
new file mode 100644
index 0000000000000..faaa725486f16
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=aarch64_be-- %s -o /dev/null -debug-only=isel -O0 2>&1 | FileCheck %s
+; REQUIRES: asserts
+
+; This test uses big endian in order to force an abort since it's not currently supported for GISel.
+; The purpose is to check that we don't fall back to FastISel. Checking the pass structure is insufficient
+; because the FastISel is set up in the SelectionDAGISel, so it doesn't appear on the pass structure.
+
+; CHECK-NOT: Enabling fast-ise
+define void @empty() {
+  ret void
+}
diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
new file mode 100644
index 0000000000000..9bda39c9fca7f
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
@@ -0,0 +1,14 @@
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
+
+@g = global i16 0, align 2
+declare void @bar(i32)
+
+; Check that only one load is generated. We fall back to
+define hidden void @foo() {
+; CHECK-NOT: ldrh
+; CHECK: ldrsh
+  %1 = load volatile i16, i16* @g, align 2
+  %2 = sext i16 %1 to i32
+  call void @bar(i32 %2)
+  ret void
+}
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
index 4ed84ed79bbaa..c3ed3316ad317 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -75,7 +75,7 @@ body: |
     ; CHECK: %w0 = COPY [[C]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
     ; CHECK: %x0 = COPY [[C1]](s64)
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT half 0xH0000
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
     ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
     ; CHECK: %w0 = COPY [[ANYEXT]](s32)
diff --git a/test/CodeGen/AArch64/dllimport.ll b/test/CodeGen/AArch64/dllimport.ll
index fad049a54cd22..281c847a39a56 100644
--- a/test/CodeGen/AArch64/dllimport.ll
+++ b/test/CodeGen/AArch64/dllimport.ll
@@ -1,4 +1,6 @@
-; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype asm -o - %s | FileCheck %s
+; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,DAG-ISEL
+; RUN: llc -mtriple aarch64-unknown-windows-msvc -fast-isel -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,FAST-ISEL
+; RUN: llc -mtriple aarch64-unknown-windows-msvc -O0 -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,GLOBAL-ISEL,GLOBAL-ISEL-FALLBACK
 
 @var = external dllimport global i32
 @ext = external global i32
@@ -23,7 +25,11 @@ define i32 @get_ext() {
 
 ; CHECK-LABEL: get_ext
 ; CHECK: adrp x8, ext
-; CHECK: ldr w0, [x8, ext]
+; DAG-ISEL: ldr w0, [x8, ext]
+; FAST-ISEL: add x8, x8, ext
+; FAST-ISEL: ldr w0, [x8]
+; GLOBAL-ISEL-FALLBACK: add x8, x8, ext
+; GLOBAL-ISEL-FALLBACK: ldr w0, [x8]
 ; CHECK: ret
 
 define i32* @get_var_pointer() {
@@ -31,8 +37,8 @@ define i32* @get_var_pointer() {
 }
 
 ; CHECK-LABEL: get_var_pointer
-; CHECK: adrp x0, __imp_var
-; CHECK: ldr x0, [x0, __imp_var]
+; CHECK: adrp [[REG1:x[0-9]+]], __imp_var
+; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]], __imp_var]
 ; CHECK: ret
 
 define i32 @call_external() {
@@ -51,4 +57,6 @@ define i32 @call_internal() {
 }
 
 ; CHECK-LABEL: call_internal
-; CHECK: b internal
+; DAG-ISEL: b internal
+; FAST-ISEL: b internal
+; GLOBAL-ISEL: bl internal
diff --git a/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir b/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
new file mode 100644
index 0000000000000..fc19173a176b9
--- /dev/null
+++ b/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-apple-ios -run-pass regallocfast -o - %s | FileCheck %s
+# This test used to crash the fast register alloc.
+# Basically, when a basic block has liveins, the fast regalloc
+# was deferencing the begin iterator of this block. However,
+# when this block is empty and it will just crashed!
+---
+name:            crashing
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: crashing
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: %x0, %x1
+  ; CHECK: bb.1:
+  ; CHECK:   renamable %w0 = MOVi32imm -1
+  ; CHECK:   RET_ReallyLR implicit killed %w0
+  bb.1:
+    liveins: %x0, %x1
+
+  bb.2:
+    %0:gpr32 = MOVi32imm -1
+    %w0 = COPY %0
+    RET_ReallyLR implicit %w0
+
+...
diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
index d6b0628956a02..fabed795c5686 100644
--- a/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
+++ b/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
@@ -234,6 +234,23 @@ define amdgpu_ps void @wqm(float %a) {
   ret void
 }
 
+; This checks that we use the 64-bit encoding when the operand is a SGPR.
+; SI-LABEL: {{^}}test_sgpr:
+; SI: v_cmpx_ge_f32_e64
+define amdgpu_ps void @test_sgpr(float inreg %a) #0 {
+  %c = fcmp ole float %a, 1.000000e+00
+  call void @llvm.amdgcn.kill(i1 %c) #1
+  ret void
+}
+
+; SI-LABEL: {{^}}test_non_inline_imm_sgpr:
+; SI-NOT: v_cmpx_ge_f32_e64
+define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 {
+  %c = fcmp ole float %a, 1.500000e+00
+  call void @llvm.amdgcn.kill(i1 %c) #1
+  ret void
+}
+
 declare void @llvm.amdgcn.kill(i1) #0
 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
 declare i1 @llvm.amdgcn.wqm.vote(i1)
diff --git a/test/CodeGen/AMDGPU/multilevel-break.ll b/test/CodeGen/AMDGPU/multilevel-break.ll
index 5b556f12f0d6d..8cc02d497098b 100644
--- a/test/CodeGen/AMDGPU/multilevel-break.ll
+++ b/test/CodeGen/AMDGPU/multilevel-break.ll
@@ -66,10 +66,9 @@ ENDIF:                                            ; preds = %LOOP
 
 ; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop(
 ; OPT: llvm.amdgcn.break
-; OPT: llvm.amdgcn.break
+; OPT: llvm.amdgcn.loop
 ; OPT: llvm.amdgcn.if.break
 ; OPT: llvm.amdgcn.if.break
-; OPT: llvm.amdgcn.loop
 ; OPT: llvm.amdgcn.end.cf
 
 ; GCN-LABEL: {{^}}multi_if_break_loop:
diff --git a/test/CodeGen/AMDGPU/nested-loop-conditions.ll b/test/CodeGen/AMDGPU/nested-loop-conditions.ll
index 96d2841e685f4..672549c8ea636 100644
--- a/test/CodeGen/AMDGPU/nested-loop-conditions.ll
+++ b/test/CodeGen/AMDGPU/nested-loop-conditions.ll
@@ -124,100 +124,55 @@ bb23:                                             ; preds = %bb10
 ; Earlier version of above, before a run of the structurizer.
 ; IR-LABEL: @nested_loop_conditions(
 
-; IR: %tmp1235 = icmp slt i32 %tmp1134, 9
-; IR:   br i1 %tmp1235, label %bb14.lr.ph, label %Flow
-
-; IR: bb14.lr.ph:
-; IR: br label %bb14
-
-; IR: Flow3:
-; IR:   call void @llvm.amdgcn.end.cf(i64 %18)
-; IR:   %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %17)
-; IR:   %1 = extractvalue { i1, i64 } %0, 0
-; IR:   %2 = extractvalue { i1, i64 } %0, 1
-; IR:   br i1 %1, label %bb4.bb13_crit_edge, label %Flow4
-
-; IR: bb4.bb13_crit_edge:
-; IR:   br label %Flow4
-
-; IR: Flow4:
-; IR:   %3 = phi i1 [ true, %bb4.bb13_crit_edge ], [ false, %Flow3 ]
-; IR:   call void @llvm.amdgcn.end.cf(i64 %2)
-; IR:   br label %Flow
-
-; IR: bb13:
-; IR:   br label %bb31
-
-; IR: Flow:
-; IR:   %4 = phi i1 [ %3, %Flow4 ], [ true, %bb ]
-; IR:   %5 = call { i1, i64 } @llvm.amdgcn.if(i1 %4)
-; IR:   %6 = extractvalue { i1, i64 } %5, 0
-; IR:   %7 = extractvalue { i1, i64 } %5, 1
-; IR:   br i1 %6, label %bb13, label %bb31
-
-; IR: bb14:
-; IR:   %phi.broken = phi i64 [ %18, %Flow2 ], [ 0, %bb14.lr.ph ]
-; IR:   %tmp1037 = phi i32 [ %tmp1033, %bb14.lr.ph ], [ %16, %Flow2 ]
-; IR:   %tmp936 = phi <4 x i32> [ %tmp932, %bb14.lr.ph ], [ %15, %Flow2 ]
-; IR:   %tmp15 = icmp eq i32 %tmp1037, 1
-; IR:   %8 = xor i1 %tmp15, true
-; IR:   %9 = call { i1, i64 } @llvm.amdgcn.if(i1 %8)
-; IR:   %10 = extractvalue { i1, i64 } %9, 0
-; IR:   %11 = extractvalue { i1, i64 } %9, 1
-; IR:   br i1 %10, label %bb31.loopexit, label %Flow1
+; IR: Flow7:
+; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %17)
+; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %15)
+; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0
+; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1
+; IR-NEXT: br i1 %1, label %bb4.bb13_crit_edge, label %Flow8
 
 ; IR: Flow1:
-; IR:   %12 = call { i1, i64 } @llvm.amdgcn.else(i64 %11)
-; IR:   %13 = extractvalue { i1, i64 } %12, 0
-; IR:   %14 = extractvalue { i1, i64 } %12, 1
-; IR:   br i1 %13, label %bb16, label %Flow2
-
-; IR: bb16:
-; IR:   %tmp17 = bitcast i64 %tmp3 to <2 x i32>
-; IR:   br label %bb18
+; IR-NEXT: %loop.phi = phi i64 [ %loop.phi9, %Flow6 ], [ %phi.broken, %bb14 ]
+; IR-NEXT: %13 = phi <4 x i32> [ %29, %Flow6 ], [ undef, %bb14 ]
+; IR-NEXT: %14 = phi i32 [ %30, %Flow6 ], [ undef, %bb14 ]
+; IR-NEXT: %15 = phi i1 [ %31, %Flow6 ], [ false, %bb14 ]
+; IR-NEXT: %16 = phi i1 [ false, %Flow6 ], [ %8, %bb14 ]
+; IR-NEXT: %17 = call i64 @llvm.amdgcn.else.break(i64 %11, i64 %loop.phi)
+; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %11)
+; IR-NEXT: %18 = call i1 @llvm.amdgcn.loop(i64 %17)
+; IR-NEXT: br i1 %18, label %Flow7, label %bb14
 
 ; IR: Flow2:
-; IR:   %loop.phi = phi i64 [ %21, %bb21 ], [ %phi.broken, %Flow1 ]
-; IR:   %15 = phi <4 x i32> [ %tmp9, %bb21 ], [ undef, %Flow1 ]
-; IR:   %16 = phi i32 [ %tmp10, %bb21 ], [ undef, %Flow1 ]
-; IR:   %17 = phi i1 [ %20, %bb21 ], [ false, %Flow1 ]
-; IR:   %18 = call i64 @llvm.amdgcn.else.break(i64 %14, i64 %loop.phi)
-; IR:   call void @llvm.amdgcn.end.cf(i64 %14)
-; IR:   %19 = call i1 @llvm.amdgcn.loop(i64 %18)
-; IR:   br i1 %19, label %Flow3, label %bb14
-
-; IR: bb18:
-; IR:   %tmp19 = load volatile i32, i32 addrspace(1)* undef
-; IR:   %tmp20 = icmp slt i32 %tmp19, 9
-; IR:   br i1 %tmp20, label %bb21, label %bb18
+; IR-NEXT: %loop.phi10 = phi i64 [ %loop.phi11, %Flow5 ], [ %12, %bb16 ]
+; IR-NEXT: %19 = phi <4 x i32> [ %29, %Flow5 ], [ undef, %bb16 ]
+; IR-NEXT: %20 = phi i32 [ %30, %Flow5 ], [ undef, %bb16 ]
+; IR-NEXT: %21 = phi i1 [ %31, %Flow5 ], [ false, %bb16 ]
+; IR-NEXT: %22 = phi i1 [ false, %Flow5 ], [ false, %bb16 ]
+; IR-NEXT: %23 = phi i1 [ false, %Flow5 ], [ %8, %bb16 ]
+; IR-NEXT: %24 = call { i1, i64 } @llvm.amdgcn.if(i1 %23)
+; IR-NEXT: %25 = extractvalue { i1, i64 } %24, 0
+; IR-NEXT: %26 = extractvalue { i1, i64 } %24, 1
+; IR-NEXT: br i1 %25, label %bb21, label %Flow3
 
 ; IR: bb21:
-; IR:   %tmp22 = extractelement <2 x i32> %tmp17, i64 1
-; IR:   %tmp23 = lshr i32 %tmp22, 16
-; IR:   %tmp24 = select i1 undef, i32 undef, i32 %tmp23
-; IR:   %tmp25 = uitofp i32 %tmp24 to float
-; IR:   %tmp26 = fmul float %tmp25, 0x3EF0001000000000
-; IR:   %tmp27 = fsub float %tmp26, undef
-; IR:   %tmp28 = fcmp olt float %tmp27, 5.000000e-01
-; IR:   %tmp29 = select i1 %tmp28, i64 1, i64 2
-; IR:   %tmp30 = extractelement <4 x i32> %tmp936, i64 %tmp29
-; IR:   %tmp7 = zext i32 %tmp30 to i64
-; IR:   %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %tmp7
-; IR:   %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
-; IR:   %tmp10 = extractelement <4 x i32> %tmp9, i64 0
-; IR:   %tmp11 = load volatile i32, i32 addrspace(1)* undef
-; IR:   %tmp12 = icmp slt i32 %tmp11, 9
-; IR:   %20 = xor i1 %tmp12, true
-; IR:   %21 = call i64 @llvm.amdgcn.if.break(i1 %20, i64 %phi.broken)
-; IR:   br label %Flow2
+; IR: %tmp12 = icmp slt i32 %tmp11, 9
+; IR-NEXT: %27 = xor i1 %tmp12, true
+; IR-NEXT: %28 = call i64 @llvm.amdgcn.if.break(i1 %27, i64 %phi.broken)
+; IR-NEXT: br label %Flow3
 
-; IR: bb31.loopexit:
-; IR:   br label %Flow1
+; IR: Flow3:
+; IR-NEXT: %loop.phi11 = phi i64 [ %phi.broken, %bb21 ], [ %phi.broken, %Flow2 ]
+; IR-NEXT: %loop.phi9 = phi i64 [ %28, %bb21 ], [ %loop.phi10, %Flow2 ]
+; IR-NEXT: %29 = phi <4 x i32> [ %tmp9, %bb21 ], [ %19, %Flow2 ]
+; IR-NEXT: %30 = phi i32 [ %tmp10, %bb21 ], [ %20, %Flow2 ]
+; IR-NEXT: %31 = phi i1 [ %27, %bb21 ], [ %21, %Flow2 ]
+; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %26)
+; IR-NEXT: br i1 %22, label %bb31.loopexit, label %Flow4
 
 ; IR: bb31:
-; IR:   call void @llvm.amdgcn.end.cf(i64 %7)
-; IR:   store volatile i32 0, i32 addrspace(1)* undef
-; IR:   ret void
+; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %7)
+; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef
+; IR-NEXT: ret void
 
 
 ; GCN-LABEL: {{^}}nested_loop_conditions:
diff --git a/test/CodeGen/X86/pr34592.ll b/test/CodeGen/X86/pr34592.ll
new file mode 100644
index 0000000000000..09dfade1ee536
--- /dev/null
+++ b/test/CodeGen/X86/pr34592.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 -O0 | FileCheck %s
+
+define <16 x i64> @pluto(<16 x i64> %arg, <16 x i64> %arg1, <16 x i64> %arg2, <16 x i64> %arg3, <16 x i64> %arg4) {
+; CHECK-LABEL: pluto:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbp, -16
+; CHECK-NEXT:    movq %rsp, %rbp
+; CHECK-NEXT:    .cfi_def_cfa_register %rbp
+; CHECK-NEXT:    andq $-32, %rsp
+; CHECK-NEXT:    subq $352, %rsp # imm = 0x160
+; CHECK-NEXT:    vmovaps 240(%rbp), %ymm8
+; CHECK-NEXT:    vmovaps 208(%rbp), %ymm9
+; CHECK-NEXT:    vmovaps 176(%rbp), %ymm10
+; CHECK-NEXT:    vmovaps 144(%rbp), %ymm11
+; CHECK-NEXT:    vmovaps 112(%rbp), %ymm12
+; CHECK-NEXT:    vmovaps 80(%rbp), %ymm13
+; CHECK-NEXT:    vmovaps 48(%rbp), %ymm14
+; CHECK-NEXT:    vmovaps 16(%rbp), %ymm15
+; CHECK-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = [0,0,18446744071562067968,18446744071562067968]
+; CHECK-NEXT:    vblendvpd %ymm0, %ymm2, %ymm6, %ymm0
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm6 = ymm2[0,1],ymm13[2,3],ymm2[4,5,6,7]
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm8 = ymm2[0,1],ymm8[2,3,4,5,6,7]
+; CHECK-NEXT:    vmovaps {{.*#+}} ymm13 = [18446744071562067968,18446744071562067968,0,0]
+; CHECK-NEXT:    vblendvpd %ymm13, %ymm9, %ymm6, %ymm6
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm9 = ymm0[0,1,2,3],ymm11[4,5],ymm0[6,7]
+; CHECK-NEXT:    vpermq {{.*#+}} ymm9 = ymm9[3,2,2,1]
+; CHECK-NEXT:    vmovaps %xmm6, %xmm11
+; CHECK-NEXT:    # implicit-def: %ymm13
+; CHECK-NEXT:    vinserti128 $1, %xmm11, %ymm13, %ymm13
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm9 = ymm9[0,1,2,3],ymm13[4,5],ymm9[6,7]
+; CHECK-NEXT:    vmovaps %xmm0, %xmm11
+; CHECK-NEXT:    # implicit-def: %ymm0
+; CHECK-NEXT:    vinserti128 $1, %xmm11, %ymm0, %ymm0
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm7[4,5],ymm8[6,7]
+; CHECK-NEXT:    vpermq {{.*#+}} ymm13 = ymm8[2,0,2,3]
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm0 = ymm13[0,1,2,3],ymm0[4,5,6,7]
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm2 = ymm7[0,1,2,3],ymm2[4,5],ymm7[6,7]
+; CHECK-NEXT:    vpermq {{.*#+}} ymm2 = ymm2[2,0,2,3]
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm5[4,5],ymm6[6,7]
+; CHECK-NEXT:    vpermq {{.*#+}} ymm6 = ymm6[0,1,1,2]
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm6[4,5,6,7]
+; CHECK-NEXT:    vpermq {{.*#+}} ymm6 = ymm8[2,1,1,3]
+; CHECK-NEXT:    vpshufd {{.*#+}} ymm5 = ymm5[0,1,0,1,4,5,4,5]
+; CHECK-NEXT:    vpblendd {{.*#+}} ymm5 = ymm6[0,1,2,3,4,5],ymm5[6,7]
+; CHECK-NEXT:    vmovaps %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm9, %ymm0
+; CHECK-NEXT:    vmovaps %ymm1, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm5, %ymm1
+; CHECK-NEXT:    vmovaps {{[0-9]+}}(%rsp), %ymm5 # 32-byte Reload
+; CHECK-NEXT:    vmovaps %ymm2, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm5, %ymm2
+; CHECK-NEXT:    vmovaps {{[0-9]+}}(%rsp), %ymm6 # 32-byte Reload
+; CHECK-NEXT:    vmovaps %ymm3, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm6, %ymm3
+; CHECK-NEXT:    vmovaps %ymm15, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm12, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm10, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm4, {{[0-9]+}}(%rsp) # 32-byte Spill
+; CHECK-NEXT:    vmovaps %ymm14, (%rsp) # 32-byte Spill
+; CHECK-NEXT:    movq %rbp, %rsp
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
+bb:
+  %tmp = select <16 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <16 x i64> %arg, <16 x i64> %arg1
+  %tmp5 = select <16 x i1> <i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x i64> %arg2, <16 x i64> zeroinitializer
+  %tmp6 = select <16 x i1> <i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true>, <16 x i64> %arg3, <16 x i64> %tmp5
+  %tmp7 = shufflevector <16 x i64> %tmp, <16 x i64> %tmp6, <16 x i32> <i32 11, i32 18, i32 24, i32 9, i32 14, i32 29, i32 29, i32 6, i32 14, i32 28, i32 8, i32 9, i32 22, i32 12, i32 25, i32 6>
+  ret <16 x i64> %tmp7
+}