diff options
Diffstat (limited to 'test/MC/AMDGPU')
| -rw-r--r-- | test/MC/AMDGPU/ds-err.s | 23 | ||||
| -rw-r--r-- | test/MC/AMDGPU/ds.s | 337 | ||||
| -rw-r--r-- | test/MC/AMDGPU/flat.s | 477 | ||||
| -rw-r--r-- | test/MC/AMDGPU/lit.local.cfg | 2 | ||||
| -rw-r--r-- | test/MC/AMDGPU/mubuf.s | 352 | ||||
| -rw-r--r-- | test/MC/AMDGPU/smrd.s | 32 | ||||
| -rw-r--r-- | test/MC/AMDGPU/sop1-err.s | 37 | ||||
| -rw-r--r-- | test/MC/AMDGPU/sop1.s | 177 | ||||
| -rw-r--r-- | test/MC/AMDGPU/sop2.s | 131 | ||||
| -rw-r--r-- | test/MC/AMDGPU/sopc.s | 9 | ||||
| -rw-r--r-- | test/MC/AMDGPU/sopk.s | 66 | ||||
| -rw-r--r-- | test/MC/AMDGPU/sopp.s | 64 | ||||
| -rw-r--r-- | test/MC/AMDGPU/vop1.s | 357 | ||||
| -rw-r--r-- | test/MC/AMDGPU/vop2-err.s | 35 | ||||
| -rw-r--r-- | test/MC/AMDGPU/vop2.s | 421 | ||||
| -rw-r--r-- | test/MC/AMDGPU/vop3-errs.s | 5 | ||||
| -rw-r--r-- | test/MC/AMDGPU/vop3.s | 149 | ||||
| -rw-r--r-- | test/MC/AMDGPU/vopc.s | 40 |
18 files changed, 2714 insertions, 0 deletions
diff --git a/test/MC/AMDGPU/ds-err.s b/test/MC/AMDGPU/ds-err.s new file mode 100644 index 0000000000000..52c2740bec256 --- /dev/null +++ b/test/MC/AMDGPU/ds-err.s @@ -0,0 +1,23 @@ +// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s + +// offset too big +// CHECK: invalid operand for instruction +ds_add_u32 v2, v4 offset:1000000000 + +// offset0 twice +// CHECK: error: not a valid operand. +ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 + +// offset1 twice +// CHECK: error: not a valid operand. +ds_write2_b32 v2, v4, v6 offset1:4 offset1:8 + +// offset0 too big +// CHECK: invalid operand for instruction +ds_write2_b32 v2, v4, v6 offset0:1000000000 + +// offset1 too big +// CHECK: invalid operand for instruction +ds_write2_b32 v2, v4, v6 offset1:1000000000 + diff --git a/test/MC/AMDGPU/ds.s b/test/MC/AMDGPU/ds.s new file mode 100644 index 0000000000000..ad63229ba2e17 --- /dev/null +++ b/test/MC/AMDGPU/ds.s @@ -0,0 +1,337 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Checks for 16-bit Offsets +//===----------------------------------------------------------------------===// + +ds_add_u32 v2, v4 offset:16 +// CHECK: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] + +//===----------------------------------------------------------------------===// +// Checks for 2 8-bit Offsets +//===----------------------------------------------------------------------===// + +ds_write2_b32 v2, v4, v6 offset0:4 +// CHECK: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 +// CHECK: ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_write2_b32 v2, v4, v6 offset1:8 +// CHECK: ds_write2_b32 v2, v4, v6 offset1:8 ; encoding: [0x00,0x08,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_read2_b32 v[8:9], v2 offset0:4 +// CHECK: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08] + +ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 +// CHECK: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0xdc,0xd8,0x02,0x00,0x00,0x08] + +ds_read2_b32 v[8:9], v2 offset1:8 +// CHECK: ds_read2_b32 v[8:9], v2 offset1:8 ; encoding: [0x00,0x08,0xdc,0xd8,0x02,0x00,0x00,0x08] +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +ds_add_u32 v2, v4 +// CHECK: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] + +ds_sub_u32 v2, v4 +// CHECK: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00] + +ds_rsub_u32 v2, v4 +// CHECK: ds_rsub_u32 v2, v4 ; encoding: [0x00,0x00,0x08,0xd8,0x02,0x04,0x00,0x00] + +ds_inc_u32 v2, v4 +// CHECK: ds_inc_u32 v2, v4 ; encoding: [0x00,0x00,0x0c,0xd8,0x02,0x04,0x00,0x00] + +ds_dec_u32 v2, v4 +// CHECK: ds_dec_u32 v2, v4 ; encoding: [0x00,0x00,0x10,0xd8,0x02,0x04,0x00,0x00] + +ds_min_i32 v2, v4 +// CHECK: ds_min_i32 v2, v4 ; encoding: [0x00,0x00,0x14,0xd8,0x02,0x04,0x00,0x00] + +ds_max_i32 v2, v4 +// CHECK: ds_max_i32 v2, v4 ; encoding: [0x00,0x00,0x18,0xd8,0x02,0x04,0x00,0x00] + +ds_min_u32 v2, v4 +// CHECK: ds_min_u32 v2, v4 ; encoding: [0x00,0x00,0x1c,0xd8,0x02,0x04,0x00,0x00] + +ds_max_u32 v2, v4 +// CHECK: ds_max_u32 v2, v4 ; encoding: [0x00,0x00,0x20,0xd8,0x02,0x04,0x00,0x00] + +ds_and_b32 v2, v4 +// CHECK: ds_and_b32 v2, v4 ; encoding: [0x00,0x00,0x24,0xd8,0x02,0x04,0x00,0x00] + +ds_or_b32 v2, v4 +// CHECK: ds_or_b32 v2, v4 ; encoding: [0x00,0x00,0x28,0xd8,0x02,0x04,0x00,0x00] + +ds_xor_b32 v2, v4 +// CHECK: ds_xor_b32 v2, v4 ; encoding: [0x00,0x00,0x2c,0xd8,0x02,0x04,0x00,0x00] + +ds_mskor_b32 v2, v4, v6 +// CHECK: ds_mskor_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x30,0xd8,0x02,0x04,0x06,0x00] + +ds_write_b32 v2, v4 +// CHECK: ds_write_b32 v2, v4 ; encoding: [0x00,0x00,0x34,0xd8,0x02,0x04,0x00,0x00] + +ds_write2_b32 v2, v4, v6 +// CHECK: ds_write2_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x38,0xd8,0x02,0x04,0x06,0x00] + +ds_write2st64_b32 v2, v4, v6 +// CHECK: ds_write2st64_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x06,0x00] + +ds_cmpst_b32 v2, v4, v6 +// CHECK: ds_cmpst_b32 v2, v4, v6 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x06,0x00] + +ds_cmpst_f32 v2, v4, v6 +// CHECK: ds_cmpst_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x06,0x00] + +ds_min_f32 v2, v4, v6 +// CHECK: ds_min_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x48,0xd8,0x02,0x04,0x06,0x00] + +ds_max_f32 v2, v4, v6 +// CHECK: ds_max_f32 v2, v4, v6 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x06,0x00] + +ds_gws_init v2 gds +// CHECK: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_sema_v v2 gds +// CHECK: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_sema_br v2 gds +// CHECK: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_sema_p v2 gds +// CHECK: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x72,0xd8,0x02,0x00,0x00,0x00] + +ds_gws_barrier v2 gds +// CHECK: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x02,0x00,0x00,0x00] + +ds_write_b8 v2, v4 +// CHECK: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00] + +ds_write_b16 v2, v4 +// CHECK: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x7c,0xd8,0x02,0x04,0x00,0x00] + +ds_add_rtn_u32 v8, v2, v4 +// CHECK: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x08] + +ds_sub_rtn_u32 v8, v2, v4 +// CHECK: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x84,0xd8,0x02,0x04,0x00,0x08] + +ds_rsub_rtn_u32 v8, v2, v4 +// CHECK: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x88,0xd8,0x02,0x04,0x00,0x08] + +ds_inc_rtn_u32 v8, v2, v4 +// CHECK: ds_inc_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x8c,0xd8,0x02,0x04,0x00,0x08] + +ds_dec_rtn_u32 v8, v2, v4 +// CHECK: ds_dec_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x90,0xd8,0x02,0x04,0x00,0x08] + +ds_min_rtn_i32 v8, v2, v4 +// CHECK: ds_min_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x94,0xd8,0x02,0x04,0x00,0x08] + +ds_max_rtn_i32 v8, v2, v4 +// CHECK: ds_max_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x98,0xd8,0x02,0x04,0x00,0x08] + +ds_min_rtn_u32 v8, v2, v4 +// CHECK: ds_min_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x9c,0xd8,0x02,0x04,0x00,0x08] + +ds_max_rtn_u32 v8, v2, v4 +// CHECK: ds_max_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0xa0,0xd8,0x02,0x04,0x00,0x08] + +ds_and_rtn_b32 v8, v2, v4 +// CHECK: ds_and_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xa4,0xd8,0x02,0x04,0x00,0x08] + +ds_or_rtn_b32 v8, v2, v4 +// CHECK: ds_or_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xa8,0xd8,0x02,0x04,0x00,0x08] + +ds_xor_rtn_b32 v8, v2, v4 +// CHECK: ds_xor_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xac,0xd8,0x02,0x04,0x00,0x08] + +ds_mskor_rtn_b32 v8, v2, v4, v6 +// CHECK: ds_mskor_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xb0,0xd8,0x02,0x04,0x06,0x08] + +ds_wrxchg_rtn_b32 v8, v2, v4 +// CHECK: ds_wrxchg_rtn_b32 v8, v2, v4 ; encoding: [0x00,0x00,0xb4,0xd8,0x02,0x04,0x00,0x08] + +ds_wrxchg2_rtn_b32 v[8:9], v2, v4, v6 +// CHECK: ds_wrxchg2_rtn_b32 v[8:9], v2, v4, v6 ; encoding: [0x00,0x00,0xb8,0xd8,0x02,0x04,0x06,0x08] + +ds_wrxchg2st64_rtn_b32 v[8:9] v2, v4, v6 +// CHECK: ds_wrxchg2st64_rtn_b32 v[8:9], v2, v4, v6 ; encoding: [0x00,0x00,0xbc,0xd8,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_b32 v8, v2, v4, v6 +// CHECK: ds_cmpst_rtn_b32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc0,0xd8,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_f32 v8, v2, v4, v6 +// CHECK: ds_cmpst_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc4,0xd8,0x02,0x04,0x06,0x08] + +ds_min_rtn_f32 v8, v2, v4, v6 +// CHECK: ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xc8,0xd8,0x02,0x04,0x06,0x08] + +ds_max_rtn_f32 v8, v2, v4, v6 +// CHECK: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x06,0x08] + +ds_swizzle_b32 v8, v2 +// CHECK: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08] + +ds_read_b32 v8, v2 +// CHECK: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08] + +ds_read2_b32 v[8:9], v2 +// CHECK: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08] + +ds_read2st64_b32 v[8:9], v2 +// CHECK: ds_read2st64_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xe0,0xd8,0x02,0x00,0x00,0x08] + +ds_read_i8 v8, v2 +// CHECK: ds_read_i8 v8, v2 ; encoding: [0x00,0x00,0xe4,0xd8,0x02,0x00,0x00,0x08] + +ds_read_u8 v8, v2 +// CHECK: ds_read_u8 v8, v2 ; encoding: [0x00,0x00,0xe8,0xd8,0x02,0x00,0x00,0x08] + +ds_read_i16 v8, v2 +// CHECK: ds_read_i16 v8, v2 ; encoding: [0x00,0x00,0xec,0xd8,0x02,0x00,0x00,0x08] + +ds_read_u16 v8, v2 +// CHECK: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08] + +ds_consume v8 +// CHECK: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08] + +ds_append v8 +// CHECK: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08] + +ds_ordered_count v8, v2 gds +// CHECK: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08] + +ds_add_u64 v2, v[4:5] +// CHECK: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x00,0xd9,0x02,0x04,0x00,0x00] + +ds_sub_u64 v2, v[4:5] +// CHECK: ds_sub_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x04,0xd9,0x02,0x04,0x00,0x00] + +ds_rsub_u64 v2, v[4:5] +// CHECK: ds_rsub_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x08,0xd9,0x02,0x04,0x00,0x00] + +ds_inc_u64 v2, v[4:5] +// CHECK: ds_inc_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x0c,0xd9,0x02,0x04,0x00,0x00] + +ds_dec_u64 v2, v[4:5] +// CHECK: ds_dec_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x10,0xd9,0x02,0x04,0x00,0x00] + +ds_min_i64 v2, v[4:5] +// CHECK: ds_min_i64 v2, v[4:5] ; encoding: [0x00,0x00,0x14,0xd9,0x02,0x04,0x00,0x00] + +ds_max_i64 v2, v[4:5] +// CHECK: ds_max_i64 v2, v[4:5] ; encoding: [0x00,0x00,0x18,0xd9,0x02,0x04,0x00,0x00] + +ds_min_u64 v2, v[4:5] +// CHECK: ds_min_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x1c,0xd9,0x02,0x04,0x00,0x00] + +ds_max_u64 v2, v[4:5] +// CHECK: ds_max_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x20,0xd9,0x02,0x04,0x00,0x00] + +ds_and_b64 v2, v[4:5] +// CHECK: ds_and_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x24,0xd9,0x02,0x04,0x00,0x00] + +ds_or_b64 v2, v[4:5] +// CHECK: ds_or_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x28,0xd9,0x02,0x04,0x00,0x00] + +ds_xor_b64 v2, v[4:5] +// CHECK: ds_xor_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x2c,0xd9,0x02,0x04,0x00,0x00] + +ds_mskor_b64 v2, v[4:5], v[6:7] +// CHECK: ds_mskor_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x30,0xd9,0x02,0x04,0x06,0x00] + +ds_write_b64 v2, v[4:5] +// CHECK: ds_write_b64 v2, v[4:5] ; encoding: [0x00,0x00,0x34,0xd9,0x02,0x04,0x00,0x00] + +ds_write2_b64 v2, v[4:5], v[6:7] +// CHECK: ds_write2_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x38,0xd9,0x02,0x04,0x06,0x00] + +ds_write2st64_b64 v2, v[4:5], v[6:7] +// CHECK: ds_write2st64_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x3c,0xd9,0x02,0x04,0x06,0x00] + +ds_cmpst_b64 v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_b64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x40,0xd9,0x02,0x04,0x06,0x00] + +ds_cmpst_f64 v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_f64 v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0x44,0xd9,0x02,0x04,0x06,0x00] + +ds_min_f64 v2, v[4:5] +// CHECK: ds_min_f64 v2, v[4:5] ; encoding: [0x00,0x00,0x48,0xd9,0x02,0x04,0x00,0x00] + +ds_max_f64 v2, v[4:5] +// CHECK: ds_max_f64 v2, v[4:5] ; encoding: [0x00,0x00,0x4c,0xd9,0x02,0x04,0x00,0x00] + +ds_add_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_add_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x80,0xd9,0x02,0x04,0x00,0x08] + +ds_sub_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_sub_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x84,0xd9,0x02,0x04,0x00,0x08] + +ds_rsub_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_rsub_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x88,0xd9,0x02,0x04,0x00,0x08] + +ds_inc_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_inc_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x8c,0xd9,0x02,0x04,0x00,0x08] + +ds_dec_rtn_u64 v[8:9] v2, v[4:5] +// CHECK: ds_dec_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x90,0xd9,0x02,0x04,0x00,0x08] + +ds_min_rtn_i64 v[8:9], v2, v[4:5] +// CHECK: ds_min_rtn_i64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x94,0xd9,0x02,0x04,0x00,0x08] + +ds_max_rtn_i64 v[8:9], v2, v[4:5] +// CHECK: ds_max_rtn_i64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x98,0xd9,0x02,0x04,0x00,0x08] + +ds_min_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_min_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0x9c,0xd9,0x02,0x04,0x00,0x08] + +ds_max_rtn_u64 v[8:9], v2, v[4:5] +// CHECK: ds_max_rtn_u64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa0,0xd9,0x02,0x04,0x00,0x08] + +ds_and_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_and_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa4,0xd9,0x02,0x04,0x00,0x08] + +ds_or_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_or_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xa8,0xd9,0x02,0x04,0x00,0x08] + +ds_xor_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_xor_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xac,0xd9,0x02,0x04,0x00,0x08] + +ds_mskor_rtn_b64 v[8:9], v2, v[4:5], v[6:7] +// CHECK: ds_mskor_rtn_b64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xb0,0xd9,0x02,0x04,0x06,0x08] + +ds_wrxchg_rtn_b64 v[8:9], v2, v[4:5] +// CHECK: ds_wrxchg_rtn_b64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xb4,0xd9,0x02,0x04,0x00,0x08] + +ds_wrxchg2_rtn_b64 v[8:11], v2, v[4:5], v[6:7] +// CHECK: ds_wrxchg2_rtn_b64 v[8:11], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xb8,0xd9,0x02,0x04,0x06,0x08] + +ds_wrxchg2st64_rtn_b64 v[8:11], v2, v[4:5], v[6:7] +// CHECK: ds_wrxchg2st64_rtn_b64 v[8:11], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xbc,0xd9,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_b64 v[8:9], v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_rtn_b64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xc0,0xd9,0x02,0x04,0x06,0x08] + +ds_cmpst_rtn_f64 v[8:9], v2, v[4:5], v[6:7] +// CHECK: ds_cmpst_rtn_f64 v[8:9], v2, v[4:5], v[6:7] ; encoding: [0x00,0x00,0xc4,0xd9,0x02,0x04,0x06,0x08] + +ds_min_rtn_f64 v[8:9], v2, v[4:5] +// CHECK: ds_min_rtn_f64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xc8,0xd9,0x02,0x04,0x00,0x08] + +ds_max_rtn_f64 v[8:9], v2, v[4:5] +// CHECK: ds_max_rtn_f64 v[8:9], v2, v[4:5] ; encoding: [0x00,0x00,0xcc,0xd9,0x02,0x04,0x00,0x08] + +ds_read_b64 v[8:9], v2 +// CHECK: ds_read_b64 v[8:9], v2 ; encoding: [0x00,0x00,0xd8,0xd9,0x02,0x00,0x00,0x08] + +ds_read2_b64 v[8:11], v2 +// CHECK: ds_read2_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xdc,0xd9,0x02,0x00,0x00,0x08] + +ds_read2st64_b64 v[8:11], v2 +// CHECK: ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xe0,0xd9,0x02,0x00,0x00,0x08] diff --git a/test/MC/AMDGPU/flat.s b/test/MC/AMDGPU/flat.s new file mode 100644 index 0000000000000..adad29a5595bb --- /dev/null +++ b/test/MC/AMDGPU/flat.s @@ -0,0 +1,477 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI +// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI + +// FIXME: These instructions give an 'invalid operand' error on SI and should +// instead be reporting an 'instruction not supported' error. + +// XUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=NOVI +// XUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI +// XUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI + +//===----------------------------------------------------------------------===// +// Operands +//===----------------------------------------------------------------------===// + +flat_load_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] glc slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] glc tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] slc glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] slc tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_load_dword v1, v[3:4] tfe slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01] + +flat_store_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] glc slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] glc tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] slc glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] slc tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +flat_store_dword v1, v[3:4] tfe slc glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00] + +// FIXME: For atomic instructions, glc must be placed immediately following +// the data regiser. These forms aren't currently supported: +// flat_atomic_add v1, v[3:4], v5 slc glc +// flat_atomic_add v1, v[3:4], v5 slc glc tfe +// flat_atomic_add v1, v[3:4], v5 slc tfe glc +// flat_atomic_add v1, v[3:4], v5 tfe glc +// flat_atomic_add v[3:4], v5 tfe glc +// flat_atomic_add v1, v[3:4], v5 tfe glc slc +// flat_atomic_add v1, v[3:4], v5 tfe slc glc + +flat_atomic_add v1 v[3:4], v5 glc slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_add v1 v[3:4], v5 glc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x80,0x01] + +flat_atomic_add v1 v[3:4], v5 glc slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01] + +flat_atomic_add v1 v[3:4], v5 glc tfe slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01] + +flat_atomic_add v[3:4], v5 slc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_add v[3:4], v5 slc tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x80,0x00] + +flat_atomic_add v[3:4], v5 tfe +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x80,0x00] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +flat_load_ubyte v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x20,0xdc,0x03,0x00,0x00,0x01] + +flat_load_sbyte v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_sbyte v1, v[3:4] ; encoding: [0x00,0x00,0x24,0xdc,0x03,0x00,0x00,0x01] + +flat_load_ushort v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_ushort v1, v[3:4] ; encoding: [0x00,0x00,0x28,0xdc,0x03,0x00,0x00,0x01] + +flat_load_sshort v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_sshort v1, v[3:4] ; encoding: [0x00,0x00,0x2c,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dwordx2 v[1:2], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x34,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dwordx4 v[5:8], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x38,0xdc,0x03,0x00,0x00,0x05] + +flat_load_dwordx3 v[5:7], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_load_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x3c,0xdc,0x03,0x00,0x00,0x05] + +flat_store_byte v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_byte v1, v[3:4] ; encoding: [0x00,0x00,0x60,0xdc,0x03,0x01,0x00,0x00] + +flat_store_short v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_short v1, v[3:4] ; encoding: [0x00,0x00,0x68,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dword v1, v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dwordx2 v[1:2], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x74,0xdc,0x03,0x01,0x00,0x00] + +flat_store_dwordx4 v[5:8], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x78,0xdc,0x03,0x05,0x00,0x00] + +flat_store_dwordx3 v[5:7], v[3:4] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_store_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x7c,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_swap v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap v[3:4], v5 ; encoding: [0x00,0x00,0xc0,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_swap v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc1,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_cmpswap v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap v[3:4], v[5:6] ; encoding: [0x00,0x00,0xc4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_cmpswap v1, v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xc5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_add v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v[3:4], v5 ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_add v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_sub v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub v[3:4], v5 ; encoding: [0x00,0x00,0xcc,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_sub v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xcd,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_smin v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin v[3:4], v5 ; encoding: [0x00,0x00,0xd4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_smin v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_umin v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin v[3:4], v5 ; encoding: [0x00,0x00,0xd8,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_umin v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd9,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_smax v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax v[3:4], v5 ; encoding: [0x00,0x00,0xdc,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_smax v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xdd,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_umax v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax v[3:4], v5 ; encoding: [0x00,0x00,0xe0,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_umax v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe1,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_and v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and v[3:4], v5 ; encoding: [0x00,0x00,0xe4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_and v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_or v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or v[3:4], v5 ; encoding: [0x00,0x00,0xe8,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_or v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe9,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_xor v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor v[3:4], v5 ; encoding: [0x00,0x00,0xec,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_xor v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xed,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_inc v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc v[3:4], v5 ; encoding: [0x00,0x00,0xf0,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_inc v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf1,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_dec v[3:4], v5 +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec v[3:4], v5 ; encoding: [0x00,0x00,0xf4,0xdc,0x03,0x05,0x00,0x00] + +flat_atomic_dec v1, v[3:4], v5 glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf5,0xdc,0x03,0x05,0x00,0x01] + +flat_atomic_swap_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x40,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x41,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_cmpswap_x2 v[3:4], v[5:8] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x44,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x45,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_add_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x48,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x49,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_sub_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x4c,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x4d,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_smin_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x54,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x55,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_umin_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x58,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x59,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_smax_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x5c,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x5d,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_umax_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x60,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x61,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_and_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x64,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x65,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_or_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x68,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x69,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_xor_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x6c,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x6d,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_inc_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x70,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x71,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_dec_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x74,0xdd,0x03,0x05,0x00,0x00] + +flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CIVI: flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x75,0xdd,0x03,0x05,0x00,0x01] + +flat_atomic_fcmpswap_x2 v[3:4], v[5:8] +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fcmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x78,0xdd,0x03,0x05,0x00,0x00] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x79,0xdd,0x03,0x05,0x00,0x01] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmin_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x7c,0xdd,0x03,0x05,0x00,0x00] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x7d,0xdd,0x03,0x05,0x00,0x01] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmax_x2 v[3:4], v[5:6] +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x80,0xdd,0x03,0x05,0x00,0x00] +// NOVI: error: instruction not supported on this GPU + +flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc +// NOSI: error: instruction not supported on this GPU +// CI: flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x81,0xdd,0x03,0x05,0x00,0x01] +// NOVI: error: instruction not supported on this GPU diff --git a/test/MC/AMDGPU/lit.local.cfg b/test/MC/AMDGPU/lit.local.cfg new file mode 100644 index 0000000000000..2a665f06be72e --- /dev/null +++ b/test/MC/AMDGPU/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'AMDGPU' in config.root.targets: + config.unsupported = True diff --git a/test/MC/AMDGPU/mubuf.s b/test/MC/AMDGPU/mubuf.s new file mode 100644 index 0000000000000..78d365abef13b --- /dev/null +++ b/test/MC/AMDGPU/mubuf.s @@ -0,0 +1,352 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Test for different operand combinations +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// load - immediate offset only +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, s[4:7], s1 +// CHECK: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 glc +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 slc +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x41,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 tfe +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x81,0x01] + +buffer_load_dword v1, s[4:7], s1 tfe glc +// CHECK: buffer_load_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x30,0xe0,0x00,0x01,0x81,0x01] + +buffer_load_dword v1, s[4:7], s1 offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01] + +buffer_load_dword v1, s[4:7], s1 glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - vgpr offset +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v2, s[4:7], s1 offen +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen tfe glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - vgpr index +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v2, s[4:7], s1 idxen +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen tfe glc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - vgpr index and offset +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// load - addr64 +//===----------------------------------------------------------------------===// + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0x01,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x41,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x30,0xe0,0x02,0x01,0x81,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01] + +buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4 +// CHECK: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - immediate offset only +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, s[4:7], s1 +// CHECK: buffer_store_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 glc +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 slc +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x41,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 tfe +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01] + +buffer_store_dword v1, s[4:7], s1 tfe glc +// CHECK: buffer_store_dword v1, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01] + +buffer_store_dword v1, s[4:7], s1 offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01] + +buffer_store_dword v1, s[4:7], s1 glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - vgpr offset +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v2, s[4:7], s1 offen +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen tfe glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - vgpr index +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v2, s[4:7], s1 idxen +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen tfe glc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - vgpr index and offset +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen tfe glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// store - addr64 +//===----------------------------------------------------------------------===// + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0x01,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x41,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 tfe glc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x70,0xe0,0x02,0x01,0x81,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc tfe slc +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01] + +buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 glc tfe slc offset:4 +// CHECK: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +buffer_load_format_x v1, s[4:7], s1 +// CHECK: buffer_load_format_x v1, s[4:7], s1 ; encoding: [0x00,0x00,0x00,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_format_xy v[1:2], s[4:7], s1 +// CHECK: buffer_load_format_xy v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x04,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_format_xyz v[1:3], s[4:7], s1 +// CHECK: buffer_load_format_xyz v[1:3], s[4:7], s1 ; encoding: [0x00,0x00,0x08,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_format_xyzw v[1:4], s[4:7], s1 +// CHECK: buffer_load_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x0c,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_x v1, s[4:7], s1 +// CHECK: buffer_store_format_x v1, s[4:7], s1 ; encoding: [0x00,0x00,0x10,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_xy v[1:2], s[4:7], s1 +// CHECK: buffer_store_format_xy v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x14,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_xyz v[1:3], s[4:7], s1 +// CHECK: buffer_store_format_xyz v[1:3], s[4:7], s1 ; encoding: [0x00,0x00,0x18,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_format_xyzw v[1:4], s[4:7], s1 +// CHECK: buffer_store_format_xyzw v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_ubyte v1, s[4:7], s1 +// CHECK: buffer_load_ubyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x20,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_sbyte v1, s[4:7], s1 +// CHECK: buffer_load_sbyte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x24,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_ushort v1, s[4:7], s1 +// CHECK: buffer_load_ushort v1, s[4:7], s1 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_sshort v1, s[4:7], s1 +// CHECK: buffer_load_sshort v1, s[4:7], s1 ; encoding: [0x00,0x00,0x2c,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dword v1, s[4:7], s1 +// CHECK: buffer_load_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dwordx2 v[1:2], s[4:7], s1 +// CHECK: buffer_load_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x34,0xe0,0x00,0x01,0x01,0x01] + +buffer_load_dwordx4 v[1:4], s[4:7], s1 +// CHECK: buffer_load_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x38,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_byte v1, s[4:7], s1 +// CHECK: buffer_store_byte v1, s[4:7], s1 ; encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_short v1, s[4:7], s1 +// CHECK: buffer_store_short v1, s[4:7], s1 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dword v1 s[4:7], s1 +// CHECK: buffer_store_dword v1, s[4:7], s1 ; encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dwordx2 v[1:2], s[4:7], s1 +// CHECK: buffer_store_dwordx2 v[1:2], s[4:7], s1 ; encoding: [0x00,0x00,0x74,0xe0,0x00,0x01,0x01,0x01] + +buffer_store_dwordx4 v[1:4], s[4:7], s1 +// CHECK: buffer_store_dwordx4 v[1:4], s[4:7], s1 ; encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x01,0x01] + +// TODO: Atomics diff --git a/test/MC/AMDGPU/smrd.s b/test/MC/AMDGPU/smrd.s new file mode 100644 index 0000000000000..b67abf7e68903 --- /dev/null +++ b/test/MC/AMDGPU/smrd.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +s_load_dword s1, s[2:3], 1 +// CHECK: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0] + +s_load_dword s1, s[2:3], s4 +// CHECK: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0] + +s_load_dwordx2 s[2:3], s[2:3], 1 +// CHECK: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0] + +s_load_dwordx2 s[2:3], s[2:3], s4 +// CHECK: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0] + +s_load_dwordx4 s[4:7], s[2:3], 1 +// CHECK: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0] + +s_load_dwordx4 s[4:7], s[2:3], s4 +// CHECK: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0] + +s_load_dwordx8 s[8:15], s[2:3], 1 +// CHECK: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0] + +s_load_dwordx8 s[8:15], s[2:3], s4 +// CHECK: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x04,0x02,0xc4,0xc0] + +s_load_dwordx16 s[16:31], s[2:3], 1 +// CHECK: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1] + +s_load_dwordx16 s[16:31], s[2:3], s4 +// CHECK: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x04,0x02,0x08,0xc1] diff --git a/test/MC/AMDGPU/sop1-err.s b/test/MC/AMDGPU/sop1-err.s new file mode 100644 index 0000000000000..f892356b623dd --- /dev/null +++ b/test/MC/AMDGPU/sop1-err.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s + +s_mov_b32 v1, s2 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s1, v0 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s[1:2], s0 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s0, s[1:2] +// CHECK: error: invalid operand for instruction + +s_mov_b32 s220, s0 +// CHECK: error: invalid operand for instruction + +s_mov_b32 s0, s220 +// CHECK: error: invalid operand for instruction + +s_mov_b64 s1, s[0:1] +// CHECK: error: invalid operand for instruction + +s_mov_b64 s[0:1], s1 +// CHECK: error: invalid operand for instruction + +// Immediate greater than 32-bits +s_mov_b32 s1, 0xfffffffff +// CHECK: error: invalid immediate: only 32-bit values are legal + +// Immediate greater than 32-bits +s_mov_b64 s[0:1], 0xfffffffff +// CHECK: error: invalid immediate: only 32-bit values are legal + +// Out of range register +s_mov_b32 s diff --git a/test/MC/AMDGPU/sop1.s b/test/MC/AMDGPU/sop1.s new file mode 100644 index 0000000000000..92ca73f250045 --- /dev/null +++ b/test/MC/AMDGPU/sop1.s @@ -0,0 +1,177 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +s_mov_b32 s1, s2 +// CHECK: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe] + +s_mov_b32 s1, 1 +// CHECK: s_mov_b32 s1, 1 ; encoding: [0x81,0x03,0x81,0xbe] + +s_mov_b32 s1, 100 +// CHECK: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x03,0x81,0xbe,0x64,0x00,0x00,0x00] + +s_mov_b64 s[2:3], s[4:5] +// CHECK: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe] + +s_mov_b64 s[2:3], 0xffffffffffffffff +// CHECK: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x04,0x82,0xbe] + +s_cmov_b32 s1, 200 +// CHECK: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x05,0x81,0xbe,0xc8,0x00,0x00,0x00] + +s_cmov_b32 s1, 1.0 +// CHECK: s_cmov_b32 s1, 1.0 ; encoding: [0xf2,0x05,0x81,0xbe] + +//s_cmov_b64 s[2:3], 1.0 +//CHECK-FIXME: s_cmov_b64 s[2:3], 1.0 ; encoding: [0xf2,0x05,0x82,0xb3] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +s_mov_b32 s1, s2 +// CHECK: s_mov_b32 s1, s2 ; encoding: [0x02,0x03,0x81,0xbe] + +s_mov_b64 s[2:3], s[4:5] +// CHECK: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x04,0x82,0xbe] + +s_cmov_b32 s1, s2 +// CHECK: s_cmov_b32 s1, s2 ; encoding: [0x02,0x05,0x81,0xbe] + +s_cmov_b64 s[2:3], s[4:5] +// CHECK: s_cmov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x06,0x82,0xbe] + +s_not_b32 s1, s2 +// CHECK: s_not_b32 s1, s2 ; encoding: [0x02,0x07,0x81,0xbe] + +s_not_b64 s[2:3], s[4:5] +// CHECK: s_not_b64 s[2:3], s[4:5] ; encoding: [0x04,0x08,0x82,0xbe] + +s_wqm_b32 s1, s2 +// CHECK: s_wqm_b32 s1, s2 ; encoding: [0x02,0x09,0x81,0xbe] + +s_wqm_b64 s[2:3], s[4:5] +// CHECK: s_wqm_b64 s[2:3], s[4:5] ; encoding: [0x04,0x0a,0x82,0xbe] + +s_brev_b32 s1, s2 +// CHECK: s_brev_b32 s1, s2 ; encoding: [0x02,0x0b,0x81,0xbe] + +s_brev_b64 s[2:3], s[4:5] +// CHECK: s_brev_b64 s[2:3], s[4:5] ; encoding: [0x04,0x0c,0x82,0xbe] + +s_bcnt0_i32_b32 s1, s2 +// CHECK: s_bcnt0_i32_b32 s1, s2 ; encoding: [0x02,0x0d,0x81,0xbe] + +s_bcnt0_i32_b64 s1, s[2:3] +// CHECK: s_bcnt0_i32_b64 s1, s[2:3] ; encoding: [0x02,0x0e,0x81,0xbe] + +s_bcnt1_i32_b32 s1, s2 +// CHECK: s_bcnt1_i32_b32 s1, s2 ; encoding: [0x02,0x0f,0x81,0xbe] + +s_bcnt1_i32_b64 s1, s[2:3] +// CHECK: s_bcnt1_i32_b64 s1, s[2:3] ; encoding: [0x02,0x10,0x81,0xbe] + +s_ff0_i32_b32 s1, s2 +// CHECK: s_ff0_i32_b32 s1, s2 ; encoding: [0x02,0x11,0x81,0xbe] + +s_ff0_i32_b64 s1, s[2:3] +// CHECK: s_ff0_i32_b64 s1, s[2:3] ; encoding: [0x02,0x12,0x81,0xbe] + +s_ff1_i32_b32 s1, s2 +// CHECK: s_ff1_i32_b32 s1, s2 ; encoding: [0x02,0x13,0x81,0xbe] + +s_ff1_i32_b64 s1, s[2:3] +// CHECK: s_ff1_i32_b64 s1, s[2:3] ; encoding: [0x02,0x14,0x81,0xbe] + +s_flbit_i32_b32 s1, s2 +// CHECK: s_flbit_i32_b32 s1, s2 ; encoding: [0x02,0x15,0x81,0xbe] + +s_flbit_i32_b64 s1, s[2:3] +// CHECK: s_flbit_i32_b64 s1, s[2:3] ; encoding: [0x02,0x16,0x81,0xbe] + +s_flbit_i32 s1, s2 +// CHECK: s_flbit_i32 s1, s2 ; encoding: [0x02,0x17,0x81,0xbe] + +s_flbit_i32_i64 s1, s[2:3] +// CHECK: s_flbit_i32_i64 s1, s[2:3] ; encoding: [0x02,0x18,0x81,0xbe] + +s_sext_i32_i8 s1, s2 +// CHECK: s_sext_i32_i8 s1, s2 ; encoding: [0x02,0x19,0x81,0xbe] + +s_sext_i32_i16 s1, s2 +// CHECK: s_sext_i32_i16 s1, s2 ; encoding: [0x02,0x1a,0x81,0xbe] + +s_bitset0_b32 s1, s2 +// CHECK: s_bitset0_b32 s1, s2 ; encoding: [0x02,0x1b,0x81,0xbe] + +s_bitset0_b64 s[2:3], s[4:5] +// CHECK: s_bitset0_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1c,0x82,0xbe] + +s_bitset1_b32 s1, s2 +// CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe] + +s_bitset1_b64 s[2:3], s[4:5] +// CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe] + +s_getpc_b64 s[2:3] +// CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe] + +s_setpc_b64 s[2:3], s[4:5] +// CHECK: s_setpc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x20,0x82,0xbe] + +s_swappc_b64 s[2:3], s[4:5] +// CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe] + +s_rfe_b64 s[2:3], s[4:5] +// CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe] + +s_and_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_and_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x24,0x82,0xbe] + +s_or_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_or_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x25,0x82,0xbe] + +s_xor_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_xor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x26,0x82,0xbe] + +s_andn2_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_andn2_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x27,0x82,0xbe] + +s_orn2_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_orn2_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x28,0x82,0xbe] + +s_nand_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_nand_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x29,0x82,0xbe] + +s_nor_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_nor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2a,0x82,0xbe] + +s_xnor_saveexec_b64 s[2:3], s[4:5] +// CHECK: s_xnor_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2b,0x82,0xbe] + +s_quadmask_b32 s1, s2 +// CHECK: s_quadmask_b32 s1, s2 ; encoding: [0x02,0x2c,0x81,0xbe] + +s_quadmask_b64 s[2:3], s[4:5] +// CHECK: s_quadmask_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe] + +s_movrels_b32 s1, s2 +// CHECK: s_movrels_b32 s1, s2 ; encoding: [0x02,0x2e,0x81,0xbe] + +s_movrels_b64 s[2:3], s[4:5] +// CHECK: s_movrels_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2f,0x82,0xbe] + +s_movreld_b32 s1, s2 +// CHECK: s_movreld_b32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe] + +s_movreld_b64 s[2:3], s[4:5] +// CHECK: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x31,0x82,0xbe] + +s_cbranch_join s[4:5] +// CHECK: s_cbranch_join s[4:5] ; encoding: [0x04,0x32,0x80,0xbe] + +s_abs_i32 s1, s2 +// CHECK: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe] + +s_mov_fed_b32 s1, s2 +// CHECK: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe] diff --git a/test/MC/AMDGPU/sop2.s b/test/MC/AMDGPU/sop2.s new file mode 100644 index 0000000000000..9a7a1c01064b9 --- /dev/null +++ b/test/MC/AMDGPU/sop2.s @@ -0,0 +1,131 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +// CHECK: s_add_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x80] +s_add_u32 s1, s2, s3 + +// CHECK: s_sub_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x80] +s_sub_u32 s1, s2, s3 + +// CHECK: s_add_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x81] +s_add_i32 s1, s2, s3 + +// CHECK: s_sub_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x81] +s_sub_i32 s1, s2, s3 + +// CHECK: s_addc_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x82] +s_addc_u32 s1, s2, s3 + +// CHECK: s_subb_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x82] +s_subb_u32 s1, s2, s3 + +// CHECK: s_min_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x83] +s_min_i32 s1, s2, s3 + +// CHECK: s_min_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x83] +s_min_u32 s1, s2, s3 + +// CHECK: s_max_i32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x84] +s_max_i32 s1, s2, s3 + +// CHECK: s_max_u32 s1, s2, s3 ; encoding: [0x02,0x03,0x81,0x84] +s_max_u32 s1, s2, s3 + +// CHECK: s_cselect_b32 s1, s2, s3 ; encoding: [0x02,0x03,0x01,0x85] +s_cselect_b32 s1, s2, s3 + +// CHECK: s_cselect_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x85] +s_cselect_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_and_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87] +s_and_b32 s2, s4, s6 + +// CHECK: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87] +s_and_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_or_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x88] +s_or_b32 s2, s4, s6 + +// CHECK: s_or_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x88] +s_or_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_xor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x89] +s_xor_b32 s2, s4, s6 + +// CHECK: s_xor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x89] +s_xor_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_andn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8a] +s_andn2_b32 s2, s4, s6 + +// CHECK: s_andn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8a] +s_andn2_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_orn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8b] +s_orn2_b32 s2, s4, s6 + +// CHECK: s_orn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8b] +s_orn2_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_nand_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8c] +s_nand_b32 s2, s4, s6 + +// CHECK: s_nand_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8c] +s_nand_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_nor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8d] +s_nor_b32 s2, s4, s6 + +// CHECK: s_nor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8d] +s_nor_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_xnor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8e] +s_xnor_b32 s2, s4, s6 + +// CHECK: s_xnor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x8e] +s_xnor_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_lshl_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8f] +s_lshl_b32 s2, s4, s6 + +// CHECK: s_lshl_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x8f] +s_lshl_b64 s[2:3], s[4:5], s6 + +// CHECK: s_lshr_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90] +s_lshr_b32 s2, s4, s6 + +// CHECK: s_lshr_b64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x90] +s_lshr_b64 s[2:3], s[4:5], s6 + +// CHECK: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x91] +s_ashr_i32 s2, s4, s6 + +// CHECK: s_ashr_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x91] +s_ashr_i64 s[2:3], s[4:5], s6 + +// CHECK: s_bfm_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92] +s_bfm_b32 s2, s4, s6 + +// CHECK: s_bfm_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x92] +s_bfm_b64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_mul_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x93] +s_mul_i32 s2, s4, s6 + +// CHECK: s_bfe_u32 s2, s4, s6 ; encoding: [0x04,0x06,0x82,0x93] +s_bfe_u32 s2, s4, s6 + +// CHECK: s_bfe_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x94] +s_bfe_i32 s2, s4, s6 + +// CHECK: s_bfe_u64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x94] +s_bfe_u64 s[2:3], s[4:5], s[6:7] + +// CHECK: s_bfe_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x02,0x95] +s_bfe_i64 s[2:3], s[4:5], s6 + +// CHECK: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x95] +s_cbranch_g_fork s[4:5], s[6:7] + +// CHECK: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x96] +s_absdiff_i32 s2, s4, s6 diff --git a/test/MC/AMDGPU/sopc.s b/test/MC/AMDGPU/sopc.s new file mode 100644 index 0000000000000..0899c1a2eede8 --- /dev/null +++ b/test/MC/AMDGPU/sopc.s @@ -0,0 +1,9 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +s_cmp_eq_i32 s1, s2 +// CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf] diff --git a/test/MC/AMDGPU/sopk.s b/test/MC/AMDGPU/sopk.s new file mode 100644 index 0000000000000..6c27aaccb80c7 --- /dev/null +++ b/test/MC/AMDGPU/sopk.s @@ -0,0 +1,66 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +s_movk_i32 s2, 0x6 +// CHECK: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0] + +s_cmovk_i32 s2, 0x6 +// CHECK: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1] + +s_cmpk_eq_i32 s2, 0x6 +// CHECK: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1] + +s_cmpk_lg_i32 s2, 0x6 +// CHECK: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2] + +s_cmpk_gt_i32 s2, 0x6 +// CHECK: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2] + +s_cmpk_ge_i32 s2, 0x6 +// CHECK: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3] + +s_cmpk_lt_i32 s2, 0x6 +// CHECK: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3] + +s_cmpk_le_i32 s2, 0x6 +// CHECK: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4] + +s_cmpk_eq_u32 s2, 0x6 +// CHECK: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4] + +s_cmpk_lg_u32 s2, 0x6 +// CHECK: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5] + +s_cmpk_gt_u32 s2, 0x6 +// CHECK: s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5] + +s_cmpk_ge_u32 s2, 0x6 +// CHECK: s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6] + +s_cmpk_lt_u32 s2, 0x6 +// CHECK: s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6] + +s_cmpk_le_u32 s2, 0x6 +// CHECK: s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7] + +s_addk_i32 s2, 0x6 +// CHECK: s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7] + +s_mulk_i32 s2, 0x6 +// CHECK: s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb8] + +s_cbranch_i_fork s[2:3], 0x6 +// CHECK: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8] + +s_getreg_b32 s2, 0x6 +// CHECK: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] + +s_setreg_b32 s2, 0x6 +// CHECK: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb9] + +s_setreg_imm32_b32 0xff, 0x6 +// CHECK: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] diff --git a/test/MC/AMDGPU/sopp.s b/test/MC/AMDGPU/sopp.s new file mode 100644 index 0000000000000..b072c16fdb24c --- /dev/null +++ b/test/MC/AMDGPU/sopp.s @@ -0,0 +1,64 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Edge Cases +//===----------------------------------------------------------------------===// + +s_nop 0 // CHECK: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf] +s_nop 0xffff // CHECK: s_nop 0xffff ; encoding: [0xff,0xff,0x80,0xbf] + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + + s_nop 1 // CHECK: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf] + s_endpgm // CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] + s_branch 2 // CHECK: s_branch 2 ; encoding: [0x02,0x00,0x82,0xbf] + s_cbranch_scc0 3 // CHECK: s_cbranch_scc0 3 ; encoding: [0x03,0x00,0x84,0xbf] + s_cbranch_scc1 4 // CHECK: s_cbranch_scc1 4 ; encoding: [0x04,0x00,0x85,0xbf] + s_cbranch_vccz 5 // CHECK: s_cbranch_vccz 5 ; encoding: [0x05,0x00,0x86,0xbf] + s_cbranch_vccnz 6 // CHECK: s_cbranch_vccnz 6 ; encoding: [0x06,0x00,0x87,0xbf] + s_cbranch_execz 7 // CHECK: s_cbranch_execz 7 ; encoding: [0x07,0x00,0x88,0xbf] + s_cbranch_execnz 8 // CHECK: s_cbranch_execnz 8 ; encoding: [0x08,0x00,0x89,0xbf] + s_barrier // CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf] + +//===----------------------------------------------------------------------===// +// s_waitcnt +//===----------------------------------------------------------------------===// + + s_waitcnt 0 + // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] + + s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0) + // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] + + s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) + // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] + + s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0) + // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf] + + s_waitcnt vmcnt(1) + // CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x07,0x8c,0xbf] + + s_waitcnt expcnt(2) + // CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x07,0x8c,0xbf] + + s_waitcnt lgkmcnt(3) + // CHECK: s_waitcnt lgkmcnt(3) ; encoding: [0x7f,0x03,0x8c,0xbf] + + s_waitcnt vmcnt(0), expcnt(0) + // CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x07,0x8c,0xbf] + + + s_sethalt 9 // CHECK: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf] + s_sleep 10 // CHECK: s_sleep 10 ; encoding: [0x0a,0x00,0x8e,0xbf] + s_setprio 1 // CHECK: s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf] + s_sendmsg 2 // CHECK: s_sendmsg Gs(nop), [m0] ; encoding: [0x02,0x00,0x90,0xbf] + s_sendmsghalt 3 // CHECK: s_sendmsghalt 3 ; encoding: [0x03,0x00,0x91,0xbf] + s_trap 4 // CHECK: s_trap 4 ; encoding: [0x04,0x00,0x92,0xbf] + s_icache_inv // CHECK: s_icache_inv ; encoding: [0x00,0x00,0x93,0xbf] + s_incperflevel 5 // CHECK: s_incperflevel 5 ; encoding: [0x05,0x00,0x94,0xbf] + s_decperflevel 6 // CHECK: s_decperflevel 6 ; encoding: [0x06,0x00,0x95,0xbf] + s_ttracedata // CHECK: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf] diff --git a/test/MC/AMDGPU/vop1.s b/test/MC/AMDGPU/vop1.s new file mode 100644 index 0000000000000..d0b00fcd18978 --- /dev/null +++ b/test/MC/AMDGPU/vop1.s @@ -0,0 +1,357 @@ +// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI + +// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI + + +// GCN: v_nop ; encoding: [0x00,0x00,0x00,0x7e] +v_nop + +// GCN: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e] +v_mov_b32 v1, v2 + +// GCN: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e] +v_readfirstlane_b32 s1, v2 + +// GCN: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e] +v_cvt_i32_f64 v1, v[2:3] + +// GCN: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e] +v_cvt_f64_i32 v[1:2], v2 + +// GCN: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e] +v_cvt_f32_i32 v1, v2 + +// GCN: v_cvt_f32_u32_e32 v1, v2 ; encoding: [0x02,0x0d,0x02,0x7e] +v_cvt_f32_u32 v1, v2 + +// GCN: v_cvt_u32_f32_e32 v1, v2 ; encoding: [0x02,0x0f,0x02,0x7e +v_cvt_u32_f32 v1, v2 + +// GCN: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e] +v_cvt_i32_f32 v1, v2 + +// SICI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +v_mov_fed_b32 v1, v2 + +// GCN: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e] +v_cvt_f16_f32 v1, v2 + +// GCN: v_cvt_f32_f16_e32 v1, v2 ; encoding: [0x02,0x17,0x02,0x7e] +v_cvt_f32_f16 v1, v2 + +// GCN: v_cvt_rpi_i32_f32_e32 v1, v2 ; encoding: [0x02,0x19,0x02,0x7e] +v_cvt_rpi_i32_f32 v1, v2 + +// GCN: v_cvt_flr_i32_f32_e32 v1, v2 ; encoding: [0x02,0x1b,0x02,0x7e] +v_cvt_flr_i32_f32 v1, v2 + +// GCN: v_cvt_off_f32_i4_e32 v1, v2 ; encoding: [0x02,0x1d,0x02,0x7e] +v_cvt_off_f32_i4_e32 v1, v2 + +// GCN: v_cvt_f32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x1f,0x02,0x7e] +v_cvt_f32_f64 v1, v[2:3] + +// GCN: v_cvt_f64_f32_e32 v[1:2], v2 ; encoding: [0x02,0x21,0x02,0x7e] +v_cvt_f64_f32 v[1:2], v2 + +// GCN: v_cvt_f32_ubyte0_e32 v1, v2 ; encoding: [0x02,0x23,0x02,0x7e] +v_cvt_f32_ubyte0 v1, v2 + +// GCN: v_cvt_f32_ubyte1_e32 v1, v2 ; encoding: [0x02,0x25,0x02,0x7e] +v_cvt_f32_ubyte1_e32 v1, v2 + +// GCN: v_cvt_f32_ubyte2_e32 v1, v2 ; encoding: [0x02,0x27,0x02,0x7e] +v_cvt_f32_ubyte2 v1, v2 + +// GCN: v_cvt_f32_ubyte3_e32 v1, v2 ; encoding: [0x02,0x29,0x02,0x7e] +v_cvt_f32_ubyte3 v1, v2 + +// GCN: v_cvt_u32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x2b,0x02,0x7e] +v_cvt_u32_f64 v1, v[2:3] + +// GCN: v_cvt_f64_u32_e32 v[1:2], v2 ; encoding: [0x02,0x2d,0x02,0x7e] +v_cvt_f64_u32 v[1:2], v2 + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_trunc_f64_e32 v[1:2], v[2:3] +// CIVI: v_trunc_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x2f,0x02,0x7e] +v_trunc_f64_e32 v[1:2], v[2:3] + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_ceil_f64_e32 v[1:2], v[2:3] +// CIVI: v_ceil_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x31,0x02,0x7e] +v_ceil_f64_e32 v[1:2], v[2:3] + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_rndne_f64_e32 v[1:2], v[2:3] +// CIVI: v_rndne_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x33,0x02,0x7e] +v_rndne_f64_e32 v[1:2], v[2:3] + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_floor_f64_e32 v[1:2], v[2:3] +// CIVI: v_floor_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x35,0x02,0x7e] +v_floor_f64_e32 v[1:2], v[2:3] + +// SICI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e] +// VI: v_fract_f32_e32 v1, v2 ; encoding: [0x02,0x37,0x02,0x7e] +v_fract_f32 v1, v2 + +// SICI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e] +// VI: v_trunc_f32_e32 v1, v2 ; encoding: [0x02,0x39,0x02,0x7e] +v_trunc_f32 v1, v2 + +// SICI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e] +// VI: v_ceil_f32_e32 v1, v2 ; encoding: [0x02,0x3b,0x02,0x7e] +v_ceil_f32 v1, v2 + +// SICI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e] +// VI: v_rndne_f32_e32 v1, v2 ; encoding: [0x02,0x3d,0x02,0x7e] +v_rndne_f32 v1, v2 + +// SICI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e] +// VI: v_floor_f32_e32 v1, v2 ; encoding: [0x02,0x3f,0x02,0x7e] +v_floor_f32_e32 v1, v2 + +// SICI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x4b,0x02,0x7e] +// VI: v_exp_f32_e32 v1, v2 ; encoding: [0x02,0x41,0x02,0x7e] +v_exp_f32 v1, v2 + +// SICI: v_log_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x4d,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_log_clamp_f32 v1, v2 +v_log_clamp_f32 v1, v2 + +// SICI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e] +// VI: v_log_f32_e32 v1, v2 ; encoding: [0x02,0x43,0x02,0x7e] +v_log_f32 v1, v2 + +// SICI: v_rcp_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x51,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rcp_clamp_f32 v1, v2 +v_rcp_clamp_f32 v1, v2 + +// SICI: v_rcp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rcp_legacy_f32 v1, v2 +v_rcp_legacy_f32 v1, v2 + +// SICI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e] +// VI: v_rcp_f32_e32 v1, v2 ; encoding: [0x02,0x45,0x02,0x7e] +v_rcp_f32 v1, v2 + +// SICI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e] +// VI: v_rcp_iflag_f32_e32 v1, v2 ; encoding: [0x02,0x47,0x02,0x7e] +v_rcp_iflag_f32 v1, v2 + +// SICI: v_rsq_clamp_f32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rsq_clamp_f32 v1, v2 +v_rsq_clamp_f32 v1, v2 + +// SICI: v_rsq_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rsq_legacy_f32 v1, v2 +v_rsq_legacy_f32 v1, v2 + +// SICI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e] +// VI: v_rsq_f32_e32 v1, v2 ; encoding: [0x02,0x49,0x02,0x7e] +v_rsq_f32_e32 v1, v2 + +// SICI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x5f,0x02,0x7e] +// VI: v_rcp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4b,0x02,0x7e] +v_rcp_f64 v[1:2], v[2:3] + +// SICI: v_rcp_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x61,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rcp_clamp_f64 v[1:2], v[2:3] +v_rcp_clamp_f64 v[1:2], v[2:3] + +// SICI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e] +// VI: v_rsq_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x4d,0x02,0x7e] +v_rsq_f64 v[1:2], v[2:3] + +// SICI: v_rsq_clamp_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_rsq_clamp_f64 v[1:2], v[2:3] +v_rsq_clamp_f64 v[1:2], v[2:3] + +// SICI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e] +// VI: v_sqrt_f32_e32 v1, v2 ; encoding: [0x02,0x4f,0x02,0x7e] +v_sqrt_f32 v1, v2 + +// SICI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x69,0x02,0x7e] +// VI: v_sqrt_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x51,0x02,0x7e] +v_sqrt_f64 v[1:2], v[2:3] + +// SICI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x6b,0x02,0x7e] +// VI: v_sin_f32_e32 v1, v2 ; encoding: [0x02,0x53,0x02,0x7e] +v_sin_f32 v1, v2 + +// SICI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e] +// VI: v_cos_f32_e32 v1, v2 ; encoding: [0x02,0x55,0x02,0x7e] +v_cos_f32 v1, v2 + +// SICI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e] +// VI: v_not_b32_e32 v1, v2 ; encoding: [0x02,0x57,0x02,0x7e] +v_not_b32 v1, v2 + +// SICI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e] +// VI: v_bfrev_b32_e32 v1, v2 ; encoding: [0x02,0x59,0x02,0x7e] +v_bfrev_b32 v1, v2 + +// SICI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e] +// VI: v_ffbh_u32_e32 v1, v2 ; encoding: [0x02,0x5b,0x02,0x7e] +v_ffbh_u32 v1, v2 + +// SICI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e] +// VI: v_ffbl_b32_e32 v1, v2 ; encoding: [0x02,0x5d,0x02,0x7e] +v_ffbl_b32 v1, v2 + +// SICI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e] +// VI: v_ffbh_i32_e32 v1, v2 ; encoding: [0x02,0x5f,0x02,0x7e] +v_ffbh_i32_e32 v1, v2 + +// SICI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x79,0x02,0x7e] +// VI: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x61,0x02,0x7e] +v_frexp_exp_i32_f64 v1, v[2:3] + +// SICI: v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7b,0x02,0x7e] +// VI; v_frexp_mant_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x63,0x02,0x7e] +v_frexp_mant_f64 v[1:2], v[2:3] + +// SICI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x7d,0x02,0x7e] +// VI: v_fract_f64_e32 v[1:2], v[2:3] ; encoding: [0x02,0x65,0x02,0x7e] +v_fract_f64 v[1:2], v[2:3] + +// SICI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e] +// VI: v_frexp_exp_i32_f32_e32 v1, v2 ; encoding: [0x02,0x67,0x02,0x7e] +v_frexp_exp_i32_f32 v1, v2 + +// SICI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e] +// VI: v_frexp_mant_f32_e32 v1, v2 ; encoding: [0x02,0x69,0x02,0x7e] +v_frexp_mant_f32 v1, v2 + +// SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e] +// VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e] +v_clrexcp + +// SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e] +// VI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e] +v_movreld_b32 v1, v2 + +// SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e] +// VI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e] +v_movrels_b32 v1, v2 + +// SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e] +// VI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e] +v_movrelsd_b32 v1, v2 + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_log_legacy_f32 v1, v2 +// CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e] +// VI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x99,0x02,0x7e] +v_log_legacy_f32 v1, v2 + +// NOSI: error: instruction not supported on this GPU +// NOSI: v_exp_legacy_f32 v1, v2 +// CI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e] +// VI: v_exp_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x97,0x02,0x7e] +v_exp_legacy_f32 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_f16_u16 v1, v2 +// VI: v_cvt_f16_u16_e32 v1, v2 ; encoding: [0x02,0x73,0x02,0x7e] +v_cvt_f16_u16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_f16_i16 v1, v2 +// VI: v_cvt_f16_i16_e32 v1, v2 ; encoding: [0x02,0x75,0x02,0x7e] +v_cvt_f16_i16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_u16_f16 v1, v2 +// VI: v_cvt_u16_f16_e32 v1, v2 ; encoding: [0x02,0x77,0x02,0x7e] +v_cvt_u16_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cvt_i16_f16 v1, v2 +// VI: v_cvt_i16_f16_e32 v1, v2 ; encoding: [0x02,0x79,0x02,0x7e] +v_cvt_i16_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_rcp_f16 v1, v2 +// VI: v_rcp_f16_e32 v1, v2 ; encoding: [0x02,0x7b,0x02,0x7e] +v_rcp_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_sqrt_f16 v1, v2 +// VI: v_sqrt_f16_e32 v1, v2 ; encoding: [0x02,0x7d,0x02,0x7e] +v_sqrt_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_rsq_f16 v1, v2 +// VI: v_rsq_f16_e32 v1, v2 ; encoding: [0x02,0x7f,0x02,0x7e] +v_rsq_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_log_f16 v1, v2 +// VI: v_log_f16_e32 v1, v2 ; encoding: [0x02,0x81,0x02,0x7e] +v_log_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_exp_f16 v1, v2 +// VI: v_exp_f16_e32 v1, v2 ; encoding: [0x02,0x83,0x02,0x7e] +v_exp_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_frexp_mant_f16 v1, v2 +// VI: v_frexp_mant_f16_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e] +v_frexp_mant_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_frexp_exp_i16_f16 v1, v2 +// VI: v_frexp_exp_i16_f16_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e] +v_frexp_exp_i16_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_floor_f16 v1, v2 +// VI: v_floor_f16_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e] +v_floor_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_ceil_f16 v1, v2 +// VI: v_ceil_f16_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e] +v_ceil_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_trunc_f16 v1, v2 +// VI: v_trunc_f16_e32 v1, v2 ; encoding: [0x02,0x8d,0x02,0x7e] +v_trunc_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_rndne_f16 v1, v2 +// VI: v_rndne_f16_e32 v1, v2 ; encoding: [0x02,0x8f,0x02,0x7e] +v_rndne_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_fract_f16 v1, v2 +// VI: v_fract_f16_e32 v1, v2 ; encoding: [0x02,0x91,0x02,0x7e] +v_fract_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_sin_f16 v1, v2 +// VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e] +v_sin_f16 v1, v2 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_cos_f16 v1, v2 +// VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e] +v_cos_f16 v1, v2 diff --git a/test/MC/AMDGPU/vop2-err.s b/test/MC/AMDGPU/vop2-err.s new file mode 100644 index 0000000000000..a1131000a9095 --- /dev/null +++ b/test/MC/AMDGPU/vop2-err.s @@ -0,0 +1,35 @@ +// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s + +//===----------------------------------------------------------------------===// +// Generic checks +//===----------------------------------------------------------------------===// + +v_mul_i32_i24 v1, v2, 100 +// CHECK: error: invalid operand for instruction + +//===----------------------------------------------------------------------===// +// _e32 checks +//===----------------------------------------------------------------------===// + +// Immediate src1 +v_mul_i32_i24_e32 v1, v2, 100 +// CHECK: error: invalid operand for instruction + +// sgpr src1 +v_mul_i32_i24_e32 v1, v2, s3 +// CHECK: error: invalid operand for instruction + +//===----------------------------------------------------------------------===// +// _e64 checks +//===----------------------------------------------------------------------===// + +// Immediate src0 +v_mul_i32_i24_e64 v1, 100, v3 +// CHECK: error: invalid operand for instruction + +// Immediate src1 +v_mul_i32_i24_e64 v1, v2, 100 +// CHECK: error: invalid operand for instruction + +// TODO: Constant bus restrictions diff --git a/test/MC/AMDGPU/vop2.s b/test/MC/AMDGPU/vop2.s new file mode 100644 index 0000000000000..a1f3b8d893652 --- /dev/null +++ b/test/MC/AMDGPU/vop2.s @@ -0,0 +1,421 @@ +// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI + +// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI + +//===----------------------------------------------------------------------===// +// Generic Checks for floating-point instructions (These have modifiers). +//===----------------------------------------------------------------------===// + +// TODO: 64-bit encoding of instructions with modifiers + +// _e32 suffix +// SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06] +v_add_f32_e32 v1, v2, v3 + +// src0 inline immediate +// SICI: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x06] +v_add_f32 v1, 1.0, v3 + +// src0 negative inline immediate +// SICI: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x06] +v_add_f32 v1, -1.0, v3 + +// src0 literal +// SICI: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0x42] +v_add_f32 v1, 100.0, v3 + +// src0 negative literal +// SICI: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0xc2] +v_add_f32 v1, -100.0, v3 + +//===----------------------------------------------------------------------===// +// Generic Checks for integer instructions (These don't have modifiers). +//===----------------------------------------------------------------------===// + +// _e32 suffix +// SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12] +v_mul_i32_i24_e32 v1, v2, v3 + +// _e64 suffix +// SICI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00] +v_mul_i32_i24_e64 v1, v2, v3 + +// src0 inline +// SICI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12] +v_mul_i32_i24 v1, 3, v3 + +// src0 negative inline +// SICI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12] +v_mul_i32_i24 v1, -3, v3 + +// src1 inline +// SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00] +v_mul_i32_i24 v1, v2, 3 + +// src1 negative inline +// SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00] +v_mul_i32_i24 v1, v2, -3 + +// src0 literal +// SICI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00] +v_mul_i32_i24 v1, 100, v3 + +// src1 negative literal +// SICI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff] +v_mul_i32_i24 v1, -100, v3 + +//===----------------------------------------------------------------------===// +// Checks for legal operands +//===----------------------------------------------------------------------===// + +// src0 sgpr +// SICI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12] +v_mul_i32_i24 v1, s2, v3 + +// src1 sgpr +// SICI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00] +v_mul_i32_i24 v1, v2, s3 + +// src0, src1 same sgpr +// SICI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00] +v_mul_i32_i24 v1, s2, s2 + +// src0 sgpr, src1 inline +// SICI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00] +v_mul_i32_i24 v1, s2, 3 + +// src0 inline src1 sgpr +// SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00] +v_mul_i32_i24 v1, 3, s3 + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +// GCN: v_cndmask_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x00] +v_cndmask_b32 v1, v2, v3 + +// SICI: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02] +// VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00] +v_readlane_b32 s1, v2, s3 + +// SICI: v_writelane_b32 v1, s2, s3 ; encoding: [0x02,0x06,0x02,0x04] +// VI: v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00] +v_writelane_b32 v1, s2, s3 + +// SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06] +// VI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02] +v_add_f32 v1, v2, v3 + +// SICI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08] +// VI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04] +v_sub_f32 v1, v2, v3 + +// SICI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a] +// VI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06] +v_subrev_f32 v1, v2, v3 + +// SICI: v_mac_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_mac_legacy_f32 v1, v2, v3 +v_mac_legacy_f32 v1, v2, v3 + +// SICI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e] +// VI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08] +v_mul_legacy_f32_e32 v1, v2, v3 + +// SICI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10] +// VI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a] +v_mul_f32 v1, v2, v3 + +// SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12] +// VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c] +v_mul_i32_i24 v1, v2, v3 + +// SICI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14] +// VI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e] +v_mul_hi_i32_i24 v1, v2, v3 + +// SICI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16] +// VI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10] +v_mul_u32_u24 v1, v2, v3 + +// SICI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18] +// VI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12] +v_mul_hi_u32_u24 v1, v2, v3 + +// SICI: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_min_legacy_f32_e32 v1, v2, v3 +v_min_legacy_f32_e32 v1, v2, v3 + +// SICI: v_max_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_max_legacy_f32 v1, v2, v3 +v_max_legacy_f32 v1, v2, v3 + +// SICI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e] +// VI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14] +v_min_f32_e32 v1, v2, v3 + +// SICI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20] +// VI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16] +v_max_f32 v1, v2 v3 + +// SICI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22] +// VI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18] +v_min_i32 v1, v2, v3 + +// SICI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24] +// VI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a] +v_max_i32 v1, v2, v3 + +// SICI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26] +// VI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c] +v_min_u32 v1, v2, v3 + +// SICI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28] +// VI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e] +v_max_u32 v1, v2, v3 + +// SICI: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_lshr_b32 v1, v2, v3 +v_lshr_b32 v1, v2, v3 + +// SICI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c] +// VI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20] +v_lshrrev_b32 v1, v2, v3 + +// SICI: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_ashr_i32 v1, v2, v3 +v_ashr_i32 v1, v2, v3 + +// SICI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30] +// VI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22] +v_ashrrev_i32 v1, v2, v3 + +// SICI: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32] +// NOVI: error: instruction not supported on this GPU +// NOVI: v_lshl_b32_e32 v1, v2, v3 +v_lshl_b32_e32 v1, v2, v3 + +// SICI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34] +// VI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24] +v_lshlrev_b32 v1, v2, v3 + +// SICI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36] +// VI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26] +v_and_b32 v1, v2, v3 + +// SICI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38] +// VI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28] +v_or_b32 v1, v2, v3 + +// SICI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a] +// VI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a] +v_xor_b32 v1, v2, v3 + +// SICI: v_bfm_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c] +// VI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00] +v_bfm_b32 v1, v2, v3 + +// SICI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e] +// VI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c] +v_mac_f32 v1, v2, v3 + +// SICI: v_madmk_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42] +// VI: v_madmk_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42] +v_madmk_f32 v1, v2, v3, 64.0 + +// SICI: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42] +// VI: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42] +v_madak_f32 v1, v2, v3, 64.0 + +// SICI: v_bcnt_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44] +// VI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00] +v_bcnt_u32_b32 v1, v2, v3 + +// SICI: v_mbcnt_lo_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46] +// VI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00] +v_mbcnt_lo_u32_b32 v1, v2, v3 + +// SICI: v_mbcnt_hi_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x48] +// VI: v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00] +v_mbcnt_hi_u32_b32 v1, v2, v3 + +// SICI: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a] +// VI: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32] +v_add_i32 v1, v2, v3 + +// SICI: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a] +// VI: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32] +v_add_u32 v1, v2, v3 + +// SICI: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c] +// VI: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34] +v_sub_i32 v1, v2, v3 + +// SICI: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c] +// VI: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34] +v_sub_u32 v1, v2, v3 + +// SICI: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e] +// VI: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36] +v_subrev_i32 v1, v2, v3 + +// SICI: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e] +// VI: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36] +v_subrev_u32 v1, v2, v3 + +// SICI: v_addc_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50] +// VI: v_addc_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38] +v_addc_u32 v1, v2, v3 + +// SICI: v_subb_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52] +// VI: v_subb_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a] +v_subb_u32 v1, v2, v3 + +// SICI: v_subbrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54] +// VI: v_subbrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c] +v_subbrev_u32 v1, v2, v3 + +// SICI: v_ldexp_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56] +// VI: v_ldexp_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x88,0xd2,0x02,0x07,0x02,0x00] +v_ldexp_f32 v1, v2, v3 + +// SICI: v_cvt_pkaccum_u8_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58] +// VI: v_cvt_pkaccum_u8_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0xf0,0xd1,0x02,0x07,0x02,0x00] +v_cvt_pkaccum_u8_f32 v1, v2, v3 + +// SICI: v_cvt_pknorm_i16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a] +// VI: v_cvt_pknorm_i16_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x94,0xd2,0x02,0x07,0x02,0x00] +v_cvt_pknorm_i16_f32 v1, v2, v3 + +// SICI: v_cvt_pknorm_u16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c] +// VI: v_cvt_pknorm_u16_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x95,0xd2,0x02,0x07,0x02,0x00] +v_cvt_pknorm_u16_f32 v1, v2, v3 + +// SICI: v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e] +// VI: v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x96,0xd2,0x02,0x07,0x02,0x00] +v_cvt_pkrtz_f16_f32 v1, v2, v3 + +// SICI: v_cvt_pk_u16_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60] +// VI: v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x97,0xd2,0x02,0x07,0x02,0x00] +v_cvt_pk_u16_u32 v1, v2, v3 + +// SICI: v_cvt_pk_i16_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62] +// VI: v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x98,0xd2,0x02,0x07,0x02,0x00] +v_cvt_pk_i16_i32 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_add_f16 v1, v2, v3 +// VI: v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e] +v_add_f16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_sub_f16 v1, v2, v3 +// VI: v_sub_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x40] +v_sub_f16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_subrev_f16 v1, v2, v3 +// VI: v_subrev_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x42] +v_subrev_f16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_mul_f16 v1, v2, v3 +// VI: v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44] +v_mul_f16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_mac_f16 v1, v2, v3 +// VI: v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46] +v_mac_f16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_madmk_f16 v1, v2, v3, 64.0 +// VI: v_madmk_f16_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x48,0x00,0x00,0x80,0x42] +v_madmk_f16 v1, v2, v3, 64.0 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_madak_f16 v1, v2, v3, 64.0 +// VI: v_madak_f16_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x00,0x80,0x42] +v_madak_f16 v1, v2, v3, 64.0 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_add_u16 v1, v2, v3 +// VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c] +v_add_u16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_sub_u16 v1, v2, v3 +// VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e] +v_sub_u16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_subrev_u16 v1, v2, v3 +// VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50] +v_subrev_u16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_mul_lo_u16 v1, v2, v3 +// VI: v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52] +v_mul_lo_u16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_lshlrev_b16 v1, v2, v3 +// VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54] +v_lshlrev_b16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_lshrrev_b16 v1, v2, v3 +// VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56] +v_lshrrev_b16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_ashrrev_b16 v1, v2, v3 +// VI: v_ashrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58] +v_ashrrev_b16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_max_f16 v1, v2, v3 +// VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a] +v_max_f16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_min_f16 v1, v2, v3 +// VI: v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c] +v_min_f16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_max_u16 v1, v2, v3 +// VI: v_max_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e] +v_max_u16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_max_i16 v1, v2, v3 +// VI: v_max_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60] +v_max_i16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_min_u16 v1, v2, v3 +// VI: v_min_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62] +v_min_u16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_min_i16 v1, v2, v3 +// VI: v_min_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x64] +v_min_i16 v1, v2, v3 + +// NOSICI: error: instruction not supported on this GPU +// NOSICI: v_ldexp_f16 v1, v2, v3 +// VI: v_ldexp_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x66] +v_ldexp_f16 v1, v2, v3 diff --git a/test/MC/AMDGPU/vop3-errs.s b/test/MC/AMDGPU/vop3-errs.s new file mode 100644 index 0000000000000..b57fe6d5314bd --- /dev/null +++ b/test/MC/AMDGPU/vop3-errs.s @@ -0,0 +1,5 @@ +// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s + +v_add_f32_e64 v0, v1 +// CHECK: error: too few operands for instruction diff --git a/test/MC/AMDGPU/vop3.s b/test/MC/AMDGPU/vop3.s new file mode 100644 index 0000000000000..2056233597481 --- /dev/null +++ b/test/MC/AMDGPU/vop3.s @@ -0,0 +1,149 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// VOPC Instructions +//===----------------------------------------------------------------------===// + +// Test forced e64 encoding + +v_cmp_lt_f32_e64 s[2:3], v4, -v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x40] + +// +// Modifier tests: +// + +v_cmp_lt_f32 s[2:3] -v4, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], -v4, v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x20] + +v_cmp_lt_f32 s[2:3] v4, -v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x40] + +v_cmp_lt_f32 s[2:3] -v4, -v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], -v4, -v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x60] + +v_cmp_lt_f32 s[2:3] |v4|, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], |v4|, v6 ; encoding: [0x02,0x01,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3] v4, |v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, |v6| ; encoding: [0x02,0x02,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3] |v4|, |v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], |v4|, |v6| ; encoding: [0x02,0x03,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3] -|v4|, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], -|v4|, v6 ; encoding: [0x02,0x01,0x02,0xd0,0x04,0x0d,0x02,0x20] + +v_cmp_lt_f32 s[2:3] v4, -|v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, -|v6| ; encoding: [0x02,0x02,0x02,0xd0,0x04,0x0d,0x02,0x40] + +v_cmp_lt_f32 s[2:3] -|v4|, -|v6| +// CHECK: v_cmp_lt_f32_e64 s[2:3], -|v4|, -|v6| ; encoding: [0x02,0x03,0x02,0xd0,0x04,0x0d,0x02,0x60] + +// +// Instruction tests: +// + +v_cmp_f_f32 s[2:3], v4, v6 +// CHECK: v_cmp_f_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x00,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lt_f32 s[2:3], v4, v6 +// CHECK: v_cmp_lt_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x02,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_eq_f32 s[2:3], v4, v6 +// CHECK: v_cmp_eq_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x04,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_le_f32 s[2:3], v4, v6 +// CHECK: v_cmp_le_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x06,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_gt_f32 s[2:3], v4, v6 +// CHECK: v_cmp_gt_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x08,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_lg_f32 s[2:3], v4, v6 +// CHECK: v_cmp_lg_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x0a,0xd0,0x04,0x0d,0x02,0x00] + +v_cmp_ge_f32 s[2:3], v4, v6 +// CHECK: v_cmp_ge_f32_e64 s[2:3], v4, v6 ; encoding: [0x02,0x00,0x0c,0xd0,0x04,0x0d,0x02,0x00] + +// TODO: Finish VOPC + +//===----------------------------------------------------------------------===// +// VOP1 Instructions +//===----------------------------------------------------------------------===// + +// +// Modifier tests: +// + +v_fract_f32 v1, -v2 +// CHECK: v_fract_f32_e64 v1, -v2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x20] + +v_fract_f32 v1, |v2| +// CHECK: v_fract_f32_e64 v1, |v2| ; encoding: [0x01,0x01,0x40,0xd3,0x02,0x01,0x00,0x00] + +v_fract_f32 v1, -|v2| +// CHECK: v_fract_f32_e64 v1, -|v2| ; encoding: [0x01,0x01,0x40,0xd3,0x02,0x01,0x00,0x20] + +v_fract_f32 v1, v2 clamp +// CHECK: v_fract_f32_e64 v1, v2 clamp ; encoding: [0x01,0x08,0x40,0xd3,0x02,0x01,0x00,0x00] + +v_fract_f32 v1, v2 mul:2 +// CHECK: v_fract_f32_e64 v1, v2 mul:2 ; encoding: [0x01,0x00,0x40,0xd3,0x02,0x01,0x00,0x08] + +v_fract_f32 v1, v2, div:2 clamp +// CHECK: v_fract_f32_e64 v1, v2 clamp div:2 ; encoding: [0x01,0x08,0x40,0xd3,0x02,0x01,0x00,0x18] + +// TODO: Finish VOP1 + +///===---------------------------------------------------------------------===// +// VOP2 Instructions +///===---------------------------------------------------------------------===// + +// Test forced e64 encoding with e32 operands + +v_ldexp_f32_e64 v1, v3, v5 +// CHECK: v_ldexp_f32_e64 v1, v3, v5 ; encoding: [0x01,0x00,0x56,0xd2,0x03,0x0b,0x02,0x00] + + +// TODO: Modifier tests + +v_cndmask_b32 v1, v3, v5, s[4:5] +// CHECK: v_cndmask_b32_e64 v1, v3, v5, s[4:5] ; encoding: [0x01,0x00,0x00,0xd2,0x03,0x0b,0x12,0x00] + +//TODO: readlane, writelane + +v_add_f32 v1, v3, s5 +// CHECK: v_add_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x06,0xd2,0x03,0x0b,0x00,0x00] + +v_sub_f32 v1, v3, s5 +// CHECK: v_sub_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x08,0xd2,0x03,0x0b,0x00,0x00] + +v_subrev_f32 v1, v3, s5 +// CHECK: v_subrev_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0a,0xd2,0x03,0x0b,0x00,0x00] + +v_mac_legacy_f32 v1, v3, s5 +// CHECK: v_mac_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0c,0xd2,0x03,0x0b,0x00,0x00] + +v_mul_legacy_f32 v1, v3, s5 +// CHECK: v_mul_legacy_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x0e,0xd2,0x03,0x0b,0x00,0x00] + +v_mul_f32 v1, v3, s5 +// CHECK: v_mul_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x10,0xd2,0x03,0x0b,0x00,0x00] + +v_mul_i32_i24 v1, v3, s5 +// CHECK: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x12,0xd2,0x03,0x0b,0x00,0x00] + +///===---------------------------------------------------------------------===// +// VOP3 Instructions +///===---------------------------------------------------------------------===// + +// TODO: Modifier tests + +v_mad_legacy_f32 v2, v4, v6, v8 +// CHECK: v_mad_legacy_f32 v2, v4, v6, v8 ; encoding: [0x02,0x00,0x80,0xd2,0x04,0x0d,0x22,0x04] + + + + + diff --git a/test/MC/AMDGPU/vopc.s b/test/MC/AMDGPU/vopc.s new file mode 100644 index 0000000000000..f44919a4f1e0c --- /dev/null +++ b/test/MC/AMDGPU/vopc.s @@ -0,0 +1,40 @@ +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s + +//===----------------------------------------------------------------------===// +// Generic Checks +//===----------------------------------------------------------------------===// + +// src0 sgpr +v_cmp_lt_f32 vcc, s2, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c] + +// src0 inline immediate +v_cmp_lt_f32 vcc, 0, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c] + +// src0 literal +v_cmp_lt_f32 vcc, 10.0, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41] + +// src0, src1 max vgpr +v_cmp_lt_f32 vcc, v255, v255 +// CHECK: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c] + +// force 32-bit encoding +v_cmp_lt_f32_e32 vcc, v2, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] + + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +v_cmp_f_f32 vcc, v2, v4 +// CHECK: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c] + +v_cmp_lt_f32 vcc, v2, v4 +// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] + +// TODO: Add tests for the rest of the instructions. + |