summaryrefslogtreecommitdiff
path: root/test/MC/AMDGPU
diff options
context:
space:
mode:
Diffstat (limited to 'test/MC/AMDGPU')
-rw-r--r--test/MC/AMDGPU/ds.s4
-rw-r--r--test/MC/AMDGPU/expressions.s8
-rw-r--r--test/MC/AMDGPU/invalid-instructions-spellcheck.s48
-rw-r--r--test/MC/AMDGPU/trap.s42
-rw-r--r--test/MC/AMDGPU/vop1-gfx9-err.s12
-rw-r--r--test/MC/AMDGPU/vop3p-err.s6
6 files changed, 112 insertions, 8 deletions
diff --git a/test/MC/AMDGPU/ds.s b/test/MC/AMDGPU/ds.s
index ef36a98f746ac..b06101a4051b8 100644
--- a/test/MC/AMDGPU/ds.s
+++ b/test/MC/AMDGPU/ds.s
@@ -511,6 +511,10 @@ ds_swizzle_b32 v8, v2
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
+ds_swizzle_b32 v8, v2 gds
+// SICI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0xd6,0xd8,0x02,0x00,0x00,0x08]
+// VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
+
ds_swizzle_b32 v8, v2 offset:0xFFFF
// SICI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x02,0x00,0x00,0x08]
diff --git a/test/MC/AMDGPU/expressions.s b/test/MC/AMDGPU/expressions.s
index 7b0e90378a065..dd4957c8baec1 100644
--- a/test/MC/AMDGPU/expressions.s
+++ b/test/MC/AMDGPU/expressions.s
@@ -46,3 +46,11 @@ BB2:
s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1
// VI: s_sub_u32 vcc_lo, vcc_lo, (BB2+4)-BB1 ; encoding: [0x6a,0xff,0xea,0x80,A,A,A,A]
// VI-NEXT: ; fixup A - offset: 4, value: (BB2+4)-BB1, kind: FK_Data_4
+
+t=1
+s_sub_u32 s0, s0, -t
+// VI: s_sub_u32 s0, s0, -1 ; encoding: [0x00,0xc1,0x80,0x80]
+
+t=-1
+s_sub_u32 s0, s0, -t
+// VI: s_sub_u32 s0, s0, 1 ; encoding: [0x00,0x81,0x80,0x80]
diff --git a/test/MC/AMDGPU/invalid-instructions-spellcheck.s b/test/MC/AMDGPU/invalid-instructions-spellcheck.s
new file mode 100644
index 0000000000000..f4198f10f4b88
--- /dev/null
+++ b/test/MC/AMDGPU/invalid-instructions-spellcheck.s
@@ -0,0 +1,48 @@
+# RUN: not llvm-mc -triple amdgcn < %s 2>&1 | FileCheck %s
+
+# This tests the mnemonic spell checker.
+
+# First check what happens when an instruction is omitted:
+
+v2, v4, v6
+
+# CHECK: unknown token in expression
+# CHECK-NEXT: v2, v4, v6
+# CHECK-NEXT: ^
+
+# CHECK: error: not a valid operand.
+# CHECK-NEXT: v2, v4, v6
+# CHECK-NEXT: ^
+
+# We don't want to see a suggestion here; the edit distance is too large to
+# give sensible suggestions:
+
+aaaaaaaaaaaaaaa v1, v2, v3
+
+# CHECK: error: invalid instruction
+# CHECK-NEXT: aaaaaaaaaaaaaaa v1, v2, v3
+# CHECK-NEXT: ^
+
+# Check that we get one suggestion: 'dsc_write_src2_b64' is 1 edit away, i.e. an deletion.
+
+dsc_write_src2_b64 v1, v2, v3
+
+# CHECK: error: invalid instruction, did you mean: ds_write_src2_b64?
+# CHECK-NEXT: dsc_write_src2_b64 v1, v2, v3
+# CHECK-NEXT: ^
+
+# Check edit distance 1 and 2, just insertions:
+
+s_mov_b v1, v2
+
+# CHECK: error: invalid instruction, did you mean: s_mov_b32, s_mov_b64?
+# CHECK-NEXT: s_mov_b v1, v2
+# CHECK-NEXT: ^
+
+# Check an instruction that is 2 edits away, and also has a lot of candidates:
+
+s_load_dwordx v1, v2, v3
+
+# CHECK: error: invalid instruction, did you mean: s_load_dword, s_load_dwordx16, s_load_dwordx2, s_load_dwordx4, s_load_dwordx8?
+# CHECK-NEXT: s_load_dwordx v1, v2, v3
+# CHECK-NEXT: ^
diff --git a/test/MC/AMDGPU/trap.s b/test/MC/AMDGPU/trap.s
index de551ca00b528..7b527ba3072e9 100644
--- a/test/MC/AMDGPU/trap.s
+++ b/test/MC/AMDGPU/trap.s
@@ -190,6 +190,48 @@ s_mov_b64 ttmp[14:15], exec
// GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
//===----------------------------------------------------------------------===//
+// Trap Handler related - 8-dword registers
+// NB: gfx7 doc states that SMRD does not support trap registers for dst
+//===----------------------------------------------------------------------===//
+
+s_buffer_load_dwordx8 ttmp[0:7], s[0:3], s0
+// VI: [0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00]
+// GFX9: [0x00,0x1b,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 ttmp[4:11], s[0:3], s0
+// VI: [0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
+// GFX9: [0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 ttmp[8:15], s[0:3], s0
+// NOSICIVI: error: not a valid operand
+// GFX9: [0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 ttmp[0:7], s[0:1], s0
+// VI: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
+// GFX9: [0x00,0x1b,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 ttmp[4:11], s[0:1], s0
+// VI: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
+// GFX9: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 ttmp[8:15], s[0:1], s0
+// NOSICIVI: error: not a valid operand
+// GFX9: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+//===----------------------------------------------------------------------===//
+// Trap Handler related - 16-dword registers
+// NB: gfx7 doc states that SMRD does not support trap registers for dst
+//===----------------------------------------------------------------------===//
+
+s_buffer_load_dwordx16 ttmp[0:15], s[0:3], s0
+// NOSICIVI: error: not a valid operand
+// GFX9: [0x00,0x1b,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 ttmp[0:15], s[0:1], s0
+// NOSICIVI: error: not a valid operand
+// GFX9: [0x00,0x1b,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+//===----------------------------------------------------------------------===//
// Trap Handler related - Some specific instructions
//===----------------------------------------------------------------------===//
diff --git a/test/MC/AMDGPU/vop1-gfx9-err.s b/test/MC/AMDGPU/vop1-gfx9-err.s
index 0036b79c71b5a..61bf5f6617595 100644
--- a/test/MC/AMDGPU/vop1-gfx9-err.s
+++ b/test/MC/AMDGPU/vop1-gfx9-err.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN,GFX9 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN,VI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefixes=GCN,CI %s
v_swap_b32 v1, 1
// GCN: :16: error: invalid operand for instruction
@@ -10,7 +10,9 @@ v_swap_b32 v1, s0
// FIXME: Better error for it requiring VOP1 encoding
v_swap_b32_e64 v1, v2
-// GCN: :1: error: unrecognized instruction mnemonic
+// GFX9: :1: error: invalid instruction, did you mean: v_swap_b32?
+// CI: :1: error: invalid instruction
+// VI: :1: error: invalid instruction
v_swap_b32 v1, v2, v1
// GCN: :20: error: invalid operand for instruction
@@ -22,4 +24,4 @@ v_swap_b32 v1, v2, v2, v2
// GCN: :20: error: invalid operand for instruction
v_swap_codegen_pseudo_b32 v1, v2
-// GCN: :1: error: unrecognized instruction mnemonic
+// GCN: :1: error: invalid instruction
diff --git a/test/MC/AMDGPU/vop3p-err.s b/test/MC/AMDGPU/vop3p-err.s
index 7dfd951b6ad0d..fe3fee97b5e72 100644
--- a/test/MC/AMDGPU/vop3p-err.s
+++ b/test/MC/AMDGPU/vop3p-err.s
@@ -59,16 +59,16 @@ v_pk_add_f16 v1, v2, |v3|
// GFX9: :22: error: invalid operand for instruction
v_pk_add_f16 v1, v2, abs(v3)
-// GFX9: :19: error: invalid operand for instruction
+// GFX9: :18: error: invalid operand for instruction
v_pk_add_f16 v1, -v2, v3
-// GFX9: :23: error: invalid operand for instruction
+// GFX9: :22: error: invalid operand for instruction
v_pk_add_f16 v1, v2, -v3
// GFX9: :18: error: invalid operand for instruction
v_pk_add_u16 v1, abs(v2), v3
-// GFX9: :19: error: invalid operand for instruction
+// GFX9: :18: error: invalid operand for instruction
v_pk_add_u16 v1, -v2, v3
//
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-03 11:36:25 +0000