diff options
Diffstat (limited to 'test/MC/Disassembler')
19 files changed, 153 insertions, 20 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 0c9aaab38c7e4..98daaa7649aac 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -51,24 +51,48 @@ # CHECKx: ldclvc p5, cr15, [r8], #-0 #0x00 0xf5 0x78 0x7c +# CHECK: ldc p13, c9, [r2, #0]! +0x00 0x9d 0xb2 0xed + +# CHECK: ldcl p1, c9, [r3, #0]! +0x00 0x91 0xf3 0xed + # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 # CHECK: ldr r5, [r7, -r10, lsl #2] 0x0a 0x51 0x17 0xe7 +# CHECK: ldr r4, [r5, #0]! +0x00 0x40 0xb5 0xe5 + +# CHECK: ldrb lr, [r10, #0]! +0x00 0xe0 0xfa 0xe5 + +# CHECK: ldrd r4, r5, [r0, #0]! +0xd0 0x40 0xe0 0xe1 + # CHECK: ldrh r0, [r2], #0 0xb0 0x00 0xd2 0xe0 # CHECK: ldrh r0, [r2] 0xb0 0x00 0xd2 0xe1 +# CHECK: ldrh lr, [sp, #0]! +0xb0 0xe0 0xfd 0xe1 + # CHECK: ldrht r0, [r2], #15 0xbf 0x00 0xf2 0xe0 +# CHECK: ldrsb r1, [lr, #0]! +0xd0 0x10 0xfe 0xe1 + # CHECK: ldrsbtvs lr, [r2], -r9 0xd9 0xe0 0x32 0x60 +# CHECK: ldrsh r9, [r1, #0] +0xf0 0x90 0xf1 0xe1 + # CHECK: lsls r0, r2, #31 0x82 0x0f 0xb0 0xe1 @@ -245,9 +269,27 @@ # CHECK: stc p2, c4, [r9], {157} 0x9d 0x42 0x89 0xec +# CHECK: stc p15, c0, [r3, #0]! +0x00 0x0f 0xa3 0xed + # CHECK: stc2 p2, c4, [r9], {157} 0x9d 0x42 0x89 0xfc +# CHECK: stcl p13, c12, [r9, #0]! +0x00 0xcd 0xe9 0xed + +# CHECK: str pc, [r11, #0]! +0x00 0xf0 0xab 0xe5 + +# CHECK: strb r9, [r10, #0]! +0x00 0x90 0xea 0xe5 + +# CHECK: strd r12, sp, [r6, #0]! +0xf0 0xc0 0xe6 0xe1 + +# CHECK: strh r7, [r9, #0]! +0xb0 0x70 0xe9 0xe1 + # CHECK: bne #-24 0xfa 0xff 0xff 0x1a diff --git a/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt b/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt new file mode 100644 index 0000000000000..d6b7cf1a0bb52 --- /dev/null +++ b/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + +#------------------------------------------------------------------------------ +# SMC +#------------------------------------------------------------------------------ + +0xff 0xf7 0x00 0x80 +0x0c 0xbf +0xf0 0xf7 0x00 0x80 + +# NOTZ-NOT: smc #15 +# NOTZ-NOT: smceq #0 +# TZ: smc #15 +# TZ: ite eq +# TZ: smceq #0 diff --git a/test/MC/Disassembler/ARM/arm-trustzone.txt b/test/MC/Disassembler/ARM/arm-trustzone.txt new file mode 100644 index 0000000000000..92d5d6b290722 --- /dev/null +++ b/test/MC/Disassembler/ARM/arm-trustzone.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + +#------------------------------------------------------------------------------ +# SMC +#------------------------------------------------------------------------------ + +0x7f 0x00 0x60 0xe1 +0x70 0x00 0x60 0x01 + +# NOTZ-NOT: smc #15 +# NOTZ-NOT: smceq #0 +# TZ: smc #15 +# TZ: smceq #0 + diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 1100ce64a947b..9f63e1e914ffd 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -707,8 +707,10 @@ # CHECK: mov r3, #7 # CHECK: mov r4, #4080 # CHECK: mov r5, #16711680 +# CHECK: mov sp, #35 # CHECK: movw r6, #65535 # CHECK: movw r9, #65535 +# CHECK: movw sp, #1193 # CHECK: movs r3, #7 # CHECK: moveq r4, #4080 # CHECK: movseq r5, #16711680 @@ -716,8 +718,10 @@ 0x07 0x30 0xa0 0xe3 0xff 0x4e 0xa0 0xe3 0xff 0x58 0xa0 0xe3 +0x23 0xd0 0xa0 0xe3 0xff 0x6f 0x0f 0xe3 0xff 0x9f 0x0f 0xe3 +0xa9 0xd4 0x00 0xe3 0x07 0x30 0xb0 0xe3 0xff 0x4e 0xa0 0x03 0xff 0x58 0xb0 0x03 @@ -740,10 +744,12 @@ #------------------------------------------------------------------------------ # CHECK: movt r3, #7 # CHECK: movt r6, #65535 +# CHECK: movt sp, #3397 # CHECK: movteq r4, #4080 0x07 0x30 0x40 0xe3 0xff 0x6f 0x4f 0xe3 +0x45 0xdd 0x40 0xe3 0xf0 0x4f 0x40 0x03 @@ -1442,15 +1448,6 @@ 0xf2 0x4f 0x38 0xc6 #------------------------------------------------------------------------------ -# SMC -#------------------------------------------------------------------------------ -# CHECK: smc #15 -# CHECK: smceq #0 - -0x7f 0x00 0x60 0xe1 -0x70 0x00 0x60 0x01 - -#------------------------------------------------------------------------------ # SMLABB/SMLABT/SMLATB/SMLATT #------------------------------------------------------------------------------ # CHECK: smlabb r3, r1, r9, r0 @@ -1826,12 +1823,13 @@ # CHECK: strexh r4, r2, [r5 # CHECK: strex r2, r1, [r7 # CHECK: strexd r6, r2, r3, [r8 +# CHECK: strexd sp, r0, r1, [r0] 0x93 0x1f 0xc4 0xe1 0x92 0x4f 0xe5 0xe1 0x91 0x2f 0x87 0xe1 0x92 0x6f 0xa8 0xe1 - +0x90 0xdf 0xa0 0xe1 #------------------------------------------------------------------------------ # SUB diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt index 0cff28ad2b2b0..ecab5a5758e21 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * # LDR_PRE/POST has encoding Inst{4} = 0. 0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-hint-arm.txt b/test/MC/Disassembler/ARM/invalid-hint-arm.txt new file mode 100644 index 0000000000000..7da96d8f15ce0 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-hint-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s 2>&1 | FileCheck %s + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +0x05 0xf0 0x20 0xe3 +# CHECK: invalid instruction encoding +0x41 0xf0 0x20 0xe3 +# CHECK: invalid instruction encoding +0xfe 0xf0 0x20 0xe3 +# CHECK: invalid instruction encoding + diff --git a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt b/test/MC/Disassembler/ARM/invalid-hint-thumb.txt new file mode 100644 index 0000000000000..1e4133668b84f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-hint-thumb.txt @@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple=thumbv7 -disassemble -show-encoding < %s 2>&1 | FileCheck %s + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +0xaf 0xf3 0x05 0x80 +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/Mips/mips-dsp.txt b/test/MC/Disassembler/Mips/mips-dsp.txt new file mode 100644 index 0000000000000..d10e62cd23cde --- /dev/null +++ b/test/MC/Disassembler/Mips/mips-dsp.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple=mipsel-unknown-linux -mattr=+dsp -disassemble < %s | FileCheck %s + +# CHECK: mfhi $21, $ac3 +0x10 0xa8 0x60 0x00 + +# CHECK: mflo $21, $ac3 +0x12 0xa8 0x60 0x00 + +# CHECK: mthi $21, $ac3 +0x11 0x18 0xa0 0x02 + +# CHECK: mtlo $21, $ac3 +0x13 0x18 0xa0 0x02 diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index 70224860bc710..ef8bf71bd3a6d 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x46 0x20 0x73 0x05 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 48fa8e2c7fac1..a0885a4bfe853 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x05 0x73 0x20 0x46 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index 3b70db3bc29d1..991eaa6cc97fe 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x46 0x20 0x73 0x05 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index ecfde7a39c4fb..10c293821c9dd 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x05 0x73 0x20 0x46 diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt index 38b137766125f..b88747370b671 100644 --- a/test/MC/Disassembler/Mips/mips64.txt +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0x67 0x4b 0x7c 0xcd diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt index a7ef0e473bbe6..ddc3c2b60be42 100644 --- a/test/MC/Disassembler/Mips/mips64_le.txt +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0xcd 0x7c 0x4b 0x67 diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt index 0b421fc551e2a..cee6f3c21f721 100644 --- a/test/MC/Disassembler/Mips/mips64r2.txt +++ b/test/MC/Disassembler/Mips/mips64r2.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0x67 0x4b 0x7c 0xcd diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt index c1d326f6d6749..82e4d6ae1ce0e 100644 --- a/test/MC/Disassembler/Mips/mips64r2_le.txt +++ b/test/MC/Disassembler/Mips/mips64r2_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0xcd 0x7c 0x4b 0x67 diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index 27694cd014461..57e602f1500e4 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -110,3 +110,12 @@ # CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8 0xc4 0x02 0x39 0x90 0x14 0x4f + +# CHECK: xsave64 OPAQUE PTR [RAX] +0x48 0x0f 0xae 0x20 + +# CHECK: xrstor64 OPAQUE PTR [RAX] +0x48 0x0f 0xae 0x28 + +# CHECK: xsaveopt64 OPAQUE PTR [RAX] +0x48 0x0f 0xae 0x30 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index 5de1d5978433c..c285af72b358e 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -112,3 +112,18 @@ # CHECK: xabort $13 0xc6 0xf8 0x0d + +# CHECK: xsaveq (%rax) +0x48 0x0f 0xae 0x20 + +# CHECK: xrstorq (%rax) +0x48 0x0f 0xae 0x28 + +# CHECK: xsaveoptq (%rax) +0x48 0x0f 0xae 0x30 + +# CHECK: clac +0x0f 0x01 0xca + +# CHECK: stac +0x0f 0x01 0xcb diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index 99e54e9857c56..116433051a5af 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # 0r instructions @@ -649,12 +648,24 @@ # CHECK: ldap r11, 53112 0x33 0xf0 0x78 0xdb +# CHECK: ldap r11, -22 +0x16 0xdc + +# CHECK: ldap r11, -9999 +0x09 0xf0 0x0f 0xdf + # CHECK: bl 8 0x08 0xd0 # CHECK: bl 38631 0x25 0xf0 0xe7 0xd2 +# CHECK: bl -222 +0xde 0xd4 + +# CHECK: bl -55132 +0x35 0xf0 0x5c 0xd7 + # CHECK: bla cp[500] 0xf4 0xe1 |