diff options
Diffstat (limited to 'test')
73 files changed, 13688 insertions, 609 deletions
diff --git a/test/CodeGen/AArch64/reg-scavenge-frame.mir b/test/CodeGen/AArch64/reg-scavenge-frame.mir new file mode 100644 index 0000000000000..3300bb1e58310 --- /dev/null +++ b/test/CodeGen/AArch64/reg-scavenge-frame.mir @@ -0,0 +1,52 @@ +# RUN: llc -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-linux-gnu" + define void @ScavengeForFrameWithoutOffset() { ret void } +... +--- +name: ScavengeForFrameWithoutOffset +tracksRegLiveness: true +stack: + - { id: 0, type: spill-slot, offset: 0, size: 32, alignment: 8 } +body: | + bb.0: + liveins: %d16_d17_d18_d19 + %x0 = COPY %xzr + %x1 = COPY %xzr + %x2 = COPY %xzr + %x3 = COPY %xzr + %x4 = COPY %xzr + %x5 = COPY %xzr + %x6 = COPY %xzr + %x7 = COPY %xzr + %x8 = COPY %xzr + %x9 = COPY %xzr + %x10 = COPY %xzr + %x11 = COPY %xzr + %x12 = COPY %xzr + %x13 = COPY %xzr + %x14 = COPY %xzr + %x15 = COPY %xzr + %x16 = COPY %xzr + %x17 = COPY %xzr + %x18 = COPY %xzr + %x19 = COPY %xzr + %x20 = COPY %xzr + %x21 = COPY %xzr + %x22 = COPY %xzr + %x23 = COPY %xzr + %x24 = COPY %xzr + %x25 = COPY %xzr + %x26 = COPY %xzr + %x27 = COPY %xzr + %x28 = COPY %xzr + %fp = COPY %xzr + %lr = COPY %xzr + ST1Fourv1d killed %d16_d17_d18_d19, %stack.0 :: (store 32 into %stack.0, align 8) +# CHECK: STRXui killed %[[SCAVREG:x[0-9]+|fp|lr]], %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1) +# CHECK-NEXT: %[[SCAVREG]] = ADDXri %sp, {{[0-9]+}}, 0 +# CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed %[[SCAVREG]] :: (store 32 into %stack.0, align 8) +# CHECK-NEXT: %[[SCAVREG]] = LDRXui %sp, [[SPOFFSET]] :: (load 8 from %stack.1) +... diff --git a/test/CodeGen/AMDGPU/add.v2i16.ll b/test/CodeGen/AMDGPU/add.v2i16.ll index a6b280578531a..e5e2d436deb03 100644 --- a/test/CodeGen/AMDGPU/add.v2i16.ll +++ b/test/CodeGen/AMDGPU/add.v2i16.ll @@ -23,7 +23,7 @@ define amdgpu_kernel void @v_test_add_v2i16(<2 x i16> addrspace(1)* %out, <2 x i ; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]] -; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VVAL1]], [[VAL0]] +; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]] ; VI: s_add_i32 ; VI: s_add_i32 @@ -50,7 +50,7 @@ define amdgpu_kernel void @s_test_add_self_v2i16(<2 x i16> addrspace(1)* %out, < ; FIXME: VI should not scalarize arg access. ; GCN-LABEL: {{^}}s_test_add_v2i16_kernarg: -; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} +; GFX9: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} ; VI: v_add_i32 ; VI: v_add_i32_sdwa @@ -62,10 +62,11 @@ define amdgpu_kernel void @s_test_add_v2i16_kernarg(<2 x i16> addrspace(1)* %out ; GCN-LABEL: {{^}}v_test_add_v2i16_constant: ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0x1c8007b{{$}} -; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[CONST]], v{{[0-9]+}} +; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0x7b, v{{[0-9]+}} -; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0x1c8, v{{[0-9]+}} +; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], 0x1c8 +; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, v[[SCONST]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD define amdgpu_kernel void @v_test_add_v2i16_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid @@ -79,10 +80,11 @@ define amdgpu_kernel void @v_test_add_v2i16_constant(<2 x i16> addrspace(1)* %ou ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_add_v2i16_neg_constant: ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0xfc21fcb3{{$}} -; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[CONST]], v{{[0-9]+}} +; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0xfffffcb3, v{{[0-9]+}} -; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0xfffffc21, v{{[0-9]+}} +; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], 0xfffffc21 +; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, v[[SCONST]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD define amdgpu_kernel void @v_test_add_v2i16_neg_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid @@ -96,11 +98,11 @@ define amdgpu_kernel void @v_test_add_v2i16_neg_constant(<2 x i16> addrspace(1)* ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_neg1: ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, -1{{$}} +; VI: v_mov_b32_e32 v[[SCONST:[0-9]+]], -1 ; VI: flat_load_ushort [[LOAD0:v[0-9]+]] ; VI: flat_load_ushort [[LOAD1:v[0-9]+]] -; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, -1, [[LOAD0]] +; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, v[[SCONST]], [[LOAD0]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, -1, [[LOAD1]] -; VI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_or_b32_e32 define amdgpu_kernel void @v_test_add_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -114,7 +116,7 @@ define amdgpu_kernel void @v_test_add_v2i16_inline_neg1(<2 x i16> addrspace(1)* ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_lo_zero_hi: ; GFX9: s_mov_b32 [[K:s[0-9]+]], 32{{$}} -; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[K]], v{{[0-9]+}}{{$}} +; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]{{$}} ; VI-NOT: v_add_u16 ; VI: v_add_u16_e32 v{{[0-9]+}}, 32, v{{[0-9]+}} @@ -134,12 +136,12 @@ define amdgpu_kernel void @v_test_add_v2i16_inline_lo_zero_hi(<2 x i16> addrspac ; The high element gives fp ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_fp_split: ; GFX9: s_mov_b32 [[K:s[0-9]+]], 1.0 -; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[K]], v{{[0-9]+}}{{$}} +; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]{{$}} ; VI-NOT: v_add_u16 -; VI: v_add_u16_e32 v{{[0-9]+}}, 0x3f80, v{{[0-9]+}} +; VI: v_mov_b32_e32 v[[K:[0-9]+]], 0x3f80 +; VI: v_add_u16_sdwa v{{[0-9]+}}, v[[K]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NOT: v_add_u16 -; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_or_b32_e32 define amdgpu_kernel void @v_test_add_v2i16_inline_fp_split(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -191,19 +193,17 @@ define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i32(<2 x i32> addrspace(1) ; GFX9: flat_load_dword [[A:v[0-9]+]] ; GFX9: flat_load_dword [[B:v[0-9]+]] -; GFX9: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] ; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] ; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] ; GFX9: buffer_store_dwordx4 +; VI-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; VI: flat_load_ushort v[[A_LO:[0-9]+]] ; VI: flat_load_ushort v[[A_HI:[0-9]+]] ; VI: flat_load_ushort v[[B_LO:[0-9]+]] ; VI: flat_load_ushort v[[B_HI:[0-9]+]] -; VI-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} -; VI-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; VI-DAG: v_add_u16_e32 ; VI-DAG: v_add_u16_e32 diff --git a/test/CodeGen/AMDGPU/bfe-combine.ll b/test/CodeGen/AMDGPU/bfe-combine.ll index 791b49f0e143a..6035e3bf4a5fe 100644 --- a/test/CodeGen/AMDGPU/bfe-combine.ll +++ b/test/CodeGen/AMDGPU/bfe-combine.ll @@ -1,12 +1,16 @@ -; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s +; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s +; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s ; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=GCN --check-prefix=CI %s ; GCN-LABEL: {{^}}bfe_combine8: ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8 ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], 2, v[[BFE]] +; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2 +; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 ; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 6, v{{[0-9]+}} ; CI: v_and_b32_e32 v[[ADDRLO:[0-9]+]], 0x3fc, v[[SHR]] ; VI: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] +; VI-SDWA: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] ; GCN: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: define amdgpu_kernel void @bfe_combine8(i32 addrspace(1)* nocapture %arg, i32 %x) { %id = tail call i32 @llvm.amdgcn.workitem.id.x() #2 @@ -22,6 +26,10 @@ define amdgpu_kernel void @bfe_combine8(i32 addrspace(1)* nocapture %arg, i32 %x ; GCN-LABEL: {{^}}bfe_combine16: ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 16, 16 ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], {{[^,]+}}, v[[BFE]] +; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 15 +; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE1:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI-SDWA: v_lshlrev_b64 v{{\[}}[[ADDRBASE:[0-9]+]]:{{[^\]+}}], 2, v{{\[}}[[ADDRBASE1]]:{{[^\]+}}] +; VI-SDWA: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] ; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 1, v{{[0-9]+}} ; CI: v_and_b32_e32 v[[AND:[0-9]+]], 0x7fff8000, v[[SHR]] ; CI: v_lshl_b64 v{{\[}}[[ADDRLO:[0-9]+]]:{{[^\]+}}], v{{\[}}[[AND]]:{{[^\]+}}], 2 diff --git a/test/CodeGen/AMDGPU/commute-compares.ll b/test/CodeGen/AMDGPU/commute-compares.ll index 973c4544d97a7..66148a43a2717 100644 --- a/test/CodeGen/AMDGPU/commute-compares.ll +++ b/test/CodeGen/AMDGPU/commute-compares.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -amdgpu-sdwa-peephole=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s declare i32 @llvm.amdgcn.workitem.id.x() #0 diff --git a/test/CodeGen/AMDGPU/commute_modifiers.ll b/test/CodeGen/AMDGPU/commute_modifiers.ll index 8820e4fd80e56..f38c1f8aa6edb 100644 --- a/test/CodeGen/AMDGPU/commute_modifiers.ll +++ b/test/CodeGen/AMDGPU/commute_modifiers.ll @@ -51,7 +51,7 @@ define amdgpu_kernel void @commute_mul_imm_fneg_f32(float addrspace(1)* %out, fl ; FUNC-LABEL: @commute_add_lit_fabs_f32 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: v_mov_b32_e32 [[K:v[0-9]+]], 0x44800000 -; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[K]], |[[X]]| +; SI: v_add_f32_e64 [[REG:v[0-9]+]], |[[X]]|, [[K]] ; SI: buffer_store_dword [[REG]] define amdgpu_kernel void @commute_add_lit_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 diff --git a/test/CodeGen/AMDGPU/copy-illegal-type.ll b/test/CodeGen/AMDGPU/copy-illegal-type.ll index 026dd7ca6c870..d772d1b679369 100644 --- a/test/CodeGen/AMDGPU/copy-illegal-type.ll +++ b/test/CodeGen/AMDGPU/copy-illegal-type.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone diff --git a/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll index e16daa6fad9d0..0328ce31002df 100644 --- a/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll +++ b/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll @@ -94,7 +94,6 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1) ; GCN-DAG: v_cvt_f32_ubyte3_e32 ; GCN-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 24 -; GCN-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16 ; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16 ; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 8 diff --git a/test/CodeGen/AMDGPU/fabs.f64.ll b/test/CodeGen/AMDGPU/fabs.f64.ll index 998e02f7bdf84..718176b80f0fb 100644 --- a/test/CodeGen/AMDGPU/fabs.f64.ll +++ b/test/CodeGen/AMDGPU/fabs.f64.ll @@ -55,7 +55,7 @@ define amdgpu_kernel void @fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x doub ; SI-LABEL: {{^}}fabs_fold_f64: ; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; SI-NOT: and -; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]| +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}} ; SI: s_endpgm define amdgpu_kernel void @fabs_fold_f64(double addrspace(1)* %out, double %in0, double %in1) { %fabs = call double @llvm.fabs.f64(double %in0) @@ -67,7 +67,7 @@ define amdgpu_kernel void @fabs_fold_f64(double addrspace(1)* %out, double %in0, ; SI-LABEL: {{^}}fabs_fn_fold_f64: ; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; SI-NOT: and -; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]| +; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}} ; SI: s_endpgm define amdgpu_kernel void @fabs_fn_fold_f64(double addrspace(1)* %out, double %in0, double %in1) { %fabs = call double @fabs(double %in0) diff --git a/test/CodeGen/AMDGPU/fabs.ll b/test/CodeGen/AMDGPU/fabs.ll index ac8fa3e45ef51..600c6cd8230eb 100644 --- a/test/CodeGen/AMDGPU/fabs.ll +++ b/test/CodeGen/AMDGPU/fabs.ll @@ -75,7 +75,7 @@ define amdgpu_kernel void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float ; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c ; GCN-NOT: and -; GCN: v_mul_f32_e64 v{{[0-9]+}}, v{{[0-9]+}}, |[[ABS_VALUE]]| +; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}} define amdgpu_kernel void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) { %fabs = call float @fabs(float %in0) %fmul = fmul float %fabs, %in1 @@ -87,7 +87,7 @@ define amdgpu_kernel void @fabs_fn_fold(float addrspace(1)* %out, float %in0, fl ; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c ; GCN-NOT: and -; GCN: v_mul_f32_e64 v{{[0-9]+}}, v{{[0-9]+}}, |[[ABS_VALUE]]| +; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}} define amdgpu_kernel void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) { %fabs = call float @llvm.fabs.f32(float %in0) %fmul = fmul float %fabs, %in1 diff --git a/test/CodeGen/AMDGPU/fadd.f16.ll b/test/CodeGen/AMDGPU/fadd.f16.ll index f76ecf58d9052..9b3d2a475a14c 100644 --- a/test/CodeGen/AMDGPU/fadd.f16.ll +++ b/test/CodeGen/AMDGPU/fadd.f16.ll @@ -96,9 +96,9 @@ entry: } ; GCN-LABEL: {{^}}fadd_v2f16_imm_a: -; GCN: buffer_load_dword v[[B_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[B_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] -; GCN: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] +; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] ; SI: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 1.0, v[[B_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] @@ -107,9 +107,9 @@ entry: ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] -; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[B_F16_1]] +; VI-DAG: v_mov_b32_e32 v[[CONST2:[0-9]+]], 0x4000 +; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[CONST2]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]] -; VI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GCN: buffer_store_dword v[[R_V2_F16]] @@ -125,9 +125,9 @@ entry: } ; GCN-LABEL: {{^}}fadd_v2f16_imm_b: -; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] -; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] +; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_add_f32_e32 v[[R_F32_0:[0-9]+]], 2.0, v[[A_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] @@ -136,10 +136,10 @@ entry: ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] -; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[A_F16_1]] +; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00 +; VI-DAG: v_add_f16_sdwa v[[R_F16_0:[0-9]+]], v[[CONST1]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[A_V2_F16]] -; VI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]] -; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_1]] +; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] ; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: s_endpgm diff --git a/test/CodeGen/AMDGPU/fadd64.ll b/test/CodeGen/AMDGPU/fadd64.ll index 7eb7747de215c..c936d98673ba1 100644 --- a/test/CodeGen/AMDGPU/fadd64.ll +++ b/test/CodeGen/AMDGPU/fadd64.ll @@ -13,7 +13,7 @@ define amdgpu_kernel void @v_fadd_f64(double addrspace(1)* %out, double addrspac } ; CHECK-LABEL: {{^}}s_fadd_f64: -; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} define amdgpu_kernel void @s_fadd_f64(double addrspace(1)* %out, double %r0, double %r1) { %r2 = fadd double %r0, %r1 store double %r2, double addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/fcanonicalize.f16.ll b/test/CodeGen/AMDGPU/fcanonicalize.f16.ll index c9787bb478ef2..9e8ddd39bbafb 100644 --- a/test/CodeGen/AMDGPU/fcanonicalize.f16.ll +++ b/test/CodeGen/AMDGPU/fcanonicalize.f16.ll @@ -205,9 +205,9 @@ define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f16(half addrspace } ; GCN-LABEL: {{^}}v_test_canonicalize_var_v2f16: -; VI: v_mul_f16_e32 [[REG0:v[0-9]+]], 1.0, {{v[0-9]+}} +; VI: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00 +; VI-DAG: v_mul_f16_sdwa [[REG0:v[0-9]+]], v[[CONST1]], {{v[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mul_f16_e32 [[REG1:v[0-9]+]], 1.0, {{v[0-9]+}} -; VI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI-NOT: v_and_b32 ; GFX9: v_pk_mul_f16 [[REG:v[0-9]+]], 1.0, {{v[0-9]+$}} @@ -223,7 +223,8 @@ define amdgpu_kernel void @v_test_canonicalize_var_v2f16(<2 x half> addrspace(1) ; GCN-LABEL: {{^}}v_test_canonicalize_fabs_var_v2f16: ; VI-DAG: v_bfe_u32 ; VI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0x7fff7fff, v{{[0-9]+}} -; VI: v_mul_f16_e32 [[REG0:v[0-9]+]], 1.0, v{{[0-9]+}} +; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00 +; VI: v_mul_f16_sdwa [[REG0:v[0-9]+]], v[[CONST1]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_mul_f16_e32 [[REG1:v[0-9]+]], 1.0, v{{[0-9]+}} ; VI-NOT: 0xffff ; VI: v_or_b32 @@ -240,9 +241,10 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_v2f16(<2 x half> addrspa } ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_fabs_var_v2f16: -; VI: v_or_b32_e32 v{{[0-9]+}}, 0x80008000, v{{[0-9]+}} -; VI: v_mul_f16_e32 [[REG0:v[0-9]+]], 1.0, v{{[0-9]+}} -; VI: v_mul_f16_e32 [[REG1:v[0-9]+]], 1.0, v{{[0-9]+}} +; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00 +; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, 0x80008000, v{{[0-9]+}} +; VI-DAG: v_mul_f16_sdwa [[REG0:v[0-9]+]], v[[CONST1]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI-DAG: v_mul_f16_e32 [[REG1:v[0-9]+]], 1.0, v{{[0-9]+}} ; VI: v_or_b32 ; GFX9: v_and_b32_e32 [[ABS:v[0-9]+]], 0x7fff7fff, v{{[0-9]+}} @@ -259,11 +261,10 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_v2f16(<2 x half> ad ; FIXME: Fold modifier ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_var_v2f16: -; VI: v_xor_b32_e32 [[FNEG:v[0-9]+]], 0x80008000, v{{[0-9]+}} -; VI-DAG: v_lshrrev_b32_e32 [[FNEG_HI:v[0-9]+]], 16, [[FNEG]] -; VI-DAG: v_mul_f16_e32 [[REG1:v[0-9]+]], 1.0, [[FNEG_HI]] +; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00 +; VI-DAG: v_xor_b32_e32 [[FNEG:v[0-9]+]], 0x80008000, v{{[0-9]+}} +; VI-DAG: v_mul_f16_sdwa [[REG1:v[0-9]+]], v[[CONST1]], [[FNEG]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mul_f16_e32 [[REG0:v[0-9]+]], 1.0, [[FNEG]] -; VI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI-NOT: 0xffff ; GFX9: v_pk_mul_f16 [[REG:v[0-9]+]], 1.0, {{v[0-9]+}} neg_lo:[0,1] neg_hi:[0,1]{{$}} diff --git a/test/CodeGen/AMDGPU/fmul.f16.ll b/test/CodeGen/AMDGPU/fmul.f16.ll index 4e96091ae2563..4ef2aa693cf49 100644 --- a/test/CodeGen/AMDGPU/fmul.f16.ll +++ b/test/CodeGen/AMDGPU/fmul.f16.ll @@ -96,17 +96,18 @@ entry: } ; GCN-LABEL: {{^}}fmul_v2f16_imm_a: -; GCN: buffer_load_dword v[[B_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[B_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] -; GCN: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] +; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] ; SI: v_mul_f32_e32 v[[R_F32_0:[0-9]+]], 0x40400000, v[[B_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 4.0, v[[B_F32_1]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI-DAG: v_mul_f16_e32 v[[R_F16_1:[0-9]+]], 4.0, v[[B_F16_1]] +; VI-DAG: v_mov_b32_e32 v[[CONST4:[0-9]+]], 0x4400 +; VI-DAG: v_mul_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[CONST4]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mul_f16_e32 v[[R_F16_0:[0-9]+]], 0x4200, v[[B_V2_F16]] -; GCN-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] +; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: s_endpgm @@ -121,17 +122,18 @@ entry: } ; GCN-LABEL: {{^}}fmul_v2f16_imm_b: -; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] -; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] +; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_mul_f32_e32 v[[R_F32_0:[0-9]+]], 4.0, v[[A_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x40400000, v[[A_F32_1]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI-DAG: v_mul_f16_e32 v[[R_F16_1:[0-9]+]], 0x4200, v[[A_F16_1]] +; VI-DAG: v_mov_b32_e32 v[[CONST3:[0-9]+]], 0x4200 +; VI-DAG: v_mul_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[CONST3]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mul_f16_e32 v[[R_F16_0:[0-9]+]], 4.0, v[[A_V2_F16]] -; GCN-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] +; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: s_endpgm diff --git a/test/CodeGen/AMDGPU/fneg-fabs.f16.ll b/test/CodeGen/AMDGPU/fneg-fabs.f16.ll index 506b2a02f8281..c256159726bf7 100644 --- a/test/CodeGen/AMDGPU/fneg-fabs.f16.ll +++ b/test/CodeGen/AMDGPU/fneg-fabs.f16.ll @@ -71,7 +71,9 @@ define amdgpu_kernel void @v_fneg_fabs_f16(half addrspace(1)* %out, half addrspa ; FIXME: single bit op ; GCN-LABEL: {{^}}s_fneg_fabs_v2f16: ; CIVI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}} -; CIVI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; VI: v_mov_b32_e32 [[VMASK:v[0-9]+]], [[MASK]] +; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; VI: v_or_b32_sdwa v{{[0-9]+}}, [[VMASK]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; CIVI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], ; CIVI: flat_store_dword @@ -85,10 +87,15 @@ define amdgpu_kernel void @s_fneg_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x ; GCN-LABEL: {{^}}fneg_fabs_v4f16: ; CIVI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}} -; CIVI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], -; CIVI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], -; CIVI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], -; CIVI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; CI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; VI: v_mov_b32_e32 [[VMASK:v[0-9]+]], [[MASK]] +; VI: v_or_b32_sdwa v{{[0-9]+}}, [[VMASK]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], +; VI: v_or_b32_sdwa v{{[0-9]+}}, [[VMASK]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], ; GFX9: s_mov_b32 [[MASK:s[0-9]+]], 0x80008000 ; GFX9: s_or_b32 s{{[0-9]+}}, [[MASK]], s{{[0-9]+}} diff --git a/test/CodeGen/AMDGPU/fneg-fabs.f64.ll b/test/CodeGen/AMDGPU/fneg-fabs.f64.ll index 85f544032171c..bc0e59980186f 100644 --- a/test/CodeGen/AMDGPU/fneg-fabs.f64.ll +++ b/test/CodeGen/AMDGPU/fneg-fabs.f64.ll @@ -5,7 +5,7 @@ ; into 2 modifiers, although theoretically that should work. ; GCN-LABEL: {{^}}fneg_fabs_fadd_f64: -; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|, {{s\[[0-9]+:[0-9]+\]}} +; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}| define amdgpu_kernel void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) { %fabs = call double @llvm.fabs.f64(double %x) %fsub = fsub double -0.000000e+00, %fabs @@ -25,7 +25,7 @@ define amdgpu_kernel void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, doubl } ; GCN-LABEL: {{^}}fneg_fabs_fmul_f64: -; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}|, {{s\[[0-9]+:[0-9]+\]}} +; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}| define amdgpu_kernel void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) { %fabs = call double @llvm.fabs.f64(double %x) %fsub = fsub double -0.000000e+00, %fabs diff --git a/test/CodeGen/AMDGPU/fneg-fabs.ll b/test/CodeGen/AMDGPU/fneg-fabs.ll index a0cf37b159dbb..0a7346f410c94 100644 --- a/test/CodeGen/AMDGPU/fneg-fabs.ll +++ b/test/CodeGen/AMDGPU/fneg-fabs.ll @@ -4,7 +4,7 @@ ; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32: ; SI-NOT: and -; SI: v_subrev_f32_e64 {{v[0-9]+}}, |{{v[0-9]+}}|, {{s[0-9]+}} +; SI: v_sub_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}| define amdgpu_kernel void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) { %fabs = call float @llvm.fabs.f32(float %x) %fsub = fsub float -0.000000e+00, %fabs @@ -15,7 +15,7 @@ define amdgpu_kernel void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x ; FUNC-LABEL: {{^}}fneg_fabs_fmul_f32: ; SI-NOT: and -; SI: v_mul_f32_e64 {{v[0-9]+}}, -|{{v[0-9]+}}|, {{s[0-9]+}} +; SI: v_mul_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}| ; SI-NOT: and define amdgpu_kernel void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) { %fabs = call float @llvm.fabs.f32(float %x) diff --git a/test/CodeGen/AMDGPU/fneg.f16.ll b/test/CodeGen/AMDGPU/fneg.f16.ll index ed36666db807d..16e4fc680bea1 100644 --- a/test/CodeGen/AMDGPU/fneg.f16.ll +++ b/test/CodeGen/AMDGPU/fneg.f16.ll @@ -130,13 +130,15 @@ define amdgpu_kernel void @v_fneg_fold_v2f16(<2 x half> addrspace(1)* %out, <2 x } ; GCN-LABEL: {{^}}v_extract_fneg_fold_v2f16: -; GCN: flat_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: flat_load_dword [[VAL:v[0-9]+]] ; CI-DAG: v_mul_f32_e32 v{{[0-9]+}}, -4.0, v{{[0-9]+}} ; CI-DAG: v_sub_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} -; GFX89: v_lshrrev_b32_e32 [[ELT1:v[0-9]+]], 16, [[VAL]] +; GFX9: v_lshrrev_b32_e32 [[ELT1:v[0-9]+]], 16, [[VAL]] ; GFX89-DAG: v_mul_f16_e32 v{{[0-9]+}}, -4.0, [[VAL]] -; GFX89-DAG: v_sub_f16_e32 v{{[0-9]+}}, 2.0, [[ELT1]] +; GFX9-DAG: v_sub_f16_e32 v{{[0-9]+}}, 2.0, [[ELT1]] +; VI-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000 +; VI-DAG: v_sub_f16_sdwa v{{[0-9]+}}, [[CONST2]], [[VAL]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 define amdgpu_kernel void @v_extract_fneg_fold_v2f16(<2 x half> addrspace(1)* %in) #0 { %val = load <2 x half>, <2 x half> addrspace(1)* %in %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val diff --git a/test/CodeGen/AMDGPU/fract.f64.ll b/test/CodeGen/AMDGPU/fract.f64.ll index 7a5bcfffa3f3b..9a56cbe983cdd 100644 --- a/test/CodeGen/AMDGPU/fract.f64.ll +++ b/test/CodeGen/AMDGPU/fract.f64.ll @@ -12,7 +12,7 @@ declare double @llvm.floor.f64(double) #0 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] ; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 ; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff -; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] +; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]] ; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3 ; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc @@ -39,7 +39,7 @@ define amdgpu_kernel void @fract_f64(double addrspace(1)* %out, double addrspace ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] ; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 ; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff -; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] +; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]] ; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3 ; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc @@ -67,7 +67,7 @@ define amdgpu_kernel void @fract_f64_neg(double addrspace(1)* %out, double addrs ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]| ; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 ; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff -; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] +; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v{{\[}}[[UPLO]]:[[UPHI]]] ; SI-DAG: v_cmp_class_f64_e64 vcc, v{{\[}}[[LO]]:[[HI]]], 3 ; SI: v_cndmask_b32_e32 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], vcc ; SI: v_cndmask_b32_e32 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], vcc diff --git a/test/CodeGen/AMDGPU/fsub.f16.ll b/test/CodeGen/AMDGPU/fsub.f16.ll index d3c5df3177713..836b480b6a676 100644 --- a/test/CodeGen/AMDGPU/fsub.f16.ll +++ b/test/CodeGen/AMDGPU/fsub.f16.ll @@ -99,7 +99,7 @@ entry: } ; GCN-LABEL: {{^}}fsub_v2f16_imm_a: -; GCN: buffer_load_dword v[[B_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[B_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] @@ -111,14 +111,13 @@ entry: ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] -; VI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] -; VI-DAG: v_sub_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[B_F16_1]] +; VI-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000 +; VI-DAG: v_sub_f16_sdwa v[[R_F16_HI:[0-9]+]], [[CONST2]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_sub_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]] -; VI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GFX9: s_mov_b32 [[K:s[0-9]+]], 0x40003c00 -; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], [[K]], v[[B_V2_F16]] neg_lo:[0,1] neg_hi:[0,1] +; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[B_V2_F16]], [[K]] neg_lo:[1,0] neg_hi:[1,0] ; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: s_endpgm @@ -134,7 +133,7 @@ entry: } ; GCN-LABEL: {{^}}fsub_v2f16_imm_b: -; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] @@ -146,14 +145,13 @@ entry: ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] -; VI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] -; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], -1.0, v[[A_F16_1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM1:v[0-9]+]], 0xbc00 +; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], [[CONSTM1]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], -2.0, v[[A_V2_F16]] -; VI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GFX9: s_mov_b32 [[K:s[0-9]+]], 0xbc00c000 -; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], [[K]], v[[A_V2_F16]]{{$}} +; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], [[K]]{{$}} ; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: s_endpgm diff --git a/test/CodeGen/AMDGPU/fsub64.ll b/test/CodeGen/AMDGPU/fsub64.ll index 1b0879d098ee0..dc332414a1527 100644 --- a/test/CodeGen/AMDGPU/fsub64.ll +++ b/test/CodeGen/AMDGPU/fsub64.ll @@ -39,7 +39,7 @@ define amdgpu_kernel void @fsub_fabs_inv_f64(double addrspace(1)* %out, double a } ; SI-LABEL: {{^}}s_fsub_f64: -; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\]}} +; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}} define amdgpu_kernel void @s_fsub_f64(double addrspace(1)* %out, double %a, double %b) { %sub = fsub double %a, %b store double %sub, double addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/immv216.ll b/test/CodeGen/AMDGPU/immv216.ll index 96132d841997b..bc951a82becd1 100644 --- a/test/CodeGen/AMDGPU/immv216.ll +++ b/test/CodeGen/AMDGPU/immv216.ll @@ -123,7 +123,8 @@ define amdgpu_kernel void @store_literal_imm_v2f16(<2 x half> addrspace(1)* %out ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST0:v[0-9]+]], 0 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST0]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_0.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -140,7 +141,8 @@ define amdgpu_kernel void @add_inline_imm_0.0_v2f16(<2 x half> addrspace(1)* %ou ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST05:v[0-9]+]], 0x3800 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST05]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_0.5_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -157,7 +159,8 @@ define amdgpu_kernel void @add_inline_imm_0.5_v2f16(<2 x half> addrspace(1)* %ou ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -0.5, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -0.5, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM05:v[0-9]+]], 0xb800 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONSTM05]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_neg_0.5_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -174,7 +177,8 @@ define amdgpu_kernel void @add_inline_imm_neg_0.5_v2f16(<2 x half> addrspace(1)* ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1.0, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1.0, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST1:v[0-9]+]], 0x3c00 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST1]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_1.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -191,7 +195,8 @@ define amdgpu_kernel void @add_inline_imm_1.0_v2f16(<2 x half> addrspace(1)* %ou ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1.0, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1.0, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM1:v[0-9]+]], 0xbc00 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONSTM1]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_neg_1.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -208,7 +213,8 @@ define amdgpu_kernel void @add_inline_imm_neg_1.0_v2f16(<2 x half> addrspace(1)* ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2.0, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2.0, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST2]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_2.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -225,7 +231,8 @@ define amdgpu_kernel void @add_inline_imm_2.0_v2f16(<2 x half> addrspace(1)* %ou ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2.0, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2.0, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM2:v[0-9]+]], 0xc000 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONSTM2]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_neg_2.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -242,7 +249,8 @@ define amdgpu_kernel void @add_inline_imm_neg_2.0_v2f16(<2 x half> addrspace(1)* ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 4.0, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 4.0, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST4:v[0-9]+]], 0x4400 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST4]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_4.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -259,7 +267,8 @@ define amdgpu_kernel void @add_inline_imm_4.0_v2f16(<2 x half> addrspace(1)* %ou ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -4.0, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -4.0, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM4:v[0-9]+]], 0xc400 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONSTM4]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_neg_4.0_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -273,10 +282,10 @@ define amdgpu_kernel void @add_inline_imm_neg_4.0_v2f16(<2 x half> addrspace(1)* ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5 ; GFX9: buffer_store_dword [[REG]] +; VI: v_mov_b32_e32 [[CONST05:v[0-9]+]], 0x3800 ; VI: buffer_load_dword ; VI-NOT: and -; VI: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, v{{[0-9]+}} +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST05]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, v{{[0-9]+}} ; VI: v_or_b32 ; VI: buffer_store_dword @@ -290,7 +299,7 @@ define amdgpu_kernel void @commute_add_inline_imm_0.5_v2f16(<2 x half> addrspace ; GCN-LABEL: {{^}}commute_add_literal_v2f16: ; GFX9-DAG: buffer_load_dword [[VAL:v[0-9]+]] ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x6400{{$}} -; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[K]], [[VAL]] op_sel_hi:[0,1]{{$}} +; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], [[K]] op_sel_hi:[1,0]{{$}} ; GFX9: buffer_store_dword [[REG]] ; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x6400{{$}} @@ -315,7 +324,8 @@ define amdgpu_kernel void @commute_add_literal_v2f16(<2 x half> addrspace(1)* %o ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 1, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST1:v[0-9]+]], 1 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST1]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_1_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -332,7 +342,8 @@ define amdgpu_kernel void @add_inline_imm_1_v2f16(<2 x half> addrspace(1)* %out, ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 2, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 2 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST2]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_2_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -349,7 +360,8 @@ define amdgpu_kernel void @add_inline_imm_2_v2f16(<2 x half> addrspace(1)* %out, ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 16, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 16, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST16:v[0-9]+]], 16 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST16]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_16_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -366,7 +378,8 @@ define amdgpu_kernel void @add_inline_imm_16_v2f16(<2 x half> addrspace(1)* %out ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -1, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM1:v[0-9]+]], 0xffff +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONSTM1]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_neg_1_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -383,7 +396,8 @@ define amdgpu_kernel void @add_inline_imm_neg_1_v2f16(<2 x half> addrspace(1)* % ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -2, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM2:v[0-9]+]], 0xfffe +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONSTM2]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_neg_2_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -400,7 +414,8 @@ define amdgpu_kernel void @add_inline_imm_neg_2_v2f16(<2 x half> addrspace(1)* % ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -16, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, -16, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONSTM16:v[0-9]+]], 0xfff0 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONSTM16]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_neg_16_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -417,7 +432,8 @@ define amdgpu_kernel void @add_inline_imm_neg_16_v2f16(<2 x half> addrspace(1)* ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 63, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 63, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST63:v[0-9]+]], 63 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST63]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_63_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { @@ -434,7 +450,8 @@ define amdgpu_kernel void @add_inline_imm_63_v2f16(<2 x half> addrspace(1)* %out ; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 64, [[VAL0]] -; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 64, [[VAL1]] +; VI-DAG: v_mov_b32_e32 [[CONST64:v[0-9]+]], 64 +; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[CONST64]], [[VAL1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI: v_or_b32 ; VI: buffer_store_dword define amdgpu_kernel void @add_inline_imm_64_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %x) #0 { diff --git a/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll index 89adcff1a2787..350dd38ef5838 100644 --- a/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll +++ b/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll @@ -258,8 +258,10 @@ define amdgpu_kernel void @v_insertelement_v2i16_0_inlineimm(<2 x i16> addrspace ; FIXME: fold lshl_or c0, c1, v0 -> or (c0 << c1), v0 ; GCN-LABEL: {{^}}v_insertelement_v2i16_1: +; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e70000 ; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] -; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 0x3e70000, [[VEC]] +; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x3e70000, [[VEC]] +; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9-DAG: s_movk_i32 [[K:s[0-9]+]], 0x3e7 ; GFX9-DAG: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] @@ -278,9 +280,12 @@ define amdgpu_kernel void @v_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, } ; GCN-LABEL: {{^}}v_insertelement_v2i16_1_inlineimm: +; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0xfff10000 ; GCN: flat_load_dword [[VEC:v[0-9]+]] -; GCN: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] -; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 0xfff10000, [[ELT0]] +; CI: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] +; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] +; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0xfff10000, [[ELT0]] +; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], -15, 16, [[ELT0]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] define amdgpu_kernel void @v_insertelement_v2i16_1_inlineimm(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { @@ -337,8 +342,10 @@ define amdgpu_kernel void @v_insertelement_v2f16_0_inlineimm(<2 x half> addrspac } ; GCN-LABEL: {{^}}v_insertelement_v2f16_1: +; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0x45000000 ; GCN-DAG: flat_load_dword [[VEC:v[0-9]+]] -; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 0x45000000, [[VEC]] +; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x45000000, [[VEC]] +; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9-DAG: s_movk_i32 [[K:s[0-9]+]], 0x4500 ; GFX9-DAG: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] @@ -357,9 +364,12 @@ define amdgpu_kernel void @v_insertelement_v2f16_1(<2 x half> addrspace(1)* %out } ; GCN-LABEL: {{^}}v_insertelement_v2f16_1_inlineimm: +; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0x230000 ; GCN: flat_load_dword [[VEC:v[0-9]+]] -; GCN: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] -; CIVI: v_or_b32_e32 [[RES:v[0-9]+]], 0x230000, [[ELT0]] +; CI: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] +; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VEC]] +; CI: v_or_b32_e32 [[RES:v[0-9]+]], 0x230000, [[ELT0]] +; VI: v_or_b32_sdwa [[RES:v[0-9]+]], [[K]], [[VEC]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX9: v_lshl_or_b32 [[RES:v[0-9]+]], 35, 16, [[ELT0]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RES]] define amdgpu_kernel void @v_insertelement_v2f16_1_inlineimm(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { @@ -411,11 +421,12 @@ define amdgpu_kernel void @v_insertelement_v2i16_dynamic_sgpr(<2 x i16> addrspac } ; GCN-LABEL: {{^}}v_insertelement_v2i16_dynamic_vgpr: +; GFX89: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} +; CI: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 ; GCN: flat_load_dword [[IDX:v[0-9]+]] ; GCN: flat_load_dword [[VEC:v[0-9]+]] -; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 +; GFX89-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 -; GFX89-DAG: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} ; GFX89-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] ; GFX89-DAG: v_lshlrev_b32_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], [[MASKK]] @@ -438,11 +449,12 @@ define amdgpu_kernel void @v_insertelement_v2i16_dynamic_vgpr(<2 x i16> addrspac } ; GCN-LABEL: {{^}}v_insertelement_v2f16_dynamic_vgpr: +; GFX89: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} +; CI: v_mov_b32_e32 [[K:v[0-9]+]], 0x1234 ; GCN: flat_load_dword [[IDX:v[0-9]+]] ; GCN: flat_load_dword [[VEC:v[0-9]+]] -; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1234 +; GFX89-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1234 -; GFX89-DAG: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} ; GFX89-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] ; GFX89-DAG: v_lshlrev_b32_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], [[MASKK]] diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll index e04d9e662cea3..3bb5e21d67ac0 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll @@ -27,7 +27,7 @@ entry: ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] ; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x4200{{$}} -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[B_F16]], v[[A_F16]], v[[C_F16]] +; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_a( @@ -46,7 +46,7 @@ entry: ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[C_F16:[0-9]+]] ; VI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x4200{{$}} -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[B_F16]], v[[A_F16]], v[[C_F16]] +; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_b( @@ -65,7 +65,7 @@ entry: ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] ; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x4200{{$}} -; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[B_F16]], v[[A_F16]], v[[C_F16]] +; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm define amdgpu_kernel void @div_fixup_f16_imm_c( diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll index a86468b07a272..2cc63ae74bf10 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll @@ -17,7 +17,7 @@ declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind re ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] ; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] -; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]] +; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]] ; GCN: buffer_store_dword [[RESULT]], ; GCN: s_endpgm define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll index c9993ee88369c..737be5d004478 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll @@ -14,7 +14,7 @@ define amdgpu_kernel void @v_fcmp_f32_dynamic_cc(i64 addrspace(1)* %out, float % } ; GCN-LABEL: {{^}}v_fcmp_f32_oeq_with_fabs: -; GCN: v_cmp_eq_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, |{{v[0-9]+}}|, {{s[0-9]+}} +; GCN: v_cmp_eq_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}}, |{{v[0-9]+}}| define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(i64 addrspace(1)* %out, float %src, float %a) { %temp = call float @llvm.fabs.f32(float %a) %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float %temp, i32 1) @@ -23,7 +23,7 @@ define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(i64 addrspace(1)* %out, floa } ; GCN-LABEL: {{^}}v_fcmp_f32_oeq_both_operands_with_fabs: -; GCN: v_cmp_eq_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, |{{v[0-9]+}}|, |{{s[0-9]+}}| +; GCN: v_cmp_eq_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, |{{s[0-9]+}}|, |{{v[0-9]+}}| define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(i64 addrspace(1)* %out, float %src, float %a) { %temp = call float @llvm.fabs.f32(float %a) %src_input = call float @llvm.fabs.f32(float %src) diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll index b47d2dbc744d4..be8462d09064a 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll @@ -27,7 +27,7 @@ define amdgpu_kernel void @test_mul_legacy_undef1_f32(float addrspace(1)* %out, } ; GCN-LABEL: {{^}}test_mul_legacy_fabs_f32: -; GCN: v_mul_legacy_f32_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, |s{{[0-9]+}}| +; GCN: v_mul_legacy_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|, |v{{[0-9]+}}| define amdgpu_kernel void @test_mul_legacy_fabs_f32(float addrspace(1)* %out, float %a, float %b) #0 { %a.fabs = call float @llvm.fabs.f32(float %a) %b.fabs = call float @llvm.fabs.f32(float %b) diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll index 1b937ab932472..ef9cda142850b 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll @@ -3,9 +3,8 @@ ; GCN-LABEL: {{^}}test_barrier: ; GFX8: buffer_store_dword -; GFX8: s_waitcnt ; GFX9: flat_store_dword -; GFX9-NOT: s_waitcnt +; GCN: s_waitcnt ; GCN: s_barrier define amdgpu_kernel void @test_barrier(i32 addrspace(1)* %out, i32 %size) #0 { entry: diff --git a/test/CodeGen/AMDGPU/llvm.fma.f16.ll b/test/CodeGen/AMDGPU/llvm.fma.f16.ll index 518fe8baaa7a1..3f4fba7d8ead0 100644 --- a/test/CodeGen/AMDGPU/llvm.fma.f16.ll +++ b/test/CodeGen/AMDGPU/llvm.fma.f16.ll @@ -39,7 +39,7 @@ define amdgpu_kernel void @fma_f16( ; SI: v_fma_f32 v[[R_F32:[0-9]+]], v[[A_F32:[0-9]]], v[[B_F32:[0-9]]], v[[C_F32:[0-9]]] ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] ; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x4200{{$}} -; VI: v_fma_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] +; VI: v_fma_f16 v[[R_F16:[0-9]+]], v[[B_F16]], v[[A_F16]], v[[C_F16]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm define amdgpu_kernel void @fma_f16_imm_a( @@ -62,7 +62,7 @@ define amdgpu_kernel void @fma_f16_imm_a( ; SI: v_fma_f32 v[[R_F32:[0-9]+]], v[[A_F32:[0-9]]], v[[B_F32:[0-9]]], v[[C_F32:[0-9]]] ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] ; VI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x4200{{$}} -; VI: v_fma_f16 v[[R_F16:[0-9]+]], v[[B_F16]], v[[A_F16]], v[[C_F16]] +; VI: v_fma_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm define amdgpu_kernel void @fma_f16_imm_b( @@ -85,7 +85,7 @@ define amdgpu_kernel void @fma_f16_imm_b( ; SI: v_fma_f32 v[[R_F32:[0-9]+]], v[[A_F32:[0-9]]], v[[B_F32:[0-9]]], v[[C_F32:[0-9]]] ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] ; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x4200{{$}} -; VI: v_fma_f16 v[[R_F16:[0-9]+]], v[[B_F16]], v[[A_F16]], v[[C_F16]] +; VI: v_fma_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm define amdgpu_kernel void @fma_f16_imm_c( diff --git a/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll b/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll index f30fd1d582043..eec1873901695 100644 --- a/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll +++ b/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll @@ -50,7 +50,7 @@ define amdgpu_kernel void @fmuladd_f16( ; VI-FLUSH: buffer_store_short v[[C_F16]] ; VI-DENORM: v_mov_b32_e32 [[KA:v[0-9]+]], 0x4200 -; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], [[KA]], v[[B_F16]], v[[C_F16]] +; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[B_F16]], [[KA]], v[[C_F16]] ; VI-DENORM: buffer_store_short [[RESULT]] ; GCN: s_endpgm @@ -78,7 +78,7 @@ define amdgpu_kernel void @fmuladd_f16_imm_a( ; VI-FLUSH: buffer_store_short v[[C_F16]] ; VI-DENORM: v_mov_b32_e32 [[KA:v[0-9]+]], 0x4200 -; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], [[KA]], v[[A_F16]], v[[C_F16]] +; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[A_F16]], [[KA]], v[[C_F16]] ; VI-DENORM buffer_store_short [[RESULT]] diff --git a/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll b/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll index 4c8dff52509a2..a4353d1136e1f 100644 --- a/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll +++ b/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll @@ -101,18 +101,19 @@ entry: } ; GCN-LABEL: {{^}}maxnum_v2f16_imm_a: -; GCN: buffer_load_dword v[[B_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[B_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] -; GCN: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] +; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] ; SI: v_max_f32_e32 v[[R_F32_0:[0-9]+]], 0x40400000, v[[B_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI: v_max_f32_e32 v[[R_F32_1:[0-9]+]], 4.0, v[[B_F32_1]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI-DAG: v_max_f16_e32 v[[R_F16_1:[0-9]+]], 4.0, v[[B_F16_1]] +; VI-DAG: v_mov_b32_e32 [[CONST4:v[0-9]+]], 0x4400 +; VI-DAG: v_max_f16_sdwa v[[R_F16_HI:[0-9]+]], [[CONST4]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_max_f16_e32 v[[R_F16_0:[0-9]+]], 0x4200, v[[B_V2_F16]] -; GCN-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] +; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GCN-NOT: and ; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GCN: buffer_store_dword v[[R_V2_F16]] @@ -128,18 +129,19 @@ entry: } ; GCN-LABEL: {{^}}maxnum_v2f16_imm_b: -; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] -; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] +; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_max_f32_e32 v[[R_F32_0:[0-9]+]], 4.0, v[[A_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI: v_max_f32_e32 v[[R_F32_1:[0-9]+]], 0x40400000, v[[A_F32_1]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI-DAG: v_max_f16_e32 v[[R_F16_1:[0-9]+]], 0x4200, v[[A_F16_1]] +; VI-DAG: v_mov_b32_e32 [[CONST3:v[0-9]+]], 0x4200 +; VI-DAG: v_max_f16_sdwa v[[R_F16_HI:[0-9]+]], [[CONST3]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_max_f16_e32 v[[R_F16_0:[0-9]+]], 4.0, v[[A_V2_F16]] -; GCN-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] +; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GCN-NOT: and ; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GCN: buffer_store_dword v[[R_V2_F16]] diff --git a/test/CodeGen/AMDGPU/llvm.minnum.f16.ll b/test/CodeGen/AMDGPU/llvm.minnum.f16.ll index b8221356b6641..4875d26fc860f 100644 --- a/test/CodeGen/AMDGPU/llvm.minnum.f16.ll +++ b/test/CodeGen/AMDGPU/llvm.minnum.f16.ll @@ -100,7 +100,7 @@ entry: } ; GCN-LABEL: {{^}}minnum_v2f16_imm_a: -; GCN: buffer_load_dword v[[B_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[B_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] @@ -110,11 +110,11 @@ entry: ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] -; VI-DAG: v_min_f16_e32 v[[R_F16_1:[0-9]+]], 4.0, v[[B_F16_1]] +; VI-DAG: v_mov_b32_e32 [[CONST4:v[0-9]+]], 0x4400 +; VI-DAG: v_min_f16_sdwa v[[R_F16_HI:[0-9]+]], [[CONST4]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_min_f16_e32 v[[R_F16_0:[0-9]+]], 0x4200, v[[B_V2_F16]] -; GCN-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] +; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GCN-NOT: and ; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GCN: buffer_store_dword v[[R_V2_F16]] @@ -130,18 +130,19 @@ entry: } ; GCN-LABEL: {{^}}minnum_v2f16_imm_b: -; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] +; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] -; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] +; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_min_f32_e32 v[[R_F32_0:[0-9]+]], 4.0, v[[A_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI: v_min_f32_e32 v[[R_F32_1:[0-9]+]], 0x40400000, v[[A_F32_1]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI-DAG: v_min_f16_e32 v[[R_F16_1:[0-9]+]], 0x4200, v[[A_F16_1]] +; VI-DAG: v_mov_b32_e32 [[CONST3:v[0-9]+]], 0x4200 +; VI-DAG: v_min_f16_sdwa v[[R_F16_HI:[0-9]+]], [[CONST3]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_min_f16_e32 v[[R_F16_0:[0-9]+]], 4.0, v[[A_V2_F16]] -; GCN-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] +; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; GCN-NOT: and ; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] ; GCN: buffer_store_dword v[[R_V2_F16]] diff --git a/test/CodeGen/AMDGPU/mad24-get-global-id.ll b/test/CodeGen/AMDGPU/mad24-get-global-id.ll index 1e78c4ebcc9f1..176d1d25f1962 100644 --- a/test/CodeGen/AMDGPU/mad24-get-global-id.ll +++ b/test/CodeGen/AMDGPU/mad24-get-global-id.ll @@ -10,7 +10,7 @@ declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 ; GCN-LABEL: {{^}}get_global_id_0: ; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff ; GCN: v_mov_b32_e32 [[VWGSIZEX:v[0-9]+]], [[WGSIZEX]] -; GCN: v_mad_u32_u24 v{{[0-9]+}}, [[VWGSIZEX]], s8, v0 +; GCN: v_mad_u32_u24 v{{[0-9]+}}, s8, [[VWGSIZEX]], v0 define amdgpu_kernel void @get_global_id_0(i32 addrspace(1)* %out) #1 { %dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %cast.dispatch.ptr = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* diff --git a/test/CodeGen/AMDGPU/madak.ll b/test/CodeGen/AMDGPU/madak.ll index 5f1fb0e2d7324..8e0014911def8 100644 --- a/test/CodeGen/AMDGPU/madak.ll +++ b/test/CodeGen/AMDGPU/madak.ll @@ -151,7 +151,7 @@ define amdgpu_kernel void @s_s_madak_f32(float addrspace(1)* %out, float %a, flo ; GCN-LABEL: {{^}}no_madak_src0_modifier_f32: ; GCN: buffer_load_dword [[VA:v[0-9]+]] ; GCN: buffer_load_dword [[VB:v[0-9]+]] -; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|, {{[sv][0-9]+}} +; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}} ; GCN: s_endpgm define amdgpu_kernel void @no_madak_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone @@ -173,7 +173,7 @@ define amdgpu_kernel void @no_madak_src0_modifier_f32(float addrspace(1)* noalia ; GCN-LABEL: {{^}}no_madak_src1_modifier_f32: ; GCN: buffer_load_dword [[VA:v[0-9]+]] ; GCN: buffer_load_dword [[VB:v[0-9]+]] -; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}} +; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|, {{[sv][0-9]+}} ; GCN: s_endpgm define amdgpu_kernel void @no_madak_src1_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/test/CodeGen/AMDGPU/madmk.ll b/test/CodeGen/AMDGPU/madmk.ll index 6e70e95383c97..6bc40e82459bb 100644 --- a/test/CodeGen/AMDGPU/madmk.ll +++ b/test/CodeGen/AMDGPU/madmk.ll @@ -129,7 +129,7 @@ define amdgpu_kernel void @scalar_vector_madmk_f32(float addrspace(1)* noalias % ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 -; GCN: v_mad_f32 {{v[0-9]+}}, [[VK]], |[[VA]]|, [[VB]] +; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[VK]], [[VB]] define amdgpu_kernel void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid @@ -171,7 +171,7 @@ define amdgpu_kernel void @no_madmk_src2_modifier_f32(float addrspace(1)* noalia ; GCN-LABEL: {{^}}madmk_add_inline_imm_f32: ; GCN: buffer_load_dword [[A:v[0-9]+]] ; GCN: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 -; GCN: v_mad_f32 {{v[0-9]+}}, [[VK]], [[A]], 2.0 +; GCN: v_mad_f32 {{v[0-9]+}}, [[A]], [[VK]], 2.0 define amdgpu_kernel void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/AMDGPU/mul.ll b/test/CodeGen/AMDGPU/mul.ll index a72a6efb07119..57c50c9804e56 100644 --- a/test/CodeGen/AMDGPU/mul.ll +++ b/test/CodeGen/AMDGPU/mul.ll @@ -211,10 +211,10 @@ endif: ; SI: s_mul_i32 ; SI: v_mul_hi_u32 ; SI: s_mul_i32 -; SI: s_mul_i32 -; SI: v_mul_hi_u32 -; SI: v_mul_hi_u32 -; SI: s_mul_i32 +; SI-DAG: s_mul_i32 +; SI-DAG: v_mul_hi_u32 +; SI-DAG: v_mul_hi_u32 +; SI-DAG: s_mul_i32 ; SI-DAG: s_mul_i32 ; SI-DAG: v_mul_hi_u32 ; SI: s_mul_i32 diff --git a/test/CodeGen/AMDGPU/scratch-simple.ll b/test/CodeGen/AMDGPU/scratch-simple.ll index 60b9b56a48d1f..6ed730ad60f42 100644 --- a/test/CodeGen/AMDGPU/scratch-simple.ll +++ b/test/CodeGen/AMDGPU/scratch-simple.ll @@ -9,13 +9,11 @@ ; GCN-LABEL: {{^}}ps_main: ; GCN-DAG: s_mov_b32 [[SWO:s[0-9]+]], s0 -; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x200 -; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0x400{{$}} ; GCN-DAG: v_lshlrev_b32_e32 [[BYTES:v[0-9]+]], 2, v0 ; GCN-DAG: v_and_b32_e32 [[CLAMP_IDX:v[0-9]+]], 0x1fc, [[BYTES]] -; GCN-DAG: v_or_b32_e32 [[LO_OFF:v[0-9]+]], [[CLAMP_IDX]], [[K]] -; GCN-DAG: v_or_b32_e32 [[HI_OFF:v[0-9]+]], [[CLAMP_IDX]], [[ZERO]] +; GCN-DAG: v_or_b32_e32 [[LO_OFF:v[0-9]+]], 0x200, [[CLAMP_IDX]] +; GCN-DAG: v_or_b32_e32 [[HI_OFF:v[0-9]+]], 0x400, [[CLAMP_IDX]] ; GCN: buffer_load_dword {{v[0-9]+}}, [[LO_OFF]], {{s\[[0-9]+:[0-9]+\]}}, [[SWO]] offen ; GCN: buffer_load_dword {{v[0-9]+}}, [[HI_OFF]], {{s\[[0-9]+:[0-9]+\]}}, [[SWO]] offen diff --git a/test/CodeGen/AMDGPU/sdiv.ll b/test/CodeGen/AMDGPU/sdiv.ll index f9ac425be7942..7ec6ca809b685 100644 --- a/test/CodeGen/AMDGPU/sdiv.ll +++ b/test/CodeGen/AMDGPU/sdiv.ll @@ -36,7 +36,7 @@ define amdgpu_kernel void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* ; FUNC-LABEL: {{^}}slow_sdiv_i32_3435: ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]], ; SI-DAG: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b -; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[MAGIC]], [[VAL]] +; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[VAL]], [[MAGIC]] ; SI: v_add_i32 ; SI: v_lshrrev_b32 ; SI: v_ashrrev_i32 diff --git a/test/CodeGen/AMDGPU/sdwa-peephole.ll b/test/CodeGen/AMDGPU/sdwa-peephole.ll index 73defc17d04f3..a319edfc5acee 100644 --- a/test/CodeGen/AMDGPU/sdwa-peephole.ll +++ b/test/CodeGen/AMDGPU/sdwa-peephole.ll @@ -345,7 +345,10 @@ entry: ; GCN-LABEL: {{^}}immediate_mul_v2i16: ; NOSDWA-NOT: v_mul_u32_u24_sdwa -; SDWA-NOT: v_mul_u32_u24_sdwa +; SDWA-DAG: v_mov_b32_e32 v[[M321:[0-9]+]], 0x141 +; SDWA-DAG: v_mov_b32_e32 v[[M123:[0-9]+]], 0x7b +; SDWA-DAG: v_mul_u32_u24_sdwa v{{[0-9]+}}, v[[M123]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; SDWA-DAG: v_mul_u32_u24_sdwa v{{[0-9]+}}, v[[M321]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 define amdgpu_kernel void @immediate_mul_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { entry: diff --git a/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir b/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir new file mode 100644 index 0000000000000..cd50e01032c38 --- /dev/null +++ b/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir @@ -0,0 +1,410 @@ +# RUN: llc -march=amdgcn -mcpu=fiji -start-before si-peephole-sdwa -o - %s | FileCheck -check-prefix=GCN %s + +# GCN-LABEL: {{^}}sdwa_imm_operand: +# GCN: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2 +# GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 2 +# GCN: BB0_1: +# GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 +# GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 + +# GCN-LABEL: {{^}}sdwa_sgpr_operand: +# GCN: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2 +# GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 2 +# GCN: BB1_1: +# GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 +# GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 + +--- | + ; ModuleID = 'sdwa-scalar-ops.opt.ll' + source_filename = "sdwa-scalar-ops.opt.ll" + target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" + + define amdgpu_kernel void @sdwa_imm_operand(i32 addrspace(1)* nocapture %arg) { + bb: + br label %bb2 + + bb1: ; preds = %bb2 + ret void + + bb2: ; preds = %bb2, %bb + %lsr.iv = phi i64 [ %lsr.iv.next, %bb2 ], [ 0, %bb ] + %bc = bitcast i32 addrspace(1)* %arg to i8 addrspace(1)* + %uglygep4 = getelementptr i8, i8 addrspace(1)* %bc, i64 %lsr.iv + %uglygep45 = bitcast i8 addrspace(1)* %uglygep4 to i32 addrspace(1)* + %tmp5 = load i32, i32 addrspace(1)* %uglygep45, align 4 + %tmp6 = lshr i32 %tmp5, 8 + %tmp7 = and i32 %tmp6, 255 + %tmp8 = zext i32 %tmp7 to i64 + %tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp8 + store i32 1, i32 addrspace(1)* %tmp9, align 4 + %scevgep = getelementptr i32, i32 addrspace(1)* %uglygep45, i64 1 + %tmp13 = load i32, i32 addrspace(1)* %scevgep, align 4 + %tmp14 = lshr i32 %tmp13, 8 + %tmp15 = and i32 %tmp14, 255 + %tmp16 = zext i32 %tmp15 to i64 + %tmp17 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp16 + store i32 1, i32 addrspace(1)* %tmp17, align 4 + %lsr.iv.next = add nuw nsw i64 %lsr.iv, 8 + %tmp1 = trunc i64 %lsr.iv.next to i32 + %tmp19 = icmp eq i32 %tmp1, 4096 + br i1 %tmp19, label %bb1, label %bb2 + } + + define amdgpu_kernel void @sdwa_sgpr_operand(i32 addrspace(1)* nocapture %arg) { + bb: + br label %bb2 + + bb1: ; preds = %bb2 + ret void + + bb2: ; preds = %bb2, %bb + %lsr.iv = phi i64 [ %lsr.iv.next, %bb2 ], [ 0, %bb ] + %bc = bitcast i32 addrspace(1)* %arg to i8 addrspace(1)* + %uglygep4 = getelementptr i8, i8 addrspace(1)* %bc, i64 %lsr.iv + %uglygep45 = bitcast i8 addrspace(1)* %uglygep4 to i32 addrspace(1)* + %tmp5 = load i32, i32 addrspace(1)* %uglygep45, align 4 + %tmp6 = lshr i32 %tmp5, 8 + %tmp7 = and i32 %tmp6, 255 + %tmp8 = zext i32 %tmp7 to i64 + %tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp8 + store i32 1, i32 addrspace(1)* %tmp9, align 4 + %scevgep = getelementptr i32, i32 addrspace(1)* %uglygep45, i64 1 + %tmp13 = load i32, i32 addrspace(1)* %scevgep, align 4 + %tmp14 = lshr i32 %tmp13, 8 + %tmp15 = and i32 %tmp14, 255 + %tmp16 = zext i32 %tmp15 to i64 + %tmp17 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp16 + store i32 1, i32 addrspace(1)* %tmp17, align 4 + %lsr.iv.next = add nuw nsw i64 %lsr.iv, 8 + %tmp1 = trunc i64 %lsr.iv.next to i32 + %tmp19 = icmp eq i32 %tmp1, 4096 + br i1 %tmp19, label %bb1, label %bb2 + } + +... +--- +name: sdwa_imm_operand +alignment: 0 +exposesReturnsTwice: false +noVRegs: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_64 } + - { id: 1, class: sreg_64 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: sgpr_128 } + - { id: 4, class: sgpr_64 } + - { id: 5, class: sreg_32_xm0 } + - { id: 6, class: sgpr_32 } + - { id: 7, class: sreg_64 } + - { id: 8, class: sreg_64 } + - { id: 9, class: sreg_64_xexec } + - { id: 10, class: sreg_32_xm0 } + - { id: 11, class: sreg_32_xm0 } + - { id: 12, class: sreg_32_xm0 } + - { id: 13, class: sreg_32_xm0 } + - { id: 14, class: sreg_32_xm0 } + - { id: 15, class: sreg_32_xm0 } + - { id: 16, class: sreg_64 } + - { id: 17, class: vgpr_32 } + - { id: 18, class: vreg_64 } + - { id: 19, class: sreg_32_xm0 } + - { id: 20, class: sreg_32 } + - { id: 21, class: sreg_32_xm0 } + - { id: 22, class: sreg_32_xm0 } + - { id: 23, class: sreg_32_xm0 } + - { id: 24, class: sreg_64 } + - { id: 25, class: sreg_32_xm0 } + - { id: 26, class: sreg_32_xm0 } + - { id: 27, class: sreg_32_xm0 } + - { id: 28, class: sreg_32_xm0 } + - { id: 29, class: sreg_64 } + - { id: 30, class: vgpr_32 } + - { id: 31, class: vreg_64 } + - { id: 32, class: sreg_32_xm0 } + - { id: 33, class: sreg_32_xm0 } + - { id: 34, class: sreg_64 } + - { id: 35, class: sreg_32_xm0 } + - { id: 36, class: sreg_32_xm0 } + - { id: 37, class: sreg_32_xm0 } + - { id: 38, class: sreg_32_xm0 } + - { id: 39, class: vreg_64 } + - { id: 40, class: vgpr_32 } + - { id: 41, class: vreg_64 } + - { id: 42, class: sreg_32_xm0 } + - { id: 43, class: sreg_32 } + - { id: 44, class: sreg_32_xm0 } + - { id: 45, class: sreg_64 } + - { id: 46, class: sreg_32_xm0 } + - { id: 47, class: sreg_32_xm0 } + - { id: 48, class: sreg_32_xm0 } + - { id: 49, class: sreg_32_xm0 } + - { id: 50, class: sreg_64 } + - { id: 51, class: vreg_64 } + - { id: 52, class: sreg_64 } + - { id: 53, class: sreg_32_xm0 } + - { id: 54, class: sreg_32_xm0 } + - { id: 55, class: sreg_32_xm0 } + - { id: 56, class: sreg_32_xm0 } + - { id: 57, class: sreg_64 } + - { id: 58, class: sreg_32_xm0 } + - { id: 59, class: sreg_32_xm0 } + - { id: 60, class: vgpr_32 } + - { id: 61, class: vgpr_32 } + - { id: 62, class: vreg_64 } + - { id: 63, class: vgpr_32 } + - { id: 64, class: vgpr_32 } + - { id: 65, class: vgpr_32 } + - { id: 66, class: vgpr_32 } + - { id: 67, class: vreg_64 } + - { id: 68, class: vgpr_32 } + - { id: 69, class: vgpr_32 } + - { id: 70, class: vgpr_32 } + - { id: 71, class: vgpr_32 } + - { id: 72, class: vgpr_32 } + - { id: 73, class: vgpr_32 } + - { id: 74, class: vgpr_32 } + - { id: 75, class: vreg_64 } + - { id: 76, class: vgpr_32 } + - { id: 77, class: vgpr_32 } + - { id: 78, class: vgpr_32 } + - { id: 79, class: vgpr_32 } + - { id: 80, class: vreg_64 } + - { id: 81, class: vgpr_32 } + - { id: 82, class: vgpr_32 } + - { id: 83, class: vgpr_32 } +liveins: + - { reg: '%sgpr4_sgpr5', virtual-reg: '%4' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.bb: + successors: %bb.2.bb2(0x80000000) + liveins: %sgpr4_sgpr5 + + %4 = COPY %sgpr4_sgpr5 + %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) + %8 = S_MOV_B64 0 + %7 = COPY %9 + %30 = V_MOV_B32_e32 1, implicit %exec + S_BRANCH %bb.2.bb2 + + bb.1.bb1: + S_ENDPGM + + bb.2.bb2: + successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000) + + %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2 + %13 = COPY %7.sub1 + %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def %scc + %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead %scc, implicit %scc + %16 = REG_SEQUENCE %14, 1, %15, 2 + %18 = COPY %16 + %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45) + %60 = V_BFE_U32 %17, 8, 8, implicit %exec + %61 = V_LSHLREV_B32_e32 2, killed %60, implicit %exec + %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def %vcc, implicit %exec + %66 = COPY %13 + %65 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec + %67 = REG_SEQUENCE %70, 1, killed %65, 2 + FLAT_STORE_DWORD %67, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9) + %37 = S_ADD_U32 %14, 4, implicit-def %scc + %38 = S_ADDC_U32 %15, 0, implicit-def dead %scc, implicit %scc + %71 = COPY killed %37 + %72 = COPY killed %38 + %41 = REG_SEQUENCE killed %71, 1, killed %72, 2 + %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep) + %73 = V_BFE_U32 %40, 8, 8, implicit %exec + %74 = V_LSHLREV_B32_e32 2, killed %73, implicit %exec + %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def %vcc, implicit %exec + %78 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec + %80 = REG_SEQUENCE %83, 1, killed %78, 2 + FLAT_STORE_DWORD %80, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17) + %55 = S_ADD_U32 %0.sub0, 8, implicit-def %scc + %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead %scc, implicit %scc + %57 = REG_SEQUENCE %55, 1, killed %56, 2 + %1 = COPY %57 + S_CMPK_EQ_I32 %55, 4096, implicit-def %scc + S_CBRANCH_SCC1 %bb.1.bb1, implicit %scc + S_BRANCH %bb.2.bb2 + +... +--- +name: sdwa_sgpr_operand +alignment: 0 +exposesReturnsTwice: false +noVRegs: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_64 } + - { id: 1, class: sreg_64 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: sgpr_128 } + - { id: 4, class: sgpr_64 } + - { id: 5, class: sreg_32_xm0 } + - { id: 6, class: sgpr_32 } + - { id: 7, class: sreg_64 } + - { id: 8, class: sreg_64 } + - { id: 9, class: sreg_64_xexec } + - { id: 10, class: sreg_32_xm0 } + - { id: 11, class: sreg_32_xm0 } + - { id: 12, class: sreg_32_xm0 } + - { id: 13, class: sreg_32_xm0 } + - { id: 14, class: sreg_32_xm0 } + - { id: 15, class: sreg_32_xm0 } + - { id: 16, class: sreg_64 } + - { id: 17, class: vgpr_32 } + - { id: 18, class: vreg_64 } + - { id: 19, class: sreg_32_xm0 } + - { id: 20, class: sreg_32 } + - { id: 21, class: sreg_32_xm0 } + - { id: 22, class: sreg_32_xm0 } + - { id: 23, class: sreg_32_xm0 } + - { id: 24, class: sreg_64 } + - { id: 25, class: sreg_32_xm0 } + - { id: 26, class: sreg_32_xm0 } + - { id: 27, class: sreg_32_xm0 } + - { id: 28, class: sreg_32_xm0 } + - { id: 29, class: sreg_64 } + - { id: 30, class: vgpr_32 } + - { id: 31, class: vreg_64 } + - { id: 32, class: sreg_32_xm0 } + - { id: 33, class: sreg_32_xm0 } + - { id: 34, class: sreg_64 } + - { id: 35, class: sreg_32_xm0 } + - { id: 36, class: sreg_32_xm0 } + - { id: 37, class: sreg_32_xm0 } + - { id: 38, class: sreg_32_xm0 } + - { id: 39, class: vreg_64 } + - { id: 40, class: vgpr_32 } + - { id: 41, class: vreg_64 } + - { id: 42, class: sreg_32_xm0 } + - { id: 43, class: sreg_32 } + - { id: 44, class: sreg_32_xm0 } + - { id: 45, class: sreg_64 } + - { id: 46, class: sreg_32_xm0 } + - { id: 47, class: sreg_32_xm0 } + - { id: 48, class: sreg_32_xm0 } + - { id: 49, class: sreg_32_xm0 } + - { id: 50, class: sreg_64 } + - { id: 51, class: vreg_64 } + - { id: 52, class: sreg_64 } + - { id: 53, class: sreg_32_xm0 } + - { id: 54, class: sreg_32_xm0 } + - { id: 55, class: sreg_32_xm0 } + - { id: 56, class: sreg_32_xm0 } + - { id: 57, class: sreg_64 } + - { id: 58, class: sreg_32_xm0 } + - { id: 59, class: sreg_32_xm0 } + - { id: 60, class: vgpr_32 } + - { id: 61, class: vgpr_32 } + - { id: 62, class: vreg_64 } + - { id: 63, class: vgpr_32 } + - { id: 64, class: vgpr_32 } + - { id: 65, class: vgpr_32 } + - { id: 66, class: vgpr_32 } + - { id: 67, class: vreg_64 } + - { id: 68, class: vgpr_32 } + - { id: 69, class: vgpr_32 } + - { id: 70, class: vgpr_32 } + - { id: 71, class: vgpr_32 } + - { id: 72, class: vgpr_32 } + - { id: 73, class: vgpr_32 } + - { id: 74, class: vgpr_32 } + - { id: 75, class: vreg_64 } + - { id: 76, class: vgpr_32 } + - { id: 77, class: vgpr_32 } + - { id: 78, class: vgpr_32 } + - { id: 79, class: vgpr_32 } + - { id: 80, class: vreg_64 } + - { id: 81, class: vgpr_32 } + - { id: 82, class: vgpr_32 } + - { id: 83, class: vgpr_32 } + - { id: 84, class: sreg_32_xm0 } +liveins: + - { reg: '%sgpr4_sgpr5', virtual-reg: '%4' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.bb: + successors: %bb.2.bb2(0x80000000) + liveins: %sgpr4_sgpr5 + + %4 = COPY %sgpr4_sgpr5 + %9 = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) + %8 = S_MOV_B64 0 + %7 = COPY %9 + %30 = V_MOV_B32_e32 1, implicit %exec + %84 = S_MOV_B32 2 + S_BRANCH %bb.2.bb2 + + bb.1.bb1: + S_ENDPGM + + bb.2.bb2: + successors: %bb.1.bb1(0x04000000), %bb.2.bb2(0x7c000000) + + %0 = PHI %8, %bb.0.bb, %1, %bb.2.bb2 + %13 = COPY %7.sub1 + %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def %scc + %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead %scc, implicit %scc + %16 = REG_SEQUENCE %14, 1, %15, 2 + %18 = COPY %16 + %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45) + %60 = V_BFE_U32 %17, 8, 8, implicit %exec + %61 = V_LSHLREV_B32_e32 %84, killed %60, implicit %exec + %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def %vcc, implicit %exec + %66 = COPY %13 + %65 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec + %67 = REG_SEQUENCE %70, 1, killed %65, 2 + FLAT_STORE_DWORD %67, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9) + %37 = S_ADD_U32 %14, 4, implicit-def %scc + %38 = S_ADDC_U32 %15, 0, implicit-def dead %scc, implicit %scc + %71 = COPY killed %37 + %72 = COPY killed %38 + %41 = REG_SEQUENCE killed %71, 1, killed %72, 2 + %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep) + %73 = V_BFE_U32 %40, 8, 8, implicit %exec + %74 = V_LSHLREV_B32_e32 %84, killed %73, implicit %exec + %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def %vcc, implicit %exec + %78 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec + %80 = REG_SEQUENCE %83, 1, killed %78, 2 + FLAT_STORE_DWORD %80, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17) + %55 = S_ADD_U32 %0.sub0, 8, implicit-def %scc + %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead %scc, implicit %scc + %57 = REG_SEQUENCE %55, 1, killed %56, 2 + %1 = COPY %57 + S_CMPK_EQ_I32 %55, 4096, implicit-def %scc + S_CBRANCH_SCC1 %bb.1.bb1, implicit %scc + S_BRANCH %bb.2.bb2 + +... diff --git a/test/CodeGen/AMDGPU/select.f16.ll b/test/CodeGen/AMDGPU/select.f16.ll index 2a7a9c9e0638f..92ee2eb7f403f 100644 --- a/test/CodeGen/AMDGPU/select.f16.ll +++ b/test/CodeGen/AMDGPU/select.f16.ll @@ -196,11 +196,11 @@ entry: ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 -; SI: v_cmp_lt_f32_e64 -; SI: v_cmp_lt_f32_e32 vcc, 0.5 +; SI-DAG: v_cmp_gt_f32_e64 +; SI-DAG: v_cmp_lt_f32_e32 vcc, 0.5 ; VI: v_cmp_lt_f16_e32 -; VI: v_cmp_lt_f16_e64 +; VI: v_cmp_gt_f16_e64 ; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e64 ; SI: v_cvt_f16_f32_e32 @@ -228,11 +228,11 @@ entry: ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 ; SI: v_cvt_f32_f16_e32 -; SI: v_cmp_gt_f32_e64 -; SI: v_cmp_gt_f32_e32 vcc, 0.5 +; SI-DAG: v_cmp_lt_f32_e64 +; SI-DAG: v_cmp_gt_f32_e32 vcc, 0.5 ; VI: v_cmp_gt_f16_e32 -; VI: v_cmp_gt_f16_e64 +; VI: v_cmp_lt_f16_e64 ; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e64 diff --git a/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll b/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll index 0a29db4a05808..4f7b61adc91d5 100644 --- a/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll +++ b/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll @@ -5,7 +5,7 @@ ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} -; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}} ; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} ; GCN: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] @@ -24,14 +24,15 @@ define amdgpu_kernel void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128 ; Extract the high bit of the 2nd quarter ; GCN-LABEL: {{^}}v_uextract_bit_63_i128: -; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}} ; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} +; GCN: v_mov_b32_e32 v[[ZERO3:[0-9]+]], v[[ZERO0]]{{$}} ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] -; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO3]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: s_endpgm define amdgpu_kernel void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() @@ -49,7 +50,7 @@ define amdgpu_kernel void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} -; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}} ; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] @@ -68,14 +69,15 @@ define amdgpu_kernel void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128 ; Extract the high bit of the 4th quarter ; GCN-LABEL: {{^}}v_uextract_bit_127_i128: -; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} -; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}} ; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} +; GCN: v_mov_b32_e32 v[[ZERO3:[0-9]+]], v[[ZERO0]]{{$}} ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] -; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO3]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: s_endpgm define amdgpu_kernel void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() @@ -90,15 +92,16 @@ define amdgpu_kernel void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128 ; Spans more than 2 dword boundaries ; GCN-LABEL: {{^}}v_uextract_bit_34_100_i128: -; GCN: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: v_lshl_b64 v{{\[}}[[SHLLO:[0-9]+]]:[[SHLHI:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, 30 ; GCN-DAG: v_lshrrev_b32_e32 v[[ELT1PART:[0-9]+]], 2, v{{[[0-9]+}} ; GCN-DAG: v_bfe_u32 v[[ELT2PART:[0-9]+]], v[[VAL3]], 2, 2{{$}} ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[SHLLO]], v[[ELT1PART]] +; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]{{$}} -; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[OR0]]:[[ZERO]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[OR0]]:[[ZERO1]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN: s_endpgm define amdgpu_kernel void @v_uextract_bit_34_100_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() diff --git a/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll b/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll index 36c33b876919b..a6026785b1739 100644 --- a/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll +++ b/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll @@ -21,10 +21,11 @@ define amdgpu_kernel void @v_uextract_bit_31_i64(i64 addrspace(1)* %out, i64 add ; Extract the high bit of the high half ; GCN-LABEL: {{^}}v_uextract_bit_63_i64: +; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] -; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} -; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO1]]{{\]}} define amdgpu_kernel void @v_uextract_bit_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x @@ -69,10 +70,11 @@ define amdgpu_kernel void @v_uextract_bit_20_i64(i64 addrspace(1)* %out, i64 add } ; GCN-LABEL: {{^}}v_uextract_bit_32_i64: -; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 1, [[VAL]] ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} -; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]]{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO1]]{{\]}} define amdgpu_kernel void @v_uextract_bit_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x @@ -85,10 +87,11 @@ define amdgpu_kernel void @v_uextract_bit_32_i64(i64 addrspace(1)* %out, i64 add } ; GCN-LABEL: {{^}}v_uextract_bit_33_i64: +; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1{{$}} -; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} -; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO1]]{{\]}} define amdgpu_kernel void @v_uextract_bit_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x @@ -167,10 +170,11 @@ define amdgpu_kernel void @v_uextract_bit_31_32_i64(i64 addrspace(1)* %out, i64 } ; GCN-LABEL: {{^}}v_uextract_bit_32_33_i64: +; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 2 -; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} -; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO1]]{{\]}} define amdgpu_kernel void @v_uextract_bit_32_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x @@ -183,11 +187,12 @@ define amdgpu_kernel void @v_uextract_bit_32_33_i64(i64 addrspace(1)* %out, i64 } ; GCN-LABEL: {{^}}v_uextract_bit_30_60_i64: +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; GCN: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 30 ; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 0x3fffffff, v[[SHRLO]]{{$}} -; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} -; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO1]]{{\]}} define amdgpu_kernel void @v_uextract_bit_30_60_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x @@ -200,10 +205,11 @@ define amdgpu_kernel void @v_uextract_bit_30_60_i64(i64 addrspace(1)* %out, i64 } ; GCN-LABEL: {{^}}v_uextract_bit_33_63_i64: +; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30 -; GCN-DAG: v_mov_b32_e32 v[[BFE:[0-9]+]], 0{{$}} -; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO1]]{{\]}} define amdgpu_kernel void @v_uextract_bit_33_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x @@ -216,9 +222,10 @@ define amdgpu_kernel void @v_uextract_bit_33_63_i64(i64 addrspace(1)* %out, i64 } ; GCN-LABEL: {{^}}v_uextract_bit_31_63_i64: +; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; GCN: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 31 -; GCN-NEXT: v_mov_b32_e32 v[[SHRHI]], 0{{$}} +; GCN-NEXT: v_mov_b32_e32 v[[SHRHI]], v[[ZERO]] ; GCN: buffer_store_dwordx2 v{{\[}}[[SHRLO]]:[[SHRHI]]{{\]}} define amdgpu_kernel void @v_uextract_bit_31_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() @@ -300,7 +307,8 @@ define amdgpu_kernel void @v_uextract_bit_31_32_i64_trunc_i32(i32 addrspace(1)* ; GCN-LABEL: {{^}}and_not_mask_i64: ; GCN-DAG: buffer_load_dwordx2 v{{\[}}[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]{{\]}} -; GCN: v_mov_b32_e32 v[[SHRHI:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[SHRHI:[0-9]+]], v[[ZERO]]{{$}} ; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 20, v[[VALLO]] ; GCN-DAG: v_and_b32_e32 v[[SHRLO:[0-9]+]], 4, [[SHR]] ; GCN-NOT: v[[SHRLO]] @@ -321,7 +329,7 @@ define amdgpu_kernel void @and_not_mask_i64(i64 addrspace(1)* %out, i64 addrspac ; keeping the 32-bit and has a smaller encoding size than the bfe. ; GCN-LABEL: {{^}}v_uextract_bit_27_29_multi_use_shift_i64: -; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] ; GCN-DAG: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 27 ; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 3, v[[SHRLO]] ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} @@ -340,8 +348,8 @@ define amdgpu_kernel void @v_uextract_bit_27_29_multi_use_shift_i64(i64 addrspac } ; GCN-LABEL: {{^}}v_uextract_bit_34_37_multi_use_shift_i64: -; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} -; GCN: v_mov_b32_e32 v[[ZERO_SHR:[0-9]+]], 0{{$}} +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO_SHR:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[ZERO_BFE:[0-9]+]], v[[ZERO_SHR]] ; GCN-DAG: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 2, [[VAL]] ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 2, 3 @@ -362,6 +370,7 @@ define amdgpu_kernel void @v_uextract_bit_34_37_multi_use_shift_i64(i64 addrspac ; GCN-LABEL: {{^}}v_uextract_bit_33_36_use_upper_half_shift_i64: ; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 3 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:{{[0-9]+\]}} ; GCN: buffer_store_dword v[[ZERO]] define amdgpu_kernel void @v_uextract_bit_33_36_use_upper_half_shift_i64(i64 addrspace(1)* %out0, i32 addrspace(1)* %out1, i64 addrspace(1)* %in) #1 { diff --git a/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/test/CodeGen/AMDGPU/sminmax.v2i16.ll index 16ce86bf8b115..5d71ad2c8ba36 100644 --- a/test/CodeGen/AMDGPU/sminmax.v2i16.ll +++ b/test/CodeGen/AMDGPU/sminmax.v2i16.ll @@ -40,13 +40,14 @@ define amdgpu_kernel void @s_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> % ; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]] ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[MAX]], 2 +; VI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 ; VI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; VI: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} ; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_add_u16_e32 v{{[0-9]+}}, 2, v{{[0-9]+}} -; VI: v_add_u16_e32 v{{[0-9]+}}, 2, v{{[0-9]+}} +; VI: v_add_u16_sdwa v{{[0-9]+}}, [[TWO]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NOT: v_and_b32 ; VI: v_or_b32_e32 define amdgpu_kernel void @v_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 { @@ -206,7 +207,7 @@ define amdgpu_kernel void @v_min_max_v2i16_user(<2 x i16> addrspace(1)* %out0, < } ; GCN-LABEL: {{^}}u_min_max_v2i16: -; GFX9: v_pk_max_u16 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} +; GFX9: v_pk_max_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} ; GFX9: v_pk_min_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @u_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) nounwind { %cond0 = icmp ugt <2 x i16> %val0, %val1 diff --git a/test/CodeGen/AMDGPU/srem.ll b/test/CodeGen/AMDGPU/srem.ll index c89f798397ae6..e067258920892 100644 --- a/test/CodeGen/AMDGPU/srem.ll +++ b/test/CodeGen/AMDGPU/srem.ll @@ -20,7 +20,7 @@ define amdgpu_kernel void @srem_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* ; FUNC-LABEL: {{^}}srem_i32_7: ; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x92492493 -; SI: v_mul_hi_i32 {{v[0-9]+}}, [[MAGIC]], +; SI: v_mul_hi_i32 {{v[0-9]+}}, {{v[0-9]+}}, [[MAGIC]] ; SI: v_mul_lo_i32 ; SI: v_sub_i32 ; SI: s_endpgm diff --git a/test/CodeGen/AMDGPU/sub.v2i16.ll b/test/CodeGen/AMDGPU/sub.v2i16.ll index 431344670ffb1..6aeff3fc3b6c1 100644 --- a/test/CodeGen/AMDGPU/sub.v2i16.ll +++ b/test/CodeGen/AMDGPU/sub.v2i16.ll @@ -23,7 +23,7 @@ define amdgpu_kernel void @v_test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i ; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]] -; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[VVAL1]], [[VAL0]] +; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]] ; VI: s_sub_i32 ; VI: s_sub_i32 @@ -47,7 +47,7 @@ define amdgpu_kernel void @s_test_sub_self_v2i16(<2 x i16> addrspace(1)* %out, < ; FIXME: VI should not scalarize arg access. ; GCN-LABEL: {{^}}s_test_sub_v2i16_kernarg: -; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} +; GFX9: v_pk_sub_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} ; VI: v_subrev_i32_e32 ; VI: v_subrev_i32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD @@ -59,9 +59,10 @@ define amdgpu_kernel void @s_test_sub_v2i16_kernarg(<2 x i16> addrspace(1)* %out ; GCN-LABEL: {{^}}v_test_sub_v2i16_constant: ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0x1c8007b{{$}} -; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[CONST]], v{{[0-9]+}} +; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] -; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0xfffffe38, v{{[0-9]+}} +; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xfffffe38 +; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, [[K]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0xffffff85, v{{[0-9]+}} define amdgpu_kernel void @v_test_sub_v2i16_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -76,9 +77,10 @@ define amdgpu_kernel void @v_test_sub_v2i16_constant(<2 x i16> addrspace(1)* %ou ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_sub_v2i16_neg_constant: ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0xfc21fcb3{{$}} -; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[CONST]], v{{[0-9]+}} +; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] -; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0x3df, v{{[0-9]+}} +; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3df +; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, [[K]], v{{[0-9]+}} ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0x34d, v{{[0-9]+}} define amdgpu_kernel void @v_test_sub_v2i16_neg_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -93,11 +95,11 @@ define amdgpu_kernel void @v_test_sub_v2i16_neg_constant(<2 x i16> addrspace(1)* ; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_neg1: ; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, -1{{$}} +; VI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 ; VI: flat_load_ushort [[LOAD0:v[0-9]+]] ; VI: flat_load_ushort [[LOAD1:v[0-9]+]] -; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 1, [[LOAD0]] +; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, [[ONE]], [[LOAD0]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 1, [[LOAD1]] -; VI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_or_b32_e32 define amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -111,7 +113,7 @@ define amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(<2 x i16> addrspace(1)* ; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_lo_zero_hi: ; GFX9: s_mov_b32 [[K:s[0-9]+]], 32{{$}} -; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[K]], v{{[0-9]+}}{{$}} +; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] ; VI-NOT: v_subrev_i16 ; VI: v_add_u16_e32 v{{[0-9]+}}, 0xffffffe0, v{{[0-9]+}} @@ -131,12 +133,12 @@ define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(<2 x i16> addrspac ; The high element gives fp ; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_fp_split: ; GFX9: s_mov_b32 [[K:s[0-9]+]], 1.0 -; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[K]], v{{[0-9]+}}{{$}} +; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] ; VI-NOT: v_subrev_i16 -; VI: v_add_u16_e32 v{{[0-9]+}}, 0xffffc080, v{{[0-9]+}} +; VI: v_mov_b32_e32 [[K:v[0-9]+]], 0xffffc080 +; VI: v_add_u16_sdwa v{{[0-9]+}}, [[K]], v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NOT: v_subrev_i16 -; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_or_b32_e32 define amdgpu_kernel void @v_test_sub_v2i16_inline_fp_split(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -185,10 +187,10 @@ define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(<2 x i32> addrspace(1) ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_sub_v2i16_zext_to_v2i64: +; GFX9: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; GFX9: flat_load_dword [[A:v[0-9]+]] ; GFX9: flat_load_dword [[B:v[0-9]+]] -; GFX9: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; GFX9: v_pk_sub_i16 [[ADD:v[0-9]+]], [[A]], [[B]] ; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] ; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] @@ -199,8 +201,6 @@ define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(<2 x i32> addrspace(1) ; VI: flat_load_ushort v[[B_LO:[0-9]+]] ; VI: flat_load_ushort v[[B_HI:[0-9]+]] -; VI-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} -; VI-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} ; VI-DAG: v_subrev_u16_e32 ; VI-DAG: v_subrev_u16_e32 diff --git a/test/CodeGen/AMDGPU/udiv.ll b/test/CodeGen/AMDGPU/udiv.ll index 2874a0cdbc05f..d9dab0d40acf6 100644 --- a/test/CodeGen/AMDGPU/udiv.ll +++ b/test/CodeGen/AMDGPU/udiv.ll @@ -74,7 +74,7 @@ define amdgpu_kernel void @udiv_i32_div_pow2(i32 addrspace(1)* %out, i32 addrspa ; FUNC-LABEL: {{^}}udiv_i32_div_k_even: ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] ; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xfabbd9c1 -; SI: v_mul_hi_u32 [[MULHI:v[0-9]+]], [[K]], [[VAL]] +; SI: v_mul_hi_u32 [[MULHI:v[0-9]+]], [[VAL]], [[K]] ; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 25, [[MULHI]] ; SI: buffer_store_dword [[RESULT]] define amdgpu_kernel void @udiv_i32_div_k_even(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { @@ -88,7 +88,7 @@ define amdgpu_kernel void @udiv_i32_div_k_even(i32 addrspace(1)* %out, i32 addrs ; FUNC-LABEL: {{^}}udiv_i32_div_k_odd: ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] ; SI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x7d5deca3 -; SI: v_mul_hi_u32 [[MULHI:v[0-9]+]], [[K]], [[VAL]] +; SI: v_mul_hi_u32 [[MULHI:v[0-9]+]], [[VAL]], [[K]] ; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 24, [[MULHI]] ; SI: buffer_store_dword [[RESULT]] define amdgpu_kernel void @udiv_i32_div_k_odd(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { @@ -176,7 +176,7 @@ define amdgpu_kernel void @test_udiv2(i32 %p) { ; FUNC-LABEL: {{^}}test_udiv_3_mulhu: ; SI: v_mov_b32_e32 v{{[0-9]+}}, 0xaaaaaaab -; SI: v_mul_hi_u32 v0, {{v[0-9]+}}, {{s[0-9]+}} +; SI: v_mul_hi_u32 v0, {{s[0-9]+}}, {{v[0-9]+}} ; SI-NEXT: v_lshrrev_b32_e32 v0, 1, v0 define amdgpu_kernel void @test_udiv_3_mulhu(i32 %p) { %i = udiv i32 %p, 3 diff --git a/test/CodeGen/AMDGPU/urem.ll b/test/CodeGen/AMDGPU/urem.ll index fd7f8fa2efab5..fb4eab43a2d66 100644 --- a/test/CodeGen/AMDGPU/urem.ll +++ b/test/CodeGen/AMDGPU/urem.ll @@ -20,7 +20,7 @@ define amdgpu_kernel void @test_urem_i32(i32 addrspace(1)* %out, i32 addrspace(1 ; FUNC-LABEL: {{^}}test_urem_i32_7: ; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x24924925 -; SI: v_mul_hi_u32 {{v[0-9]+}}, [[MAGIC]] +; SI: v_mul_hi_u32 [[MAGIC]], {{v[0-9]+}} ; SI: v_subrev_i32 ; SI: v_mul_lo_i32 ; SI: v_sub_i32 diff --git a/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll b/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll index f8e6b7edfe358..e6bdb68a4f775 100644 --- a/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll +++ b/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll @@ -54,8 +54,8 @@ define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace( ; VI: buffer_load_dword [[VA0:v[0-9]+]] ; VI: buffer_load_dword [[VA1:v[0-9]+]] -; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VA0]], [[SA]], [[VB]] -; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VA1]], [[SA]], [[VB]] +; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SA]], [[VA0]], [[VB]] +; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SA]], [[VA1]], [[VB]] ; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT1]] define amdgpu_kernel void @test_use_s_v_s(float addrspace(1)* %out, float %a, float %b, float addrspace(1)* %in) #0 { @@ -74,7 +74,7 @@ define amdgpu_kernel void @test_use_s_v_s(float addrspace(1)* %out, float %a, fl ; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] -; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]] +; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]] ; GCN: buffer_store_dword [[RESULT]] define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 { %fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1 @@ -88,7 +88,7 @@ define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace( ; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] -; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]] +; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]] ; GCN: buffer_store_dword [[RESULT]] define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 { %fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1 @@ -228,7 +228,7 @@ define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k_x2(float addr ; GCN-DAG: v_mov_b32_e32 [[VK0:v[0-9]+]], 0x44800000 ; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], [[SGPR1]] -; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VS1]], [[SGPR0]], [[VK0]] +; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SGPR0]], [[VS1]], [[VK0]] ; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SGPR0]], [[VS1]], [[VK1]] @@ -251,7 +251,7 @@ define amdgpu_kernel void @test_s0_s1_k_f32(float addrspace(1)* %out, float %a, ; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB0:[0-9]+]], s[[SGPR1_SUB0]] ; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB1:[0-9]+]], s[[SGPR1_SUB1]] -; GCN: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, [[SGPR0]], v{{\[}}[[VZERO]]:[[VK0_SUB1]]{{\]}} +; GCN: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK0_SUB1]]{{\]}} ; Same zero component is re-used for half of each immediate. ; GCN: v_mov_b32_e32 v[[VK1_SUB1:[0-9]+]], 0x40b00000 diff --git a/test/CodeGen/AMDGPU/v_mac_f16.ll b/test/CodeGen/AMDGPU/v_mac_f16.ll index c45af522ec49b..3da1a0324042a 100644 --- a/test/CodeGen/AMDGPU/v_mac_f16.ll +++ b/test/CodeGen/AMDGPU/v_mac_f16.ll @@ -482,8 +482,9 @@ entry: ; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A0]] ; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A1]] -; VI: v_sub_f16_e32 v[[NEG_A0:[0-9]+]], 0, v{{[0-9]+}} -; VI: v_sub_f16_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}} +; VI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 +; VI-DAG: v_sub_f16_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}} +; VI-DAG: v_sub_f16_sdwa v[[NEG_A0:[0-9]+]], [[ZERO]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mac_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-DAG: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A1]] @@ -513,8 +514,9 @@ entry: ; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v[[NEG_A0]], v{{[0-9]+}} ; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v[[NEG_A1]], v{{[0-9]+}} -; VI: v_sub_f16_e32 v[[NEG_A0:[0-9]+]], 0, v{{[0-9]+}} +; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 ; VI: v_sub_f16_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}} +; VI: v_sub_f16_sdwa v[[NEG_A0:[0-9]+]], [[ZERO]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mac_f16_sdwa v{{[0-9]+}}, v[[NEG_A0]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mac_f16_e32 v{{[0-9]+}}, v[[NEG_A1]], v{{[0-9]+}} @@ -544,8 +546,9 @@ entry: ; SI-DAG: v_mac_f32_e32 v[[NEG_A0]], v{{[0-9]+}}, v{{[0-9]+}} ; SI-DAG: v_mac_f32_e32 v[[NEG_A1]], v{{[0-9]+}}, v{{[0-9]+}} -; VI: v_sub_f16_e32 v[[NEG_A0:[0-9]+]], 0, v{{[0-9]+}} +; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 ; VI: v_sub_f16_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}} +; VI: v_sub_f16_sdwa v[[NEG_A0:[0-9]+]], [[ZERO]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; VI-DAG: v_mac_f16_sdwa v[[NEG_A0]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-DAG: v_mac_f16_e32 v[[NEG_A1]], v{{[0-9]+}}, v{{[0-9]+}} diff --git a/test/CodeGen/AMDGPU/wqm.ll b/test/CodeGen/AMDGPU/wqm.ll index 9f277b2c9a59d..133aaa35981e1 100644 --- a/test/CodeGen/AMDGPU/wqm.ll +++ b/test/CodeGen/AMDGPU/wqm.ll @@ -349,7 +349,7 @@ main_body: ; CHECK: [[LOOPHDR:BB[0-9]+_[0-9]+]]: ; %body ; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]] -; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]] +; CHECK: v_cmp_gt_f32_e32 vcc, [[CTR]], [[SEVEN]] ; CHECK: s_cbranch_vccz [[LOOPHDR]] ; CHECK: ; %break diff --git a/test/CodeGen/WebAssembly/negative-base-reg.ll b/test/CodeGen/WebAssembly/negative-base-reg.ll index 377966ffa8d98..fc3a287f58580 100644 --- a/test/CodeGen/WebAssembly/negative-base-reg.ll +++ b/test/CodeGen/WebAssembly/negative-base-reg.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" -target triple = "wasm32" +target triple = "wasm32---elf" @args = hidden local_unnamed_addr global [32 x i32] zeroinitializer, align 16 diff --git a/test/CodeGen/X86/bitcast-and-setcc-128.ll b/test/CodeGen/X86/bitcast-and-setcc-128.ll new file mode 100644 index 0000000000000..a681c3b0aa429 --- /dev/null +++ b/test/CodeGen/X86/bitcast-and-setcc-128.ll @@ -0,0 +1,1155 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+sse2 < %s | FileCheck %s --check-prefixes=SSE2-SSSE3,SSE2 +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+ssse3 < %s | FileCheck %s --check-prefixes=SSE2-SSSE3,SSSE3 +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx < %s | FileCheck %s --check-prefixes=AVX12,AVX1 +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx2 < %s | FileCheck %s --check-prefixes=AVX12,AVX2 +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx512f,+avx512vl,+avx512bw < %s | FileCheck %s --check-prefixes=AVX512 + +define i8 @v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { +; SSE2-SSSE3-LABEL: v8i16: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtw %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: pextrw $7, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $6, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $5, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $4, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $3, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $2, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $1, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movd %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v8i16: +; AVX12: ## BB#0: +; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtw %xmm3, %xmm2, %xmm1 +; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrw $7, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $6, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $5, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $4, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $3, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $2, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $1, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovd %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v8i16: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtw %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtw %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: retq + %x0 = icmp sgt <8 x i16> %a, %b + %x1 = icmp sgt <8 x i16> %c, %d + %y = and <8 x i1> %x0, %x1 + %res = bitcast <8 x i1> %y to i8 + ret i8 %res +} + +define i4 @v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { +; SSE2-SSSE3-LABEL: v4i32: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: movd %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v4i32: +; AVX12: ## BB#0: +; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1 +; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrd $3, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $2, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $1, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovd %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v4i32: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtd %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtd %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = icmp sgt <4 x i32> %a, %b + %x1 = icmp sgt <4 x i32> %c, %d + %y = and <4 x i1> %x0, %x1 + %res = bitcast <4 x i1> %y to i4 + ret i4 %res +} + +define i4 @v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { +; SSE2-SSSE3-LABEL: v4f32: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: cmpltps %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: cmpltps %xmm2, %xmm3 +; SSE2-SSSE3-NEXT: andps %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: movd %xmm3, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,0,1] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v4f32: +; AVX12: ## BB#0: +; AVX12-NEXT: vcmpltps %xmm0, %xmm1, %xmm0 +; AVX12-NEXT: vcmpltps %xmm2, %xmm3, %xmm1 +; AVX12-NEXT: vandps %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrd $3, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $2, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $1, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovd %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v4f32: +; AVX512: ## BB#0: +; AVX512-NEXT: vcmpltps %xmm0, %xmm1, %k1 +; AVX512-NEXT: vcmpltps %xmm2, %xmm3, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = fcmp ogt <4 x float> %a, %b + %x1 = fcmp ogt <4 x float> %c, %d + %y = and <4 x i1> %x0, %x1 + %res = bitcast <4 x i1> %y to i4 + ret i4 %res +} + +define i16 @v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { +; SSE2-SSSE3-LABEL: v16i8: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtb %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %cl +; SSE2-SSSE3-NEXT: andb $1, %cl +; SSE2-SSSE3-NEXT: movb %cl, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: andb $1, %al +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v16i8: +; AVX12: ## BB#0: +; AVX12-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm1 +; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrb $15, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $14, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $13, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $12, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $11, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $10, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $9, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $8, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $7, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $6, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $5, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $4, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $3, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $2, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $1, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrb $0, %xmm0, %eax +; AVX12-NEXT: andb $1, %al +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax +; AVX12-NEXT: retq +; +; AVX512-LABEL: v16i8: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtb %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtb %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: retq + %x0 = icmp sgt <16 x i8> %a, %b + %x1 = icmp sgt <16 x i8> %c, %d + %y = and <16 x i1> %x0, %x1 + %res = bitcast <16 x i1> %y to i16 + ret i16 %res +} + +define i2 @v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) { +; SSE2-SSSE3-LABEL: v2i8: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: psllq $56, %xmm2 +; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $24, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1] +; SSE2-SSSE3-NEXT: psllq $56, %xmm3 +; SSE2-SSSE3-NEXT: movdqa %xmm3, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $24, %xmm3 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] +; SSE2-SSSE3-NEXT: psllq $56, %xmm0 +; SSE2-SSSE3-NEXT: movdqa %xmm0, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $24, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1] +; SSE2-SSSE3-NEXT: psllq $56, %xmm1 +; SSE2-SSSE3-NEXT: movdqa %xmm1, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $24, %xmm1 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1] +; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,0,2147483648,0] +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm1 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm0 +; SSE2-SSSE3-NEXT: movdqa %xmm0, %xmm5 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm5 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm6, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm3 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm2 +; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm4, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX1-LABEL: v2i8: +; AVX1: ## BB#0: +; AVX1-NEXT: vpsllq $56, %xmm3, %xmm3 +; AVX1-NEXT: vpsrad $31, %xmm3, %xmm4 +; AVX1-NEXT: vpsrad $24, %xmm3, %xmm3 +; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $56, %xmm2, %xmm2 +; AVX1-NEXT: vpsrad $31, %xmm2, %xmm4 +; AVX1-NEXT: vpsrad $24, %xmm2, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $56, %xmm1, %xmm1 +; AVX1-NEXT: vpsrad $31, %xmm1, %xmm4 +; AVX1-NEXT: vpsrad $24, %xmm1, %xmm1 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm4[2,3],xmm1[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $56, %xmm0, %xmm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm4 +; AVX1-NEXT: vpsrad $24, %xmm0, %xmm0 +; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7] +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpextrq $1, %xmm0, %rax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX1-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX1-NEXT: retq +; +; AVX2-LABEL: v2i8: +; AVX2: ## BB#0: +; AVX2-NEXT: vpsllq $56, %xmm3, %xmm3 +; AVX2-NEXT: vpsrad $31, %xmm3, %xmm4 +; AVX2-NEXT: vpsrad $24, %xmm3, %xmm3 +; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2],xmm4[3] +; AVX2-NEXT: vpsllq $56, %xmm2, %xmm2 +; AVX2-NEXT: vpsrad $31, %xmm2, %xmm4 +; AVX2-NEXT: vpsrad $24, %xmm2, %xmm2 +; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0],xmm4[1],xmm2[2],xmm4[3] +; AVX2-NEXT: vpsllq $56, %xmm1, %xmm1 +; AVX2-NEXT: vpsrad $31, %xmm1, %xmm4 +; AVX2-NEXT: vpsrad $24, %xmm1, %xmm1 +; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm4[1],xmm1[2],xmm4[3] +; AVX2-NEXT: vpsllq $56, %xmm0, %xmm0 +; AVX2-NEXT: vpsrad $31, %xmm0, %xmm4 +; AVX2-NEXT: vpsrad $24, %xmm0, %xmm0 +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm4[1],xmm0[2],xmm4[3] +; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX2-NEXT: retq +; +; AVX512-LABEL: v2i8: +; AVX512: ## BB#0: +; AVX512-NEXT: vpsllq $56, %xmm3, %xmm3 +; AVX512-NEXT: vpsraq $56, %xmm3, %xmm3 +; AVX512-NEXT: vpsllq $56, %xmm2, %xmm2 +; AVX512-NEXT: vpsraq $56, %xmm2, %xmm2 +; AVX512-NEXT: vpsllq $56, %xmm1, %xmm1 +; AVX512-NEXT: vpsraq $56, %xmm1, %xmm1 +; AVX512-NEXT: vpsllq $56, %xmm0, %xmm0 +; AVX512-NEXT: vpsraq $56, %xmm0, %xmm0 +; AVX512-NEXT: vpcmpgtq %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtq %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = icmp sgt <2 x i8> %a, %b + %x1 = icmp sgt <2 x i8> %c, %d + %y = and <2 x i1> %x0, %x1 + %res = bitcast <2 x i1> %y to i2 + ret i2 %res +} + +define i2 @v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d) { +; SSE2-SSSE3-LABEL: v2i16: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: psllq $48, %xmm2 +; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $16, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1] +; SSE2-SSSE3-NEXT: psllq $48, %xmm3 +; SSE2-SSSE3-NEXT: movdqa %xmm3, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $16, %xmm3 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] +; SSE2-SSSE3-NEXT: psllq $48, %xmm0 +; SSE2-SSSE3-NEXT: movdqa %xmm0, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $16, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1] +; SSE2-SSSE3-NEXT: psllq $48, %xmm1 +; SSE2-SSSE3-NEXT: movdqa %xmm1, %xmm4 +; SSE2-SSSE3-NEXT: psrad $31, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $16, %xmm1 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1] +; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,0,2147483648,0] +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm1 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm0 +; SSE2-SSSE3-NEXT: movdqa %xmm0, %xmm5 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm5 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm6, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm3 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm2 +; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm4, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX1-LABEL: v2i16: +; AVX1: ## BB#0: +; AVX1-NEXT: vpsllq $48, %xmm3, %xmm3 +; AVX1-NEXT: vpsrad $31, %xmm3, %xmm4 +; AVX1-NEXT: vpsrad $16, %xmm3, %xmm3 +; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $48, %xmm2, %xmm2 +; AVX1-NEXT: vpsrad $31, %xmm2, %xmm4 +; AVX1-NEXT: vpsrad $16, %xmm2, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $48, %xmm1, %xmm1 +; AVX1-NEXT: vpsrad $31, %xmm1, %xmm4 +; AVX1-NEXT: vpsrad $16, %xmm1, %xmm1 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm4[2,3],xmm1[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $48, %xmm0, %xmm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm4 +; AVX1-NEXT: vpsrad $16, %xmm0, %xmm0 +; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7] +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpextrq $1, %xmm0, %rax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX1-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX1-NEXT: retq +; +; AVX2-LABEL: v2i16: +; AVX2: ## BB#0: +; AVX2-NEXT: vpsllq $48, %xmm3, %xmm3 +; AVX2-NEXT: vpsrad $31, %xmm3, %xmm4 +; AVX2-NEXT: vpsrad $16, %xmm3, %xmm3 +; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2],xmm4[3] +; AVX2-NEXT: vpsllq $48, %xmm2, %xmm2 +; AVX2-NEXT: vpsrad $31, %xmm2, %xmm4 +; AVX2-NEXT: vpsrad $16, %xmm2, %xmm2 +; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0],xmm4[1],xmm2[2],xmm4[3] +; AVX2-NEXT: vpsllq $48, %xmm1, %xmm1 +; AVX2-NEXT: vpsrad $31, %xmm1, %xmm4 +; AVX2-NEXT: vpsrad $16, %xmm1, %xmm1 +; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm4[1],xmm1[2],xmm4[3] +; AVX2-NEXT: vpsllq $48, %xmm0, %xmm0 +; AVX2-NEXT: vpsrad $31, %xmm0, %xmm4 +; AVX2-NEXT: vpsrad $16, %xmm0, %xmm0 +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm4[1],xmm0[2],xmm4[3] +; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX2-NEXT: retq +; +; AVX512-LABEL: v2i16: +; AVX512: ## BB#0: +; AVX512-NEXT: vpsllq $48, %xmm3, %xmm3 +; AVX512-NEXT: vpsraq $48, %xmm3, %xmm3 +; AVX512-NEXT: vpsllq $48, %xmm2, %xmm2 +; AVX512-NEXT: vpsraq $48, %xmm2, %xmm2 +; AVX512-NEXT: vpsllq $48, %xmm1, %xmm1 +; AVX512-NEXT: vpsraq $48, %xmm1, %xmm1 +; AVX512-NEXT: vpsllq $48, %xmm0, %xmm0 +; AVX512-NEXT: vpsraq $48, %xmm0, %xmm0 +; AVX512-NEXT: vpcmpgtq %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtq %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = icmp sgt <2 x i16> %a, %b + %x1 = icmp sgt <2 x i16> %c, %d + %y = and <2 x i1> %x0, %x1 + %res = bitcast <2 x i1> %y to i2 + ret i2 %res +} + +define i2 @v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) { +; SSE2-SSSE3-LABEL: v2i32: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: psllq $32, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $31, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] +; SSE2-SSSE3-NEXT: psllq $32, %xmm3 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $31, %xmm3 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE2-SSSE3-NEXT: psllq $32, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $31, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1] +; SSE2-SSSE3-NEXT: psllq $32, %xmm1 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,3,2,3] +; SSE2-SSSE3-NEXT: psrad $31, %xmm1 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] +; SSE2-SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,0,2147483648,0] +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: movdqa %xmm3, %xmm5 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm0, %xmm5 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm0, %xmm3 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm6, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm5[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm0, %xmm3 +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm2 +; SSE2-SSSE3-NEXT: pxor %xmm1, %xmm4 +; SSE2-SSSE3-NEXT: movdqa %xmm4, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm2, %xmm4 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm1, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pand %xmm3, %xmm0 +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX1-LABEL: v2i32: +; AVX1: ## BB#0: +; AVX1-NEXT: vpsllq $32, %xmm3, %xmm3 +; AVX1-NEXT: vpsrad $31, %xmm3, %xmm4 +; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $32, %xmm2, %xmm2 +; AVX1-NEXT: vpsrad $31, %xmm2, %xmm4 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $32, %xmm1, %xmm1 +; AVX1-NEXT: vpsrad $31, %xmm1, %xmm4 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm4[2,3],xmm1[4,5],xmm4[6,7] +; AVX1-NEXT: vpsllq $32, %xmm0, %xmm0 +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm4 +; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7] +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpextrq $1, %xmm0, %rax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: andl $1, %eax +; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX1-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX1-NEXT: retq +; +; AVX2-LABEL: v2i32: +; AVX2: ## BB#0: +; AVX2-NEXT: vpsllq $32, %xmm3, %xmm3 +; AVX2-NEXT: vpsrad $31, %xmm3, %xmm4 +; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2],xmm4[3] +; AVX2-NEXT: vpsllq $32, %xmm2, %xmm2 +; AVX2-NEXT: vpsrad $31, %xmm2, %xmm4 +; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0],xmm4[1],xmm2[2],xmm4[3] +; AVX2-NEXT: vpsllq $32, %xmm1, %xmm1 +; AVX2-NEXT: vpsrad $31, %xmm1, %xmm4 +; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm4[1],xmm1[2],xmm4[3] +; AVX2-NEXT: vpsllq $32, %xmm0, %xmm0 +; AVX2-NEXT: vpsrad $31, %xmm0, %xmm4 +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm4[1],xmm0[2],xmm4[3] +; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrq $1, %xmm0, %rax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vmovq %xmm0, %rax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX2-NEXT: retq +; +; AVX512-LABEL: v2i32: +; AVX512: ## BB#0: +; AVX512-NEXT: vpsllq $32, %xmm3, %xmm3 +; AVX512-NEXT: vpsraq $32, %xmm3, %xmm3 +; AVX512-NEXT: vpsllq $32, %xmm2, %xmm2 +; AVX512-NEXT: vpsraq $32, %xmm2, %xmm2 +; AVX512-NEXT: vpsllq $32, %xmm1, %xmm1 +; AVX512-NEXT: vpsraq $32, %xmm1, %xmm1 +; AVX512-NEXT: vpsllq $32, %xmm0, %xmm0 +; AVX512-NEXT: vpsraq $32, %xmm0, %xmm0 +; AVX512-NEXT: vpcmpgtq %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtq %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = icmp sgt <2 x i32> %a, %b + %x1 = icmp sgt <2 x i32> %c, %d + %y = and <2 x i1> %x0, %x1 + %res = bitcast <2 x i1> %y to i2 + ret i2 %res +} + +define i2 @v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) { +; SSE2-SSSE3-LABEL: v2i64: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,0,2147483648,0] +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm1 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm0 +; SSE2-SSSE3-NEXT: movdqa %xmm0, %xmm5 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm5 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm6, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm3 +; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm2 +; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm0 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] +; SSE2-SSSE3-NEXT: pcmpeqd %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-SSSE3-NEXT: pand %xmm4, %xmm2 +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v2i64: +; AVX12: ## BB#0: +; AVX12-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 +; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrq $1, %xmm0, %rax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovq %xmm0, %rax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v2i64: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtq %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtq %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = icmp sgt <2 x i64> %a, %b + %x1 = icmp sgt <2 x i64> %c, %d + %y = and <2 x i1> %x0, %x1 + %res = bitcast <2 x i1> %y to i2 + ret i2 %res +} + +define i2 @v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { +; SSE2-SSSE3-LABEL: v2f64: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: cmpltpd %xmm0, %xmm1 +; SSE2-SSSE3-NEXT: cmpltpd %xmm2, %xmm3 +; SSE2-SSSE3-NEXT: andpd %xmm1, %xmm3 +; SSE2-SSSE3-NEXT: movq %xmm3, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,0,1] +; SSE2-SSSE3-NEXT: movq %xmm0, %rax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v2f64: +; AVX12: ## BB#0: +; AVX12-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0 +; AVX12-NEXT: vcmpltpd %xmm2, %xmm3, %xmm1 +; AVX12-NEXT: vandpd %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrq $1, %xmm0, %rax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovq %xmm0, %rax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v2f64: +; AVX512: ## BB#0: +; AVX512-NEXT: vcmpltpd %xmm0, %xmm1, %k1 +; AVX512-NEXT: vcmpltpd %xmm2, %xmm3, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = fcmp ogt <2 x double> %a, %b + %x1 = fcmp ogt <2 x double> %c, %d + %y = and <2 x i1> %x0, %x1 + %res = bitcast <2 x i1> %y to i2 + ret i2 %res +} + +define i4 @v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i8> %d) { +; SSE2-SSSE3-LABEL: v4i8: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: pslld $24, %xmm3 +; SSE2-SSSE3-NEXT: psrad $24, %xmm3 +; SSE2-SSSE3-NEXT: pslld $24, %xmm2 +; SSE2-SSSE3-NEXT: psrad $24, %xmm2 +; SSE2-SSSE3-NEXT: pslld $24, %xmm1 +; SSE2-SSSE3-NEXT: psrad $24, %xmm1 +; SSE2-SSSE3-NEXT: pslld $24, %xmm0 +; SSE2-SSSE3-NEXT: psrad $24, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: movd %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v4i8: +; AVX12: ## BB#0: +; AVX12-NEXT: vpslld $24, %xmm3, %xmm3 +; AVX12-NEXT: vpsrad $24, %xmm3, %xmm3 +; AVX12-NEXT: vpslld $24, %xmm2, %xmm2 +; AVX12-NEXT: vpsrad $24, %xmm2, %xmm2 +; AVX12-NEXT: vpslld $24, %xmm1, %xmm1 +; AVX12-NEXT: vpsrad $24, %xmm1, %xmm1 +; AVX12-NEXT: vpslld $24, %xmm0, %xmm0 +; AVX12-NEXT: vpsrad $24, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1 +; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrd $3, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $2, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $1, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovd %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v4i8: +; AVX512: ## BB#0: +; AVX512-NEXT: vpslld $24, %xmm3, %xmm3 +; AVX512-NEXT: vpsrad $24, %xmm3, %xmm3 +; AVX512-NEXT: vpslld $24, %xmm2, %xmm2 +; AVX512-NEXT: vpsrad $24, %xmm2, %xmm2 +; AVX512-NEXT: vpslld $24, %xmm1, %xmm1 +; AVX512-NEXT: vpsrad $24, %xmm1, %xmm1 +; AVX512-NEXT: vpslld $24, %xmm0, %xmm0 +; AVX512-NEXT: vpsrad $24, %xmm0, %xmm0 +; AVX512-NEXT: vpcmpgtd %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtd %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = icmp sgt <4 x i8> %a, %b + %x1 = icmp sgt <4 x i8> %c, %d + %y = and <4 x i1> %x0, %x1 + %res = bitcast <4 x i1> %y to i4 + ret i4 %res +} + +define i4 @v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) { +; SSE2-SSSE3-LABEL: v4i16: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: pslld $16, %xmm3 +; SSE2-SSSE3-NEXT: psrad $16, %xmm3 +; SSE2-SSSE3-NEXT: pslld $16, %xmm2 +; SSE2-SSSE3-NEXT: psrad $16, %xmm2 +; SSE2-SSSE3-NEXT: pslld $16, %xmm1 +; SSE2-SSSE3-NEXT: psrad $16, %xmm1 +; SSE2-SSSE3-NEXT: pslld $16, %xmm0 +; SSE2-SSSE3-NEXT: psrad $16, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: movd %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,2,3] +; SSE2-SSSE3-NEXT: movd %xmm0, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v4i16: +; AVX12: ## BB#0: +; AVX12-NEXT: vpslld $16, %xmm3, %xmm3 +; AVX12-NEXT: vpsrad $16, %xmm3, %xmm3 +; AVX12-NEXT: vpslld $16, %xmm2, %xmm2 +; AVX12-NEXT: vpsrad $16, %xmm2, %xmm2 +; AVX12-NEXT: vpslld $16, %xmm1, %xmm1 +; AVX12-NEXT: vpsrad $16, %xmm1, %xmm1 +; AVX12-NEXT: vpslld $16, %xmm0, %xmm0 +; AVX12-NEXT: vpsrad $16, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1 +; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrd $3, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $2, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrd $1, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovd %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v4i16: +; AVX512: ## BB#0: +; AVX512-NEXT: vpslld $16, %xmm3, %xmm3 +; AVX512-NEXT: vpsrad $16, %xmm3, %xmm3 +; AVX512-NEXT: vpslld $16, %xmm2, %xmm2 +; AVX512-NEXT: vpsrad $16, %xmm2, %xmm2 +; AVX512-NEXT: vpslld $16, %xmm1, %xmm1 +; AVX512-NEXT: vpsrad $16, %xmm1, %xmm1 +; AVX512-NEXT: vpslld $16, %xmm0, %xmm0 +; AVX512-NEXT: vpsrad $16, %xmm0, %xmm0 +; AVX512-NEXT: vpcmpgtd %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtd %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: retq + %x0 = icmp sgt <4 x i16> %a, %b + %x1 = icmp sgt <4 x i16> %c, %d + %y = and <4 x i1> %x0, %x1 + %res = bitcast <4 x i1> %y to i4 + ret i4 %res +} + +define i8 @v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) { +; SSE2-SSSE3-LABEL: v8i8: +; SSE2-SSSE3: ## BB#0: +; SSE2-SSSE3-NEXT: psllw $8, %xmm3 +; SSE2-SSSE3-NEXT: psraw $8, %xmm3 +; SSE2-SSSE3-NEXT: psllw $8, %xmm2 +; SSE2-SSSE3-NEXT: psraw $8, %xmm2 +; SSE2-SSSE3-NEXT: psllw $8, %xmm1 +; SSE2-SSSE3-NEXT: psraw $8, %xmm1 +; SSE2-SSSE3-NEXT: psllw $8, %xmm0 +; SSE2-SSSE3-NEXT: psraw $8, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 +; SSE2-SSSE3-NEXT: pcmpgtw %xmm3, %xmm2 +; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 +; SSE2-SSSE3-NEXT: pextrw $7, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $6, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $5, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $4, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $3, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $2, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: pextrw $1, %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movd %xmm2, %eax +; SSE2-SSSE3-NEXT: andl $1, %eax +; SSE2-SSSE3-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; SSE2-SSSE3-NEXT: movb -{{[0-9]+}}(%rsp), %al +; SSE2-SSSE3-NEXT: retq +; +; AVX12-LABEL: v8i8: +; AVX12: ## BB#0: +; AVX12-NEXT: vpsllw $8, %xmm3, %xmm3 +; AVX12-NEXT: vpsraw $8, %xmm3, %xmm3 +; AVX12-NEXT: vpsllw $8, %xmm2, %xmm2 +; AVX12-NEXT: vpsraw $8, %xmm2, %xmm2 +; AVX12-NEXT: vpsllw $8, %xmm1, %xmm1 +; AVX12-NEXT: vpsraw $8, %xmm1, %xmm1 +; AVX12-NEXT: vpsllw $8, %xmm0, %xmm0 +; AVX12-NEXT: vpsraw $8, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpcmpgtw %xmm3, %xmm2, %xmm1 +; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX12-NEXT: vpextrw $7, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $6, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $5, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $4, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $3, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $2, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vpextrw $1, %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: vmovd %xmm0, %eax +; AVX12-NEXT: andl $1, %eax +; AVX12-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX12-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX12-NEXT: retq +; +; AVX512-LABEL: v8i8: +; AVX512: ## BB#0: +; AVX512-NEXT: vpsllw $8, %xmm3, %xmm3 +; AVX512-NEXT: vpsraw $8, %xmm3, %xmm3 +; AVX512-NEXT: vpsllw $8, %xmm2, %xmm2 +; AVX512-NEXT: vpsraw $8, %xmm2, %xmm2 +; AVX512-NEXT: vpsllw $8, %xmm1, %xmm1 +; AVX512-NEXT: vpsraw $8, %xmm1, %xmm1 +; AVX512-NEXT: vpsllw $8, %xmm0, %xmm0 +; AVX512-NEXT: vpsraw $8, %xmm0, %xmm0 +; AVX512-NEXT: vpcmpgtw %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpgtw %xmm3, %xmm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: retq + %x0 = icmp sgt <8 x i8> %a, %b + %x1 = icmp sgt <8 x i8> %c, %d + %y = and <8 x i1> %x0, %x1 + %res = bitcast <8 x i1> %y to i8 + ret i8 %res +} diff --git a/test/CodeGen/X86/bitcast-and-setcc-256.ll b/test/CodeGen/X86/bitcast-and-setcc-256.ll new file mode 100644 index 0000000000000..06b1a76f6baed --- /dev/null +++ b/test/CodeGen/X86/bitcast-and-setcc-256.ll @@ -0,0 +1,403 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx2 < %s | FileCheck %s --check-prefix=AVX2 +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=x86-64 -mattr=+avx512f,+avx512vl,+avx512bw < %s | FileCheck %s --check-prefix=AVX512 + +define i4 @v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i64> %d) { +; AVX2-LABEL: v4i64: +; AVX2: ## BB#0: +; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm1 +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrd $3, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrd $2, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrd $1, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: v4i64: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %k1 +; AVX512-NEXT: vpcmpgtq %ymm3, %ymm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %x0 = icmp sgt <4 x i64> %a, %b + %x1 = icmp sgt <4 x i64> %c, %d + %y = and <4 x i1> %x0, %x1 + %res = bitcast <4 x i1> %y to i4 + ret i4 %res +} + +define i4 @v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x double> %d) { +; AVX2-LABEL: v4f64: +; AVX2: ## BB#0: +; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vcmpltpd %ymm2, %ymm3, %ymm1 +; AVX2-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrd $3, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrd $2, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrd $1, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: v4f64: +; AVX512: ## BB#0: +; AVX512-NEXT: vcmpltpd %ymm0, %ymm1, %k1 +; AVX512-NEXT: vcmpltpd %ymm2, %ymm3, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX512-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %x0 = fcmp ogt <4 x double> %a, %b + %x1 = fcmp ogt <4 x double> %c, %d + %y = and <4 x i1> %x0, %x1 + %res = bitcast <4 x i1> %y to i4 + ret i4 %res +} + +define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) { +; AVX2-LABEL: v16i16: +; AVX2: ## BB#0: +; AVX2-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtw %ymm3, %ymm2, %ymm1 +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrb $15, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $14, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $13, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $12, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $11, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $10, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $9, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $8, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $7, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $6, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $5, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $4, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $3, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $2, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $1, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrb $0, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: v16i16: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtw %ymm1, %ymm0, %k1 +; AVX512-NEXT: vpcmpgtw %ymm3, %ymm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %x0 = icmp sgt <16 x i16> %a, %b + %x1 = icmp sgt <16 x i16> %c, %d + %y = and <16 x i1> %x0, %x1 + %res = bitcast <16 x i1> %y to i16 + ret i16 %res +} + +define i8 @v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { +; AVX2-LABEL: v8i32: +; AVX2: ## BB#0: +; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtd %ymm3, %ymm2, %ymm1 +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrw $7, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $6, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $5, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $4, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $3, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $2, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $1, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: v8i32: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %k1 +; AVX512-NEXT: vpcmpgtd %ymm3, %ymm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %x0 = icmp sgt <8 x i32> %a, %b + %x1 = icmp sgt <8 x i32> %c, %d + %y = and <8 x i1> %x0, %x1 + %res = bitcast <8 x i1> %y to i8 + ret i8 %res +} + +define i8 @v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) { +; AVX2-LABEL: v8f32: +; AVX2: ## BB#0: +; AVX2-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vcmpltps %ymm2, %ymm3, %ymm1 +; AVX2-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpextrw $7, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $6, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $5, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $4, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $3, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $2, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vpextrw $1, %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: vmovd %xmm0, %eax +; AVX2-NEXT: andl $1, %eax +; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX2-NEXT: movb -{{[0-9]+}}(%rsp), %al +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: v8f32: +; AVX512: ## BB#0: +; AVX512-NEXT: vcmpltps %ymm0, %ymm1, %k1 +; AVX512-NEXT: vcmpltps %ymm2, %ymm3, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %x0 = fcmp ogt <8 x float> %a, %b + %x1 = fcmp ogt <8 x float> %c, %d + %y = and <8 x i1> %x0, %x1 + %res = bitcast <8 x i1> %y to i8 + ret i8 %res +} + +define i32 @v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i8> %d) { +; AVX2-LABEL: v32i8: +; AVX2: ## BB#0: +; AVX2-NEXT: pushq %rbp +; AVX2-NEXT: Lcfi0: +; AVX2-NEXT: .cfi_def_cfa_offset 16 +; AVX2-NEXT: Lcfi1: +; AVX2-NEXT: .cfi_offset %rbp, -16 +; AVX2-NEXT: movq %rsp, %rbp +; AVX2-NEXT: Lcfi2: +; AVX2-NEXT: .cfi_def_cfa_register %rbp +; AVX2-NEXT: andq $-32, %rsp +; AVX2-NEXT: subq $32, %rsp +; AVX2-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpcmpgtb %ymm3, %ymm2, %ymm1 +; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpextrb $15, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $14, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $13, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $12, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $11, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $10, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $9, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $8, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $7, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $6, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $5, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $4, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $3, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $2, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $1, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $0, %xmm1, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $15, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $14, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $13, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $12, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $11, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $10, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $9, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $8, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $7, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $6, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $5, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $4, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $3, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $2, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $1, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: vpextrb $0, %xmm0, %eax +; AVX2-NEXT: andb $1, %al +; AVX2-NEXT: movb %al, (%rsp) +; AVX2-NEXT: movl (%rsp), %eax +; AVX2-NEXT: movq %rbp, %rsp +; AVX2-NEXT: popq %rbp +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: v32i8: +; AVX512: ## BB#0: +; AVX512-NEXT: vpcmpgtb %ymm1, %ymm0, %k1 +; AVX512-NEXT: vpcmpgtb %ymm3, %ymm2, %k0 {%k1} +; AVX512-NEXT: kmovd %k0, %eax +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %x0 = icmp sgt <32 x i8> %a, %b + %x1 = icmp sgt <32 x i8> %c, %d + %y = and <32 x i1> %x0, %x1 + %res = bitcast <32 x i1> %y to i32 + ret i32 %res +} diff --git a/test/CodeGen/X86/mul-constant-i16.ll b/test/CodeGen/X86/mul-constant-i16.ll index e3e2737cf3e62..6d2465ddd3a87 100644 --- a/test/CodeGen/X86/mul-constant-i16.ll +++ b/test/CodeGen/X86/mul-constant-i16.ll @@ -188,13 +188,16 @@ define i16 @test_mul_by_11(i16 %x) { ; X86-LABEL: test_mul_by_11: ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $11, %eax, %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: leal (%eax,%ecx,2), %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_11: ; X64: # BB#0: -; X64-NEXT: imull $11, %edi, %eax +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,4), %eax +; X64-NEXT: leal (%rdi,%rax,2), %eax ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 11 @@ -225,13 +228,16 @@ define i16 @test_mul_by_13(i16 %x) { ; X86-LABEL: test_mul_by_13: ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $13, %eax, %eax +; X86-NEXT: leal (%eax,%eax,2), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_13: ; X64: # BB#0: -; X64-NEXT: imull $13, %edi, %eax +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,2), %eax +; X64-NEXT: leal (%rdi,%rax,4), %eax ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 13 @@ -241,14 +247,19 @@ define i16 @test_mul_by_13(i16 %x) { define i16 @test_mul_by_14(i16 %x) { ; X86-LABEL: test_mul_by_14: ; X86: # BB#0: -; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $14, %eax, %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,2), %eax +; X86-NEXT: leal (%ecx,%eax,4), %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_14: ; X64: # BB#0: -; X64-NEXT: imull $14, %edi, %eax +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,2), %eax +; X64-NEXT: leal (%rdi,%rax,4), %eax +; X64-NEXT: addl %edi, %eax ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 14 @@ -338,14 +349,19 @@ define i16 @test_mul_by_19(i16 %x) { ; X86-LABEL: test_mul_by_19: ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $19, %eax, %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: shll $2, %ecx +; X86-NEXT: subl %ecx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_19: ; X64: # BB#0: -; X64-NEXT: imull $19, %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,4), %eax +; X64-NEXT: shll $2, %eax +; X64-NEXT: subl %eax, %edi +; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq %mul = mul nsw i16 %x, 19 ret i16 %mul @@ -375,13 +391,16 @@ define i16 @test_mul_by_21(i16 %x) { ; X86-LABEL: test_mul_by_21: ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $21, %eax, %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_21: ; X64: # BB#0: -; X64-NEXT: imull $21, %edi, %eax +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,4), %eax +; X64-NEXT: leal (%rdi,%rax,4), %eax ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 21 @@ -391,14 +410,19 @@ define i16 @test_mul_by_21(i16 %x) { define i16 @test_mul_by_22(i16 %x) { ; X86-LABEL: test_mul_by_22: ; X86: # BB#0: -; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $22, %eax, %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,4), %eax +; X86-NEXT: leal (%ecx,%eax,4), %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_22: ; X64: # BB#0: -; X64-NEXT: imull $22, %edi, %eax +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,4), %eax +; X64-NEXT: leal (%rdi,%rax,4), %eax +; X64-NEXT: addl %edi, %eax ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 22 @@ -409,14 +433,19 @@ define i16 @test_mul_by_23(i16 %x) { ; X86-LABEL: test_mul_by_23: ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $23, %eax, %eax +; X86-NEXT: leal (%eax,%eax,2), %ecx +; X86-NEXT: shll $3, %ecx +; X86-NEXT: subl %ecx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_23: ; X64: # BB#0: -; X64-NEXT: imull $23, %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,2), %eax +; X64-NEXT: shll $3, %eax +; X64-NEXT: subl %eax, %edi +; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq %mul = mul nsw i16 %x, 23 ret i16 %mul @@ -466,14 +495,19 @@ define i16 @test_mul_by_26(i16 %x) { ; X86-LABEL: test_mul_by_26: ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $26, %eax, %eax +; X86-NEXT: leal (%eax,%eax,8), %ecx +; X86-NEXT: leal (%ecx,%ecx,2), %ecx +; X86-NEXT: subl %ecx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_26: ; X64: # BB#0: -; X64-NEXT: imull $26, %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,8), %eax +; X64-NEXT: leal (%rax,%rax,2), %eax +; X64-NEXT: subl %eax, %edi +; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq %mul = mul nsw i16 %x, 26 ret i16 %mul @@ -502,14 +536,19 @@ define i16 @test_mul_by_27(i16 %x) { define i16 @test_mul_by_28(i16 %x) { ; X86-LABEL: test_mul_by_28: ; X86: # BB#0: -; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $28, %eax, %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,8), %eax +; X86-NEXT: leal (%eax,%eax,2), %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_28: ; X64: # BB#0: -; X64-NEXT: imull $28, %edi, %eax +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,8), %eax +; X64-NEXT: leal (%rax,%rax,2), %eax +; X64-NEXT: addl %edi, %eax ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 28 @@ -519,14 +558,21 @@ define i16 @test_mul_by_28(i16 %x) { define i16 @test_mul_by_29(i16 %x) { ; X86-LABEL: test_mul_by_29: ; X86: # BB#0: -; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $29, %eax, %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,8), %eax +; X86-NEXT: leal (%eax,%eax,2), %eax +; X86-NEXT: addl %ecx, %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_29: ; X64: # BB#0: -; X64-NEXT: imull $29, %edi, %eax +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal (%rdi,%rdi,8), %eax +; X64-NEXT: leal (%rax,%rax,2), %eax +; X64-NEXT: addl %edi, %eax +; X64-NEXT: addl %edi, %eax ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 29 @@ -537,14 +583,22 @@ define i16 @test_mul_by_30(i16 %x) { ; X86-LABEL: test_mul_by_30: ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: imull $30, %eax, %eax +; X86-NEXT: movl %eax, %ecx +; X86-NEXT: shll $5, %ecx +; X86-NEXT: movl %eax, %edx +; X86-NEXT: subl %ecx, %edx +; X86-NEXT: subl %edx, %eax ; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_30: ; X64: # BB#0: -; X64-NEXT: imull $30, %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: movl %edi, %eax +; X64-NEXT: shll $5, %eax +; X64-NEXT: movl %edi, %ecx +; X64-NEXT: subl %eax, %ecx +; X64-NEXT: subl %ecx, %edi +; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq %mul = mul nsw i16 %x, 30 ret i16 %mul @@ -587,3 +641,30 @@ define i16 @test_mul_by_32(i16 %x) { %mul = mul nsw i16 %x, 32 ret i16 %mul } + +; (x*9+42)*(x*5+2) +define i16 @test_mul_spec(i16 %x) nounwind { +; X86-LABEL: test_mul_spec: +; X86: # BB#0: +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal 42(%eax,%eax,8), %ecx +; X86-NEXT: leal 2(%eax,%eax,4), %eax +; X86-NEXT: imull %ecx, %eax +; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: retl +; +; X64-LABEL: test_mul_spec: +; X64: # BB#0: +; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: leal 42(%rdi,%rdi,8), %ecx +; X64-NEXT: leal 2(%rdi,%rdi,4), %eax +; X64-NEXT: imull %ecx, %eax +; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: retq + %mul = mul nsw i16 %x, 9 + %add = add nsw i16 %mul, 42 + %mul2 = mul nsw i16 %x, 5 + %add2 = add nsw i16 %mul2, 2 + %mul3 = mul nsw i16 %add, %add2 + ret i16 %mul3 +} diff --git a/test/CodeGen/X86/mul-constant-i32.ll b/test/CodeGen/X86/mul-constant-i32.ll index 76e46e1f1b09e..b1e9a929b7f26 100644 --- a/test/CodeGen/X86/mul-constant-i32.ll +++ b/test/CodeGen/X86/mul-constant-i32.ll @@ -1,6 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86 -; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule=true -mcpu=haswell| FileCheck %s --check-prefix=X64-HSW +; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule=true -mcpu=btver2| FileCheck %s --check-prefix=X64-JAG +; RUN: llc < %s -mtriple=i686-unknown -mul-constant-optimization=false | FileCheck %s --check-prefix=X86-NOOPT +; RUN: llc < %s -mtriple=x86_64-unknown -mul-constant-optimization=false -print-schedule=true -mcpu=haswell| FileCheck %s --check-prefix=HSW-NOOPT +; RUN: llc < %s -mtriple=x86_64-unknown -mul-constant-optimization=false -print-schedule=true -mcpu=btver2| FileCheck %s --check-prefix=JAG-NOOPT +; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule=true -mcpu=slm| FileCheck %s --check-prefix=X64-SLM +; RUN: llc < %s -mtriple=x86_64-unknown -mul-constant-optimization=false -print-schedule=true -mcpu=slm| FileCheck %s --check-prefix=SLM-NOOPT define i32 @test_mul_by_1(i32 %x) { ; X86-LABEL: test_mul_by_1: @@ -8,10 +14,40 @@ define i32 @test_mul_by_1(i32 %x) { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_1: -; X64: # BB#0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_1: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_1: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_1: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_1: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.25] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_1: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.17] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_1: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: movl %edi, %eax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_1: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.50] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 1 ret i32 %mul } @@ -23,11 +59,47 @@ define i32 @test_mul_by_2(i32 %x) { ; X86-NEXT: addl %eax, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_2: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (%rdi,%rdi), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_2: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_2: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_2: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: addl %eax, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_2: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_2: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_2: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (%rdi,%rdi), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_2: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: leal (%rdi,%rdi), %eax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 2 ret i32 %mul } @@ -38,11 +110,46 @@ define i32 @test_mul_by_3(i32 %x) { ; X86-NEXT: imull $3, {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_3: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_3: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_3: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_3: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $3, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_3: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_3: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_3: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_3: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 3 ret i32 %mul } @@ -54,11 +161,47 @@ define i32 @test_mul_by_4(i32 %x) { ; X86-NEXT: shll $2, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_4: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (,%rdi,4), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_4: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_4: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_4: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: shll $2, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_4: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_4: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_4: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_4: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: leal (,%rdi,4), %eax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 4 ret i32 %mul } @@ -69,11 +212,46 @@ define i32 @test_mul_by_5(i32 %x) { ; X86-NEXT: imull $5, {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_5: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_5: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_5: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_5: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $5, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_5: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_5: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_5: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_5: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 5 ret i32 %mul } @@ -86,12 +264,46 @@ define i32 @test_mul_by_6(i32 %x) { ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_6: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: addl %edi, %edi -; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_6: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: addl %edi, %edi # sched: [1:0.25] +; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_6: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_6: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $6, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_6: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $6, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_6: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $6, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_6: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_6: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $6, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 6 ret i32 %mul } @@ -104,12 +316,46 @@ define i32 @test_mul_by_7(i32 %x) { ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_7: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (,%rdi,8), %eax -; X64-NEXT: subl %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_7: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: subl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_7: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: subl %edi, %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_7: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $7, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_7: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $7, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_7: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $7, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_7: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (,%rdi,8), %eax # sched: [1:1.00] +; X64-SLM-NEXT: subl %edi, %eax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_7: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $7, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 7 ret i32 %mul } @@ -121,11 +367,47 @@ define i32 @test_mul_by_8(i32 %x) { ; X86-NEXT: shll $3, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_8: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (,%rdi,8), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_8: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_8: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_8: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: shll $3, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_8: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_8: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_8: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (,%rdi,8), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_8: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: leal (,%rdi,8), %eax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 8 ret i32 %mul } @@ -136,11 +418,46 @@ define i32 @test_mul_by_9(i32 %x) { ; X86-NEXT: imull $9, {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_9: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (%rdi,%rdi,8), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_9: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_9: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_9: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $9, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_9: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_9: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_9: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_9: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 9 ret i32 %mul } @@ -153,12 +470,46 @@ define i32 @test_mul_by_10(i32 %x) { ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_10: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: addl %edi, %edi -; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_10: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: addl %edi, %edi # sched: [1:0.25] +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_10: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_10: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $10, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_10: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $10, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_10: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $10, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_10: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_10: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $10, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 10 ret i32 %mul } @@ -166,13 +517,49 @@ define i32 @test_mul_by_10(i32 %x) { define i32 @test_mul_by_11(i32 %x) { ; X86-LABEL: test_mul_by_11: ; X86: # BB#0: -; X86-NEXT: imull $11, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: leal (%eax,%ecx,2), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_11: -; X64: # BB#0: -; X64-NEXT: imull $11, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_11: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rax,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_11: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rax,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_11: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $11, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_11: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $11, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_11: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $11, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_11: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $11, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_11: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $11, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 11 ret i32 %mul } @@ -185,12 +572,46 @@ define i32 @test_mul_by_12(i32 %x) { ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_12: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: shll $2, %edi -; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_12: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: shll $2, %edi # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_12: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: shll $2, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_12: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $12, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_12: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $12, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_12: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $12, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_12: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: shll $2, %edi # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_12: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $12, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 12 ret i32 %mul } @@ -198,13 +619,49 @@ define i32 @test_mul_by_12(i32 %x) { define i32 @test_mul_by_13(i32 %x) { ; X86-LABEL: test_mul_by_13: ; X86: # BB#0: -; X86-NEXT: imull $13, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,2), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_13: -; X64: # BB#0: -; X64-NEXT: imull $13, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_13: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_13: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_13: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $13, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_13: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $13, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_13: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $13, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_13: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $13, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_13: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $13, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 13 ret i32 %mul } @@ -212,13 +669,52 @@ define i32 @test_mul_by_13(i32 %x) { define i32 @test_mul_by_14(i32 %x) { ; X86-LABEL: test_mul_by_14: ; X86: # BB#0: -; X86-NEXT: imull $14, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,2), %eax +; X86-NEXT: leal (%ecx,%eax,4), %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_14: -; X64: # BB#0: -; X64-NEXT: imull $14, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_14: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_14: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_14: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $14, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_14: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $14, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_14: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $14, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_14: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $14, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_14: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $14, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 14 ret i32 %mul } @@ -231,12 +727,46 @@ define i32 @test_mul_by_15(i32 %x) { ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_15: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: leal (%rax,%rax,2), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_15: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_15: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_15: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $15, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_15: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $15, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_15: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $15, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_15: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rax,%rax,2), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_15: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $15, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 15 ret i32 %mul } @@ -248,11 +778,47 @@ define i32 @test_mul_by_16(i32 %x) { ; X86-NEXT: shll $4, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_16: -; X64: # BB#0: -; X64-NEXT: shll $4, %edi -; X64-NEXT: movl %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_16: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: shll $4, %edi # sched: [1:0.50] +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_16: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: shll $4, %edi # sched: [1:0.50] +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_16: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: shll $4, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_16: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: shll $4, %edi # sched: [1:0.50] +; HSW-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.25] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_16: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: shll $4, %edi # sched: [1:0.50] +; JAG-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.17] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_16: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: shll $4, %edi # sched: [1:1.00] +; X64-SLM-NEXT: movl %edi, %eax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_16: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: shll $4, %edi # sched: [1:1.00] +; SLM-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.50] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 16 ret i32 %mul } @@ -266,13 +832,49 @@ define i32 @test_mul_by_17(i32 %x) { ; X86-NEXT: addl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_17: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: movl %edi, %eax -; X64-NEXT: shll $4, %eax -; X64-NEXT: leal (%rax,%rdi), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_17: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: shll $4, %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rax,%rdi), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_17: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: shll $4, %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rax,%rdi), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_17: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $17, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_17: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $17, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_17: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $17, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_17: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: movl %edi, %eax # sched: [1:0.50] +; X64-SLM-NEXT: shll $4, %eax # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rax,%rdi), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_17: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $17, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 17 ret i32 %mul } @@ -285,12 +887,46 @@ define i32 @test_mul_by_18(i32 %x) { ; X86-NEXT: leal (%eax,%eax,8), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_18: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: addl %edi, %edi -; X64-NEXT: leal (%rdi,%rdi,8), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_18: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: addl %edi, %edi # sched: [1:0.25] +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_18: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_18: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $18, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_18: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $18, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_18: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $18, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_18: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-SLM-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_18: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $18, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 18 ret i32 %mul } @@ -298,13 +934,54 @@ define i32 @test_mul_by_18(i32 %x) { define i32 @test_mul_by_19(i32 %x) { ; X86-LABEL: test_mul_by_19: ; X86: # BB#0: -; X86-NEXT: imull $19, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: shll $2, %ecx +; X86-NEXT: subl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_19: -; X64: # BB#0: -; X64-NEXT: imull $19, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_19: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: shll $2, %eax # sched: [1:0.50] +; X64-HSW-NEXT: subl %eax, %edi # sched: [1:0.25] +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_19: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: shll $2, %eax # sched: [1:0.50] +; X64-JAG-NEXT: subl %eax, %edi # sched: [1:0.50] +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_19: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $19, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_19: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $19, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_19: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $19, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_19: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $19, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_19: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $19, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 19 ret i32 %mul } @@ -317,12 +994,46 @@ define i32 @test_mul_by_20(i32 %x) { ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_20: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: shll $2, %edi -; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_20: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: shll $2, %edi # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_20: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: shll $2, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_20: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $20, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_20: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $20, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_20: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $20, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_20: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: shll $2, %edi # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_20: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $20, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 20 ret i32 %mul } @@ -330,13 +1041,49 @@ define i32 @test_mul_by_20(i32 %x) { define i32 @test_mul_by_21(i32 %x) { ; X86-LABEL: test_mul_by_21: ; X86: # BB#0: -; X86-NEXT: imull $21, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_21: -; X64: # BB#0: -; X64-NEXT: imull $21, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_21: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_21: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_21: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $21, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_21: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $21, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_21: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $21, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_21: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $21, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_21: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $21, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 21 ret i32 %mul } @@ -344,13 +1091,52 @@ define i32 @test_mul_by_21(i32 %x) { define i32 @test_mul_by_22(i32 %x) { ; X86-LABEL: test_mul_by_22: ; X86: # BB#0: -; X86-NEXT: imull $22, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,4), %eax +; X86-NEXT: leal (%ecx,%eax,4), %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_22: -; X64: # BB#0: -; X64-NEXT: imull $22, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_22: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_22: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_22: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $22, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_22: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $22, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_22: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $22, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_22: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $22, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_22: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $22, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 22 ret i32 %mul } @@ -358,13 +1144,54 @@ define i32 @test_mul_by_22(i32 %x) { define i32 @test_mul_by_23(i32 %x) { ; X86-LABEL: test_mul_by_23: ; X86: # BB#0: -; X86-NEXT: imull $23, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,2), %ecx +; X86-NEXT: shll $3, %ecx +; X86-NEXT: subl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_23: -; X64: # BB#0: -; X64-NEXT: imull $23, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_23: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: shll $3, %eax # sched: [1:0.50] +; X64-HSW-NEXT: subl %eax, %edi # sched: [1:0.25] +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_23: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: shll $3, %eax # sched: [1:0.50] +; X64-JAG-NEXT: subl %eax, %edi # sched: [1:0.50] +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_23: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $23, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_23: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $23, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_23: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $23, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_23: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $23, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_23: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $23, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 23 ret i32 %mul } @@ -377,12 +1204,46 @@ define i32 @test_mul_by_24(i32 %x) { ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_24: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: shll $3, %edi -; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_24: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: shll $3, %edi # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_24: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: shll $3, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_24: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $24, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_24: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $24, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_24: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $24, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_24: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: shll $3, %edi # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_24: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $24, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 24 ret i32 %mul } @@ -395,12 +1256,46 @@ define i32 @test_mul_by_25(i32 %x) { ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_25: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: leal (%rax,%rax,4), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_25: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rax,%rax,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_25: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rax,%rax,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_25: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $25, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_25: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $25, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_25: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $25, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_25: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rax,%rax,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_25: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $25, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 25 ret i32 %mul } @@ -408,13 +1303,54 @@ define i32 @test_mul_by_25(i32 %x) { define i32 @test_mul_by_26(i32 %x) { ; X86-LABEL: test_mul_by_26: ; X86: # BB#0: -; X86-NEXT: imull $26, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,8), %ecx +; X86-NEXT: leal (%ecx,%ecx,2), %ecx +; X86-NEXT: subl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_26: -; X64: # BB#0: -; X64-NEXT: imull $26, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_26: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: subl %eax, %edi # sched: [1:0.25] +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_26: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: subl %eax, %edi # sched: [1:0.50] +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_26: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $26, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_26: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $26, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_26: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $26, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_26: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $26, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_26: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $26, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 26 ret i32 %mul } @@ -427,12 +1363,46 @@ define i32 @test_mul_by_27(i32 %x) { ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_27: -; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: leal (%rdi,%rdi,8), %eax -; X64-NEXT: leal (%rax,%rax,2), %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_27: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_27: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_27: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $27, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_27: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $27, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_27: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $27, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_27: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rax,%rax,2), %eax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_27: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $27, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 27 ret i32 %mul } @@ -440,13 +1410,52 @@ define i32 @test_mul_by_27(i32 %x) { define i32 @test_mul_by_28(i32 %x) { ; X86-LABEL: test_mul_by_28: ; X86: # BB#0: -; X86-NEXT: imull $28, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,8), %eax +; X86-NEXT: leal (%eax,%eax,2), %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_28: -; X64: # BB#0: -; X64-NEXT: imull $28, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_28: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_28: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_28: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $28, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_28: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $28, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_28: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $28, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_28: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $28, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_28: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $28, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 28 ret i32 %mul } @@ -454,13 +1463,55 @@ define i32 @test_mul_by_28(i32 %x) { define i32 @test_mul_by_29(i32 %x) { ; X86-LABEL: test_mul_by_29: ; X86: # BB#0: -; X86-NEXT: imull $29, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,8), %eax +; X86-NEXT: leal (%eax,%eax,2), %eax +; X86-NEXT: addl %ecx, %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_29: -; X64: # BB#0: -; X64-NEXT: imull $29, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_29: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_29: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] +; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] +; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_29: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $29, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_29: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $29, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_29: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $29, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_29: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $29, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_29: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $29, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 29 ret i32 %mul } @@ -468,13 +1519,58 @@ define i32 @test_mul_by_29(i32 %x) { define i32 @test_mul_by_30(i32 %x) { ; X86-LABEL: test_mul_by_30: ; X86: # BB#0: -; X86-NEXT: imull $30, {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl %eax, %ecx +; X86-NEXT: shll $5, %ecx +; X86-NEXT: movl %eax, %edx +; X86-NEXT: subl %ecx, %edx +; X86-NEXT: subl %edx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_30: -; X64: # BB#0: -; X64-NEXT: imull $30, %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_30: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: shll $5, %eax # sched: [1:0.50] +; X64-HSW-NEXT: movl %edi, %ecx # sched: [1:0.25] +; X64-HSW-NEXT: subl %eax, %ecx # sched: [1:0.25] +; X64-HSW-NEXT: subl %ecx, %edi # sched: [1:0.25] +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_30: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: movl %edi, %ecx # sched: [1:0.17] +; X64-JAG-NEXT: shll $5, %eax # sched: [1:0.50] +; X64-JAG-NEXT: subl %eax, %ecx # sched: [1:0.50] +; X64-JAG-NEXT: subl %ecx, %edi # sched: [1:0.50] +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_30: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $30, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_30: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $30, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_30: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $30, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_30: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imull $30, %edi, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_30: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $30, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 30 ret i32 %mul } @@ -488,12 +1584,46 @@ define i32 @test_mul_by_31(i32 %x) { ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_31: -; X64: # BB#0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: shll $5, %eax -; X64-NEXT: subl %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_31: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: shll $5, %eax # sched: [1:0.50] +; X64-HSW-NEXT: subl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_31: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: shll $5, %eax # sched: [1:0.50] +; X64-JAG-NEXT: subl %edi, %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_31: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: imull $31, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_31: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imull $31, %edi, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_31: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imull $31, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_31: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: movl %edi, %eax # sched: [1:0.50] +; X64-SLM-NEXT: shll $5, %eax # sched: [1:1.00] +; X64-SLM-NEXT: subl %edi, %eax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_31: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imull $31, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 31 ret i32 %mul } @@ -505,11 +1635,124 @@ define i32 @test_mul_by_32(i32 %x) { ; X86-NEXT: shll $5, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_32: -; X64: # BB#0: -; X64-NEXT: shll $5, %edi -; X64-NEXT: movl %edi, %eax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_32: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: shll $5, %edi # sched: [1:0.50] +; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_32: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: shll $5, %edi # sched: [1:0.50] +; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_32: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: shll $5, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_32: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: shll $5, %edi # sched: [1:0.50] +; HSW-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.25] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_32: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: shll $5, %edi # sched: [1:0.50] +; JAG-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.17] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_32: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: shll $5, %edi # sched: [1:1.00] +; X64-SLM-NEXT: movl %edi, %eax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_32: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: shll $5, %edi # sched: [1:1.00] +; SLM-NOOPT-NEXT: movl %edi, %eax # sched: [1:0.50] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 32 ret i32 %mul } + +; (x*9+42)*(x*5+2) +define i32 @test_mul_spec(i32 %x) nounwind { +; X86-LABEL: test_mul_spec: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal 42(%eax,%eax,8), %ecx +; X86-NEXT: leal 2(%eax,%eax,4), %eax +; X86-NEXT: imull %ecx, %eax +; X86-NEXT: retl +; +; X64-HSW-LABEL: test_mul_spec: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %ecx # sched: [1:0.50] +; X64-HSW-NEXT: addl $42, %ecx # sched: [1:0.25] +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: addl $2, %eax # sched: [1:0.25] +; X64-HSW-NEXT: imull %ecx, %eax # sched: [4:1.00] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_spec: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:0.50] +; X64-JAG-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-JAG-NEXT: imull %ecx, %eax # sched: [3:1.00] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_spec: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: leal 42(%eax,%eax,8), %ecx +; X86-NOOPT-NEXT: leal 2(%eax,%eax,4), %eax +; X86-NOOPT-NEXT: imull %ecx, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_spec: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: leal (%rdi,%rdi,8), %ecx # sched: [1:0.50] +; HSW-NOOPT-NEXT: addl $42, %ecx # sched: [1:0.25] +; HSW-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; HSW-NOOPT-NEXT: addl $2, %eax # sched: [1:0.25] +; HSW-NOOPT-NEXT: imull %ecx, %eax # sched: [4:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_spec: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:0.50] +; JAG-NOOPT-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:0.50] +; JAG-NOOPT-NEXT: imull %ecx, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_spec: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:1.00] +; X64-SLM-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: imull %ecx, %eax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_spec: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:1.00] +; SLM-NOOPT-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:1.00] +; SLM-NOOPT-NEXT: imull %ecx, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] + %mul = mul nsw i32 %x, 9 + %add = add nsw i32 %mul, 42 + %mul2 = mul nsw i32 %x, 5 + %add2 = add nsw i32 %mul2, 2 + %mul3 = mul nsw i32 %add, %add2 + ret i32 %mul3 +} diff --git a/test/CodeGen/X86/mul-constant-i64.ll b/test/CodeGen/X86/mul-constant-i64.ll index 8579179a82315..22eb0bdc6c3f8 100644 --- a/test/CodeGen/X86/mul-constant-i64.ll +++ b/test/CodeGen/X86/mul-constant-i64.ll @@ -1,18 +1,55 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86 -; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule=true -mcpu=haswell| FileCheck %s --check-prefix=X64-HSW +; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule=true -mcpu=btver2| FileCheck %s --check-prefix=X64-JAG +; RUN: llc < %s -mtriple=i686-unknown -mul-constant-optimization=false | FileCheck %s --check-prefix=X86-NOOPT +; RUN: llc < %s -mtriple=x86_64-unknown -mul-constant-optimization=false -print-schedule=true -mcpu=haswell| FileCheck %s --check-prefix=HSW-NOOPT +; RUN: llc < %s -mtriple=x86_64-unknown -mul-constant-optimization=false -print-schedule=true -mcpu=btver2| FileCheck %s --check-prefix=JAG-NOOPT +; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule=true -mcpu=slm| FileCheck %s --check-prefix=X64-SLM +; RUN: llc < %s -mtriple=x86_64-unknown -mul-constant-optimization=false -print-schedule=true -mcpu=slm| FileCheck %s --check-prefix=SLM-NOOPT -define i64 @test_mul_by_1(i64 %x) { +define i64 @test_mul_by_1(i64 %x) nounwind { ; X86-LABEL: test_mul_by_1: ; X86: # BB#0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_1: -; X64: # BB#0: -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_1: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_1: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_1: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_1: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.25] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_1: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.17] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_1: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: movq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_1: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.50] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 1 ret i64 %mul } @@ -26,10 +63,43 @@ define i64 @test_mul_by_2(i64 %x) { ; X86-NEXT: addl %eax, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_2: -; X64: # BB#0: -; X64-NEXT: leaq (%rdi,%rdi), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_2: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_2: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_2: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NOOPT-NEXT: shldl $1, %eax, %edx +; X86-NOOPT-NEXT: addl %eax, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_2: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: leaq (%rdi,%rdi), %rax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_2: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: leaq (%rdi,%rdi), %rax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_2: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (%rdi,%rdi), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_2: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: leaq (%rdi,%rdi), %rax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 2 ret i64 %mul } @@ -43,10 +113,43 @@ define i64 @test_mul_by_3(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_3: -; X64: # BB#0: -; X64-NEXT: leaq (%rdi,%rdi,2), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_3: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_3: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_3: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $3, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $3, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_3: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_3: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_3: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_3: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 3 ret i64 %mul } @@ -60,10 +163,43 @@ define i64 @test_mul_by_4(i64 %x) { ; X86-NEXT: shll $2, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_4: -; X64: # BB#0: -; X64-NEXT: leaq (,%rdi,4), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_4: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_4: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_4: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NOOPT-NEXT: shldl $2, %eax, %edx +; X86-NOOPT-NEXT: shll $2, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_4: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: leaq (,%rdi,4), %rax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_4: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: leaq (,%rdi,4), %rax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_4: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_4: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: leaq (,%rdi,4), %rax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 4 ret i64 %mul } @@ -77,10 +213,43 @@ define i64 @test_mul_by_5(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_5: -; X64: # BB#0: -; X64-NEXT: leaq (%rdi,%rdi,4), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_5: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_5: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_5: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $5, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $5, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_5: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_5: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_5: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_5: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 5 ret i64 %mul } @@ -95,11 +264,46 @@ define i64 @test_mul_by_6(i64 %x) { ; X86-NEXT: leal (%edx,%ecx,2), %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_6: -; X64: # BB#0: -; X64-NEXT: addq %rdi, %rdi -; X64-NEXT: leaq (%rdi,%rdi,2), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_6: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: addq %rdi, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_6: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_6: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $6, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $6, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_6: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $6, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_6: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $6, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_6: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-SLM-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_6: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $6, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 6 ret i64 %mul } @@ -115,11 +319,46 @@ define i64 @test_mul_by_7(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_7: -; X64: # BB#0: -; X64-NEXT: leaq (,%rdi,8), %rax -; X64-NEXT: subq %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_7: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: subq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_7: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: subq %rdi, %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_7: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $7, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $7, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_7: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $7, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_7: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $7, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_7: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (,%rdi,8), %rax # sched: [1:1.00] +; X64-SLM-NEXT: subq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_7: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $7, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 7 ret i64 %mul } @@ -133,10 +372,43 @@ define i64 @test_mul_by_8(i64 %x) { ; X86-NEXT: shll $3, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_8: -; X64: # BB#0: -; X64-NEXT: leaq (,%rdi,8), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_8: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_8: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_8: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NOOPT-NEXT: shldl $3, %eax, %edx +; X86-NOOPT-NEXT: shll $3, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_8: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: leaq (,%rdi,8), %rax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_8: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: leaq (,%rdi,8), %rax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_8: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (,%rdi,8), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_8: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: leaq (,%rdi,8), %rax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 8 ret i64 %mul } @@ -150,10 +422,43 @@ define i64 @test_mul_by_9(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_9: -; X64: # BB#0: -; X64-NEXT: leaq (%rdi,%rdi,8), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_9: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_9: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_9: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $9, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $9, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_9: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_9: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_9: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_9: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 9 ret i64 %mul } @@ -168,11 +473,46 @@ define i64 @test_mul_by_10(i64 %x) { ; X86-NEXT: leal (%edx,%ecx,2), %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_10: -; X64: # BB#0: -; X64-NEXT: addq %rdi, %rdi -; X64-NEXT: leaq (%rdi,%rdi,4), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_10: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: addq %rdi, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_10: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_10: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $10, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $10, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_10: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $10, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_10: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $10, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_10: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-SLM-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_10: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $10, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 10 ret i64 %mul } @@ -180,16 +520,53 @@ define i64 @test_mul_by_10(i64 %x) { define i64 @test_mul_by_11(i64 %x) { ; X86-LABEL: test_mul_by_11: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: leal (%eax,%ecx,2), %ecx ; X86-NEXT: movl $11, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $11, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_11: -; X64: # BB#0: -; X64-NEXT: imulq $11, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_11: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rax,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_11: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rax,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_11: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $11, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $11, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_11: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $11, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_11: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $11, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_11: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $11, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_11: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $11, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 11 ret i64 %mul } @@ -204,11 +581,46 @@ define i64 @test_mul_by_12(i64 %x) { ; X86-NEXT: leal (%edx,%ecx,4), %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_12: -; X64: # BB#0: -; X64-NEXT: shlq $2, %rdi -; X64-NEXT: leaq (%rdi,%rdi,2), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_12: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: shlq $2, %rdi # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_12: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: shlq $2, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_12: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $12, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $12, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_12: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $12, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_12: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $12, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_12: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: shlq $2, %rdi # sched: [1:1.00] +; X64-SLM-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_12: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $12, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 12 ret i64 %mul } @@ -216,16 +628,53 @@ define i64 @test_mul_by_12(i64 %x) { define i64 @test_mul_by_13(i64 %x) { ; X86-LABEL: test_mul_by_13: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,2), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %ecx ; X86-NEXT: movl $13, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $13, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_13: -; X64: # BB#0: -; X64-NEXT: imulq $13, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_13: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_13: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_13: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $13, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $13, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_13: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $13, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_13: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $13, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_13: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $13, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_13: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $13, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 13 ret i64 %mul } @@ -233,16 +682,56 @@ define i64 @test_mul_by_13(i64 %x) { define i64 @test_mul_by_14(i64 %x) { ; X86-LABEL: test_mul_by_14: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,2), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %ecx +; X86-NEXT: addl %eax, %ecx ; X86-NEXT: movl $14, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $14, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_14: -; X64: # BB#0: -; X64-NEXT: imulq $14, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_14: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: addq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_14: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: addq %rdi, %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_14: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $14, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $14, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_14: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $14, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_14: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $14, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_14: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $14, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_14: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $14, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 14 ret i64 %mul } @@ -258,11 +747,46 @@ define i64 @test_mul_by_15(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_15: -; X64: # BB#0: -; X64-NEXT: leaq (%rdi,%rdi,4), %rax -; X64-NEXT: leaq (%rax,%rax,2), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_15: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_15: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_15: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $15, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $15, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_15: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $15, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_15: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $15, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_15: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_15: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $15, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 15 ret i64 %mul } @@ -276,11 +800,49 @@ define i64 @test_mul_by_16(i64 %x) { ; X86-NEXT: shll $4, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_16: -; X64: # BB#0: -; X64-NEXT: shlq $4, %rdi -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_16: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: shlq $4, %rdi # sched: [1:0.50] +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_16: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: shlq $4, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_16: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NOOPT-NEXT: shldl $4, %eax, %edx +; X86-NOOPT-NEXT: shll $4, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_16: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: shlq $4, %rdi # sched: [1:0.50] +; HSW-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.25] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_16: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: shlq $4, %rdi # sched: [1:0.50] +; JAG-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.17] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_16: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: shlq $4, %rdi # sched: [1:1.00] +; X64-SLM-NEXT: movq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_16: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: shlq $4, %rdi # sched: [1:1.00] +; SLM-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.50] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 16 ret i64 %mul } @@ -297,12 +859,49 @@ define i64 @test_mul_by_17(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_17: -; X64: # BB#0: -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: shlq $4, %rax -; X64-NEXT: leaq (%rax,%rdi), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_17: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: shlq $4, %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rax,%rdi), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_17: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: shlq $4, %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rax,%rdi), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_17: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $17, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $17, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_17: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $17, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_17: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $17, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_17: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: movq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: shlq $4, %rax # sched: [1:1.00] +; X64-SLM-NEXT: addq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_17: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $17, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 17 ret i64 %mul } @@ -317,11 +916,46 @@ define i64 @test_mul_by_18(i64 %x) { ; X86-NEXT: leal (%edx,%ecx,2), %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_18: -; X64: # BB#0: -; X64-NEXT: addq %rdi, %rdi -; X64-NEXT: leaq (%rdi,%rdi,8), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_18: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: addq %rdi, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_18: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_18: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $18, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $18, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_18: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $18, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_18: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $18, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_18: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-SLM-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_18: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $18, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 18 ret i64 %mul } @@ -329,16 +963,58 @@ define i64 @test_mul_by_18(i64 %x) { define i64 @test_mul_by_19(i64 %x) { ; X86-LABEL: test_mul_by_19: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,4), %eax +; X86-NEXT: shll $2, %eax +; X86-NEXT: subl %eax, %ecx ; X86-NEXT: movl $19, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $19, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_19: -; X64: # BB#0: -; X64-NEXT: imulq $19, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_19: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: shlq $2, %rax # sched: [1:0.50] +; X64-HSW-NEXT: subq %rax, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_19: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: shlq $2, %rax # sched: [1:0.50] +; X64-JAG-NEXT: subq %rax, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_19: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $19, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $19, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_19: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $19, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_19: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $19, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_19: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $19, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_19: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $19, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 19 ret i64 %mul } @@ -353,11 +1029,46 @@ define i64 @test_mul_by_20(i64 %x) { ; X86-NEXT: leal (%edx,%ecx,4), %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_20: -; X64: # BB#0: -; X64-NEXT: shlq $2, %rdi -; X64-NEXT: leaq (%rdi,%rdi,4), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_20: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: shlq $2, %rdi # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_20: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: shlq $2, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_20: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $20, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $20, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_20: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $20, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_20: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $20, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_20: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: shlq $2, %rdi # sched: [1:1.00] +; X64-SLM-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_20: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $20, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 20 ret i64 %mul } @@ -365,16 +1076,53 @@ define i64 @test_mul_by_20(i64 %x) { define i64 @test_mul_by_21(i64 %x) { ; X86-LABEL: test_mul_by_21: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %ecx ; X86-NEXT: movl $21, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $21, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_21: -; X64: # BB#0: -; X64-NEXT: imulq $21, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_21: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_21: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_21: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $21, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $21, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_21: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $21, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_21: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $21, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_21: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $21, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_21: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $21, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 21 ret i64 %mul } @@ -382,16 +1130,56 @@ define i64 @test_mul_by_21(i64 %x) { define i64 @test_mul_by_22(i64 %x) { ; X86-LABEL: test_mul_by_22: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,4), %ecx +; X86-NEXT: leal (%eax,%ecx,4), %ecx +; X86-NEXT: addl %eax, %ecx ; X86-NEXT: movl $22, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $22, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_22: -; X64: # BB#0: -; X64-NEXT: imulq $22, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_22: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: addq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_22: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rax,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: addq %rdi, %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_22: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $22, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $22, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_22: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $22, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_22: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $22, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_22: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $22, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_22: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $22, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 22 ret i64 %mul } @@ -399,16 +1187,58 @@ define i64 @test_mul_by_22(i64 %x) { define i64 @test_mul_by_23(i64 %x) { ; X86-LABEL: test_mul_by_23: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,2), %eax +; X86-NEXT: shll $3, %eax +; X86-NEXT: subl %eax, %ecx ; X86-NEXT: movl $23, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $23, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_23: -; X64: # BB#0: -; X64-NEXT: imulq $23, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_23: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: shlq $3, %rax # sched: [1:0.50] +; X64-HSW-NEXT: subq %rax, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_23: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: shlq $3, %rax # sched: [1:0.50] +; X64-JAG-NEXT: subq %rax, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_23: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $23, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $23, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_23: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $23, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_23: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $23, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_23: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $23, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_23: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $23, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 23 ret i64 %mul } @@ -423,11 +1253,46 @@ define i64 @test_mul_by_24(i64 %x) { ; X86-NEXT: leal (%edx,%ecx,8), %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_24: -; X64: # BB#0: -; X64-NEXT: shlq $3, %rdi -; X64-NEXT: leaq (%rdi,%rdi,2), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_24: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: shlq $3, %rdi # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_24: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: shlq $3, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_24: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $24, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $24, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_24: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $24, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_24: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $24, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_24: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: shlq $3, %rdi # sched: [1:1.00] +; X64-SLM-NEXT: leaq (%rdi,%rdi,2), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_24: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $24, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 24 ret i64 %mul } @@ -443,11 +1308,46 @@ define i64 @test_mul_by_25(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_25: -; X64: # BB#0: -; X64-NEXT: leaq (%rdi,%rdi,4), %rax -; X64-NEXT: leaq (%rax,%rax,4), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_25: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rax,%rax,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_25: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rax,%rax,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_25: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $25, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $25, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_25: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $25, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_25: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $25, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_25: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: leaq (%rax,%rax,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_25: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $25, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 25 ret i64 %mul } @@ -455,16 +1355,58 @@ define i64 @test_mul_by_25(i64 %x) { define i64 @test_mul_by_26(i64 %x) { ; X86-LABEL: test_mul_by_26: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: leal (%ecx,%ecx,8), %eax +; X86-NEXT: leal (%eax,%eax,2), %eax +; X86-NEXT: subl %eax, %ecx ; X86-NEXT: movl $26, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $26, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_26: -; X64: # BB#0: -; X64-NEXT: imulq $26, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_26: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: subq %rax, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_26: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: subq %rax, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_26: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $26, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $26, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_26: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $26, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_26: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $26, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_26: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $26, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_26: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $26, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 26 ret i64 %mul } @@ -480,11 +1422,46 @@ define i64 @test_mul_by_27(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_27: -; X64: # BB#0: -; X64-NEXT: leaq (%rdi,%rdi,8), %rax -; X64-NEXT: leaq (%rax,%rax,2), %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_27: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_27: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_27: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $27, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $27, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_27: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $27, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_27: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $27, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_27: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:1.00] +; X64-SLM-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_27: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $27, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 27 ret i64 %mul } @@ -492,16 +1469,56 @@ define i64 @test_mul_by_27(i64 %x) { define i64 @test_mul_by_28(i64 %x) { ; X86-LABEL: test_mul_by_28: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,8), %ecx +; X86-NEXT: leal (%ecx,%ecx,2), %ecx +; X86-NEXT: addl %eax, %ecx ; X86-NEXT: movl $28, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $28, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_28: -; X64: # BB#0: -; X64-NEXT: imulq $28, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_28: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: addq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_28: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: addq %rdi, %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_28: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $28, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $28, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_28: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $28, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_28: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $28, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_28: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $28, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_28: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $28, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 28 ret i64 %mul } @@ -509,16 +1526,59 @@ define i64 @test_mul_by_28(i64 %x) { define i64 @test_mul_by_29(i64 %x) { ; X86-LABEL: test_mul_by_29: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,8), %ecx +; X86-NEXT: leal (%ecx,%ecx,2), %ecx +; X86-NEXT: addl %eax, %ecx +; X86-NEXT: addl %eax, %ecx ; X86-NEXT: movl $29, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $29, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_29: -; X64: # BB#0: -; X64-NEXT: imulq $29, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_29: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-HSW-NEXT: addq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: addq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_29: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rax,%rax,2), %rax # sched: [1:0.50] +; X64-JAG-NEXT: addq %rdi, %rax # sched: [1:0.50] +; X64-JAG-NEXT: addq %rdi, %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_29: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $29, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $29, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_29: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $29, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_29: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $29, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_29: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $29, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_29: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $29, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 29 ret i64 %mul } @@ -526,16 +1586,60 @@ define i64 @test_mul_by_29(i64 %x) { define i64 @test_mul_by_30(i64 %x) { ; X86-LABEL: test_mul_by_30: ; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: shll $5, %ecx ; X86-NEXT: movl $30, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: imull $30, {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_30: -; X64: # BB#0: -; X64-NEXT: imulq $30, %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_30: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: shlq $5, %rax # sched: [1:0.50] +; X64-HSW-NEXT: movq %rdi, %rcx # sched: [1:0.25] +; X64-HSW-NEXT: subq %rax, %rcx # sched: [1:0.25] +; X64-HSW-NEXT: subq %rcx, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_30: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: movq %rdi, %rcx # sched: [1:0.17] +; X64-JAG-NEXT: shlq $5, %rax # sched: [1:0.50] +; X64-JAG-NEXT: subq %rax, %rcx # sched: [1:0.50] +; X64-JAG-NEXT: subq %rcx, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_30: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $30, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $30, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_30: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $30, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_30: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $30, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_30: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: imulq $30, %rdi, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_30: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $30, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 30 ret i64 %mul } @@ -552,12 +1656,49 @@ define i64 @test_mul_by_31(i64 %x) { ; X86-NEXT: addl %ecx, %edx ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_31: -; X64: # BB#0: -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: shlq $5, %rax -; X64-NEXT: subq %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_31: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: shlq $5, %rax # sched: [1:0.50] +; X64-HSW-NEXT: subq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_31: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: shlq $5, %rax # sched: [1:0.50] +; X64-JAG-NEXT: subq %rdi, %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_31: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl $31, %eax +; X86-NOOPT-NEXT: mull {{[0-9]+}}(%esp) +; X86-NOOPT-NEXT: imull $31, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_31: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: imulq $31, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_31: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: imulq $31, %rdi, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_31: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: movq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: shlq $5, %rax # sched: [1:1.00] +; X64-SLM-NEXT: subq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_31: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: imulq $31, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 31 ret i64 %mul } @@ -571,11 +1712,168 @@ define i64 @test_mul_by_32(i64 %x) { ; X86-NEXT: shll $5, %eax ; X86-NEXT: retl ; -; X64-LABEL: test_mul_by_32: -; X64: # BB#0: -; X64-NEXT: shlq $5, %rdi -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: retq +; X64-HSW-LABEL: test_mul_by_32: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: shlq $5, %rdi # sched: [1:0.50] +; X64-HSW-NEXT: movq %rdi, %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_by_32: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: shlq $5, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: movq %rdi, %rax # sched: [1:0.17] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_32: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NOOPT-NEXT: shldl $5, %eax, %edx +; X86-NOOPT-NEXT: shll $5, %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_32: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: shlq $5, %rdi # sched: [1:0.50] +; HSW-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.25] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_32: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: shlq $5, %rdi # sched: [1:0.50] +; JAG-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.17] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_32: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: shlq $5, %rdi # sched: [1:1.00] +; X64-SLM-NEXT: movq %rdi, %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_32: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: shlq $5, %rdi # sched: [1:1.00] +; SLM-NOOPT-NEXT: movq %rdi, %rax # sched: [1:0.50] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i64 %x, 32 ret i64 %mul } + +; (x*9+42)*(x*5+2) +define i64 @test_mul_spec(i64 %x) nounwind { +; X86-LABEL: test_mul_spec: +; X86: # BB#0: +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl $9, %edx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: movl %eax, %esi +; X86-NEXT: leal (%edi,%edi,8), %ebx +; X86-NEXT: addl $42, %esi +; X86-NEXT: adcl %edx, %ebx +; X86-NEXT: movl $5, %edx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: movl %eax, %ecx +; X86-NEXT: leal (%edi,%edi,4), %edi +; X86-NEXT: addl $2, %ecx +; X86-NEXT: adcl %edx, %edi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: mull %ecx +; X86-NEXT: imull %esi, %edi +; X86-NEXT: addl %edi, %edx +; X86-NEXT: imull %ebx, %ecx +; X86-NEXT: addl %ecx, %edx +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: retl +; +; X64-HSW-LABEL: test_mul_spec: +; X64-HSW: # BB#0: +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rcx # sched: [1:0.50] +; X64-HSW-NEXT: addq $42, %rcx # sched: [1:0.25] +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: addq $2, %rax # sched: [1:0.25] +; X64-HSW-NEXT: imulq %rcx, %rax # sched: [3:1.00] +; X64-HSW-NEXT: retq # sched: [1:1.00] +; +; X64-JAG-LABEL: test_mul_spec: +; X64-JAG: # BB#0: +; X64-JAG-NEXT: leaq 42(%rdi,%rdi,8), %rcx # sched: [1:0.50] +; X64-JAG-NEXT: leaq 2(%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-JAG-NEXT: imulq %rcx, %rax # sched: [3:1.00] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_spec: +; X86-NOOPT: # BB#0: +; X86-NOOPT-NEXT: pushl %ebx +; X86-NOOPT-NEXT: pushl %edi +; X86-NOOPT-NEXT: pushl %esi +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NOOPT-NEXT: movl $9, %edx +; X86-NOOPT-NEXT: movl %ecx, %eax +; X86-NOOPT-NEXT: mull %edx +; X86-NOOPT-NEXT: movl %eax, %esi +; X86-NOOPT-NEXT: leal (%edi,%edi,8), %ebx +; X86-NOOPT-NEXT: addl $42, %esi +; X86-NOOPT-NEXT: adcl %edx, %ebx +; X86-NOOPT-NEXT: movl $5, %edx +; X86-NOOPT-NEXT: movl %ecx, %eax +; X86-NOOPT-NEXT: mull %edx +; X86-NOOPT-NEXT: movl %eax, %ecx +; X86-NOOPT-NEXT: leal (%edi,%edi,4), %edi +; X86-NOOPT-NEXT: addl $2, %ecx +; X86-NOOPT-NEXT: adcl %edx, %edi +; X86-NOOPT-NEXT: movl %esi, %eax +; X86-NOOPT-NEXT: mull %ecx +; X86-NOOPT-NEXT: imull %esi, %edi +; X86-NOOPT-NEXT: addl %edi, %edx +; X86-NOOPT-NEXT: imull %ebx, %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: popl %esi +; X86-NOOPT-NEXT: popl %edi +; X86-NOOPT-NEXT: popl %ebx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_spec: +; HSW-NOOPT: # BB#0: +; HSW-NOOPT-NEXT: leaq (%rdi,%rdi,8), %rcx # sched: [1:0.50] +; HSW-NOOPT-NEXT: addq $42, %rcx # sched: [1:0.25] +; HSW-NOOPT-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; HSW-NOOPT-NEXT: addq $2, %rax # sched: [1:0.25] +; HSW-NOOPT-NEXT: imulq %rcx, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [1:1.00] +; +; JAG-NOOPT-LABEL: test_mul_spec: +; JAG-NOOPT: # BB#0: +; JAG-NOOPT-NEXT: leaq 42(%rdi,%rdi,8), %rcx # sched: [1:0.50] +; JAG-NOOPT-NEXT: leaq 2(%rdi,%rdi,4), %rax # sched: [1:0.50] +; JAG-NOOPT-NEXT: imulq %rcx, %rax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_spec: +; X64-SLM: # BB#0: +; X64-SLM-NEXT: leaq 42(%rdi,%rdi,8), %rcx # sched: [1:1.00] +; X64-SLM-NEXT: leaq 2(%rdi,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: imulq %rcx, %rax # sched: [3:1.00] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_spec: +; SLM-NOOPT: # BB#0: +; SLM-NOOPT-NEXT: leaq 42(%rdi,%rdi,8), %rcx # sched: [1:1.00] +; SLM-NOOPT-NEXT: leaq 2(%rdi,%rdi,4), %rax # sched: [1:1.00] +; SLM-NOOPT-NEXT: imulq %rcx, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] + %mul = mul nsw i64 %x, 9 + %add = add nsw i64 %mul, 42 + %mul2 = mul nsw i64 %x, 5 + %add2 = add nsw i64 %mul2, 2 + %mul3 = mul nsw i64 %add, %add2 + ret i64 %mul3 +} diff --git a/test/CodeGen/X86/setcc-lowering.ll b/test/CodeGen/X86/setcc-lowering.ll index 391f1cc9fb43f..1b8f8e7ae559c 100644 --- a/test/CodeGen/X86/setcc-lowering.ll +++ b/test/CodeGen/X86/setcc-lowering.ll @@ -41,14 +41,67 @@ entry: ret <8 x i16> %3 } -define void @pr26232(i64 %a) { +define void @pr26232(i64 %a, <16 x i1> %b) { ; AVX-LABEL: pr26232: ; AVX: # BB#0: # %for_loop599.preheader +; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX-NEXT: .p2align 4, 0x90 ; AVX-NEXT: .LBB1_1: # %for_loop599 ; AVX-NEXT: # =>This Inner Loop Header: Depth=1 +; AVX-NEXT: xorl %eax, %eax ; AVX-NEXT: cmpq $65536, %rdi # imm = 0x10000 -; AVX-NEXT: setl -{{[0-9]+}}(%rsp) +; AVX-NEXT: setl %al +; AVX-NEXT: vmovd %eax, %xmm2 +; AVX-NEXT: vpshufb %xmm1, %xmm2, %xmm2 +; AVX-NEXT: vpand %xmm0, %xmm2, %xmm2 +; AVX-NEXT: vpextrb $15, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $14, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $13, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $12, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $11, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $10, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $9, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $8, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $7, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $6, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $5, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $4, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $3, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $2, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $1, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) +; AVX-NEXT: vpextrb $0, %xmm2, %eax +; AVX-NEXT: andb $1, %al +; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) ; AVX-NEXT: cmpw $0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: jne .LBB1_1 ; AVX-NEXT: # BB#2: # %for_exit600 @@ -61,6 +114,9 @@ define void @pr26232(i64 %a) { ; KNL-32-NEXT: .cfi_def_cfa_offset 8 ; KNL-32-NEXT: .Lcfi1: ; KNL-32-NEXT: .cfi_offset %esi, -8 +; KNL-32-NEXT: vpmovsxbd %xmm0, %zmm0 +; KNL-32-NEXT: vpslld $31, %zmm0, %zmm0 +; KNL-32-NEXT: vptestmd %zmm0, %zmm0, %k0 ; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; KNL-32-NEXT: movw $-1, %dx @@ -72,6 +128,9 @@ define void @pr26232(i64 %a) { ; KNL-32-NEXT: sbbl $0, %esi ; KNL-32-NEXT: movl $0, %esi ; KNL-32-NEXT: cmovlw %dx, %si +; KNL-32-NEXT: kmovw %esi, %k1 +; KNL-32-NEXT: kandw %k0, %k1, %k1 +; KNL-32-NEXT: kmovw %k1, %esi ; KNL-32-NEXT: testw %si, %si ; KNL-32-NEXT: jne .LBB1_1 ; KNL-32-NEXT: # BB#2: # %for_exit600 @@ -87,7 +146,7 @@ for_loop599: ; preds = %for_loop599, %for_t %less_i_load605_ = icmp slt i64 %a, 65536 %less_i_load605__broadcast_init = insertelement <16 x i1> undef, i1 %less_i_load605_, i32 0 %less_i_load605__broadcast = shufflevector <16 x i1> %less_i_load605__broadcast_init, <16 x i1> undef, <16 x i32> zeroinitializer - %"oldMask&test607" = and <16 x i1> %less_i_load605__broadcast, undef + %"oldMask&test607" = and <16 x i1> %less_i_load605__broadcast, %b %intmask.i894 = bitcast <16 x i1> %"oldMask&test607" to i16 %res.i895 = icmp eq i16 %intmask.i894, 0 br i1 %res.i895, label %for_exit600, label %for_loop599 diff --git a/test/CodeGen/X86/vector-sext.ll b/test/CodeGen/X86/vector-sext.ll index 8cc1d8c765ac3..53e471d6f1758 100644 --- a/test/CodeGen/X86/vector-sext.ll +++ b/test/CodeGen/X86/vector-sext.ll @@ -1749,6 +1749,62 @@ entry: ret <4 x i64> %Y } +define <2 x i64> @load_sext_4i8_to_4i64_extract(<4 x i8> *%ptr) { +; SSE2-LABEL: load_sext_4i8_to_4i64_extract: +; SSE2: # BB#0: +; SSE2-NEXT: movsbq 3(%rdi), %rax +; SSE2-NEXT: movq %rax, %xmm1 +; SSE2-NEXT: movsbq 2(%rdi), %rax +; SSE2-NEXT: movq %rax, %xmm0 +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE2-NEXT: retq +; +; SSSE3-LABEL: load_sext_4i8_to_4i64_extract: +; SSSE3: # BB#0: +; SSSE3-NEXT: movsbq 3(%rdi), %rax +; SSSE3-NEXT: movq %rax, %xmm1 +; SSSE3-NEXT: movsbq 2(%rdi), %rax +; SSSE3-NEXT: movq %rax, %xmm0 +; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSSE3-NEXT: retq +; +; SSE41-LABEL: load_sext_4i8_to_4i64_extract: +; SSE41: # BB#0: +; SSE41-NEXT: pmovsxbq 2(%rdi), %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: load_sext_4i8_to_4i64_extract: +; AVX1: # BB#0: +; AVX1-NEXT: vpmovsxbd (%rdi), %xmm0 +; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: load_sext_4i8_to_4i64_extract: +; AVX2: # BB#0: +; AVX2-NEXT: vpmovsxbq (%rdi), %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_sext_4i8_to_4i64_extract: +; AVX512: # BB#0: +; AVX512-NEXT: vpmovsxbq (%rdi), %ymm0 +; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq +; +; X32-SSE41-LABEL: load_sext_4i8_to_4i64_extract: +; X32-SSE41: # BB#0: +; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax +; X32-SSE41-NEXT: pmovsxbq 2(%eax), %xmm0 +; X32-SSE41-NEXT: retl + %ld = load <4 x i8>, <4 x i8>* %ptr + %sext = sext <4 x i8> %ld to <4 x i64> + %extract = shufflevector <4 x i64> %sext, <4 x i64> undef, <2 x i32> <i32 2, i32 3> + ret <2 x i64> %extract +} + define <8 x i16> @load_sext_8i1_to_8i16(<8 x i1> *%ptr) { ; SSE2-LABEL: load_sext_8i1_to_8i16: ; SSE2: # BB#0: # %entry diff --git a/test/CodeGen/X86/xchg-nofold.ll b/test/CodeGen/X86/xchg-nofold.ll new file mode 100644 index 0000000000000..fddc7906e08f9 --- /dev/null +++ b/test/CodeGen/X86/xchg-nofold.ll @@ -0,0 +1,37 @@ +; RUN: llc -mtriple=x86_64-linux-gnu < %s | FileCheck %s + +%"struct.std::atomic" = type { %"struct.std::atomic_bool" } +%"struct.std::atomic_bool" = type { %"struct.std::__atomic_base" } +%"struct.std::__atomic_base" = type { i8 } + +; CHECK-LABEL: _Z3fooRSt6atomicIbEb +define zeroext i1 @_Z3fooRSt6atomicIbEb(%"struct.std::atomic"* nocapture dereferenceable(1) %a, i1 returned zeroext %b) nounwind { +entry: + %frombool.i.i = zext i1 %b to i8 + %_M_i.i.i = getelementptr inbounds %"struct.std::atomic", %"struct.std::atomic"* %a, i64 0, i32 0, i32 0, i32 0 + %0 = ptrtoint i8* %_M_i.i.i to i64 + %1 = lshr i64 %0, 3 + %2 = add i64 %1, 2147450880 + %3 = inttoptr i64 %2 to i8* + %4 = load i8, i8* %3 + %5 = icmp ne i8 %4, 0 + br i1 %5, label %6, label %11 + +; <label>:6: ; preds = %entry + %7 = and i64 %0, 7 + %8 = trunc i64 %7 to i8 + %9 = icmp sge i8 %8, %4 + br i1 %9, label %10, label %11 + +; <label>:10: ; preds = %6 + call void @__asan_report_store1(i64 %0) + call void asm sideeffect "", ""() + unreachable + +; <label>:11: ; preds = %6, %entry + store atomic i8 %frombool.i.i, i8* %_M_i.i.i seq_cst, align 1 +; CHECK: xchgb %{{.*}}, (%{{.*}}) + ret i1 %b +} + +declare void @__asan_report_store1(i64) diff --git a/test/MC/AArch64/ldr-pseudo.s b/test/MC/AArch64/ldr-pseudo.s index e132f7cf651f1..1d99d14018017 100644 --- a/test/MC/AArch64/ldr-pseudo.s +++ b/test/MC/AArch64/ldr-pseudo.s @@ -205,6 +205,13 @@ f18: ldr x1, =0x320064 // CHECK: ldr x1, .Ltmp[[TMP26:[0-9]+]] +// We previously used a DenseMap with constant values as keys, check that +// sentinel values can be used. + ldr x0, =0x7ffffffffffffffe +// CHECK: ldr x0, .Ltmp[[TMP27:[0-9]+]] + ldr x1, =0x7fffffffffffffff +// CHECK: ldr x1, .Ltmp[[TMP28:[0-9]+]] + // // Constant Pools // @@ -311,3 +318,8 @@ f18: // CHECK: .p2align 2 // CHECK: .Ltmp[[TMP25]] // CHECK: .word 3276900 + +// CHECK: .Ltmp[[TMP27]] +// CHECK: .xword 9223372036854775806 +// CHECK: .Ltmp[[TMP28]] +// CHECK: .xword 9223372036854775807 diff --git a/test/MC/Disassembler/SystemZ/insns-z13.txt b/test/MC/Disassembler/SystemZ/insns-z13.txt index 4f5ec43f73487..c48bdee8d6134 100644 --- a/test/MC/Disassembler/SystemZ/insns-z13.txt +++ b/test/MC/Disassembler/SystemZ/insns-z13.txt @@ -2,6 +2,114 @@ # RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z13 \ # RUN: | FileCheck %s +# CHECK: cdpt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xae + +# CHECK: cdpt %f15, 0(1), 0 +0xed 0x00 0x00 0x00 0xf0 0xae + +# CHECK: cdpt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xae + +# CHECK: cdpt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xae + +# CHECK: cdpt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xae + +# CHECK: cdpt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xae + +# CHECK: cdpt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xae + +# CHECK: cdpt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xae + +# CHECK: cdpt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xae + +# CHECK: cpdt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xac + +# CHECK: cpdt %f15, 0(1), 0 +0xed 0x00 0x00 0x00 0xf0 0xac + +# CHECK: cpdt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xac + +# CHECK: cpdt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xac + +# CHECK: cpdt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xac + +# CHECK: cpdt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xac + +# CHECK: cpdt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xac + +# CHECK: cpdt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xac + +# CHECK: cpdt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xac + +# CHECK: cpxt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xad + +# CHECK: cpxt %f13, 0(1), 0 +0xed 0x00 0x00 0x00 0xd0 0xad + +# CHECK: cpxt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xad + +# CHECK: cpxt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xad + +# CHECK: cpxt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xad + +# CHECK: cpxt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xad + +# CHECK: cpxt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xad + +# CHECK: cpxt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xad + +# CHECK: cpxt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xad + +# CHECK: cxpt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xaf + +# CHECK: cxpt %f13, 0(1), 0 +0xed 0x00 0x00 0x00 0xd0 0xaf + +# CHECK: cxpt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xaf + +# CHECK: cxpt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xaf + +# CHECK: cxpt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xaf + +# CHECK: cxpt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xaf + +# CHECK: cxpt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xaf + +# CHECK: cxpt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xaf + +# CHECK: cxpt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xaf + # CHECK: lcbb %r0, 0, 0 0xe7 0x00 0x00 0x00 0x00 0x27 diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index dac94099f276a..75f7f9669b5cd 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -22,6 +22,27 @@ # CHECK: a %r15, 0 0x5a 0xf0 0x00 0x00 +# CHECK: ad %f0, 0 +0x6a 0x00 0x00 0x00 + +# CHECK: ad %f0, 4095 +0x6a 0x00 0x0f 0xff + +# CHECK: ad %f0, 0(%r1) +0x6a 0x00 0x10 0x00 + +# CHECK: ad %f0, 0(%r15) +0x6a 0x00 0xf0 0x00 + +# CHECK: ad %f0, 4095(%r1,%r15) +0x6a 0x01 0xff 0xff + +# CHECK: ad %f0, 4095(%r15,%r1) +0x6a 0x0f 0x1f 0xff + +# CHECK: ad %f15, 0 +0x6a 0xf0 0x00 0x00 + # CHECK: adb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x1a @@ -55,6 +76,72 @@ # CHECK: adbr %f15, %f0 0xb3 0x1a 0x00 0xf0 +# CHECK: adr %f0, %f0 +0x2a 0x00 + +# CHECK: adr %f0, %f15 +0x2a 0x0f + +# CHECK: adr %f7, %f8 +0x2a 0x78 + +# CHECK: adr %f15, %f0 +0x2a 0xf0 + +# CHECK: adtr %f0, %f0, %f0 +0xb3 0xd2 0x00 0x00 + +# CHECK: adtr %f0, %f0, %f15 +0xb3 0xd2 0xf0 0x00 + +# CHECK: adtr %f0, %f15, %f0 +0xb3 0xd2 0x00 0x0f + +# CHECK: adtr %f15, %f0, %f0 +0xb3 0xd2 0x00 0xf0 + +# CHECK: adtr %f7, %f8, %f9 +0xb3 0xd2 0x90 0x78 + +# CHECK: adtra %f0, %f0, %f0, 1 +0xb3 0xd2 0x01 0x00 + +# CHECK: adtra %f0, %f0, %f0, 15 +0xb3 0xd2 0x0f 0x00 + +# CHECK: adtra %f0, %f0, %f15, 1 +0xb3 0xd2 0xf1 0x00 + +# CHECK: adtra %f0, %f15, %f0, 1 +0xb3 0xd2 0x01 0x0f + +# CHECK: adtra %f15, %f0, %f0, 1 +0xb3 0xd2 0x01 0xf0 + +# CHECK: adtra %f7, %f8, %f9, 10 +0xb3 0xd2 0x9a 0x78 + +# CHECK: ae %f0, 0 +0x7a 0x00 0x00 0x00 + +# CHECK: ae %f0, 4095 +0x7a 0x00 0x0f 0xff + +# CHECK: ae %f0, 0(%r1) +0x7a 0x00 0x10 0x00 + +# CHECK: ae %f0, 0(%r15) +0x7a 0x00 0xf0 0x00 + +# CHECK: ae %f0, 4095(%r1,%r15) +0x7a 0x01 0xff 0xff + +# CHECK: ae %f0, 4095(%r15,%r1) +0x7a 0x0f 0x1f 0xff + +# CHECK: ae %f15, 0 +0x7a 0xf0 0x00 0x00 + # CHECK: aeb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x0a @@ -88,6 +175,18 @@ # CHECK: aebr %f15, %f0 0xb3 0x0a 0x00 0xf0 +# CHECK: aer %f0, %f0 +0x3a 0x00 + +# CHECK: aer %f0, %f15 +0x3a 0x0f + +# CHECK: aer %f7, %f8 +0x3a 0x78 + +# CHECK: aer %f15, %f0 +0x3a 0xf0 + # CHECK: afi %r0, -2147483648 0xc2 0x09 0x80 0x00 0x00 0x00 @@ -856,6 +955,72 @@ # CHECK: asi 524287(%r15), 42 0xeb 0x2a 0xff 0xff 0x7f 0x6a +# CHECK: au %f0, 0 +0x7e 0x00 0x00 0x00 + +# CHECK: au %f0, 4095 +0x7e 0x00 0x0f 0xff + +# CHECK: au %f0, 0(%r1) +0x7e 0x00 0x10 0x00 + +# CHECK: au %f0, 0(%r15) +0x7e 0x00 0xf0 0x00 + +# CHECK: au %f0, 4095(%r1,%r15) +0x7e 0x01 0xff 0xff + +# CHECK: au %f0, 4095(%r15,%r1) +0x7e 0x0f 0x1f 0xff + +# CHECK: au %f15, 0 +0x7e 0xf0 0x00 0x00 + +# CHECK: aur %f0, %f0 +0x3e 0x00 + +# CHECK: aur %f0, %f15 +0x3e 0x0f + +# CHECK: aur %f7, %f8 +0x3e 0x78 + +# CHECK: aur %f15, %f0 +0x3e 0xf0 + +# CHECK: aw %f0, 0 +0x6e 0x00 0x00 0x00 + +# CHECK: aw %f0, 4095 +0x6e 0x00 0x0f 0xff + +# CHECK: aw %f0, 0(%r1) +0x6e 0x00 0x10 0x00 + +# CHECK: aw %f0, 0(%r15) +0x6e 0x00 0xf0 0x00 + +# CHECK: aw %f0, 4095(%r1,%r15) +0x6e 0x01 0xff 0xff + +# CHECK: aw %f0, 4095(%r15,%r1) +0x6e 0x0f 0x1f 0xff + +# CHECK: aw %f15, 0 +0x6e 0xf0 0x00 0x00 + +# CHECK: awr %f0, %f0 +0x2e 0x00 + +# CHECK: awr %f0, %f15 +0x2e 0x0f + +# CHECK: awr %f7, %f8 +0x2e 0x78 + +# CHECK: awr %f15, %f0 +0x2e 0xf0 + # CHECK: axbr %f0, %f0 0xb3 0x4a 0x00 0x00 @@ -868,6 +1033,51 @@ # CHECK: axbr %f13, %f0 0xb3 0x4a 0x00 0xd0 +# CHECK: axr %f0, %f0 +0x36 0x00 + +# CHECK: axr %f0, %f13 +0x36 0x0d + +# CHECK: axr %f8, %f8 +0x36 0x88 + +# CHECK: axr %f13, %f0 +0x36 0xd0 + +# CHECK: axtr %f0, %f0, %f0 +0xb3 0xda 0x00 0x00 + +# CHECK: axtr %f0, %f0, %f13 +0xb3 0xda 0xd0 0x00 + +# CHECK: axtr %f0, %f13, %f0 +0xb3 0xda 0x00 0x0d + +# CHECK: axtr %f13, %f0, %f0 +0xb3 0xda 0x00 0xd0 + +# CHECK: axtr %f8, %f8, %f8 +0xb3 0xda 0x80 0x88 + +# CHECK: axtra %f0, %f0, %f0, 1 +0xb3 0xda 0x01 0x00 + +# CHECK: axtra %f0, %f0, %f0, 15 +0xb3 0xda 0x0f 0x00 + +# CHECK: axtra %f0, %f0, %f13, 1 +0xb3 0xda 0xd1 0x00 + +# CHECK: axtra %f0, %f13, %f0, 1 +0xb3 0xda 0x01 0x0d + +# CHECK: axtra %f13, %f0, %f0, 1 +0xb3 0xda 0x01 0xd0 + +# CHECK: axtra %f8, %f8, %f8, 8 +0xb3 0xda 0x88 0x88 + # CHECK: ay %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x5a @@ -1348,6 +1558,27 @@ # CHECK: c %r15, 0 0x59 0xf0 0x00 0x00 +# CHECK: cd %f0, 0 +0x69 0x00 0x00 0x00 + +# CHECK: cd %f0, 4095 +0x69 0x00 0x0f 0xff + +# CHECK: cd %f0, 0(%r1) +0x69 0x00 0x10 0x00 + +# CHECK: cd %f0, 0(%r15) +0x69 0x00 0xf0 0x00 + +# CHECK: cd %f0, 4095(%r1,%r15) +0x69 0x01 0xff 0xff + +# CHECK: cd %f0, 4095(%r15,%r1) +0x69 0x0f 0x1f 0xff + +# CHECK: cd %f15, 0 +0x69 0xf0 0x00 0x00 + # CHECK: cdb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x19 @@ -1414,6 +1645,39 @@ # CHECK: cdfbra %f15, 0, %r0, 1 0xb3 0x95 0x01 0xf0 +# CHECK: cdfr %f0, %r0 +0xb3 0xb5 0x00 0x00 + +# CHECK: cdfr %f0, %r15 +0xb3 0xb5 0x00 0x0f + +# CHECK: cdfr %f15, %r0 +0xb3 0xb5 0x00 0xf0 + +# CHECK: cdfr %f7, %r8 +0xb3 0xb5 0x00 0x78 + +# CHECK: cdfr %f15, %r15 +0xb3 0xb5 0x00 0xff + +# CHECK: cdftr %f0, 0, %r0, 0 +0xb9 0x51 0x00 0x00 + +# CHECK: cdftr %f0, 0, %r0, 15 +0xb9 0x51 0x0f 0x00 + +# CHECK: cdftr %f0, 0, %r15, 0 +0xb9 0x51 0x00 0x0f + +# CHECK: cdftr %f0, 15, %r0, 0 +0xb9 0x51 0xf0 0x00 + +# CHECK: cdftr %f4, 5, %r6, 7 +0xb9 0x51 0x57 0x46 + +# CHECK: cdftr %f15, 0, %r0, 0 +0xb9 0x51 0x00 0xf0 + # CHECK: cdgbr %f0, %r0 0xb3 0xa5 0x00 0x00 @@ -1447,6 +1711,54 @@ # CHECK: cdgbra %f15, 0, %r0, 1 0xb3 0xa5 0x01 0xf0 +# CHECK: cdgr %f0, %r0 +0xb3 0xc5 0x00 0x00 + +# CHECK: cdgr %f0, %r15 +0xb3 0xc5 0x00 0x0f + +# CHECK: cdgr %f15, %r0 +0xb3 0xc5 0x00 0xf0 + +# CHECK: cdgr %f7, %r8 +0xb3 0xc5 0x00 0x78 + +# CHECK: cdgr %f15, %r15 +0xb3 0xc5 0x00 0xff + +# CHECK: cdgtr %f0, %r0 +0xb3 0xf1 0x00 0x00 + +# CHECK: cdgtr %f0, %r15 +0xb3 0xf1 0x00 0x0f + +# CHECK: cdgtr %f15, %r0 +0xb3 0xf1 0x00 0xf0 + +# CHECK: cdgtr %f7, %r8 +0xb3 0xf1 0x00 0x78 + +# CHECK: cdgtr %f15, %r15 +0xb3 0xf1 0x00 0xff + +# CHECK: cdgtra %f0, 0, %r0, 1 +0xb3 0xf1 0x01 0x00 + +# CHECK: cdgtra %f0, 0, %r0, 15 +0xb3 0xf1 0x0f 0x00 + +# CHECK: cdgtra %f0, 0, %r15, 1 +0xb3 0xf1 0x01 0x0f + +# CHECK: cdgtra %f0, 15, %r0, 1 +0xb3 0xf1 0xf1 0x00 + +# CHECK: cdgtra %f4, 5, %r6, 7 +0xb3 0xf1 0x57 0x46 + +# CHECK: cdgtra %f15, 0, %r0, 1 +0xb3 0xf1 0x01 0xf0 + # CHECK: cdlfbr %f0, 0, %r0, 1 0xb3 0x91 0x01 0x00 @@ -1465,6 +1777,24 @@ # CHECK: cdlfbr %f15, 0, %r0, 1 0xb3 0x91 0x01 0xf0 +# CHECK: cdlftr %f0, 0, %r0, 0 +0xb9 0x53 0x00 0x00 + +# CHECK: cdlftr %f0, 0, %r0, 15 +0xb9 0x53 0x0f 0x00 + +# CHECK: cdlftr %f0, 0, %r15, 0 +0xb9 0x53 0x00 0x0f + +# CHECK: cdlftr %f0, 15, %r0, 0 +0xb9 0x53 0xf0 0x00 + +# CHECK: cdlftr %f4, 5, %r6, 7 +0xb9 0x53 0x57 0x46 + +# CHECK: cdlftr %f15, 0, %r0, 0 +0xb9 0x53 0x00 0xf0 + # CHECK: cdlgbr %f0, 0, %r0, 1 0xb3 0xa1 0x01 0x00 @@ -1483,6 +1813,36 @@ # CHECK: cdlgbr %f15, 0, %r0, 1 0xb3 0xa1 0x01 0xf0 +# CHECK: cdlgtr %f0, 0, %r0, 0 +0xb9 0x52 0x00 0x00 + +# CHECK: cdlgtr %f0, 0, %r0, 15 +0xb9 0x52 0x0f 0x00 + +# CHECK: cdlgtr %f0, 0, %r15, 0 +0xb9 0x52 0x00 0x0f + +# CHECK: cdlgtr %f0, 15, %r0, 0 +0xb9 0x52 0xf0 0x00 + +# CHECK: cdlgtr %f4, 5, %r6, 7 +0xb9 0x52 0x57 0x46 + +# CHECK: cdlgtr %f15, 0, %r0, 0 +0xb9 0x52 0x00 0xf0 + +# CHECK: cdr %f0, %f0 +0x29 0x00 + +# CHECK: cdr %f0, %f15 +0x29 0x0f + +# CHECK: cdr %f7, %f8 +0x29 0x78 + +# CHECK: cdr %f15, %f0 +0x29 0xf0 + # CHECK: cds %r0, %r0, 0 0xbb 0x00 0x00 0x00 @@ -1540,6 +1900,21 @@ # CHECK: cdsg %r14, %r0, 0 0xeb 0xe0 0x00 0x00 0x00 0x3e +# CHECK: cdstr %f0, %r0 +0xb3 0xf3 0x00 0x00 + +# CHECK: cdstr %f0, %r15 +0xb3 0xf3 0x00 0x0f + +# CHECK: cdstr %f15, %r0 +0xb3 0xf3 0x00 0xf0 + +# CHECK: cdstr %f7, %r8 +0xb3 0xf3 0x00 0x78 + +# CHECK: cdstr %f15, %r15 +0xb3 0xf3 0x00 0xff + # CHECK: cdsy %r0, %r0, -524288 0xeb 0x00 0x00 0x00 0x80 0x31 @@ -1573,6 +1948,81 @@ # CHECK: cdsy %r14, %r0, 0 0xeb 0xe0 0x00 0x00 0x00 0x31 +# CHECK: cdtr %f0, %f0 +0xb3 0xe4 0x00 0x00 + +# CHECK: cdtr %f0, %f15 +0xb3 0xe4 0x00 0x0f + +# CHECK: cdtr %f7, %f8 +0xb3 0xe4 0x00 0x78 + +# CHECK: cdtr %f15, %f0 +0xb3 0xe4 0x00 0xf0 + +# CHECK: cdutr %f0, %r0 +0xb3 0xf2 0x00 0x00 + +# CHECK: cdutr %f0, %r15 +0xb3 0xf2 0x00 0x0f + +# CHECK: cdutr %f15, %r0 +0xb3 0xf2 0x00 0xf0 + +# CHECK: cdutr %f7, %r8 +0xb3 0xf2 0x00 0x78 + +# CHECK: cdutr %f15, %r15 +0xb3 0xf2 0x00 0xff + +# CHECK: cdzt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xaa + +# CHECK: cdzt %f15, 0(1), 0 +0xed 0x00 0x00 0x00 0xf0 0xaa + +# CHECK: cdzt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xaa + +# CHECK: cdzt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xaa + +# CHECK: cdzt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xaa + +# CHECK: cdzt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xaa + +# CHECK: cdzt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xaa + +# CHECK: cdzt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xaa + +# CHECK: cdzt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xaa + +# CHECK: ce %f0, 0 +0x79 0x00 0x00 0x00 + +# CHECK: ce %f0, 4095 +0x79 0x00 0x0f 0xff + +# CHECK: ce %f0, 0(%r1) +0x79 0x00 0x10 0x00 + +# CHECK: ce %f0, 0(%r15) +0x79 0x00 0xf0 0x00 + +# CHECK: ce %f0, 4095(%r1,%r15) +0x79 0x01 0xff 0xff + +# CHECK: ce %f0, 4095(%r15,%r1) +0x79 0x0f 0x1f 0xff + +# CHECK: ce %f15, 0 +0x79 0xf0 0x00 0x00 + # CHECK: ceb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x09 @@ -1606,6 +2056,18 @@ # CHECK: cebr %f15, %f0 0xb3 0x09 0x00 0xf0 +# CHECK: cedtr %f0, %f0 +0xb3 0xf4 0x00 0x00 + +# CHECK: cedtr %f0, %f15 +0xb3 0xf4 0x00 0x0f + +# CHECK: cedtr %f7, %f8 +0xb3 0xf4 0x00 0x78 + +# CHECK: cedtr %f15, %f0 +0xb3 0xf4 0x00 0xf0 + # CHECK: cefbr %f0, %r0 0xb3 0x94 0x00 0x00 @@ -1639,6 +2101,21 @@ # CHECK: cefbra %f15, 0, %r0, 1 0xb3 0x94 0x01 0xf0 +# CHECK: cefr %f0, %r0 +0xb3 0xb4 0x00 0x00 + +# CHECK: cefr %f0, %r15 +0xb3 0xb4 0x00 0x0f + +# CHECK: cefr %f15, %r0 +0xb3 0xb4 0x00 0xf0 + +# CHECK: cefr %f7, %r8 +0xb3 0xb4 0x00 0x78 + +# CHECK: cefr %f15, %r15 +0xb3 0xb4 0x00 0xff + # CHECK: cegbr %f0, %r0 0xb3 0xa4 0x00 0x00 @@ -1672,6 +2149,21 @@ # CHECK: cegbra %f15, 0, %r0, 1 0xb3 0xa4 0x01 0xf0 +# CHECK: cegr %f0, %r0 +0xb3 0xc4 0x00 0x00 + +# CHECK: cegr %f0, %r15 +0xb3 0xc4 0x00 0x0f + +# CHECK: cegr %f15, %r0 +0xb3 0xc4 0x00 0xf0 + +# CHECK: cegr %f7, %r8 +0xb3 0xc4 0x00 0x78 + +# CHECK: cegr %f15, %r15 +0xb3 0xc4 0x00 0xff + # CHECK: celfbr %f0, 0, %r0, 1 0xb3 0x90 0x01 0x00 @@ -1708,6 +2200,30 @@ # CHECK: celgbr %f15, 0, %r0, 1 0xb3 0xa0 0x01 0xf0 +# CHECK: cer %f0, %f0 +0x39 0x00 + +# CHECK: cer %f0, %f15 +0x39 0x0f + +# CHECK: cer %f7, %f8 +0x39 0x78 + +# CHECK: cer %f15, %f0 +0x39 0xf0 + +# CHECK: cextr %f0, %f0 +0xb3 0xfc 0x00 0x00 + +# CHECK: cextr %f0, %f13 +0xb3 0xfc 0x00 0x0d + +# CHECK: cextr %f8, %f8 +0xb3 0xfc 0x00 0x88 + +# CHECK: cextr %f13, %f0 +0xb3 0xfc 0x00 0xd0 + # CHECK: cfc 0 0xb2 0x1a 0x00 0x00 @@ -1759,6 +2275,39 @@ # CHECK: cfdbra %r15, 0, %f0, 1 0xb3 0x99 0x01 0xf0 +# CHECK: cfdr %r0, 0, %f0 +0xb3 0xb9 0x00 0x00 + +# CHECK: cfdr %r0, 0, %f15 +0xb3 0xb9 0x00 0x0f + +# CHECK: cfdr %r0, 15, %f0 +0xb3 0xb9 0xf0 0x00 + +# CHECK: cfdr %r4, 5, %f6 +0xb3 0xb9 0x50 0x46 + +# CHECK: cfdr %r15, 0, %f0 +0xb3 0xb9 0x00 0xf0 + +# CHECK: cfdtr %r0, 0, %f0, 0 +0xb9 0x41 0x00 0x00 + +# CHECK: cfdtr %r0, 0, %f0, 15 +0xb9 0x41 0x0f 0x00 + +# CHECK: cfdtr %r0, 0, %f15, 0 +0xb9 0x41 0x00 0x0f + +# CHECK: cfdtr %r0, 15, %f0, 0 +0xb9 0x41 0xf0 0x00 + +# CHECK: cfdtr %r4, 5, %f6, 7 +0xb9 0x41 0x57 0x46 + +# CHECK: cfdtr %r15, 0, %f0, 0 +0xb9 0x41 0x00 0xf0 + # CHECK: cfebr %r0, 0, %f0 0xb3 0x98 0x00 0x00 @@ -1792,6 +2341,21 @@ # CHECK: cfebra %r15, 0, %f0, 1 0xb3 0x98 0x01 0xf0 +# CHECK: cfer %r0, 0, %f0 +0xb3 0xb8 0x00 0x00 + +# CHECK: cfer %r0, 0, %f15 +0xb3 0xb8 0x00 0x0f + +# CHECK: cfer %r0, 15, %f0 +0xb3 0xb8 0xf0 0x00 + +# CHECK: cfer %r4, 5, %f6 +0xb3 0xb8 0x50 0x46 + +# CHECK: cfer %r15, 0, %f0 +0xb3 0xb8 0x00 0xf0 + # CHECK: cfi %r0, -2147483648 0xc2 0x0d 0x80 0x00 0x00 0x00 @@ -1843,6 +2407,39 @@ # CHECK: cfxbra %r15, 0, %f0, 1 0xb3 0x9a 0x01 0xf0 +# CHECK: cfxr %r0, 0, %f0 +0xb3 0xba 0x00 0x00 + +# CHECK: cfxr %r0, 0, %f13 +0xb3 0xba 0x00 0x0d + +# CHECK: cfxr %r0, 15, %f0 +0xb3 0xba 0xf0 0x00 + +# CHECK: cfxr %r4, 5, %f8 +0xb3 0xba 0x50 0x48 + +# CHECK: cfxr %r15, 0, %f0 +0xb3 0xba 0x00 0xf0 + +# CHECK: cfxtr %r0, 0, %f0, 0 +0xb9 0x49 0x00 0x00 + +# CHECK: cfxtr %r0, 0, %f0, 15 +0xb9 0x49 0x0f 0x00 + +# CHECK: cfxtr %r0, 0, %f13, 0 +0xb9 0x49 0x00 0x0d + +# CHECK: cfxtr %r0, 15, %f0, 0 +0xb9 0x49 0xf0 0x00 + +# CHECK: cfxtr %r7, 5, %f8, 9 +0xb9 0x49 0x59 0x78 + +# CHECK: cfxtr %r15, 0, %f0, 0 +0xb9 0x49 0x00 0xf0 + # CHECK: cg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x20 @@ -1906,6 +2503,54 @@ # CHECK: cgdbra %r15, 0, %f0, 1 0xb3 0xa9 0x01 0xf0 +# CHECK: cgdr %r0, 0, %f0 +0xb3 0xc9 0x00 0x00 + +# CHECK: cgdr %r0, 0, %f15 +0xb3 0xc9 0x00 0x0f + +# CHECK: cgdr %r0, 15, %f0 +0xb3 0xc9 0xf0 0x00 + +# CHECK: cgdr %r4, 5, %f6 +0xb3 0xc9 0x50 0x46 + +# CHECK: cgdr %r15, 0, %f0 +0xb3 0xc9 0x00 0xf0 + +# CHECK: cgdtr %r0, 0, %f0 +0xb3 0xe1 0x00 0x00 + +# CHECK: cgdtr %r0, 0, %f15 +0xb3 0xe1 0x00 0x0f + +# CHECK: cgdtr %r0, 15, %f0 +0xb3 0xe1 0xf0 0x00 + +# CHECK: cgdtr %r4, 5, %f6 +0xb3 0xe1 0x50 0x46 + +# CHECK: cgdtr %r15, 0, %f0 +0xb3 0xe1 0x00 0xf0 + +# CHECK: cgdtra %r0, 0, %f0, 1 +0xb3 0xe1 0x01 0x00 + +# CHECK: cgdtra %r0, 0, %f0, 15 +0xb3 0xe1 0x0f 0x00 + +# CHECK: cgdtra %r0, 0, %f15, 1 +0xb3 0xe1 0x01 0x0f + +# CHECK: cgdtra %r0, 15, %f0, 1 +0xb3 0xe1 0xf1 0x00 + +# CHECK: cgdtra %r4, 5, %f6, 7 +0xb3 0xe1 0x57 0x46 + +# CHECK: cgdtra %r15, 0, %f0, 1 +0xb3 0xe1 0x01 0xf0 + # CHECK: cgebr %r0, 0, %f0 0xb3 0xa8 0x00 0x00 @@ -1939,6 +2584,21 @@ # CHECK: cgebra %r15, 0, %f0, 1 0xb3 0xa8 0x01 0xf0 +# CHECK: cger %r0, 0, %f0 +0xb3 0xc8 0x00 0x00 + +# CHECK: cger %r0, 0, %f15 +0xb3 0xc8 0x00 0x0f + +# CHECK: cger %r0, 15, %f0 +0xb3 0xc8 0xf0 0x00 + +# CHECK: cger %r4, 5, %f6 +0xb3 0xc8 0x50 0x46 + +# CHECK: cger %r15, 0, %f0 +0xb3 0xc8 0x00 0xf0 + # CHECK: cgf %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x30 @@ -2299,6 +2959,54 @@ # CHECK: cgxbra %r15, 0, %f0, 1 0xb3 0xaa 0x01 0xf0 +# CHECK: cgxr %r0, 0, %f0 +0xb3 0xca 0x00 0x00 + +# CHECK: cgxr %r0, 0, %f13 +0xb3 0xca 0x00 0x0d + +# CHECK: cgxr %r0, 15, %f0 +0xb3 0xca 0xf0 0x00 + +# CHECK: cgxr %r4, 5, %f8 +0xb3 0xca 0x50 0x48 + +# CHECK: cgxr %r15, 0, %f0 +0xb3 0xca 0x00 0xf0 + +# CHECK: cgxtr %r0, 0, %f0 +0xb3 0xe9 0x00 0x00 + +# CHECK: cgxtr %r0, 0, %f13 +0xb3 0xe9 0x00 0x0d + +# CHECK: cgxtr %r0, 15, %f0 +0xb3 0xe9 0xf0 0x00 + +# CHECK: cgxtr %r4, 5, %f8 +0xb3 0xe9 0x50 0x48 + +# CHECK: cgxtr %r15, 0, %f0 +0xb3 0xe9 0x00 0xf0 + +# CHECK: cgxtra %r0, 0, %f0, 1 +0xb3 0xe9 0x01 0x00 + +# CHECK: cgxtra %r0, 0, %f0, 15 +0xb3 0xe9 0x0f 0x00 + +# CHECK: cgxtra %r0, 0, %f13, 1 +0xb3 0xe9 0x01 0x0d + +# CHECK: cgxtra %r0, 15, %f0, 1 +0xb3 0xe9 0xf1 0x00 + +# CHECK: cgxtra %r7, 5, %f8, 9 +0xb3 0xe9 0x59 0x78 + +# CHECK: cgxtra %r15, 0, %f0, 1 +0xb3 0xe9 0x01 0xf0 + # CHECK: ch %r0, 0 0x49 0x00 0x00 0x00 @@ -2722,6 +3430,24 @@ # CHECK: clfdbr %r15, 0, %f0, 1 0xb3 0x9d 0x01 0xf0 +# CHECK: clfdtr %r0, 0, %f0, 0 +0xb9 0x43 0x00 0x00 + +# CHECK: clfdtr %r0, 0, %f0, 15 +0xb9 0x43 0x0f 0x00 + +# CHECK: clfdtr %r0, 0, %f15, 0 +0xb9 0x43 0x00 0x0f + +# CHECK: clfdtr %r0, 15, %f0, 0 +0xb9 0x43 0xf0 0x00 + +# CHECK: clfdtr %r4, 5, %f6, 7 +0xb9 0x43 0x57 0x46 + +# CHECK: clfdtr %r15, 0, %f0, 0 +0xb9 0x43 0x00 0xf0 + # CHECK: clfebr %r0, 0, %f0, 1 0xb3 0x9c 0x01 0x00 @@ -2758,6 +3484,24 @@ # CHECK: clfxbr %r15, 0, %f0, 1 0xb3 0x9e 0x01 0xf0 +# CHECK: clfxtr %r0, 0, %f0, 0 +0xb9 0x4b 0x00 0x00 + +# CHECK: clfxtr %r0, 0, %f0, 15 +0xb9 0x4b 0x0f 0x00 + +# CHECK: clfxtr %r0, 0, %f13, 0 +0xb9 0x4b 0x00 0x0d + +# CHECK: clfxtr %r0, 15, %f0, 0 +0xb9 0x4b 0xf0 0x00 + +# CHECK: clfxtr %r7, 5, %f8, 9 +0xb9 0x4b 0x59 0x78 + +# CHECK: clfxtr %r15, 0, %f0, 0 +0xb9 0x4b 0x00 0xf0 + # CHECK: clgdbr %r0, 0, %f0, 1 0xb3 0xad 0x01 0x00 @@ -2776,6 +3520,24 @@ # CHECK: clgdbr %r15, 0, %f0, 1 0xb3 0xad 0x01 0xf0 +# CHECK: clgdtr %r0, 0, %f0, 0 +0xb9 0x42 0x00 0x00 + +# CHECK: clgdtr %r0, 0, %f0, 15 +0xb9 0x42 0x0f 0x00 + +# CHECK: clgdtr %r0, 0, %f15, 0 +0xb9 0x42 0x00 0x0f + +# CHECK: clgdtr %r0, 15, %f0, 0 +0xb9 0x42 0xf0 0x00 + +# CHECK: clgdtr %r4, 5, %f6, 7 +0xb9 0x42 0x57 0x46 + +# CHECK: clgdtr %r15, 0, %f0, 0 +0xb9 0x42 0x00 0xf0 + # CHECK: clgebr %r0, 0, %f0, 1 0xb3 0xac 0x01 0x00 @@ -2884,6 +3646,24 @@ # CHECK: clgxbr %r15, 0, %f0, 1 0xb3 0xae 0x01 0xf0 +# CHECK: clgxtr %r0, 0, %f0, 0 +0xb9 0x4a 0x00 0x00 + +# CHECK: clgxtr %r0, 0, %f0, 15 +0xb9 0x4a 0x0f 0x00 + +# CHECK: clgxtr %r0, 0, %f13, 0 +0xb9 0x4a 0x00 0x0d + +# CHECK: clgxtr %r0, 15, %f0, 0 +0xb9 0x4a 0xf0 0x00 + +# CHECK: clgxtr %r7, 5, %f8, 9 +0xb9 0x4a 0x59 0x78 + +# CHECK: clgxtr %r15, 0, %f0, 0 +0xb9 0x4a 0x00 0xf0 + # CHECK: clfhsi 0, 0 0xe5 0x5d 0x00 0x00 0x00 0x00 @@ -3844,6 +4624,21 @@ # CHECK: cs %r15, %r0, 0 0xba 0xf0 0x00 0x00 +# CHECK: csdtr %r0, %f0, 0 +0xb3 0xe3 0x00 0x00 + +# CHECK: csdtr %r0, %f15, 0 +0xb3 0xe3 0x00 0x0f + +# CHECK: csdtr %r0, %f0, 15 +0xb3 0xe3 0x0f 0x00 + +# CHECK: csdtr %r4, %f5, 6 +0xb3 0xe3 0x06 0x45 + +# CHECK: csdtr %r15, %f0, 0 +0xb3 0xe3 0x00 0xf0 + # CHECK: csg %r0, %r0, -524288 0xeb 0x00 0x00 0x00 0x80 0x30 @@ -3898,6 +4693,21 @@ # CHECK: csst 4095(%r1), 0(%r15), %r2 0xc8 0x22 0x1f 0xff 0xf0 0x00 +# CHECK: csxtr %r0, %f0, 0 +0xb3 0xeb 0x00 0x00 + +# CHECK: csxtr %r0, %f13, 0 +0xb3 0xeb 0x00 0x0d + +# CHECK: csxtr %r0, %f0, 15 +0xb3 0xeb 0x0f 0x00 + +# CHECK: csxtr %r4, %f5, 6 +0xb3 0xeb 0x06 0x45 + +# CHECK: csxtr %r14, %f0, 0 +0xb3 0xeb 0x00 0xe0 + # CHECK: csy %r0, %r0, -524288 0xeb 0x00 0x00 0x00 0x80 0x14 @@ -4027,6 +4837,21 @@ # CHECK: cu42 %r6, %r8 0xb9 0xb3 0x00 0x68 +# CHECK: cudtr %r0, %f0 +0xb3 0xe2 0x00 0x00 + +# CHECK: cudtr %r0, %f15 +0xb3 0xe2 0x00 0x0f + +# CHECK: cudtr %r15, %f0 +0xb3 0xe2 0x00 0xf0 + +# CHECK: cudtr %r7, %f8 +0xb3 0xe2 0x00 0x78 + +# CHECK: cudtr %r15, %f15 +0xb3 0xe2 0x00 0xff + # CHECK: cuse %r0, %r0 0xb2 0x57 0x00 0x00 @@ -4039,6 +4864,21 @@ # CHECK: cuse %r6, %r8 0xb2 0x57 0x00 0x68 +# CHECK: cuxtr %r0, %f0 +0xb3 0xea 0x00 0x00 + +# CHECK: cuxtr %r0, %f13 +0xb3 0xea 0x00 0x0d + +# CHECK: cuxtr %r14, %f0 +0xb3 0xea 0x00 0xe0 + +# CHECK: cuxtr %r6, %f8 +0xb3 0xea 0x00 0x68 + +# CHECK: cuxtr %r14, %f13 +0xb3 0xea 0x00 0xed + # CHECK: cvb %r0, 0 0x4f 0x00 0x00 0x00 @@ -4246,6 +5086,39 @@ # CHECK: cxfbra %f13, 0, %r0, 1 0xb3 0x96 0x01 0xd0 +# CHECK: cxfr %f0, %r0 +0xb3 0xb6 0x00 0x00 + +# CHECK: cxfr %f0, %r15 +0xb3 0xb6 0x00 0x0f + +# CHECK: cxfr %f13, %r0 +0xb3 0xb6 0x00 0xd0 + +# CHECK: cxfr %f8, %r7 +0xb3 0xb6 0x00 0x87 + +# CHECK: cxfr %f13, %r15 +0xb3 0xb6 0x00 0xdf + +# CHECK: cxftr %f0, 0, %r0, 0 +0xb9 0x59 0x00 0x00 + +# CHECK: cxftr %f0, 0, %r0, 15 +0xb9 0x59 0x0f 0x00 + +# CHECK: cxftr %f0, 0, %r15, 0 +0xb9 0x59 0x00 0x0f + +# CHECK: cxftr %f0, 15, %r0, 0 +0xb9 0x59 0xf0 0x00 + +# CHECK: cxftr %f4, 5, %r9, 10 +0xb9 0x59 0x5a 0x49 + +# CHECK: cxftr %f13, 0, %r0, 0 +0xb9 0x59 0x00 0xd0 + # CHECK: cxgbr %f0, %r0 0xb3 0xa6 0x00 0x00 @@ -4279,6 +5152,54 @@ # CHECK: cxgbra %f13, 0, %r0, 1 0xb3 0xa6 0x01 0xd0 +# CHECK: cxgr %f0, %r0 +0xb3 0xc6 0x00 0x00 + +# CHECK: cxgr %f0, %r15 +0xb3 0xc6 0x00 0x0f + +# CHECK: cxgr %f13, %r0 +0xb3 0xc6 0x00 0xd0 + +# CHECK: cxgr %f8, %r7 +0xb3 0xc6 0x00 0x87 + +# CHECK: cxgr %f13, %r15 +0xb3 0xc6 0x00 0xdf + +# CHECK: cxgtr %f0, %r0 +0xb3 0xf9 0x00 0x00 + +# CHECK: cxgtr %f0, %r15 +0xb3 0xf9 0x00 0x0f + +# CHECK: cxgtr %f13, %r0 +0xb3 0xf9 0x00 0xd0 + +# CHECK: cxgtr %f8, %r7 +0xb3 0xf9 0x00 0x87 + +# CHECK: cxgtr %f13, %r15 +0xb3 0xf9 0x00 0xdf + +# CHECK: cxgtra %f0, 0, %r0, 1 +0xb3 0xf9 0x01 0x00 + +# CHECK: cxgtra %f0, 0, %r0, 15 +0xb3 0xf9 0x0f 0x00 + +# CHECK: cxgtra %f0, 0, %r15, 1 +0xb3 0xf9 0x01 0x0f + +# CHECK: cxgtra %f0, 15, %r0, 1 +0xb3 0xf9 0xf1 0x00 + +# CHECK: cxgtra %f4, 5, %r9, 10 +0xb3 0xf9 0x5a 0x49 + +# CHECK: cxgtra %f13, 0, %r0, 1 +0xb3 0xf9 0x01 0xd0 + # CHECK: cxlfbr %f0, 0, %r0, 1 0xb3 0x92 0x01 0x00 @@ -4297,6 +5218,24 @@ # CHECK: cxlfbr %f13, 0, %r0, 1 0xb3 0x92 0x01 0xd0 +# CHECK: cxlftr %f0, 0, %r0, 0 +0xb9 0x5b 0x00 0x00 + +# CHECK: cxlftr %f0, 0, %r0, 15 +0xb9 0x5b 0x0f 0x00 + +# CHECK: cxlftr %f0, 0, %r15, 0 +0xb9 0x5b 0x00 0x0f + +# CHECK: cxlftr %f0, 15, %r0, 0 +0xb9 0x5b 0xf0 0x00 + +# CHECK: cxlftr %f4, 5, %r9, 10 +0xb9 0x5b 0x5a 0x49 + +# CHECK: cxlftr %f13, 0, %r0, 0 +0xb9 0x5b 0x00 0xd0 + # CHECK: cxlgbr %f0, 0, %r0, 1 0xb3 0xa2 0x01 0x00 @@ -4315,6 +5254,105 @@ # CHECK: cxlgbr %f13, 0, %r0, 1 0xb3 0xa2 0x01 0xd0 +# CHECK: cxlgtr %f0, 0, %r0, 0 +0xb9 0x5a 0x00 0x00 + +# CHECK: cxlgtr %f0, 0, %r0, 15 +0xb9 0x5a 0x0f 0x00 + +# CHECK: cxlgtr %f0, 0, %r15, 0 +0xb9 0x5a 0x00 0x0f + +# CHECK: cxlgtr %f0, 15, %r0, 0 +0xb9 0x5a 0xf0 0x00 + +# CHECK: cxlgtr %f4, 5, %r9, 10 +0xb9 0x5a 0x5a 0x49 + +# CHECK: cxlgtr %f13, 0, %r0, 0 +0xb9 0x5a 0x00 0xd0 + +# CHECK: cxr %f0, %f0 +0xb3 0x69 0x00 0x00 + +# CHECK: cxr %f0, %f13 +0xb3 0x69 0x00 0x0d + +# CHECK: cxr %f8, %f8 +0xb3 0x69 0x00 0x88 + +# CHECK: cxr %f13, %f0 +0xb3 0x69 0x00 0xd0 + +# CHECK: cxstr %f0, %r0 +0xb3 0xfb 0x00 0x00 + +# CHECK: cxstr %f0, %r14 +0xb3 0xfb 0x00 0x0e + +# CHECK: cxstr %f13, %r0 +0xb3 0xfb 0x00 0xd0 + +# CHECK: cxstr %f8, %r6 +0xb3 0xfb 0x00 0x86 + +# CHECK: cxstr %f13, %r14 +0xb3 0xfb 0x00 0xde + +# CHECK: cxtr %f0, %f0 +0xb3 0xec 0x00 0x00 + +# CHECK: cxtr %f0, %f13 +0xb3 0xec 0x00 0x0d + +# CHECK: cxtr %f8, %f8 +0xb3 0xec 0x00 0x88 + +# CHECK: cxtr %f13, %f0 +0xb3 0xec 0x00 0xd0 + +# CHECK: cxutr %f0, %r0 +0xb3 0xfa 0x00 0x00 + +# CHECK: cxutr %f0, %r14 +0xb3 0xfa 0x00 0x0e + +# CHECK: cxutr %f13, %r0 +0xb3 0xfa 0x00 0xd0 + +# CHECK: cxutr %f8, %r6 +0xb3 0xfa 0x00 0x86 + +# CHECK: cxutr %f13, %r14 +0xb3 0xfa 0x00 0xde + +# CHECK: cxzt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xab + +# CHECK: cxzt %f13, 0(1), 0 +0xed 0x00 0x00 0x00 0xd0 0xab + +# CHECK: cxzt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xab + +# CHECK: cxzt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xab + +# CHECK: cxzt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xab + +# CHECK: cxzt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xab + +# CHECK: cxzt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xab + +# CHECK: cxzt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xab + +# CHECK: cxzt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xab + # CHECK: cy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x59 @@ -4345,6 +5383,60 @@ # CHECK: cy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x59 +# CHECK: czdt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xa8 + +# CHECK: czdt %f15, 0(1), 0 +0xed 0x00 0x00 0x00 0xf0 0xa8 + +# CHECK: czdt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xa8 + +# CHECK: czdt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xa8 + +# CHECK: czdt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xa8 + +# CHECK: czdt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xa8 + +# CHECK: czdt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xa8 + +# CHECK: czdt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xa8 + +# CHECK: czdt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xa8 + +# CHECK: czxt %f0, 0(1), 0 +0xed 0x00 0x00 0x00 0x00 0xa9 + +# CHECK: czxt %f13, 0(1), 0 +0xed 0x00 0x00 0x00 0xd0 0xa9 + +# CHECK: czxt %f0, 0(1), 15 +0xed 0x00 0x00 0x00 0x0f 0xa9 + +# CHECK: czxt %f0, 0(1,%r1), 0 +0xed 0x00 0x10 0x00 0x00 0xa9 + +# CHECK: czxt %f0, 0(1,%r15), 0 +0xed 0x00 0xf0 0x00 0x00 0xa9 + +# CHECK: czxt %f0, 4095(1,%r1), 0 +0xed 0x00 0x1f 0xff 0x00 0xa9 + +# CHECK: czxt %f0, 4095(1,%r15), 0 +0xed 0x00 0xff 0xff 0x00 0xa9 + +# CHECK: czxt %f0, 0(256,%r1), 0 +0xed 0xff 0x10 0x00 0x00 0xa9 + +# CHECK: czxt %f0, 0(256,%r15), 0 +0xed 0xff 0xf0 0x00 0x00 0xa9 + # CHECK: d %r0, 0 0x5d 0x00 0x00 0x00 @@ -4366,6 +5458,27 @@ # CHECK: d %r14, 0 0x5d 0xe0 0x00 0x00 +# CHECK: dd %f0, 0 +0x6d 0x00 0x00 0x00 + +# CHECK: dd %f0, 4095 +0x6d 0x00 0x0f 0xff + +# CHECK: dd %f0, 0(%r1) +0x6d 0x00 0x10 0x00 + +# CHECK: dd %f0, 0(%r15) +0x6d 0x00 0xf0 0x00 + +# CHECK: dd %f0, 4095(%r1,%r15) +0x6d 0x01 0xff 0xff + +# CHECK: dd %f0, 4095(%r15,%r1) +0x6d 0x0f 0x1f 0xff + +# CHECK: dd %f15, 0 +0x6d 0xf0 0x00 0x00 + # CHECK: ddb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x1d @@ -4399,6 +5512,72 @@ # CHECK: ddbr %f15, %f0 0xb3 0x1d 0x00 0xf0 +# CHECK: ddr %f0, %f0 +0x2d 0x00 + +# CHECK: ddr %f0, %f15 +0x2d 0x0f + +# CHECK: ddr %f7, %f8 +0x2d 0x78 + +# CHECK: ddr %f15, %f0 +0x2d 0xf0 + +# CHECK: ddtr %f0, %f0, %f0 +0xb3 0xd1 0x00 0x00 + +# CHECK: ddtr %f0, %f0, %f15 +0xb3 0xd1 0xf0 0x00 + +# CHECK: ddtr %f0, %f15, %f0 +0xb3 0xd1 0x00 0x0f + +# CHECK: ddtr %f15, %f0, %f0 +0xb3 0xd1 0x00 0xf0 + +# CHECK: ddtr %f7, %f8, %f9 +0xb3 0xd1 0x90 0x78 + +# CHECK: ddtra %f0, %f0, %f0, 1 +0xb3 0xd1 0x01 0x00 + +# CHECK: ddtra %f0, %f0, %f0, 15 +0xb3 0xd1 0x0f 0x00 + +# CHECK: ddtra %f0, %f0, %f15, 1 +0xb3 0xd1 0xf1 0x00 + +# CHECK: ddtra %f0, %f15, %f0, 1 +0xb3 0xd1 0x01 0x0f + +# CHECK: ddtra %f15, %f0, %f0, 1 +0xb3 0xd1 0x01 0xf0 + +# CHECK: ddtra %f7, %f8, %f9, 10 +0xb3 0xd1 0x9a 0x78 + +# CHECK: de %f0, 0 +0x7d 0x00 0x00 0x00 + +# CHECK: de %f0, 4095 +0x7d 0x00 0x0f 0xff + +# CHECK: de %f0, 0(%r1) +0x7d 0x00 0x10 0x00 + +# CHECK: de %f0, 0(%r15) +0x7d 0x00 0xf0 0x00 + +# CHECK: de %f0, 4095(%r1,%r15) +0x7d 0x01 0xff 0xff + +# CHECK: de %f0, 4095(%r15,%r1) +0x7d 0x0f 0x1f 0xff + +# CHECK: de %f15, 0 +0x7d 0xf0 0x00 0x00 + # CHECK: deb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x0d @@ -4432,6 +5611,18 @@ # CHECK: debr %f15, %f0 0xb3 0x0d 0x00 0xf0 +# CHECK: der %f0, %f0 +0x3d 0x00 + +# CHECK: der %f0, %f15 +0x3d 0x0f + +# CHECK: der %f7, %f8 +0x3d 0x78 + +# CHECK: der %f15, %f0 +0x3d 0xf0 + # CHECK: didbr %f0, %f0, %f0, 1 0xb3 0x5b 0x01 0x00 @@ -4702,6 +5893,51 @@ # CHECK: dxbr %f13, %f0 0xb3 0x4d 0x00 0xd0 +# CHECK: dxr %f0, %f0 +0xb2 0x2d 0x00 0x00 + +# CHECK: dxr %f0, %f13 +0xb2 0x2d 0x00 0x0d + +# CHECK: dxr %f8, %f8 +0xb2 0x2d 0x00 0x88 + +# CHECK: dxr %f13, %f0 +0xb2 0x2d 0x00 0xd0 + +# CHECK: dxtr %f0, %f0, %f0 +0xb3 0xd9 0x00 0x00 + +# CHECK: dxtr %f0, %f0, %f13 +0xb3 0xd9 0xd0 0x00 + +# CHECK: dxtr %f0, %f13, %f0 +0xb3 0xd9 0x00 0x0d + +# CHECK: dxtr %f13, %f0, %f0 +0xb3 0xd9 0x00 0xd0 + +# CHECK: dxtr %f8, %f8, %f8 +0xb3 0xd9 0x80 0x88 + +# CHECK: dxtra %f0, %f0, %f0, 1 +0xb3 0xd9 0x01 0x00 + +# CHECK: dxtra %f0, %f0, %f0, 15 +0xb3 0xd9 0x0f 0x00 + +# CHECK: dxtra %f0, %f0, %f13, 1 +0xb3 0xd9 0xd1 0x00 + +# CHECK: dxtra %f0, %f13, %f0, 1 +0xb3 0xd9 0x01 0x0d + +# CHECK: dxtra %f13, %f0, %f0, 1 +0xb3 0xd9 0x01 0xd0 + +# CHECK: dxtra %f8, %f8, %f8, 8 +0xb3 0xd9 0x88 0x88 + # CHECK: ear %r0, %a0 0xb2 0x4f 0x00 0x00 @@ -4849,6 +6085,30 @@ # CHECK: edmk 0(256,%r15), 0 0xdf 0xff 0xf0 0x00 0x00 0x00 +# CHECK: eedtr %f0, %f9 +0xb3 0xe5 0x00 0x09 + +# CHECK: eedtr %f0, %f15 +0xb3 0xe5 0x00 0x0f + +# CHECK: eedtr %f15, %f0 +0xb3 0xe5 0x00 0xf0 + +# CHECK: eedtr %f15, %f9 +0xb3 0xe5 0x00 0xf9 + +# CHECK: eextr %f0, %f8 +0xb3 0xed 0x00 0x08 + +# CHECK: eextr %f0, %f13 +0xb3 0xed 0x00 0x0d + +# CHECK: eextr %f13, %f0 +0xb3 0xed 0x00 0xd0 + +# CHECK: eextr %f13, %f9 +0xb3 0xed 0x00 0xd9 + # CHECK: efpc %r0 0xb3 0x8c 0x00 0x00 @@ -4870,6 +6130,30 @@ # CHECK: epsw %r6, %r8 0xb9 0x8d 0x00 0x68 +# CHECK: esdtr %f0, %f9 +0xb3 0xe7 0x00 0x09 + +# CHECK: esdtr %f0, %f15 +0xb3 0xe7 0x00 0x0f + +# CHECK: esdtr %f15, %f0 +0xb3 0xe7 0x00 0xf0 + +# CHECK: esdtr %f15, %f9 +0xb3 0xe7 0x00 0xf9 + +# CHECK: esxtr %f0, %f8 +0xb3 0xef 0x00 0x08 + +# CHECK: esxtr %f0, %f13 +0xb3 0xef 0x00 0x0d + +# CHECK: esxtr %f13, %f0 +0xb3 0xef 0x00 0xd0 + +# CHECK: esxtr %f13, %f9 +0xb3 0xef 0x00 0xd9 + # CHECK: etnd %r0 0xb2 0xec 0x00 0x00 @@ -4933,6 +6217,36 @@ # CHECK: fidbra %f15, 0, %f0, 1 0xb3 0x5f 0x01 0xf0 +# CHECK: fidr %f0, %f0 +0xb3 0x7f 0x00 0x00 + +# CHECK: fidr %f0, %f15 +0xb3 0x7f 0x00 0x0f + +# CHECK: fidr %f4, %f6 +0xb3 0x7f 0x00 0x46 + +# CHECK: fidr %f15, %f0 +0xb3 0x7f 0x00 0xf0 + +# CHECK: fidtr %f0, 0, %f0, 0 +0xb3 0xd7 0x00 0x00 + +# CHECK: fidtr %f0, 0, %f0, 15 +0xb3 0xd7 0x0f 0x00 + +# CHECK: fidtr %f0, 0, %f15, 0 +0xb3 0xd7 0x00 0x0f + +# CHECK: fidtr %f0, 15, %f0, 0 +0xb3 0xd7 0xf0 0x00 + +# CHECK: fidtr %f4, 5, %f6, 7 +0xb3 0xd7 0x57 0x46 + +# CHECK: fidtr %f15, 0, %f0, 0 +0xb3 0xd7 0x00 0xf0 + # CHECK: fiebr %f0, 0, %f0 0xb3 0x57 0x00 0x00 @@ -4966,6 +6280,18 @@ # CHECK: fiebra %f15, 0, %f0, 1 0xb3 0x57 0x01 0xf0 +# CHECK: fier %f0, %f0 +0xb3 0x77 0x00 0x00 + +# CHECK: fier %f0, %f15 +0xb3 0x77 0x00 0x0f + +# CHECK: fier %f4, %f6 +0xb3 0x77 0x00 0x46 + +# CHECK: fier %f15, %f0 +0xb3 0x77 0x00 0xf0 + # CHECK: fixbr %f0, 0, %f0 0xb3 0x47 0x00 0x00 @@ -4999,6 +6325,36 @@ # CHECK: fixbra %f13, 0, %f0, 1 0xb3 0x47 0x01 0xd0 +# CHECK: fixr %f0, %f0 +0xb3 0x67 0x00 0x00 + +# CHECK: fixr %f0, %f13 +0xb3 0x67 0x00 0x0d + +# CHECK: fixr %f4, %f8 +0xb3 0x67 0x00 0x48 + +# CHECK: fixr %f13, %f0 +0xb3 0x67 0x00 0xd0 + +# CHECK: fixtr %f0, 0, %f0, 0 +0xb3 0xdf 0x00 0x00 + +# CHECK: fixtr %f0, 0, %f0, 15 +0xb3 0xdf 0x0f 0x00 + +# CHECK: fixtr %f0, 0, %f13, 0 +0xb3 0xdf 0x00 0x0d + +# CHECK: fixtr %f0, 15, %f0, 0 +0xb3 0xdf 0xf0 0x00 + +# CHECK: fixtr %f4, 5, %f8, 9 +0xb3 0xdf 0x59 0x48 + +# CHECK: fixtr %f13, 0, %f0, 0 +0xb3 0xdf 0x00 0xd0 + # CHECK: flogr %r0, %r0 0xb9 0x83 0x00 0x00 @@ -5011,6 +6367,30 @@ # CHECK: flogr %r14, %r0 0xb9 0x83 0x00 0xe0 +# CHECK: hdr %f0, %f0 +0x24 0x00 + +# CHECK: hdr %f0, %f15 +0x24 0x0f + +# CHECK: hdr %f7, %f8 +0x24 0x78 + +# CHECK: hdr %f15, %f0 +0x24 0xf0 + +# CHECK: her %f0, %f0 +0x34 0x00 + +# CHECK: her %f0, %f15 +0x34 0x0f + +# CHECK: her %f7, %f8 +0x34 0x78 + +# CHECK: her %f15, %f0 +0x34 0xf0 + # CHECK: ic %r0, 0 0x43 0x00 0x00 0x00 @@ -5143,6 +6523,42 @@ # CHECK: icy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x73 +# CHECK: iedtr %f0, %f0, %f0 +0xb3 0xf6 0x00 0x00 + +# CHECK: iedtr %f0, %f0, %f15 +0xb3 0xf6 0x00 0x0f + +# CHECK: iedtr %f0, %f15, %f0 +0xb3 0xf6 0xf0 0x00 + +# CHECK: iedtr %f15, %f0, %f0 +0xb3 0xf6 0x00 0xf0 + +# CHECK: iedtr %f1, %f2, %f3 +0xb3 0xf6 0x20 0x13 + +# CHECK: iedtr %f15, %f15, %f15 +0xb3 0xf6 0xf0 0xff + +# CHECK: iextr %f0, %f0, %f0 +0xb3 0xfe 0x00 0x00 + +# CHECK: iextr %f0, %f0, %f13 +0xb3 0xfe 0x00 0x0d + +# CHECK: iextr %f0, %f13, %f0 +0xb3 0xfe 0xd0 0x00 + +# CHECK: iextr %f13, %f0, %f0 +0xb3 0xfe 0x00 0xd0 + +# CHECK: iextr %f1, %f8, %f4 +0xb3 0xfe 0x80 0x14 + +# CHECK: iextr %f13, %f13, %f13 +0xb3 0xfe 0xd0 0xdd + # CHECK: iihf %r0, 0 0xc0 0x08 0x00 0x00 0x00 0x00 @@ -5251,6 +6667,18 @@ # CHECK: kdbr %f15, %f0 0xb3 0x18 0x00 0xf0 +# CHECK: kdtr %f0, %f0 +0xb3 0xe0 0x00 0x00 + +# CHECK: kdtr %f0, %f15 +0xb3 0xe0 0x00 0x0f + +# CHECK: kdtr %f7, %f8 +0xb3 0xe0 0x00 0x78 + +# CHECK: kdtr %f15, %f0 +0xb3 0xe0 0x00 0xf0 + # CHECK: keb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x08 @@ -5392,6 +6820,18 @@ # CHECK: kxbr %f13, %f0 0xb3 0x48 0x00 0xd0 +# CHECK: kxtr %f0, %f0 +0xb3 0xe8 0x00 0x00 + +# CHECK: kxtr %f0, %f13 +0xb3 0xe8 0x00 0x0d + +# CHECK: kxtr %f8, %f8 +0xb3 0xe8 0x00 0x88 + +# CHECK: kxtr %f13, %f0 +0xb3 0xe8 0x00 0xd0 + # CHECK: l %r0, 0 0x58 0x00 0x00 0x00 @@ -6025,6 +7465,18 @@ # CHECK: lcdbr %f15, %f9 0xb3 0x13 0x00 0xf9 +# CHECK: lcdr %f0, %f9 +0x23 0x09 + +# CHECK: lcdr %f0, %f15 +0x23 0x0f + +# CHECK: lcdr %f15, %f0 +0x23 0xf0 + +# CHECK: lcdr %f15, %f9 +0x23 0xf9 + # CHECK: lcebr %f0, %f9 0xb3 0x03 0x00 0x09 @@ -6037,9 +7489,20 @@ # CHECK: lcebr %f15, %f9 0xb3 0x03 0x00 0xf9 +# CHECK: lcer %f0, %f9 +0x33 0x09 + +# CHECK: lcer %f0, %f15 +0x33 0x0f + +# CHECK: lcer %f15, %f0 +0x33 0xf0 + +# CHECK: lcer %f15, %f9 +0x33 0xf9 + # CHECK: lcgfr %r0, %r0 0xb9 0x13 0x00 0x00 - # CHECK: lcgfr %r0, %r15 0xb9 0x13 0x00 0x0f @@ -6085,6 +7548,18 @@ # CHECK: lcxbr %f13, %f9 0xb3 0x43 0x00 0xd9 +# CHECK: lcxr %f0, %f8 +0xb3 0x63 0x00 0x08 + +# CHECK: lcxr %f0, %f13 +0xb3 0x63 0x00 0x0d + +# CHECK: lcxr %f13, %f0 +0xb3 0x63 0x00 0xd0 + +# CHECK: lcxr %f13, %f9 +0xb3 0x63 0x00 0xd9 + # CHECK: ld %f0, 0 0x68 0x00 0x00 0x00 @@ -6106,6 +7581,27 @@ # CHECK: ld %f15, 0 0x68 0xf0 0x00 0x00 +# CHECK: lde %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x24 + +# CHECK: lde %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x24 + +# CHECK: lde %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x24 + +# CHECK: lde %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x24 + +# CHECK: lde %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x24 + +# CHECK: lde %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x24 + +# CHECK: lde %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x24 + # CHECK: ldeb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x04 @@ -6136,6 +7632,27 @@ # CHECK: ldebr %f15, %f0 0xb3 0x04 0x00 0xf0 +# CHECK: lder %f0, %f15 +0xb3 0x24 0x00 0x0f + +# CHECK: lder %f7, %f8 +0xb3 0x24 0x00 0x78 + +# CHECK: lder %f15, %f0 +0xb3 0x24 0x00 0xf0 + +# CHECK: ldetr %f0, %f0, 15 +0xb3 0xd4 0x0f 0x00 + +# CHECK: ldetr %f0, %f15, 0 +0xb3 0xd4 0x00 0x0f + +# CHECK: ldetr %f7, %f8, 9 +0xb3 0xd4 0x09 0x78 + +# CHECK: ldetr %f15, %f0, 0 +0xb3 0xd4 0x00 0xf0 + # CHECK: ldgr %f0, %r0 0xb3 0xc1 0x00 0x00 @@ -6196,6 +7713,39 @@ # CHECK: ldxbra %f13, 0, %f0, 1 0xb3 0x45 0x01 0xd0 +# CHECK: ldxr %f0, %f0 +0x25 0x00 + +# CHECK: ldxr %f0, %f13 +0x25 0x0d + +# CHECK: ldxr %f7, %f8 +0x25 0x78 + +# CHECK: ldxr %f15, %f0 +0x25 0xf0 + +# CHECK: ldxr %f15, %f13 +0x25 0xfd + +# CHECK: ldxtr %f0, 0, %f0, 0 +0xb3 0xdd 0x00 0x00 + +# CHECK: ldxtr %f0, 0, %f0, 15 +0xb3 0xdd 0x0f 0x00 + +# CHECK: ldxtr %f0, 0, %f13, 0 +0xb3 0xdd 0x00 0x0d + +# CHECK: ldxtr %f0, 15, %f0, 0 +0xb3 0xdd 0xf0 0x00 + +# CHECK: ldxtr %f4, 5, %f8, 9 +0xb3 0xdd 0x59 0x48 + +# CHECK: ldxtr %f13, 0, %f0, 0 +0xb3 0xdd 0x00 0xd0 + # CHECK: ldy %f0, -524288 0xed 0x00 0x00 0x00 0x80 0x65 @@ -6280,6 +7830,36 @@ # CHECK: ledbra %f15, 0, %f0, 1 0xb3 0x44 0x01 0xf0 +# CHECK: ledr %f0, %f0 +0x35 0x00 + +# CHECK: ledr %f0, %f15 +0x35 0x0f + +# CHECK: ledr %f7, %f8 +0x35 0x78 + +# CHECK: ledr %f15, %f0 +0x35 0xf0 + +# CHECK: ledr %f15, %f15 +0x35 0xff + +# CHECK: ledtr %f0, 0, %f0, 15 +0xb3 0xd5 0x0f 0x00 + +# CHECK: ledtr %f0, 0, %f15, 0 +0xb3 0xd5 0x00 0x0f + +# CHECK: ledtr %f0, 15, %f0, 0 +0xb3 0xd5 0xf0 0x00 + +# CHECK: ledtr %f4, 5, %f6, 7 +0xb3 0xd5 0x57 0x46 + +# CHECK: ledtr %f15, 0, %f0, 0 +0xb3 0xd5 0x00 0xf0 + # CHECK: ler %f0, %f9 0x38 0x09 @@ -6325,6 +7905,21 @@ # CHECK: lexbra %f13, 0, %f0, 1 0xb3 0x46 0x01 0xd0 +# CHECK: lexr %f0, %f0 +0xb3 0x66 0x00 0x00 + +# CHECK: lexr %f0, %f13 +0xb3 0x66 0x00 0x0d + +# CHECK: lexr %f7, %f8 +0xb3 0x66 0x00 0x78 + +# CHECK: lexr %f15, %f0 +0xb3 0x66 0x00 0xf0 + +# CHECK: lexr %f15, %f13 +0xb3 0x66 0x00 0xfd + # CHECK: ley %f0, -524288 0xed 0x00 0x00 0x00 0x80 0x64 @@ -7399,6 +8994,18 @@ # CHECK: lndbr %f15, %f9 0xb3 0x11 0x00 0xf9 +# CHECK: lndr %f0, %f9 +0x21 0x09 + +# CHECK: lndr %f0, %f15 +0x21 0x0f + +# CHECK: lndr %f15, %f0 +0x21 0xf0 + +# CHECK: lndr %f15, %f9 +0x21 0xf9 + # CHECK: lnebr %f0, %f9 0xb3 0x01 0x00 0x09 @@ -7411,6 +9018,18 @@ # CHECK: lnebr %f15, %f9 0xb3 0x01 0x00 0xf9 +# CHECK: lner %f0, %f9 +0x31 0x09 + +# CHECK: lner %f0, %f15 +0x31 0x0f + +# CHECK: lner %f15, %f0 +0x31 0xf0 + +# CHECK: lner %f15, %f9 +0x31 0xf9 + # CHECK: lngfr %r0, %r0 0xb9 0x11 0x00 0x00 @@ -7459,6 +9078,18 @@ # CHECK: lnxbr %f13, %f9 0xb3 0x41 0x00 0xd9 +# CHECK: lnxr %f0, %f8 +0xb3 0x61 0x00 0x08 + +# CHECK: lnxr %f0, %f13 +0xb3 0x61 0x00 0x0d + +# CHECK: lnxr %f13, %f0 +0xb3 0x61 0x00 0xd0 + +# CHECK: lnxr %f13, %f9 +0xb3 0x61 0x00 0xd9 + # CHECK: loc %r7, 6399(%r8), 0 0xeb 0x70 0x88 0xff 0x01 0xf2 @@ -7705,6 +9336,18 @@ # CHECK: lpdg %r2, 4095(%r1), 0(%r15) 0xc8 0x25 0x1f 0xff 0xf0 0x00 +# CHECK: lpdr %f0, %f9 +0x20 0x09 + +# CHECK: lpdr %f0, %f15 +0x20 0x0f + +# CHECK: lpdr %f15, %f0 +0x20 0xf0 + +# CHECK: lpdr %f15, %f9 +0x20 0xf9 + # CHECK: lpebr %f0, %f9 0xb3 0x00 0x00 0x09 @@ -7717,6 +9360,18 @@ # CHECK: lpebr %f15, %f9 0xb3 0x00 0x00 0xf9 +# CHECK: lper %f0, %f9 +0x30 0x09 + +# CHECK: lper %f0, %f15 +0x30 0x0f + +# CHECK: lper %f15, %f0 +0x30 0xf0 + +# CHECK: lper %f15, %f9 +0x30 0xf9 + # CHECK: lpgfr %r0, %r0 0xb9 0x10 0x00 0x00 @@ -7795,6 +9450,18 @@ # CHECK: lpxbr %f13, %f9 0xb3 0x40 0x00 0xd9 +# CHECK: lpxr %f0, %f8 +0xb3 0x60 0x00 0x08 + +# CHECK: lpxr %f0, %f13 +0xb3 0x60 0x00 0x0d + +# CHECK: lpxr %f13, %f0 +0xb3 0x60 0x00 0xd0 + +# CHECK: lpxr %f13, %f9 +0xb3 0x60 0x00 0xd9 + # CHECK: lr %r0, %r9 0x18 0x09 @@ -7969,6 +9636,30 @@ # CHECK: ltdbr %f15, %f9 0xb3 0x12 0x00 0xf9 +# CHECK: ltdr %f0, %f9 +0x22 0x09 + +# CHECK: ltdr %f0, %f15 +0x22 0x0f + +# CHECK: ltdr %f15, %f0 +0x22 0xf0 + +# CHECK: ltdr %f15, %f9 +0x22 0xf9 + +# CHECK: ltdtr %f0, %f9 +0xb3 0xd6 0x00 0x09 + +# CHECK: ltdtr %f0, %f15 +0xb3 0xd6 0x00 0x0f + +# CHECK: ltdtr %f15, %f0 +0xb3 0xd6 0x00 0xf0 + +# CHECK: ltdtr %f15, %f9 +0xb3 0xd6 0x00 0xf9 + # CHECK: ltebr %f0, %f9 0xb3 0x02 0x00 0x09 @@ -7981,6 +9672,18 @@ # CHECK: ltebr %f15, %f9 0xb3 0x02 0x00 0xf9 +# CHECK: lter %f0, %f9 +0x32 0x09 + +# CHECK: lter %f0, %f15 +0x32 0x0f + +# CHECK: lter %f15, %f0 +0x32 0xf0 + +# CHECK: lter %f15, %f9 +0x32 0xf9 + # CHECK: ltg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x02 @@ -8089,6 +9792,168 @@ # CHECK: ltxbr %f13, %f9 0xb3 0x42 0x00 0xd9 +# CHECK: ltxr %f0, %f9 +0xb3 0x62 0x00 0x09 + +# CHECK: ltxr %f0, %f13 +0xb3 0x62 0x00 0x0d + +# CHECK: ltxr %f13, %f0 +0xb3 0x62 0x00 0xd0 + +# CHECK: ltxr %f13, %f9 +0xb3 0x62 0x00 0xd9 + +# CHECK: ltxtr %f0, %f9 +0xb3 0xde 0x00 0x09 + +# CHECK: ltxtr %f0, %f13 +0xb3 0xde 0x00 0x0d + +# CHECK: ltxtr %f13, %f0 +0xb3 0xde 0x00 0xd0 + +# CHECK: ltxtr %f13, %f9 +0xb3 0xde 0x00 0xd9 + +# CHECK: lxd %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x25 + +# CHECK: lxd %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x25 + +# CHECK: lxd %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x25 + +# CHECK: lxd %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x25 + +# CHECK: lxd %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x25 + +# CHECK: lxd %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x25 + +# CHECK: lxdb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x05 + +# CHECK: lxdb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x05 + +# CHECK: lxdb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x05 + +# CHECK: lxdb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x05 + +# CHECK: lxdb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x05 + +# CHECK: lxdb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x05 + +# CHECK: lxdb %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x05 + +# CHECK: lxdbr %f0, %f8 +0xb3 0x05 0x00 0x08 + +# CHECK: lxdbr %f0, %f13 +0xb3 0x05 0x00 0x0d + +# CHECK: lxdbr %f13, %f0 +0xb3 0x05 0x00 0xd0 + +# CHECK: lxdbr %f13, %f15 +0xb3 0x05 0x00 0xdf + +# CHECK: lxdr %f0, %f8 +0xb3 0x25 0x00 0x08 + +# CHECK: lxdr %f0, %f13 +0xb3 0x25 0x00 0x0d + +# CHECK: lxdr %f13, %f0 +0xb3 0x25 0x00 0xd0 + +# CHECK: lxdr %f13, %f15 +0xb3 0x25 0x00 0xdf + +# CHECK: lxdtr %f0, %f0, 15 +0xb3 0xdc 0x0f 0x00 + +# CHECK: lxdtr %f0, %f15, 0 +0xb3 0xdc 0x00 0x0f + +# CHECK: lxdtr %f5, %f8, 9 +0xb3 0xdc 0x09 0x58 + +# CHECK: lxdtr %f13, %f0, 0 +0xb3 0xdc 0x00 0xd0 + +# CHECK: lxe %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x26 + +# CHECK: lxe %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x26 + +# CHECK: lxe %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x26 + +# CHECK: lxe %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x26 + +# CHECK: lxe %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x26 + +# CHECK: lxe %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x26 + +# CHECK: lxeb %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x06 + +# CHECK: lxeb %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x06 + +# CHECK: lxeb %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x06 + +# CHECK: lxeb %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x06 + +# CHECK: lxeb %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x06 + +# CHECK: lxeb %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x06 + +# CHECK: lxeb %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x06 + +# CHECK: lxebr %f0, %f8 +0xb3 0x06 0x00 0x08 + +# CHECK: lxebr %f0, %f13 +0xb3 0x06 0x00 0x0d + +# CHECK: lxebr %f13, %f0 +0xb3 0x06 0x00 0xd0 + +# CHECK: lxebr %f13, %f15 +0xb3 0x06 0x00 0xdf + +# CHECK: lxer %f0, %f8 +0xb3 0x26 0x00 0x08 + +# CHECK: lxer %f0, %f13 +0xb3 0x26 0x00 0x0d + +# CHECK: lxer %f13, %f0 +0xb3 0x26 0x00 0xd0 + +# CHECK: lxer %f13, %f15 +0xb3 0x26 0x00 0xdf + # CHECK: lxr %f0, %f8 0xb3 0x65 0x00 0x08 @@ -8179,6 +10044,33 @@ # CHECK: m %r14, 0 0x5c 0xe0 0x00 0x00 +# CHECK: mad %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x3e + +# CHECK: mad %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x3e + +# CHECK: mad %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x3e + +# CHECK: mad %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x3e + +# CHECK: mad %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x3e + +# CHECK: mad %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x3e + +# CHECK: mad %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x3e + +# CHECK: mad %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x3e + +# CHECK: mad %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x3e + # CHECK: madb %f0, %f0, 0 0xed 0x00 0x00 0x00 0x00 0x1e @@ -8224,6 +10116,51 @@ # CHECK: madbr %f15, %f15, %f15 0xb3 0x1e 0xf0 0xff +# CHECK: madr %f0, %f0, %f0 +0xb3 0x3e 0x00 0x00 + +# CHECK: madr %f0, %f0, %f15 +0xb3 0x3e 0x00 0x0f + +# CHECK: madr %f0, %f15, %f0 +0xb3 0x3e 0x00 0xf0 + +# CHECK: madr %f15, %f0, %f0 +0xb3 0x3e 0xf0 0x00 + +# CHECK: madr %f7, %f8, %f9 +0xb3 0x3e 0x70 0x89 + +# CHECK: madr %f15, %f15, %f15 +0xb3 0x3e 0xf0 0xff + +# CHECK: mae %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x2e + +# CHECK: mae %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x2e + +# CHECK: mae %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x2e + +# CHECK: mae %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x2e + +# CHECK: mae %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x2e + +# CHECK: mae %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x2e + +# CHECK: mae %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x2e + +# CHECK: mae %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x2e + +# CHECK: mae %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x2e + # CHECK: maeb %f0, %f0, 0 0xed 0x00 0x00 0x00 0x00 0x0e @@ -8269,6 +10206,159 @@ # CHECK: maebr %f15, %f15, %f15 0xb3 0x0e 0xf0 0xff +# CHECK: maer %f0, %f0, %f0 +0xb3 0x2e 0x00 0x00 + +# CHECK: maer %f0, %f0, %f15 +0xb3 0x2e 0x00 0x0f + +# CHECK: maer %f0, %f15, %f0 +0xb3 0x2e 0x00 0xf0 + +# CHECK: maer %f15, %f0, %f0 +0xb3 0x2e 0xf0 0x00 + +# CHECK: maer %f7, %f8, %f9 +0xb3 0x2e 0x70 0x89 + +# CHECK: maer %f15, %f15, %f15 +0xb3 0x2e 0xf0 0xff + +# CHECK: may %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x3a + +# CHECK: may %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x3a + +# CHECK: may %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x3a + +# CHECK: may %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x3a + +# CHECK: may %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x3a + +# CHECK: may %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x3a + +# CHECK: may %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x3a + +# CHECK: may %f13, %f0, 0 +0xed 0x00 0x00 0x00 0xd0 0x3a + +# CHECK: may %f13, %f15, 0 +0xed 0xf0 0x00 0x00 0xd0 0x3a + +# CHECK: mayh %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x3c + +# CHECK: mayh %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x3c + +# CHECK: mayh %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x3c + +# CHECK: mayh %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x3c + +# CHECK: mayh %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x3c + +# CHECK: mayh %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x3c + +# CHECK: mayh %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x3c + +# CHECK: mayh %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x3c + +# CHECK: mayh %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x3c + +# CHECK: mayhr %f0, %f0, %f0 +0xb3 0x3c 0x00 0x00 + +# CHECK: mayhr %f0, %f0, %f15 +0xb3 0x3c 0x00 0x0f + +# CHECK: mayhr %f0, %f15, %f0 +0xb3 0x3c 0x00 0xf0 + +# CHECK: mayhr %f15, %f0, %f0 +0xb3 0x3c 0xf0 0x00 + +# CHECK: mayhr %f7, %f8, %f9 +0xb3 0x3c 0x70 0x89 + +# CHECK: mayhr %f15, %f15, %f15 +0xb3 0x3c 0xf0 0xff + +# CHECK: mayl %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x38 + +# CHECK: mayl %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x38 + +# CHECK: mayl %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x38 + +# CHECK: mayl %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x38 + +# CHECK: mayl %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x38 + +# CHECK: mayl %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x38 + +# CHECK: mayl %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x38 + +# CHECK: mayl %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x38 + +# CHECK: mayl %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x38 + +# CHECK: maylr %f0, %f0, %f0 +0xb3 0x38 0x00 0x00 + +# CHECK: maylr %f0, %f0, %f15 +0xb3 0x38 0x00 0x0f + +# CHECK: maylr %f0, %f15, %f0 +0xb3 0x38 0x00 0xf0 + +# CHECK: maylr %f15, %f0, %f0 +0xb3 0x38 0xf0 0x00 + +# CHECK: maylr %f7, %f8, %f9 +0xb3 0x38 0x70 0x89 + +# CHECK: maylr %f15, %f15, %f15 +0xb3 0x38 0xf0 0xff + +# CHECK: mayr %f0, %f0, %f0 +0xb3 0x3a 0x00 0x00 + +# CHECK: mayr %f0, %f0, %f15 +0xb3 0x3a 0x00 0x0f + +# CHECK: mayr %f0, %f15, %f0 +0xb3 0x3a 0x00 0xf0 + +# CHECK: mayr %f13, %f0, %f0 +0xb3 0x3a 0xd0 0x00 + +# CHECK: mayr %f5, %f8, %f9 +0xb3 0x3a 0x50 0x89 + +# CHECK: mayr %f13, %f15, %f15 +0xb3 0x3a 0xd0 0xff + # CHECK: mc 0, 0 0xaf 0x00 0x00 0x00 @@ -8290,6 +10380,27 @@ # CHECK: mc 4095(%r15), 42 0xaf 0x2a 0xff 0xff +# CHECK: md %f0, 0 +0x6c 0x00 0x00 0x00 + +# CHECK: md %f0, 4095 +0x6c 0x00 0x0f 0xff + +# CHECK: md %f0, 0(%r1) +0x6c 0x00 0x10 0x00 + +# CHECK: md %f0, 0(%r15) +0x6c 0x00 0xf0 0x00 + +# CHECK: md %f0, 4095(%r1,%r15) +0x6c 0x01 0xff 0xff + +# CHECK: md %f0, 4095(%r15,%r1) +0x6c 0x0f 0x1f 0xff + +# CHECK: md %f15, 0 +0x6c 0xf0 0x00 0x00 + # CHECK: mdb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x1c @@ -8323,6 +10434,27 @@ # CHECK: mdbr %f15, %f0 0xb3 0x1c 0x00 0xf0 +# CHECK: mde %f0, 0 +0x7c 0x00 0x00 0x00 + +# CHECK: mde %f0, 4095 +0x7c 0x00 0x0f 0xff + +# CHECK: mde %f0, 0(%r1) +0x7c 0x00 0x10 0x00 + +# CHECK: mde %f0, 0(%r15) +0x7c 0x00 0xf0 0x00 + +# CHECK: mde %f0, 4095(%r1,%r15) +0x7c 0x01 0xff 0xff + +# CHECK: mde %f0, 4095(%r15,%r1) +0x7c 0x0f 0x1f 0xff + +# CHECK: mde %f15, 0 +0x7c 0xf0 0x00 0x00 + # CHECK: mdeb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x0c @@ -8356,6 +10488,84 @@ # CHECK: mdebr %f15, %f0 0xb3 0x0c 0x00 0xf0 +# CHECK: mder %f0, %f0 +0x3c 0x00 + +# CHECK: mder %f0, %f15 +0x3c 0x0f + +# CHECK: mder %f7, %f8 +0x3c 0x78 + +# CHECK: mder %f15, %f0 +0x3c 0xf0 + +# CHECK: mdr %f0, %f0 +0x2c 0x00 + +# CHECK: mdr %f0, %f15 +0x2c 0x0f + +# CHECK: mdr %f7, %f8 +0x2c 0x78 + +# CHECK: mdr %f15, %f0 +0x2c 0xf0 + +# CHECK: mdtr %f0, %f0, %f0 +0xb3 0xd0 0x00 0x00 + +# CHECK: mdtr %f0, %f0, %f15 +0xb3 0xd0 0xf0 0x00 + +# CHECK: mdtr %f0, %f15, %f0 +0xb3 0xd0 0x00 0x0f + +# CHECK: mdtr %f15, %f0, %f0 +0xb3 0xd0 0x00 0xf0 + +# CHECK: mdtr %f7, %f8, %f9 +0xb3 0xd0 0x90 0x78 + +# CHECK: mdtra %f0, %f0, %f0, 1 +0xb3 0xd0 0x01 0x00 + +# CHECK: mdtra %f0, %f0, %f0, 15 +0xb3 0xd0 0x0f 0x00 + +# CHECK: mdtra %f0, %f0, %f15, 1 +0xb3 0xd0 0xf1 0x00 + +# CHECK: mdtra %f0, %f15, %f0, 1 +0xb3 0xd0 0x01 0x0f + +# CHECK: mdtra %f15, %f0, %f0, 1 +0xb3 0xd0 0x01 0xf0 + +# CHECK: mdtra %f7, %f8, %f9, 10 +0xb3 0xd0 0x9a 0x78 + +# CHECK: mee %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x37 + +# CHECK: mee %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x37 + +# CHECK: mee %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x37 + +# CHECK: mee %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x37 + +# CHECK: mee %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x37 + +# CHECK: mee %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x37 + +# CHECK: mee %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x37 + # CHECK: meeb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x17 @@ -8389,6 +10599,18 @@ # CHECK: meebr %f15, %f0 0xb3 0x17 0x00 0xf0 +# CHECK: meer %f0, %f0 +0xb3 0x37 0x00 0x00 + +# CHECK: meer %f0, %f15 +0xb3 0x37 0x00 0x0f + +# CHECK: meer %f7, %f8 +0xb3 0x37 0x00 0x78 + +# CHECK: meer %f15, %f0 +0xb3 0x37 0x00 0xf0 + # CHECK: mfy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x5c @@ -8665,6 +10887,33 @@ # CHECK: ms %r15, 0 0x71 0xf0 0x00 0x00 +# CHECK: msd %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x3f + +# CHECK: msd %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x3f + +# CHECK: msd %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x3f + +# CHECK: msd %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x3f + +# CHECK: msd %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x3f + +# CHECK: msd %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x3f + +# CHECK: msd %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x3f + +# CHECK: msd %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x3f + +# CHECK: msd %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x3f + # CHECK: msdb %f0, %f0, 0 0xed 0x00 0x00 0x00 0x00 0x1f @@ -8710,6 +10959,51 @@ # CHECK: msdbr %f15, %f15, %f15 0xb3 0x1f 0xf0 0xff +# CHECK: msdr %f0, %f0, %f0 +0xb3 0x3f 0x00 0x00 + +# CHECK: msdr %f0, %f0, %f15 +0xb3 0x3f 0x00 0x0f + +# CHECK: msdr %f0, %f15, %f0 +0xb3 0x3f 0x00 0xf0 + +# CHECK: msdr %f15, %f0, %f0 +0xb3 0x3f 0xf0 0x00 + +# CHECK: msdr %f7, %f8, %f9 +0xb3 0x3f 0x70 0x89 + +# CHECK: msdr %f15, %f15, %f15 +0xb3 0x3f 0xf0 0xff + +# CHECK: mse %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x2f + +# CHECK: mse %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x2f + +# CHECK: mse %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x2f + +# CHECK: mse %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x2f + +# CHECK: mse %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x2f + +# CHECK: mse %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x2f + +# CHECK: mse %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x2f + +# CHECK: mse %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x2f + +# CHECK: mse %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x2f + # CHECK: mseb %f0, %f0, 0 0xed 0x00 0x00 0x00 0x00 0x0f @@ -8755,6 +11049,24 @@ # CHECK: msebr %f15, %f15, %f15 0xb3 0x0f 0xf0 0xff +# CHECK: mser %f0, %f0, %f0 +0xb3 0x2f 0x00 0x00 + +# CHECK: mser %f0, %f0, %f15 +0xb3 0x2f 0x00 0x0f + +# CHECK: mser %f0, %f15, %f0 +0xb3 0x2f 0x00 0xf0 + +# CHECK: mser %f15, %f0, %f0 +0xb3 0x2f 0xf0 0x00 + +# CHECK: mser %f7, %f8, %f9 +0xb3 0x2f 0x70 0x89 + +# CHECK: mser %f15, %f15, %f15 +0xb3 0x2f 0xf0 0xff + # CHECK: msfi %r0, -2147483648 0xc2 0x01 0x80 0x00 0x00 0x00 @@ -9361,6 +11673,27 @@ # CHECK: mxbr %f13, %f13 0xb3 0x4c 0x00 0xdd +# CHECK: mxd %f0, 0 +0x67 0x00 0x00 0x00 + +# CHECK: mxd %f0, 4095 +0x67 0x00 0x0f 0xff + +# CHECK: mxd %f0, 0(%r1) +0x67 0x00 0x10 0x00 + +# CHECK: mxd %f0, 0(%r15) +0x67 0x00 0xf0 0x00 + +# CHECK: mxd %f0, 4095(%r1,%r15) +0x67 0x01 0xff 0xff + +# CHECK: mxd %f0, 4095(%r15,%r1) +0x67 0x0f 0x1f 0xff + +# CHECK: mxd %f13, 0 +0x67 0xd0 0x00 0x00 + # CHECK: mxdb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x07 @@ -9394,6 +11727,198 @@ # CHECK: mxdbr %f13, %f0 0xb3 0x07 0x00 0xd0 +# CHECK: mxdr %f0, %f0 +0x27 0x00 + +# CHECK: mxdr %f0, %f15 +0x27 0x0f + +# CHECK: mxdr %f8, %f8 +0x27 0x88 + +# CHECK: mxdr %f13, %f0 +0x27 0xd0 + +# CHECK: mxr %f0, %f0 +0x26 0x00 + +# CHECK: mxr %f0, %f13 +0x26 0x0d + +# CHECK: mxr %f8, %f5 +0x26 0x85 + +# CHECK: mxr %f13, %f13 +0x26 0xdd + +# CHECK: mxtr %f0, %f0, %f0 +0xb3 0xd8 0x00 0x00 + +# CHECK: mxtr %f0, %f0, %f13 +0xb3 0xd8 0xd0 0x00 + +# CHECK: mxtr %f0, %f13, %f0 +0xb3 0xd8 0x00 0x0d + +# CHECK: mxtr %f13, %f0, %f0 +0xb3 0xd8 0x00 0xd0 + +# CHECK: mxtr %f8, %f8, %f8 +0xb3 0xd8 0x80 0x88 + +# CHECK: mxtra %f0, %f0, %f0, 1 +0xb3 0xd8 0x01 0x00 + +# CHECK: mxtra %f0, %f0, %f0, 15 +0xb3 0xd8 0x0f 0x00 + +# CHECK: mxtra %f0, %f0, %f13, 1 +0xb3 0xd8 0xd1 0x00 + +# CHECK: mxtra %f0, %f13, %f0, 1 +0xb3 0xd8 0x01 0x0d + +# CHECK: mxtra %f13, %f0, %f0, 1 +0xb3 0xd8 0x01 0xd0 + +# CHECK: mxtra %f8, %f8, %f8, 8 +0xb3 0xd8 0x88 0x88 + +# CHECK: my %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x3b + +# CHECK: my %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x3b + +# CHECK: my %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x3b + +# CHECK: my %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x3b + +# CHECK: my %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x3b + +# CHECK: my %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x3b + +# CHECK: my %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x3b + +# CHECK: my %f13, %f0, 0 +0xed 0x00 0x00 0x00 0xd0 0x3b + +# CHECK: my %f13, %f15, 0 +0xed 0xf0 0x00 0x00 0xd0 0x3b + +# CHECK: myh %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x3d + +# CHECK: myh %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x3d + +# CHECK: myh %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x3d + +# CHECK: myh %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x3d + +# CHECK: myh %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x3d + +# CHECK: myh %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x3d + +# CHECK: myh %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x3d + +# CHECK: myh %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x3d + +# CHECK: myh %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x3d + +# CHECK: myhr %f0, %f0, %f0 +0xb3 0x3d 0x00 0x00 + +# CHECK: myhr %f0, %f0, %f15 +0xb3 0x3d 0x00 0x0f + +# CHECK: myhr %f0, %f15, %f0 +0xb3 0x3d 0x00 0xf0 + +# CHECK: myhr %f15, %f0, %f0 +0xb3 0x3d 0xf0 0x00 + +# CHECK: myhr %f7, %f8, %f9 +0xb3 0x3d 0x70 0x89 + +# CHECK: myhr %f15, %f15, %f15 +0xb3 0x3d 0xf0 0xff + +# CHECK: myl %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x39 + +# CHECK: myl %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x39 + +# CHECK: myl %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x39 + +# CHECK: myl %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x39 + +# CHECK: myl %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x39 + +# CHECK: myl %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x39 + +# CHECK: myl %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x39 + +# CHECK: myl %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x39 + +# CHECK: myl %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x39 + +# CHECK: mylr %f0, %f0, %f0 +0xb3 0x39 0x00 0x00 + +# CHECK: mylr %f0, %f0, %f15 +0xb3 0x39 0x00 0x0f + +# CHECK: mylr %f0, %f15, %f0 +0xb3 0x39 0x00 0xf0 + +# CHECK: mylr %f15, %f0, %f0 +0xb3 0x39 0xf0 0x00 + +# CHECK: mylr %f7, %f8, %f9 +0xb3 0x39 0x70 0x89 + +# CHECK: mylr %f15, %f15, %f15 +0xb3 0x39 0xf0 0xff + +# CHECK: myr %f0, %f0, %f0 +0xb3 0x3b 0x00 0x00 + +# CHECK: myr %f0, %f0, %f15 +0xb3 0x3b 0x00 0x0f + +# CHECK: myr %f0, %f15, %f0 +0xb3 0x3b 0x00 0xf0 + +# CHECK: myr %f13, %f0, %f0 +0xb3 0x3b 0xd0 0x00 + +# CHECK: myr %f5, %f8, %f9 +0xb3 0x3b 0x50 0x89 + +# CHECK: myr %f13, %f15, %f15 +0xb3 0x3b 0xd0 0xff + # CHECK: n %r0, 0 0x54 0x00 0x00 0x00 @@ -10051,6 +12576,9 @@ # CHECK: pfd 15, 0 0xe3 0xf0 0x00 0x00 0x00 0x36 +# CHECK: pfpo +0x01 0x0a + # CHECK: pka 0, 0(1) 0xe9 0x00 0x00 0x00 0x00 0x00 @@ -10174,6 +12702,42 @@ # CHECK: pr 0x01 0x01 +# CHECK: qadtr %f0, %f0, %f0, 0 +0xb3 0xf5 0x00 0x00 + +# CHECK: qadtr %f0, %f0, %f0, 15 +0xb3 0xf5 0x0f 0x00 + +# CHECK: qadtr %f0, %f0, %f15, 0 +0xb3 0xf5 0x00 0x0f + +# CHECK: qadtr %f0, %f15, %f0, 0 +0xb3 0xf5 0xf0 0x00 + +# CHECK: qadtr %f4, %f5, %f6, 7 +0xb3 0xf5 0x57 0x46 + +# CHECK: qadtr %f15, %f0, %f0, 0 +0xb3 0xf5 0x00 0xf0 + +# CHECK: qaxtr %f0, %f0, %f0, 0 +0xb3 0xfd 0x00 0x00 + +# CHECK: qaxtr %f0, %f0, %f0, 15 +0xb3 0xfd 0x0f 0x00 + +# CHECK: qaxtr %f0, %f0, %f13, 0 +0xb3 0xfd 0x00 0x0d + +# CHECK: qaxtr %f0, %f13, %f0, 0 +0xb3 0xfd 0xd0 0x00 + +# CHECK: qaxtr %f8, %f8, %f8, 8 +0xb3 0xfd 0x88 0x88 + +# CHECK: qaxtr %f13, %f0, %f0, 0 +0xb3 0xfd 0x00 0xd0 + # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 @@ -10372,6 +12936,42 @@ # CHECK: rosbg %r4, %r5, 6, 7, 8 0xec 0x45 0x06 0x07 0x08 0x56 +# CHECK: rrdtr %f0, %f0, %f0, 0 +0xb3 0xf7 0x00 0x00 + +# CHECK: rrdtr %f0, %f0, %f0, 15 +0xb3 0xf7 0x0f 0x00 + +# CHECK: rrdtr %f0, %f0, %f15, 0 +0xb3 0xf7 0x00 0x0f + +# CHECK: rrdtr %f0, %f15, %f0, 0 +0xb3 0xf7 0xf0 0x00 + +# CHECK: rrdtr %f4, %f5, %f6, 7 +0xb3 0xf7 0x57 0x46 + +# CHECK: rrdtr %f15, %f0, %f0, 0 +0xb3 0xf7 0x00 0xf0 + +# CHECK: rrxtr %f0, %f0, %f0, 0 +0xb3 0xff 0x00 0x00 + +# CHECK: rrxtr %f0, %f0, %f0, 15 +0xb3 0xff 0x0f 0x00 + +# CHECK: rrxtr %f0, %f0, %f13, 0 +0xb3 0xff 0x00 0x0d + +# CHECK: rrxtr %f0, %f13, %f0, 0 +0xb3 0xff 0xd0 0x00 + +# CHECK: rrxtr %f8, %f8, %f8, 8 +0xb3 0xff 0x88 0x88 + +# CHECK: rrxtr %f13, %f0, %f0, 0 +0xb3 0xff 0x00 0xd0 + # CHECK: rxsbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x57 @@ -10438,6 +13038,27 @@ # CHECK: sar %a15, %r15 0xb2 0x4e 0x00 0xff +# CHECK: sd %f0, 0 +0x6b 0x00 0x00 0x00 + +# CHECK: sd %f0, 4095 +0x6b 0x00 0x0f 0xff + +# CHECK: sd %f0, 0(%r1) +0x6b 0x00 0x10 0x00 + +# CHECK: sd %f0, 0(%r15) +0x6b 0x00 0xf0 0x00 + +# CHECK: sd %f0, 4095(%r1,%r15) +0x6b 0x01 0xff 0xff + +# CHECK: sd %f0, 4095(%r15,%r1) +0x6b 0x0f 0x1f 0xff + +# CHECK: sd %f15, 0 +0x6b 0xf0 0x00 0x00 + # CHECK: sdb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x1b @@ -10471,6 +13092,72 @@ # CHECK: sdbr %f15, %f0 0xb3 0x1b 0x00 0xf0 +# CHECK: sdr %f0, %f0 +0x2b 0x00 + +# CHECK: sdr %f0, %f15 +0x2b 0x0f + +# CHECK: sdr %f7, %f8 +0x2b 0x78 + +# CHECK: sdr %f15, %f0 +0x2b 0xf0 + +# CHECK: sdtr %f0, %f0, %f0 +0xb3 0xd3 0x00 0x00 + +# CHECK: sdtr %f0, %f0, %f15 +0xb3 0xd3 0xf0 0x00 + +# CHECK: sdtr %f0, %f15, %f0 +0xb3 0xd3 0x00 0x0f + +# CHECK: sdtr %f15, %f0, %f0 +0xb3 0xd3 0x00 0xf0 + +# CHECK: sdtr %f7, %f8, %f9 +0xb3 0xd3 0x90 0x78 + +# CHECK: sdtra %f0, %f0, %f0, 1 +0xb3 0xd3 0x01 0x00 + +# CHECK: sdtra %f0, %f0, %f0, 15 +0xb3 0xd3 0x0f 0x00 + +# CHECK: sdtra %f0, %f0, %f15, 1 +0xb3 0xd3 0xf1 0x00 + +# CHECK: sdtra %f0, %f15, %f0, 1 +0xb3 0xd3 0x01 0x0f + +# CHECK: sdtra %f15, %f0, %f0, 1 +0xb3 0xd3 0x01 0xf0 + +# CHECK: sdtra %f7, %f8, %f9, 10 +0xb3 0xd3 0x9a 0x78 + +# CHECK: se %f0, 0 +0x7b 0x00 0x00 0x00 + +# CHECK: se %f0, 4095 +0x7b 0x00 0x0f 0xff + +# CHECK: se %f0, 0(%r1) +0x7b 0x00 0x10 0x00 + +# CHECK: se %f0, 0(%r15) +0x7b 0x00 0xf0 0x00 + +# CHECK: se %f0, 4095(%r1,%r15) +0x7b 0x01 0xff 0xff + +# CHECK: se %f0, 4095(%r15,%r1) +0x7b 0x0f 0x1f 0xff + +# CHECK: se %f15, 0 +0x7b 0xf0 0x00 0x00 + # CHECK: seb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x0b @@ -10504,6 +13191,18 @@ # CHECK: sebr %f15, %f0 0xb3 0x0b 0x00 0xf0 +# CHECK: ser %f0, %f0 +0x3b 0x00 + +# CHECK: ser %f0, %f15 +0x3b 0x0f + +# CHECK: ser %f7, %f8 +0x3b 0x78 + +# CHECK: ser %f15, %f0 +0x3b 0xf0 + # CHECK: sfasr %r0 0xb3 0x85 0x00 0x00 @@ -10912,6 +13611,33 @@ # CHECK: sldl %r0, 4095(%r15) 0x8d 0x00 0xff 0xff +# CHECK: sldt %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x40 + +# CHECK: sldt %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x40 + +# CHECK: sldt %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x40 + +# CHECK: sldt %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x40 + +# CHECK: sldt %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x40 + +# CHECK: sldt %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x40 + +# CHECK: sldt %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x40 + +# CHECK: sldt %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x40 + +# CHECK: sldt %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x40 + # CHECK: slfi %r0, 0 0xc2 0x05 0x00 0x00 0x00 0x00 @@ -11134,6 +13860,33 @@ # CHECK: slrk %r2, %r3, %r4 0xb9 0xfb 0x40 0x23 +# CHECK: slxt %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x48 + +# CHECK: slxt %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x48 + +# CHECK: slxt %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x48 + +# CHECK: slxt %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x48 + +# CHECK: slxt %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x48 + +# CHECK: slxt %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x48 + +# CHECK: slxt %f0, %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x48 + +# CHECK: slxt %f13, %f0, 0 +0xed 0x00 0x00 0x00 0xd0 0x48 + +# CHECK: slxt %f13, %f13, 0 +0xed 0xd0 0x00 0x00 0xd0 0x48 + # CHECK: sly %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x5f @@ -11215,6 +13968,27 @@ # CHECK: spm %r15 0x04 0xf0 +# CHECK: sqd %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x35 + +# CHECK: sqd %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x35 + +# CHECK: sqd %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x35 + +# CHECK: sqd %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x35 + +# CHECK: sqd %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x35 + +# CHECK: sqd %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x35 + +# CHECK: sqd %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x35 + # CHECK: sqdb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x15 @@ -11248,6 +14022,39 @@ # CHECK: sqdbr %f15, %f0 0xb3 0x15 0x00 0xf0 +# CHECK: sqdr %f0, %f0 +0xb2 0x44 0x00 0x00 + +# CHECK: sqdr %f0, %f15 +0xb2 0x44 0x00 0x0f + +# CHECK: sqdr %f7, %f8 +0xb2 0x44 0x00 0x78 + +# CHECK: sqdr %f15, %f0 +0xb2 0x44 0x00 0xf0 + +# CHECK: sqe %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x34 + +# CHECK: sqe %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x34 + +# CHECK: sqe %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x34 + +# CHECK: sqe %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x34 + +# CHECK: sqe %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x34 + +# CHECK: sqe %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x34 + +# CHECK: sqe %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x34 + # CHECK: sqeb %f0, 0 0xed 0x00 0x00 0x00 0x00 0x14 @@ -11281,6 +14088,18 @@ # CHECK: sqebr %f15, %f0 0xb3 0x14 0x00 0xf0 +# CHECK: sqer %f0, %f0 +0xb2 0x45 0x00 0x00 + +# CHECK: sqer %f0, %f15 +0xb2 0x45 0x00 0x0f + +# CHECK: sqer %f7, %f8 +0xb2 0x45 0x00 0x78 + +# CHECK: sqer %f15, %f0 +0xb2 0x45 0x00 0xf0 + # CHECK: sqxbr %f0, %f0 0xb3 0x16 0x00 0x00 @@ -11293,6 +14112,18 @@ # CHECK: sqxbr %f13, %f0 0xb3 0x16 0x00 0xd0 +# CHECK: sqxr %f0, %f0 +0xb3 0x36 0x00 0x00 + +# CHECK: sqxr %f0, %f13 +0xb3 0x36 0x00 0x0d + +# CHECK: sqxr %f8, %f8 +0xb3 0x36 0x00 0x88 + +# CHECK: sqxr %f13, %f0 +0xb3 0x36 0x00 0xd0 + # CHECK: sr %r0, %r0 0x1b 0x00 @@ -11449,6 +14280,33 @@ # CHECK: srdl %r0, 4095(%r15) 0x8c 0x00 0xff 0xff +# CHECK: srdt %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x41 + +# CHECK: srdt %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x41 + +# CHECK: srdt %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x41 + +# CHECK: srdt %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x41 + +# CHECK: srdt %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x41 + +# CHECK: srdt %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x41 + +# CHECK: srdt %f0, %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x41 + +# CHECK: srdt %f15, %f0, 0 +0xed 0x00 0x00 0x00 0xf0 0x41 + +# CHECK: srdt %f15, %f15, 0 +0xed 0xf0 0x00 0x00 0xf0 0x41 + # CHECK: srk %r0, %r0, %r0 0xb9 0xf9 0x00 0x00 @@ -11668,6 +14526,33 @@ # CHECK: srstu %r7, %r8 0xb9 0xbe 0x00 0x78 +# CHECK: srxt %f0, %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x49 + +# CHECK: srxt %f0, %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x49 + +# CHECK: srxt %f0, %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x49 + +# CHECK: srxt %f0, %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x49 + +# CHECK: srxt %f0, %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x49 + +# CHECK: srxt %f0, %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x49 + +# CHECK: srxt %f0, %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x49 + +# CHECK: srxt %f13, %f0, 0 +0xed 0x00 0x00 0x00 0xd0 0x49 + +# CHECK: srxt %f13, %f13, 0 +0xed 0xd0 0x00 0x00 0xd0 0x49 + # CHECK: st %r0, 0 0x50 0x00 0x00 0x00 @@ -12664,6 +15549,39 @@ # CHECK: sty %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x50 +# CHECK: su %f0, 0 +0x7f 0x00 0x00 0x00 + +# CHECK: su %f0, 4095 +0x7f 0x00 0x0f 0xff + +# CHECK: su %f0, 0(%r1) +0x7f 0x00 0x10 0x00 + +# CHECK: su %f0, 0(%r15) +0x7f 0x00 0xf0 0x00 + +# CHECK: su %f0, 4095(%r1,%r15) +0x7f 0x01 0xff 0xff + +# CHECK: su %f0, 4095(%r15,%r1) +0x7f 0x0f 0x1f 0xff + +# CHECK: su %f15, 0 +0x7f 0xf0 0x00 0x00 + +# CHECK: sur %f0, %f0 +0x3f 0x00 + +# CHECK: sur %f0, %f15 +0x3f 0x0f + +# CHECK: sur %f7, %f8 +0x3f 0x78 + +# CHECK: sur %f15, %f0 +0x3f 0xf0 + # CHECK: svc 0 0x0a 0x00 @@ -12676,6 +15594,39 @@ # CHECK: svc 255 0x0a 0xff +# CHECK: sw %f0, 0 +0x6f 0x00 0x00 0x00 + +# CHECK: sw %f0, 4095 +0x6f 0x00 0x0f 0xff + +# CHECK: sw %f0, 0(%r1) +0x6f 0x00 0x10 0x00 + +# CHECK: sw %f0, 0(%r15) +0x6f 0x00 0xf0 0x00 + +# CHECK: sw %f0, 4095(%r1,%r15) +0x6f 0x01 0xff 0xff + +# CHECK: sw %f0, 4095(%r15,%r1) +0x6f 0x0f 0x1f 0xff + +# CHECK: sw %f15, 0 +0x6f 0xf0 0x00 0x00 + +# CHECK: swr %f0, %f0 +0x2f 0x00 + +# CHECK: swr %f0, %f15 +0x2f 0x0f + +# CHECK: swr %f7, %f8 +0x2f 0x78 + +# CHECK: swr %f15, %f0 +0x2f 0xf0 + # CHECK: sxbr %f0, %f0 0xb3 0x4b 0x00 0x00 @@ -12688,6 +15639,51 @@ # CHECK: sxbr %f13, %f0 0xb3 0x4b 0x00 0xd0 +# CHECK: sxr %f0, %f0 +0x37 0x00 + +# CHECK: sxr %f0, %f13 +0x37 0x0d + +# CHECK: sxr %f8, %f8 +0x37 0x88 + +# CHECK: sxr %f13, %f0 +0x37 0xd0 + +# CHECK: sxtr %f0, %f0, %f0 +0xb3 0xdb 0x00 0x00 + +# CHECK: sxtr %f0, %f0, %f13 +0xb3 0xdb 0xd0 0x00 + +# CHECK: sxtr %f0, %f13, %f0 +0xb3 0xdb 0x00 0x0d + +# CHECK: sxtr %f13, %f0, %f0 +0xb3 0xdb 0x00 0xd0 + +# CHECK: sxtr %f8, %f8, %f8 +0xb3 0xdb 0x80 0x88 + +# CHECK: sxtra %f0, %f0, %f0, 1 +0xb3 0xdb 0x01 0x00 + +# CHECK: sxtra %f0, %f0, %f0, 15 +0xb3 0xdb 0x0f 0x00 + +# CHECK: sxtra %f0, %f0, %f13, 1 +0xb3 0xdb 0xd1 0x00 + +# CHECK: sxtra %f0, %f13, %f0, 1 +0xb3 0xdb 0x01 0x0d + +# CHECK: sxtra %f13, %f0, %f0, 1 +0xb3 0xdb 0x01 0xd0 + +# CHECK: sxtra %f8, %f8, %f8, 8 +0xb3 0xdb 0x88 0x88 + # CHECK: sy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x5b @@ -12739,6 +15735,36 @@ # CHECK: tam 0x01 0x0b +# CHECK: tbdr %f0, 0, %f0 +0xb3 0x51 0x00 0x00 + +# CHECK: tbdr %f0, 0, %f15 +0xb3 0x51 0x00 0x0f + +# CHECK: tbdr %f0, 15, %f0 +0xb3 0x51 0xf0 0x00 + +# CHECK: tbdr %f4, 5, %f6 +0xb3 0x51 0x50 0x46 + +# CHECK: tbdr %f15, 0, %f0 +0xb3 0x51 0x00 0xf0 + +# CHECK: tbedr %f0, 0, %f0 +0xb3 0x50 0x00 0x00 + +# CHECK: tbedr %f0, 0, %f15 +0xb3 0x50 0x00 0x0f + +# CHECK: tbedr %f0, 15, %f0 +0xb3 0x50 0xf0 0x00 + +# CHECK: tbedr %f4, 5, %f6 +0xb3 0x50 0x50 0x46 + +# CHECK: tbedr %f15, 0, %f0 +0xb3 0x50 0x00 0xf0 + # CHECK: tbegin 0, 0 0xe5 0x60 0x00 0x00 0x00 0x00 @@ -12868,9 +15894,159 @@ # CHECK: tcxb %f13, 0 0xed 0xd0 0x00 0x00 0x00 0x12 +# CHECK: tdcdt %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x54 + +# CHECK: tdcdt %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x54 + +# CHECK: tdcdt %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x54 + +# CHECK: tdcdt %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x54 + +# CHECK: tdcdt %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x54 + +# CHECK: tdcdt %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x54 + +# CHECK: tdcdt %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x54 + +# CHECK: tdcet %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x50 + +# CHECK: tdcet %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x50 + +# CHECK: tdcet %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x50 + +# CHECK: tdcet %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x50 + +# CHECK: tdcet %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x50 + +# CHECK: tdcet %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x50 + +# CHECK: tdcet %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x50 + +# CHECK: tdcxt %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x58 + +# CHECK: tdcxt %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x58 + +# CHECK: tdcxt %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x58 + +# CHECK: tdcxt %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x58 + +# CHECK: tdcxt %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x58 + +# CHECK: tdcxt %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x58 + +# CHECK: tdcxt %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x58 + +# CHECK: tdgdt %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x55 + +# CHECK: tdgdt %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x55 + +# CHECK: tdgdt %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x55 + +# CHECK: tdgdt %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x55 + +# CHECK: tdgdt %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x55 + +# CHECK: tdgdt %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x55 + +# CHECK: tdgdt %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x55 + +# CHECK: tdget %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x51 + +# CHECK: tdget %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x51 + +# CHECK: tdget %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x51 + +# CHECK: tdget %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x51 + +# CHECK: tdget %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x51 + +# CHECK: tdget %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x51 + +# CHECK: tdget %f15, 0 +0xed 0xf0 0x00 0x00 0x00 0x51 + +# CHECK: tdgxt %f0, 0 +0xed 0x00 0x00 0x00 0x00 0x59 + +# CHECK: tdgxt %f0, 4095 +0xed 0x00 0x0f 0xff 0x00 0x59 + +# CHECK: tdgxt %f0, 0(%r1) +0xed 0x00 0x10 0x00 0x00 0x59 + +# CHECK: tdgxt %f0, 0(%r15) +0xed 0x00 0xf0 0x00 0x00 0x59 + +# CHECK: tdgxt %f0, 4095(%r1,%r15) +0xed 0x01 0xff 0xff 0x00 0x59 + +# CHECK: tdgxt %f0, 4095(%r15,%r1) +0xed 0x0f 0x1f 0xff 0x00 0x59 + +# CHECK: tdgxt %f13, 0 +0xed 0xd0 0x00 0x00 0x00 0x59 + # CHECK: tend 0xb2 0xf8 0x00 0x00 +# CHECK: thder %f0, %f9 +0xb3 0x58 0x00 0x09 + +# CHECK: thder %f0, %f15 +0xb3 0x58 0x00 0x0f + +# CHECK: thder %f15, %f0 +0xb3 0x58 0x00 0xf0 + +# CHECK: thder %f15, %f9 +0xb3 0x58 0x00 0xf9 + +# CHECK: thdr %f0, %f9 +0xb3 0x59 0x00 0x09 + +# CHECK: thdr %f0, %f15 +0xb3 0x59 0x00 0x0f + +# CHECK: thdr %f15, %f0 +0xb3 0x59 0x00 0xf0 + +# CHECK: thdr %f15, %f9 +0xb3 0x59 0x00 0xf9 + # CHECK: tm 0, 0 0x91 0x00 0x00 0x00 diff --git a/test/MC/Mips/macro-li.d.s b/test/MC/Mips/macro-li.d.s new file mode 100644 index 0000000000000..e54b69ea08628 --- /dev/null +++ b/test/MC/Mips/macro-li.d.s @@ -0,0 +1,443 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32 -target-abi=o32 | FileCheck %s --check-prefixes=ALL,O32-N32-NO-PIC,O32 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -target-abi=o32 | FileCheck %s --check-prefixes=ALL,CHECK-MIPS32r2 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32 -target-abi=o32 -position-independent | FileCheck %s --check-prefixes=ALL,O32-N32-PIC,O32 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n32 | FileCheck %s --check-prefixes=ALL,O32-N32-NO-PIC,N32-N64 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n32 -position-independent | FileCheck %s --check-prefixes=ALL,O32-N32-PIC,N32-N64 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n64 | FileCheck %s --check-prefixes=ALL,N64-NO-PIC,N32-N64 +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n64 -position-independent | FileCheck %s --check-prefixes=ALL,N64-PIC,N32-N64 + +li.d $4, 0 +# O32: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# O32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# N32-N64: daddiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x64] + +li.d $4, 0.0 +# O32: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] +# O32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] +# N32-N64: daddiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x64] + +li.d $4, 1.12345 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1072822694 +# ALL: .4byte 3037400872 +# ALL: .text +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# O32-N32-NO-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32: lw $4, 0($1) # encoding: [0x00,0x00,0x24,0x8c] +# O32: lw $5, 4($1) # encoding: [0x04,0x00,0x25,0x8c] +# N32-N64: ld $4, 0($1) # encoding: [0x00,0x00,0x24,0xdc] + +li.d $4, 1 +# ALL: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# O32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 1.0 +# ALL: lui $4, 16368 # encoding: [0xf0,0x3f,0x04,0x3c] +# O32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1107754720 +# ALL: .4byte 3790602240 +# ALL: .text +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# O32-N32-NO-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32: lw $4, 0($1) # encoding: [0x00,0x00,0x24,0x8c] +# O32: lw $5, 4($1) # encoding: [0x04,0x00,0x25,0x8c] +# N32-N64: ld $4, 0($1) # encoding: [0x00,0x00,0x24,0xdc] + +li.d $4, 12345678910.0 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1107754720 +# ALL: .4byte 3790602240 +# ALL: .text +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# O32-N32-NO-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32: lw $4, 0($1) # encoding: [0x00,0x00,0x24,0x8c] +# O32: lw $5, 4($1) # encoding: [0x04,0x00,0x25,0x8c] +# N32-N64: ld $4, 0($1) # encoding: [0x00,0x00,0x24,0xdc] + +li.d $4, 0.4 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1071225241 +# ALL: .4byte 2576980378 +# ALL: .text +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# O32-N32-NO-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32: lw $4, 0($1) # encoding: [0x00,0x00,0x24,0x8c] +# O32: lw $5, 4($1) # encoding: [0x04,0x00,0x25,0x8c] +# N32-N64: ld $4, 0($1) # encoding: [0x00,0x00,0x24,0xdc] + +li.d $4, 1.5 +# ALL: lui $4, 16376 # encoding: [0xf8,0x3f,0x04,0x3c] +# O32: addiu $5, $zero, 0 # encoding: [0x00,0x00,0x05,0x24] + +li.d $4, 12345678910.12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1107754720 +# ALL: .4byte 3790666967 +# ALL: .text +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# O32-N32-NO-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32: lw $4, 0($1) # encoding: [0x00,0x00,0x24,0x8c] +# O32: lw $5, 4($1) # encoding: [0x04,0x00,0x25,0x8c] +# N32-N64: ld $4, 0($1) # encoding: [0x00,0x00,0x24,0xdc] + + +li.d $4, 12345678910123456789.12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1139108501 +# ALL: .4byte 836738583 +# ALL: .text +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# O32-N32-NO-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-PIC: addiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x24] +# O32-N32-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: daddiu $1, $1, %lo([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-PIC: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 +# O32: lw $4, 0($1) # encoding: [0x00,0x00,0x24,0x8c] +# O32: lw $5, 4($1) # encoding: [0x04,0x00,0x25,0x8c] +# N32-N64: ld $4, 0($1) # encoding: [0x00,0x00,0x24,0xdc] + +li.d $f4, 0 +# O32: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# N32-N64: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 0.0 +# O32: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# N32-N64: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 1.12345 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1072822694 +# ALL: .4byte 3037400872 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: ldc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xd4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.d $f4, 1 +# O32: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# N32-N64: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 1.0 +# O32: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# N32-N64: lui $1, 16368 # encoding: [0xf0,0x3f,0x01,0x3c] +# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1107754720 +# ALL: .4byte 3790602240 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: ldc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xd4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.d $f4, 12345678910.0 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1107754720 +# ALL: .4byte 3790602240 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: ldc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xd4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.d $f4, 0.4 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1071225241 +# ALL: .4byte 2576980378 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: ldc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xd4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.d $f4, 1.5 +# O32: lui $1, 16376 # encoding: [0xf8,0x3f,0x01,0x3c] +# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16376 # encoding: [0xf8,0x3f,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# N32-N64: lui $1, 16376 # encoding: [0xf8,0x3f,0x01,0x3c] +# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 2.5 +# O32: lui $1, 16388 # encoding: [0x04,0x40,0x01,0x3c] +# O32: mtc1 $1, $f5 # encoding: [0x00,0x28,0x81,0x44] +# O32: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: lui $1, 16388 # encoding: [0x04,0x40,0x01,0x3c] +# CHECK-MIPS32r2: mtc1 $zero, $f4 # encoding: [0x00,0x20,0x80,0x44] +# CHECK-MIPS32r2: mthc1 $1, $f4 # encoding: [0x00,0x20,0xe1,0x44] +# N32-N64: lui $1, 16388 # encoding: [0x04,0x40,0x01,0x3c] +# N32-N64: dmtc1 $1, $f4 # encoding: [0x00,0x20,0xa1,0x44] + +li.d $f4, 2.515625 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1074012160 +# ALL: .4byte 0 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: ldc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xd4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.d $f4, 12345678910.12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1107754720 +# ALL: .4byte 3790666967 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: ldc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xd4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.d $f4, 12345678910123456789.12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1139108501 +# ALL: .4byte 836738583 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: ldc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xd4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 diff --git a/test/MC/Mips/macro-li.s.s b/test/MC/Mips/macro-li.s.s new file mode 100644 index 0000000000000..01eb3646211fb --- /dev/null +++ b/test/MC/Mips/macro-li.s.s @@ -0,0 +1,198 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -target-abi=o32 | FileCheck %s --check-prefixes=ALL,O32-N32-NO-PIC +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -target-abi=o32 -position-independent | FileCheck %s --check-prefixes=ALL,O32-N32-PIC +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n32 | FileCheck %s --check-prefixes=ALL,O32-N32-NO-PIC +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n32 -position-independent | FileCheck %s --check-prefixes=ALL,O32-N32-PIC +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n64 | FileCheck %s --check-prefixes=ALL,N64-NO-PIC +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64 -target-abi=n64 -position-independent | FileCheck %s --check-prefixes=ALL,N64-PIC + +li.s $4, 0 +# ALL: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] + +li.s $4, 0.0 +# ALL: addiu $4, $zero, 0 # encoding: [0x00,0x00,0x04,0x24] + +li.s $4, 1.12345 +# ALL: lui $4, 16271 # encoding: [0x8f,0x3f,0x04,0x3c] +# ALL: ori $4, $4, 52534 # encoding: [0x36,0xcd,0x84,0x34] + +li.s $4, 1 +# ALL: lui $4, 16256 # encoding: [0x80,0x3f,0x04,0x3c] + +li.s $4, 1.0 +# ALL: lui $4, 16256 # encoding: [0x80,0x3f,0x04,0x3c] + +li.s $4, 12345678910 +# ALL: lui $4, 20535 # encoding: [0x37,0x50,0x04,0x3c] +# ALL: ori $4, $4, 63239 # encoding: [0x07,0xf7,0x84,0x34] + +li.s $4, 12345678910.0 +# ALL: lui $4, 20535 # encoding: [0x37,0x50,0x04,0x3c] +# ALL: ori $4, $4, 63239 # encoding: [0x07,0xf7,0x84,0x34] + +li.s $4, 0.4 +# ALL: lui $4, 16076 # encoding: [0xcc,0x3e,0x04,0x3c] +# ALL: ori $4, $4, 52429 # encoding: [0xcd,0xcc,0x84,0x34] + +li.s $4, 1.5 +# ALL: lui $4, 16320 # encoding: [0xc0,0x3f,0x04,0x3c] + +li.s $4, 12345678910.12345678910 +# ALL: lui $4, 20535 # encoding: [0x37,0x50,0x04,0x3c] +# ALL: ori $4, $4, 63239 # encoding: [0x07,0xf7,0x84,0x34] + +li.s $4, 12345678910123456789.12345678910 +# ALL: lui $4, 24363 # encoding: [0x2b,0x5f,0x04,0x3c] +# ALL: ori $4, $4, 21674 # encoding: [0xaa,0x54,0x84,0x34] + +li.s $f4, 0 +# ALL: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# ALL: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 0.0 +# ALL: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24] +# ALL: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 1.12345 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1066388790 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: lwc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xc4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.s $f4, 1 +# ALL: lui $1, 16256 # encoding: [0x80,0x3f,0x01,0x3c] +# ALL: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 1.0 +# ALL: lui $1, 16256 # encoding: [0x80,0x3f,0x01,0x3c] +# ALL: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1345844999 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: lwc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xc4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.s $f4, 12345678910.0 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1345844999 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: lwc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xc4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + + +li.s $f4, 0.4 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1053609165 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: lwc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xc4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.s $f4, 1.5 +# ALL: lui $1, 16320 # encoding: [0xc0,0x3f,0x01,0x3c] +# ALL: mtc1 $1, $f4 # encoding: [0x00,0x20,0x81,0x44] + +li.s $f4, 12345678910.12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1345844999 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: lwc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xc4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 + +li.s $f4, 12345678910123456789.12345678910 +# ALL: .section .rodata,"a",@progbits +# ALL: [[LABEL:\$tmp[0-9]+]]: +# ALL: .4byte 1596675242 +# ALL: .text +# O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f] +# O32-N32-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# O32-N32-NO-PIC: lui $1, %hi([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# O32-N32-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-PIC: ld $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0xdf] +# N64-PIC: # fixup A - offset: 0, value: %got([[LABEL]]), kind: fixup_Mips_GOT +# N64-NO-PIC: lui $1, %highest([[LABEL]]) # encoding: [A,A,0x01,0x3c] +# N64-NO-PIC: # fixup A - offset: 0, value: %highest([[LABEL]]), kind: fixup_Mips_HIGHEST +# N64-NO-PIC: daddiu $1, $1, %higher([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %higher([[LABEL]]), kind: fixup_Mips_HIGHER +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# N64-NO-PIC: daddiu $1, $1, %hi([[LABEL]]) # encoding: [A,A,0x21,0x64] +# N64-NO-PIC: # fixup A - offset: 0, value: %hi([[LABEL]]), kind: fixup_Mips_HI16 +# N64-NO-PIC: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00] +# ALL: lwc1 $f4, %lo([[LABEL]])($1) # encoding: [A,A,0x24,0xc4] +# ALL: # fixup A - offset: 0, value: %lo([[LABEL]]), kind: fixup_Mips_LO16 diff --git a/test/MC/SystemZ/insn-bad-z13.s b/test/MC/SystemZ/insn-bad-z13.s index 82f47feeb8a92..e9fac44aa8835 100644 --- a/test/MC/SystemZ/insn-bad-z13.s +++ b/test/MC/SystemZ/insn-bad-z13.s @@ -5,6 +5,152 @@ # RUN: FileCheck < %t %s #CHECK: error: invalid operand +#CHECK: cdpt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: cdpt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: cdpt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: cdpt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdpt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdpt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdpt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdpt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: cdpt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cdpt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: cdpt %f0, 0(-), 0 + + cdpt %f0, 0(1), -1 + cdpt %f0, 0(1), 16 + cdpt %f0, 0, 0 + cdpt %f0, 0(%r1), 0 + cdpt %f0, 0(0,%r1), 0 + cdpt %f0, 0(257,%r1), 0 + cdpt %f0, -1(1,%r1), 0 + cdpt %f0, 4096(1,%r1), 0 + cdpt %f0, 0(1,%r0), 0 + cdpt %f0, 0(%r1,%r2), 0 + cdpt %f0, 0(-), 0 + +#CHECK: error: invalid operand +#CHECK: cpdt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: cpdt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: cpdt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: cpdt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpdt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpdt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpdt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpdt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: cpdt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cpdt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: cpdt %f0, 0(-), 0 + + cpdt %f0, 0(1), -1 + cpdt %f0, 0(1), 16 + cpdt %f0, 0, 0 + cpdt %f0, 0(%r1), 0 + cpdt %f0, 0(0,%r1), 0 + cpdt %f0, 0(257,%r1), 0 + cpdt %f0, -1(1,%r1), 0 + cpdt %f0, 4096(1,%r1), 0 + cpdt %f0, 0(1,%r0), 0 + cpdt %f0, 0(%r1,%r2), 0 + cpdt %f0, 0(-), 0 + +#CHECK: error: invalid operand +#CHECK: cpxt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: cpxt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: cpxt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: cpxt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpxt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpxt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpxt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cpxt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: cpxt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cpxt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: cpxt %f0, 0(-), 0 +#CHECK: error: invalid register pair +#CHECK: cpxt %f15, 0(1), 0 + + cpxt %f0, 0(1), -1 + cpxt %f0, 0(1), 16 + cpxt %f0, 0, 0 + cpxt %f0, 0(%r1), 0 + cpxt %f0, 0(0,%r1), 0 + cpxt %f0, 0(257,%r1), 0 + cpxt %f0, -1(1,%r1), 0 + cpxt %f0, 4096(1,%r1), 0 + cpxt %f0, 0(1,%r0), 0 + cpxt %f0, 0(%r1,%r2), 0 + cpxt %f0, 0(-), 0 + cpxt %f15, 0(1), 0 + +#CHECK: error: invalid operand +#CHECK: cxpt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: cxpt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: cxpt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: cxpt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxpt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxpt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxpt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxpt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: cxpt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cxpt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: cxpt %f0, 0(-), 0 +#CHECK: error: invalid register pair +#CHECK: cxpt %f15, 0(1), 0 + + cxpt %f0, 0(1), -1 + cxpt %f0, 0(1), 16 + cxpt %f0, 0, 0 + cxpt %f0, 0(%r1), 0 + cxpt %f0, 0(0,%r1), 0 + cxpt %f0, 0(257,%r1), 0 + cxpt %f0, -1(1,%r1), 0 + cxpt %f0, 4096(1,%r1), 0 + cxpt %f0, 0(1,%r0), 0 + cxpt %f0, 0(%r1,%r2), 0 + cxpt %f0, 0(-), 0 + cxpt %f15, 0(1), 0 + +#CHECK: error: invalid operand #CHECK: lcbb %r0, 0, -1 #CHECK: error: invalid operand #CHECK: lcbb %r0, 0, 16 diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s index 04c19ff6319cd..78d50bca9746f 100644 --- a/test/MC/SystemZ/insn-bad-z196.s +++ b/test/MC/SystemZ/insn-bad-z196.s @@ -5,6 +5,14 @@ # RUN: FileCheck < %t %s #CHECK: error: invalid operand +#CHECK: adtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: adtra %f0, %f0, %f0, 16 + + adtra %f0, %f0, %f0, -1 + adtra %f0, %f0, %f0, 16 + +#CHECK: error: invalid operand #CHECK: aghik %r0, %r1, -32769 #CHECK: error: invalid operand #CHECK: aghik %r0, %r1, 32768 @@ -34,6 +42,23 @@ aih %r0, (-1 << 31) - 1 aih %r0, (1 << 31) +#CHECK: error: invalid operand +#CHECK: axtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: axtra %f0, %f0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: axtra %f0, %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: axtra %f0, %f2, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: axtra %f2, %f0, %f0, 0 + + axtra %f0, %f0, %f0, -1 + axtra %f0, %f0, %f0, 16 + axtra %f0, %f0, %f2, 0 + axtra %f0, %f2, %f0, 0 + axtra %f2, %f0, %f0, 0 + #CHECK: error: instruction requires: execution-hint #CHECK: bpp 0, 0, 0 @@ -73,6 +98,20 @@ cdfbra %f0, 16, %r0, 0 #CHECK: error: invalid operand +#CHECK: cdftr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cdftr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cdftr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cdftr %f0, 16, %r0, 0 + + cdftr %f0, 0, %r0, -1 + cdftr %f0, 0, %r0, 16 + cdftr %f0, -1, %r0, 0 + cdftr %f0, 16, %r0, 0 + +#CHECK: error: invalid operand #CHECK: cdgbra %f0, 0, %r0, -1 #CHECK: error: invalid operand #CHECK: cdgbra %f0, 0, %r0, 16 @@ -87,6 +126,20 @@ cdgbra %f0, 16, %r0, 0 #CHECK: error: invalid operand +#CHECK: cdgtra %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cdgtra %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cdgtra %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cdgtra %f0, 16, %r0, 0 + + cdgtra %f0, 0, %r0, -1 + cdgtra %f0, 0, %r0, 16 + cdgtra %f0, -1, %r0, 0 + cdgtra %f0, 16, %r0, 0 + +#CHECK: error: invalid operand #CHECK: cdlfbr %f0, 0, %r0, -1 #CHECK: error: invalid operand #CHECK: cdlfbr %f0, 0, %r0, 16 @@ -101,6 +154,25 @@ cdlfbr %f0, 16, %r0, 0 #CHECK: error: invalid operand +#CHECK: cdlftr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cdlftr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cdlftr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cdlftr %f0, 16, %r0, 0 + + cdlftr %f0, 0, %r0, -1 + cdlftr %f0, 0, %r0, 16 + cdlftr %f0, -1, %r0, 0 + cdlftr %f0, 16, %r0, 0 + +#CHECK: error: instruction requires: dfp-zoned-conversion +#CHECK: cdzt %f0, 0(1), 0 + + cdzt %f0, 0(1), 0 + +#CHECK: error: invalid operand #CHECK: cdlgbr %f0, 0, %r0, -1 #CHECK: error: invalid operand #CHECK: cdlgbr %f0, 0, %r0, 16 @@ -115,6 +187,20 @@ cdlgbr %f0, 16, %r0, 0 #CHECK: error: invalid operand +#CHECK: cdlgtr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cdlgtr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cdlgtr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cdlgtr %f0, 16, %r0, 0 + + cdlgtr %f0, 0, %r0, -1 + cdlgtr %f0, 0, %r0, 16 + cdlgtr %f0, -1, %r0, 0 + cdlgtr %f0, 16, %r0, 0 + +#CHECK: error: invalid operand #CHECK: cefbra %f0, 0, %r0, -1 #CHECK: error: invalid operand #CHECK: cefbra %f0, 0, %r0, 16 @@ -185,6 +271,20 @@ cfdbra %r0, 16, %f0, 0 #CHECK: error: invalid operand +#CHECK: cfdtr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: cfdtr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: cfdtr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: cfdtr %r0, 16, %f0, 0 + + cfdtr %r0, 0, %f0, -1 + cfdtr %r0, 0, %f0, 16 + cfdtr %r0, -1, %f0, 0 + cfdtr %r0, 16, %f0, 0 + +#CHECK: error: invalid operand #CHECK: cfebra %r0, 0, %f0, -1 #CHECK: error: invalid operand #CHECK: cfebra %r0, 0, %f0, 16 @@ -216,6 +316,23 @@ cfxbra %r0, 0, %f14, 0 #CHECK: error: invalid operand +#CHECK: cfxtr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: cfxtr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: cfxtr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: cfxtr %r0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: cfxtr %r0, 0, %f14, 0 + + cfxtr %r0, 0, %f0, -1 + cfxtr %r0, 0, %f0, 16 + cfxtr %r0, -1, %f0, 0 + cfxtr %r0, 16, %f0, 0 + cfxtr %r0, 0, %f14, 0 + +#CHECK: error: invalid operand #CHECK: cgdbra %r0, 0, %f0, -1 #CHECK: error: invalid operand #CHECK: cgdbra %r0, 0, %f0, 16 @@ -230,6 +347,20 @@ cgdbra %r0, 16, %f0, 0 #CHECK: error: invalid operand +#CHECK: cgdtra %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: cgdtra %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: cgdtra %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: cgdtra %r0, 16, %f0, 0 + + cgdtra %r0, 0, %f0, -1 + cgdtra %r0, 0, %f0, 16 + cgdtra %r0, -1, %f0, 0 + cgdtra %r0, 16, %f0, 0 + +#CHECK: error: invalid operand #CHECK: cgebra %r0, 0, %f0, -1 #CHECK: error: invalid operand #CHECK: cgebra %r0, 0, %f0, 16 @@ -261,6 +392,23 @@ cgxbra %r0, 0, %f14, 0 #CHECK: error: invalid operand +#CHECK: cgxtra %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: cgxtra %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: cgxtra %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: cgxtra %r0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: cgxtra %r0, 0, %f14, 0 + + cgxtra %r0, 0, %f0, -1 + cgxtra %r0, 0, %f0, 16 + cgxtra %r0, -1, %f0, 0 + cgxtra %r0, 16, %f0, 0 + cgxtra %r0, 0, %f14, 0 + +#CHECK: error: invalid operand #CHECK: chf %r0, -524289 #CHECK: error: invalid operand #CHECK: chf %r0, 524288 @@ -291,6 +439,20 @@ clfdbr %r0, 16, %f0, 0 #CHECK: error: invalid operand +#CHECK: clfdtr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clfdtr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clfdtr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clfdtr %r0, 16, %f0, 0 + + clfdtr %r0, 0, %f0, -1 + clfdtr %r0, 0, %f0, 16 + clfdtr %r0, -1, %f0, 0 + clfdtr %r0, 16, %f0, 0 + +#CHECK: error: invalid operand #CHECK: clfebr %r0, 0, %f0, -1 #CHECK: error: invalid operand #CHECK: clfebr %r0, 0, %f0, 16 @@ -322,6 +484,23 @@ clfxbr %r0, 0, %f14, 0 #CHECK: error: invalid operand +#CHECK: clfxtr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clfxtr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clfxtr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clfxtr %r0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: clfxtr %r0, 0, %f14, 0 + + clfxtr %r0, 0, %f0, -1 + clfxtr %r0, 0, %f0, 16 + clfxtr %r0, -1, %f0, 0 + clfxtr %r0, 16, %f0, 0 + clfxtr %r0, 0, %f14, 0 + +#CHECK: error: invalid operand #CHECK: clgdbr %r0, 0, %f0, -1 #CHECK: error: invalid operand #CHECK: clgdbr %r0, 0, %f0, 16 @@ -336,6 +515,20 @@ clgdbr %r0, 16, %f0, 0 #CHECK: error: invalid operand +#CHECK: clgdtr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clgdtr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clgdtr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clgdtr %r0, 16, %f0, 0 + + clgdtr %r0, 0, %f0, -1 + clgdtr %r0, 0, %f0, 16 + clgdtr %r0, -1, %f0, 0 + clgdtr %r0, 16, %f0, 0 + +#CHECK: error: invalid operand #CHECK: clgebr %r0, 0, %f0, -1 #CHECK: error: invalid operand #CHECK: clgebr %r0, 0, %f0, 16 @@ -367,6 +560,23 @@ clgxbr %r0, 0, %f14, 0 #CHECK: error: invalid operand +#CHECK: clgxtr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clgxtr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clgxtr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clgxtr %r0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: clgxtr %r0, 0, %f14, 0 + + clgxtr %r0, 0, %f0, -1 + clgxtr %r0, 0, %f0, 16 + clgxtr %r0, -1, %f0, 0 + clgxtr %r0, 16, %f0, 0 + clgxtr %r0, 0, %f14, 0 + +#CHECK: error: invalid operand #CHECK: clhf %r0, -524289 #CHECK: error: invalid operand #CHECK: clhf %r0, 524288 @@ -400,6 +610,23 @@ cxfbra %f2, 0, %r0, 0 #CHECK: error: invalid operand +#CHECK: cxftr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cxftr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cxftr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cxftr %f0, 16, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cxftr %f2, 0, %r0, 0 + + cxftr %f0, 0, %r0, -1 + cxftr %f0, 0, %r0, 16 + cxftr %f0, -1, %r0, 0 + cxftr %f0, 16, %r0, 0 + cxftr %f2, 0, %r0, 0 + +#CHECK: error: invalid operand #CHECK: cxgbra %f0, 0, %r0, -1 #CHECK: error: invalid operand #CHECK: cxgbra %f0, 0, %r0, 16 @@ -417,6 +644,23 @@ cxgbra %f2, 0, %r0, 0 #CHECK: error: invalid operand +#CHECK: cxgtra %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cxgtra %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cxgtra %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cxgtra %f0, 16, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cxgtra %f2, 0, %r0, 0 + + cxgtra %f0, 0, %r0, -1 + cxgtra %f0, 0, %r0, 16 + cxgtra %f0, -1, %r0, 0 + cxgtra %f0, 16, %r0, 0 + cxgtra %f2, 0, %r0, 0 + +#CHECK: error: invalid operand #CHECK: cxlfbr %f0, 0, %r0, -1 #CHECK: error: invalid operand #CHECK: cxlfbr %f0, 0, %r0, 16 @@ -434,6 +678,23 @@ cxlfbr %f2, 0, %r0, 0 #CHECK: error: invalid operand +#CHECK: cxlftr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cxlftr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cxlftr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cxlftr %f0, 16, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cxlftr %f2, 0, %r0, 0 + + cxlftr %f0, 0, %r0, -1 + cxlftr %f0, 0, %r0, 16 + cxlftr %f0, -1, %r0, 0 + cxlftr %f0, 16, %r0, 0 + cxlftr %f2, 0, %r0, 0 + +#CHECK: error: invalid operand #CHECK: cxlgbr %f0, 0, %r0, -1 #CHECK: error: invalid operand #CHECK: cxlgbr %f0, 0, %r0, 16 @@ -450,6 +711,63 @@ cxlgbr %f0, 16, %r0, 0 cxlgbr %f2, 0, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cxlgtr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cxlgtr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cxlgtr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cxlgtr %f0, 16, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cxlgtr %f2, 0, %r0, 0 + + cxlgtr %f0, 0, %r0, -1 + cxlgtr %f0, 0, %r0, 16 + cxlgtr %f0, -1, %r0, 0 + cxlgtr %f0, 16, %r0, 0 + cxlgtr %f2, 0, %r0, 0 + +#CHECK: error: instruction requires: dfp-zoned-conversion +#CHECK: cxzt %f0, 0(1), 0 + + cxzt %f0, 0(1), 0 + +#CHECK: error: instruction requires: dfp-zoned-conversion +#CHECK: czdt %f0, 0(1), 0 + + czdt %f0, 0(1), 0 + +#CHECK: error: instruction requires: dfp-zoned-conversion +#CHECK: czxt %f0, 0(1), 0 + + czxt %f0, 0(1), 0 + +#CHECK: error: invalid operand +#CHECK: ddtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: ddtra %f0, %f0, %f0, 16 + + ddtra %f0, %f0, %f0, -1 + ddtra %f0, %f0, %f0, 16 + +#CHECK: error: invalid operand +#CHECK: dxtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: dxtra %f0, %f0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: dxtra %f0, %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: dxtra %f0, %f2, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: dxtra %f2, %f0, %f0, 0 + + dxtra %f0, %f0, %f0, -1 + dxtra %f0, %f0, %f0, 16 + dxtra %f0, %f0, %f2, 0 + dxtra %f0, %f2, %f0, 0 + dxtra %f2, %f0, %f0, 0 + #CHECK: error: instruction requires: transactional-execution #CHECK: etnd %r7 @@ -824,6 +1142,31 @@ lpdg %r2, 0(%r1), -1(%r15) lpdg %r2, 0(%r1), 4096(%r15) +#CHECK: error: invalid operand +#CHECK: mdtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mdtra %f0, %f0, %f0, 16 + + mdtra %f0, %f0, %f0, -1 + mdtra %f0, %f0, %f0, 16 + +#CHECK: error: invalid operand +#CHECK: mxtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mxtra %f0, %f0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: mxtra %f0, %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: mxtra %f0, %f2, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: mxtra %f2, %f0, %f0, 0 + + mxtra %f0, %f0, %f0, -1 + mxtra %f0, %f0, %f0, 16 + mxtra %f0, %f0, %f2, 0 + mxtra %f0, %f2, %f0, 0 + mxtra %f2, %f0, %f0, 0 + #CHECK: error: instruction requires: execution-hint #CHECK: niai 0, 0 @@ -885,6 +1228,14 @@ risblg %r0,%r0,256,0,0 #CHECK: error: invalid operand +#CHECK: sdtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: sdtra %f0, %f0, %f0, 16 + + sdtra %f0, %f0, %f0, -1 + sdtra %f0, %f0, %f0, 16 + +#CHECK: error: invalid operand #CHECK: slak %r0,%r0,-524289 #CHECK: error: invalid operand #CHECK: slak %r0,%r0,524288 @@ -1009,6 +1360,23 @@ stocg %r0,524288,1 stocg %r0,0(%r1,%r2),1 +#CHECK: error: invalid operand +#CHECK: sxtra %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: sxtra %f0, %f0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: sxtra %f0, %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: sxtra %f0, %f2, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: sxtra %f2, %f0, %f0, 0 + + sxtra %f0, %f0, %f0, -1 + sxtra %f0, %f0, %f0, 16 + sxtra %f0, %f0, %f2, 0 + sxtra %f0, %f2, %f0, 0 + sxtra %f2, %f0, %f0, 0 + #CHECK: error: instruction requires: transactional-execution #CHECK: tabort 4095(%r1) diff --git a/test/MC/SystemZ/insn-bad-zEC12.s b/test/MC/SystemZ/insn-bad-zEC12.s index 4bc3be3292e4d..80197a3c1ef15 100644 --- a/test/MC/SystemZ/insn-bad-zEC12.s +++ b/test/MC/SystemZ/insn-bad-zEC12.s @@ -62,6 +62,46 @@ bprp 0, 0, 1 bprp 0, 0, 0x1000000 +#CHECK: error: instruction requires: dfp-packed-conversion +#CHECK: cdpt %f0, 0(1), 0 + + cdpt %f0, 0(1), 0 + +#CHECK: error: invalid operand +#CHECK: cdzt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: cdzt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: cdzt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: cdzt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdzt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdzt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdzt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cdzt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: cdzt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cdzt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: cdzt %f0, 0(-), 0 + + cdzt %f0, 0(1), -1 + cdzt %f0, 0(1), 16 + cdzt %f0, 0, 0 + cdzt %f0, 0(%r1), 0 + cdzt %f0, 0(0,%r1), 0 + cdzt %f0, 0(257,%r1), 0 + cdzt %f0, -1(1,%r1), 0 + cdzt %f0, 4096(1,%r1), 0 + cdzt %f0, 0(1,%r0), 0 + cdzt %f0, 0(%r1,%r2), 0 + cdzt %f0, 0(-), 0 + #CHECK: error: invalid operand #CHECK: clgt %r0, -1, 0 #CHECK: error: invalid operand @@ -112,6 +152,132 @@ cltno %r0, 0 clto %r0, 0 +#CHECK: error: instruction requires: dfp-packed-conversion +#CHECK: cpdt %f0, 0(1), 0 + + cpdt %f0, 0(1), 0 + +#CHECK: error: instruction requires: dfp-packed-conversion +#CHECK: cpxt %f0, 0(1), 0 + + cpxt %f0, 0(1), 0 + +#CHECK: error: instruction requires: dfp-packed-conversion +#CHECK: cxpt %f0, 0(1), 0 + + cxpt %f0, 0(1), 0 + +#CHECK: error: invalid operand +#CHECK: cxzt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: cxzt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: cxzt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: cxzt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxzt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxzt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxzt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: cxzt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: cxzt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cxzt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: cxzt %f0, 0(-), 0 +#CHECK: error: invalid register pair +#CHECK: cxzt %f15, 0(1), 0 + + cxzt %f0, 0(1), -1 + cxzt %f0, 0(1), 16 + cxzt %f0, 0, 0 + cxzt %f0, 0(%r1), 0 + cxzt %f0, 0(0,%r1), 0 + cxzt %f0, 0(257,%r1), 0 + cxzt %f0, -1(1,%r1), 0 + cxzt %f0, 4096(1,%r1), 0 + cxzt %f0, 0(1,%r0), 0 + cxzt %f0, 0(%r1,%r2), 0 + cxzt %f0, 0(-), 0 + cxzt %f15, 0(1), 0 + +#CHECK: error: invalid operand +#CHECK: czdt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: czdt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: czdt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: czdt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: czdt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: czdt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: czdt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: czdt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: czdt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: czdt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: czdt %f0, 0(-), 0 + + czdt %f0, 0(1), -1 + czdt %f0, 0(1), 16 + czdt %f0, 0, 0 + czdt %f0, 0(%r1), 0 + czdt %f0, 0(0,%r1), 0 + czdt %f0, 0(257,%r1), 0 + czdt %f0, -1(1,%r1), 0 + czdt %f0, 4096(1,%r1), 0 + czdt %f0, 0(1,%r0), 0 + czdt %f0, 0(%r1,%r2), 0 + czdt %f0, 0(-), 0 + +#CHECK: error: invalid operand +#CHECK: czxt %f0, 0(1), -1 +#CHECK: error: invalid operand +#CHECK: czxt %f0, 0(1), 16 +#CHECK: error: missing length in address +#CHECK: czxt %f0, 0, 0 +#CHECK: error: missing length in address +#CHECK: czxt %f0, 0(%r1), 0 +#CHECK: error: invalid operand +#CHECK: czxt %f0, 0(0,%r1), 0 +#CHECK: error: invalid operand +#CHECK: czxt %f0, 0(257,%r1), 0 +#CHECK: error: invalid operand +#CHECK: czxt %f0, -1(1,%r1), 0 +#CHECK: error: invalid operand +#CHECK: czxt %f0, 4096(1,%r1), 0 +#CHECK: error: %r0 used in an address +#CHECK: czxt %f0, 0(1,%r0), 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: czxt %f0, 0(%r1,%r2), 0 +#CHECK: error: unknown token in expression +#CHECK: czxt %f0, 0(-), 0 +#CHECK: error: invalid register pair +#CHECK: czxt %f15, 0(1), 0 + + czxt %f0, 0(1), -1 + czxt %f0, 0(1), 16 + czxt %f0, 0, 0 + czxt %f0, 0(%r1), 0 + czxt %f0, 0(0,%r1), 0 + czxt %f0, 0(257,%r1), 0 + czxt %f0, -1(1,%r1), 0 + czxt %f0, 4096(1,%r1), 0 + czxt %f0, 0(1,%r0), 0 + czxt %f0, 0(%r1,%r2), 0 + czxt %f0, 0(-), 0 + czxt %f15, 0(1), 0 + #CHECK: error: invalid operand #CHECK: lat %r0, -524289 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s index b96c661ae3da4..259ad05e5f4af 100644 --- a/test/MC/SystemZ/insn-bad.s +++ b/test/MC/SystemZ/insn-bad.s @@ -13,6 +13,14 @@ a %r0, 4096 #CHECK: error: invalid operand +#CHECK: ad %f0, -1 +#CHECK: error: invalid operand +#CHECK: ad %f0, 4096 + + ad %f0, -1 + ad %f0, 4096 + +#CHECK: error: invalid operand #CHECK: adb %f0, -1 #CHECK: error: invalid operand #CHECK: adb %f0, 4096 @@ -20,6 +28,19 @@ adb %f0, -1 adb %f0, 4096 +#CHECK: error: instruction requires: fp-extension +#CHECK: adtra %f0, %f0, %f0, 0 + + adtra %f0, %f0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: ae %f0, -1 +#CHECK: error: invalid operand +#CHECK: ae %f0, 4096 + + ae %f0, -1 + ae %f0, 4096 + #CHECK: error: invalid operand #CHECK: aeb %f0, -1 #CHECK: error: invalid operand @@ -328,6 +349,22 @@ asi 0, -129 asi 0, 128 +#CHECK: error: invalid operand +#CHECK: au %f0, -1 +#CHECK: error: invalid operand +#CHECK: au %f0, 4096 + + au %f0, -1 + au %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: aw %f0, -1 +#CHECK: error: invalid operand +#CHECK: aw %f0, 4096 + + aw %f0, -1 + aw %f0, 4096 + #CHECK: error: invalid register pair #CHECK: axbr %f0, %f2 #CHECK: error: invalid register pair @@ -336,6 +373,29 @@ axbr %f0, %f2 axbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: axr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: axr %f2, %f0 + + axr %f0, %f2 + axr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: axtr %f0, %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: axtr %f0, %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: axtr %f2, %f0, %f0 + + axtr %f0, %f0, %f2 + axtr %f0, %f2, %f0 + axtr %f2, %f0, %f0 + +#CHECK: error: instruction requires: fp-extension +#CHECK: axtra %f0, %f0, %f0, 0 + + axtra %f0, %f0, %f0, 0 #CHECK: error: invalid operand #CHECK: ay %r0, -524289 @@ -613,6 +673,14 @@ c %r0, 4096 #CHECK: error: invalid operand +#CHECK: cd %f0, -1 +#CHECK: error: invalid operand +#CHECK: cd %f0, 4096 + + cd %f0, -1 + cd %f0, 4096 + +#CHECK: error: invalid operand #CHECK: cdb %f0, -1 #CHECK: error: invalid operand #CHECK: cdb %f0, 4096 @@ -626,20 +694,40 @@ cdfbra %f0, 0, %r0, 0 #CHECK: error: instruction requires: fp-extension +#CHECK: cdftr %f0, 0, %r0, 0 + + cdftr %f0, 0, %r0, 0 + +#CHECK: error: instruction requires: fp-extension #CHECK: cdgbra %f0, 0, %r0, 0 cdgbra %f0, 0, %r0, 0 #CHECK: error: instruction requires: fp-extension +#CHECK: cdgtra %f0, 0, %r0, 0 + + cdgtra %f0, 0, %r0, 0 + +#CHECK: error: instruction requires: fp-extension #CHECK: cdlfbr %f0, 0, %r0, 0 cdlfbr %f0, 0, %r0, 0 #CHECK: error: instruction requires: fp-extension +#CHECK: cdlftr %f0, 0, %r0, 0 + + cdlftr %f0, 0, %r0, 0 + +#CHECK: error: instruction requires: fp-extension #CHECK: cdlgbr %f0, 0, %r0, 0 cdlgbr %f0, 0, %r0, 0 +#CHECK: error: instruction requires: fp-extension +#CHECK: cdlgtr %f0, 0, %r0, 0 + + cdlgtr %f0, 0, %r0, 0 + #CHECK: error: invalid register pair #CHECK: cds %r1, %r0, 0 #CHECK: error: invalid register pair @@ -692,6 +780,14 @@ cdsy %r0, %r0, 0(%r1,%r2) #CHECK: error: invalid operand +#CHECK: ce %f0, -1 +#CHECK: error: invalid operand +#CHECK: ce %f0, 4096 + + ce %f0, -1 + ce %f0, 4096 + +#CHECK: error: invalid operand #CHECK: ceb %f0, -1 #CHECK: error: invalid operand #CHECK: ceb %f0, 4096 @@ -719,6 +815,14 @@ celgbr %f0, 0, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cextr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: cextr %f2, %f0 + + cextr %f0, %f2 + cextr %f2, %f0 + #CHECK: error: invalid operand #CHECK: cfc -1 #CHECK: error: invalid operand @@ -743,6 +847,11 @@ cfdbra %r0, 0, %f0, 0 +#CHECK: error: instruction requires: fp-extension +#CHECK: cfdtr %r0, 0, %f0, 0 + + cfdtr %r0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: cfebr %r0, -1, %f0 #CHECK: error: invalid operand @@ -780,6 +889,22 @@ cfxbra %r0, 0, %f0, 0 +#CHECK: error: instruction requires: fp-extension +#CHECK: cfxtr %r0, 0, %f0, 0 + + cfxtr %r0, 0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: cfxr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cfxr %r0, 16, %f0 +#CHECK: error: invalid register pair +#CHECK: cfxr %r0, 0, %f2 + + cfxr %r0, -1, %f0 + cfxr %r0, 16, %f0 + cfxr %r0, 0, %f2 + #CHECK: error: invalid operand #CHECK: cg %r0, -524289 #CHECK: error: invalid operand @@ -802,6 +927,19 @@ cgdbra %r0, 0, %f0, 0 #CHECK: error: invalid operand +#CHECK: cgdtr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cgdtr %r0, 16, %f0 + + cgdtr %r0, -1, %f0 + cgdtr %r0, 16, %f0 + +#CHECK: error: instruction requires: fp-extension +#CHECK: cgdtra %r0, 0, %f0, 0 + + cgdtra %r0, 0, %f0, 0 + +#CHECK: error: invalid operand #CHECK: cgebr %r0, -1, %f0 #CHECK: error: invalid operand #CHECK: cgebr %r0, 16, %f0 @@ -999,6 +1137,33 @@ cgxbra %r0, 0, %f0, 0 #CHECK: error: invalid operand +#CHECK: cgxtr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cgxtr %r0, 16, %f0 +#CHECK: error: invalid register pair +#CHECK: cgxtr %r0, 0, %f2 + + cgxtr %r0, -1, %f0 + cgxtr %r0, 16, %f0 + cgxtr %r0, 0, %f2 + +#CHECK: error: instruction requires: fp-extension +#CHECK: cgxtra %r0, 0, %f0, 0 + + cgxtra %r0, 0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: cgxr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cgxr %r0, 16, %f0 +#CHECK: error: invalid register pair +#CHECK: cgxr %r0, 0, %f2 + + cgxr %r0, -1, %f0 + cgxr %r0, 16, %f0 + cgxr %r0, 0, %f2 + +#CHECK: error: invalid operand #CHECK: ch %r0, -1 #CHECK: error: invalid operand #CHECK: ch %r0, 4096 @@ -1226,6 +1391,11 @@ clfdbr %r0, 0, %f0, 0 #CHECK: error: instruction requires: fp-extension +#CHECK: clfdtr %r0, 0, %f0, 0 + + clfdtr %r0, 0, %f0, 0 + +#CHECK: error: instruction requires: fp-extension #CHECK: clfebr %r0, 0, %f0, 0 clfebr %r0, 0, %f0, 0 @@ -1274,6 +1444,11 @@ clfxbr %r0, 0, %f0, 0 +#CHECK: error: instruction requires: fp-extension +#CHECK: clfxtr %r0, 0, %f0, 0 + + clfxtr %r0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: clg %r0, -524289 #CHECK: error: invalid operand @@ -1288,6 +1463,11 @@ clgdbr %r0, 0, %f0, 0 #CHECK: error: instruction requires: fp-extension +#CHECK: clgdtr %r0, 0, %f0, 0 + + clgdtr %r0, 0, %f0, 0 + +#CHECK: error: instruction requires: fp-extension #CHECK: clgebr %r0, 0, %f0, 0 clgebr %r0, 0, %f0, 0 @@ -1438,6 +1618,11 @@ clgxbr %r0, 0, %f0, 0 +#CHECK: error: instruction requires: fp-extension +#CHECK: clgxtr %r0, 0, %f0, 0 + + clgxtr %r0, 0, %f0, 0 + #CHECK: error: instruction requires: high-word #CHECK: clhf %r0, 0 @@ -1754,6 +1939,14 @@ cs %r0, %r0, 0(%r1,%r2) #CHECK: error: invalid operand +#CHECK: csdtr %r0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: csdtr %r0, %f0, 16 + + csdtr %r0, %f0, -1 + csdtr %r0, %f0, 16 + +#CHECK: error: invalid operand #CHECK: csg %r0, %r0, -524289 #CHECK: error: invalid operand #CHECK: csg %r0, %r0, 524288 @@ -1782,6 +1975,20 @@ csst 0(%r1), 4096(%r15), %r2 #CHECK: error: invalid operand +#CHECK: csxtr %r0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: csxtr %r0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: csxtr %r0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: csxtr %r1, %f0, 0 + + csxtr %r0, %f0, -1 + csxtr %r0, %f0, 16 + csxtr %r0, %f2, 0 + csxtr %r1, %f0, 0 + +#CHECK: error: invalid operand #CHECK: csy %r0, %r0, -524289 #CHECK: error: invalid operand #CHECK: csy %r0, %r0, 524288 @@ -1900,6 +2107,14 @@ cuutf %r2, %r4, -1 cuutf %r2, %r4, 16 +#CHECK: error: invalid register pair +#CHECK: cuxtr %r0, %f2 +#CHECK: error: invalid register pair +#CHECK: cuxtr %r1, %f0 + + cuxtr %r0, %f2 + cuxtr %r1, %f0 + #CHECK: error: invalid operand #CHECK: cvb %r0, -1 #CHECK: error: invalid operand @@ -1966,6 +2181,16 @@ cxfbra %f0, 0, %r0, 0 +#CHECK: error: instruction requires: fp-extension +#CHECK: cxftr %f0, 0, %r0, 0 + + cxftr %f0, 0, %r0, 0 + +#CHECK: error: invalid register pair +#CHECK: cxfr %f2, %r0 + + cxfr %f2, %r0 + #CHECK: error: invalid register pair #CHECK: cxgbr %f2, %r0 @@ -1976,16 +2201,73 @@ cxgbra %f0, 0, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cxgr %f2, %r0 + + cxgr %f2, %r0 + +#CHECK: error: invalid register pair +#CHECK: cxgtr %f2, %r0 + + cxgtr %f2, %r0 + +#CHECK: error: instruction requires: fp-extension +#CHECK: cxgtra %f0, 0, %r0, 0 + + cxgtra %f0, 0, %r0, 0 + #CHECK: error: instruction requires: fp-extension #CHECK: cxlfbr %f0, 0, %r0, 0 cxlfbr %f0, 0, %r0, 0 #CHECK: error: instruction requires: fp-extension +#CHECK: cxlftr %f0, 0, %r0, 0 + + cxlftr %f0, 0, %r0, 0 + +#CHECK: error: instruction requires: fp-extension #CHECK: cxlgbr %f0, 0, %r0, 0 cxlgbr %f0, 0, %r0, 0 +#CHECK: error: instruction requires: fp-extension +#CHECK: cxlgtr %f0, 0, %r0, 0 + + cxlgtr %f0, 0, %r0, 0 + +#CHECK: error: invalid register pair +#CHECK: cxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: cxr %f2, %f0 + + cxr %f0, %f2 + cxr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: cxstr %f0, %r1 +#CHECK: error: invalid register pair +#CHECK: cxstr %f2, %r0 + + cxstr %f0, %r1 + cxstr %f2, %r0 + +#CHECK: error: invalid register pair +#CHECK: cxtr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: cxtr %f2, %f0 + + cxtr %f0, %f2 + cxtr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: cxutr %f0, %r1 +#CHECK: error: invalid register pair +#CHECK: cxutr %f2, %r0 + + cxutr %f0, %r1 + cxutr %f2, %r0 + #CHECK: error: invalid operand #CHECK: cy %r0, -524289 #CHECK: error: invalid operand @@ -2006,6 +2288,14 @@ d %r1, 0 #CHECK: error: invalid operand +#CHECK: dd %f0, -1 +#CHECK: error: invalid operand +#CHECK: dd %f0, 4096 + + dd %f0, -1 + dd %f0, 4096 + +#CHECK: error: invalid operand #CHECK: ddb %f0, -1 #CHECK: error: invalid operand #CHECK: ddb %f0, 4096 @@ -2013,6 +2303,19 @@ ddb %f0, -1 ddb %f0, 4096 +#CHECK: error: instruction requires: fp-extension +#CHECK: ddtra %f0, %f0, %f0, 0 + + ddtra %f0, %f0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: de %f0, -1 +#CHECK: error: invalid operand +#CHECK: de %f0, 4096 + + de %f0, -1 + de %f0, 4096 + #CHECK: error: invalid operand #CHECK: deb %f0, -1 #CHECK: error: invalid operand @@ -2167,6 +2470,30 @@ dxbr %f0, %f2 dxbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: dxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: dxr %f2, %f0 + + dxr %f0, %f2 + dxr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: dxtr %f0, %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: dxtr %f0, %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: dxtr %f2, %f0, %f0 + + dxtr %f0, %f0, %f2 + dxtr %f0, %f2, %f0 + dxtr %f2, %f0, %f0 + +#CHECK: error: instruction requires: fp-extension +#CHECK: dxtra %f0, %f0, %f0, 0 + + dxtra %f0, %f0, %f0, 0 + #CHECK: error: invalid operand #CHECK: ecag %r0, %r0, -524289 #CHECK: error: invalid operand @@ -2283,6 +2610,22 @@ edmk 0(1,%r2), 0(%r1,%r2) edmk 0(-), 0 +#CHECK: error: invalid register pair +#CHECK: eextr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: eextr %f2, %f0 + + eextr %f0, %f2 + eextr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: esxtr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: esxtr %f2, %f0 + + esxtr %f0, %f2 + esxtr %f2, %f0 + #CHECK: error: invalid operand #CHECK: ex %r0, -1 #CHECK: error: invalid operand @@ -2305,6 +2648,20 @@ fidbra %f0, 0, %f0, 0 #CHECK: error: invalid operand +#CHECK: fidtr %f0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: fidtr %f0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: fidtr %f0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: fidtr %f0, 16, %f0, 0 + + fidtr %f0, 0, %f0, -1 + fidtr %f0, 0, %f0, 16 + fidtr %f0, -1, %f0, 0 + fidtr %f0, 16, %f0, 0 + +#CHECK: error: invalid operand #CHECK: fiebr %f0, -1, %f0 #CHECK: error: invalid operand #CHECK: fiebr %f0, 16, %f0 @@ -2337,6 +2694,34 @@ fixbra %f0, 0, %f0, 0 #CHECK: error: invalid register pair +#CHECK: fixr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: fixr %f2, %f0 + + fixr %f0, %f2 + fixr %f2, %f0 + +#CHECK: error: invalid operand +#CHECK: fixtr %f0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: fixtr %f0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: fixtr %f0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: fixtr %f0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: fixtr %f0, 0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: fixtr %f2, 0, %f0, 0 + + fixtr %f0, 0, %f0, -1 + fixtr %f0, 0, %f0, 16 + fixtr %f0, -1, %f0, 0 + fixtr %f0, 16, %f0, 0 + fixtr %f0, 0, %f2, 0 + fixtr %f2, 0, %f0, 0 + +#CHECK: error: invalid register pair #CHECK: flogr %r1, %r0 flogr %r1, %r0 @@ -2399,6 +2784,17 @@ icy %r0, -524289 icy %r0, 524288 +#CHECK: error: invalid register pair +#CHECK: iextr %f0, %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: iextr %f0, %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: iextr %f2, %f0, %f0 + + iextr %f0, %f0, %f2 + iextr %f0, %f2, %f0 + iextr %f2, %f0, %f0 + #CHECK: error: invalid operand #CHECK: iihf %r0, -1 #CHECK: error: invalid operand @@ -2517,6 +2913,14 @@ kxbr %f0, %f2 kxbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: kxtr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: kxtr %f2, %f0 + + kxtr %f0, %f2 + kxtr %f2, %f0 + #CHECK: error: invalid operand #CHECK: l %r0, -1 #CHECK: error: invalid operand @@ -2651,6 +3055,14 @@ lcxbr %f0, %f2 lcxbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: lcxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: lcxr %f2, %f0 + + lcxr %f0, %f2 + lcxr %f2, %f0 + #CHECK: error: invalid operand #CHECK: ld %f0, -1 #CHECK: error: invalid operand @@ -2667,6 +3079,14 @@ ldeb %f0, -1 ldeb %f0, 4096 +#CHECK: error: invalid operand +#CHECK: ldetr %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: ldetr %f0, %f0, 16 + + ldetr %f0, %f0, -1 + ldetr %f0, %f0, 16 + #CHECK: error: invalid register pair #CHECK: ldxbr %f0, %f2 #CHECK: error: invalid register pair @@ -2680,6 +3100,31 @@ ldxbra %f0, 0, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: ldxr %f0, %f2 + + ldxr %f0, %f2 + +#CHECK: error: invalid operand +#CHECK: ldxtr %f0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: ldxtr %f0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: ldxtr %f0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: ldxtr %f0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: ldxtr %f0, 0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: ldxtr %f2, 0, %f0, 0 + + ldxtr %f0, 0, %f0, -1 + ldxtr %f0, 0, %f0, 16 + ldxtr %f0, -1, %f0, 0 + ldxtr %f0, 16, %f0, 0 + ldxtr %f0, 0, %f2, 0 + ldxtr %f2, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: ldy %f0, -524289 #CHECK: error: invalid operand @@ -2701,6 +3146,20 @@ ledbra %f0, 0, %f0, 0 +#CHECK: error: invalid operand +#CHECK: ledtr %f0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: ledtr %f0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: ledtr %f0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: ledtr %f0, 16, %f0, 0 + + ledtr %f0, 0, %f0, -1 + ledtr %f0, 0, %f0, 16 + ledtr %f0, -1, %f0, 0 + ledtr %f0, 16, %f0, 0 + #CHECK: error: invalid register pair #CHECK: lexbr %f0, %f2 #CHECK: error: invalid register pair @@ -2714,6 +3173,11 @@ lexbra %f0, 0, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: lexr %f0, %f2 + + lexr %f0, %f2 + #CHECK: error: invalid operand #CHECK: ley %f0, -524289 #CHECK: error: invalid operand @@ -3102,6 +3566,14 @@ lnxbr %f0, %f2 lnxbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: lnxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: lnxr %f2, %f0 + + lnxr %f0, %f2 + lnxr %f2, %f0 + #CHECK: error: instruction requires: interlocked-access1 #CHECK: lpd %r0, 0, 0 lpd %r0, 0, 0 @@ -3129,6 +3601,19 @@ lpxbr %f0, %f2 lpxbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: lpxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: lpxr %f2, %f0 + + lpxr %f0, %f2 + lpxr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: lrdr %f0, %f2 + + lrdr %f0, %f2 + #CHECK: error: offset out of range #CHECK: lrl %r0, -0x1000000002 #CHECK: error: offset out of range @@ -3192,6 +3677,97 @@ ltxbr %f14, %f0 #CHECK: error: invalid register pair +#CHECK: ltxr %f0, %f14 +#CHECK: error: invalid register pair +#CHECK: ltxr %f14, %f0 + + ltxr %f0, %f14 + ltxr %f14, %f0 + +#CHECK: error: invalid register pair +#CHECK: ltxtr %f0, %f14 +#CHECK: error: invalid register pair +#CHECK: ltxtr %f14, %f0 + + ltxtr %f0, %f14 + ltxtr %f14, %f0 + +#CHECK: error: invalid operand +#CHECK: lxd %f0, -1 +#CHECK: error: invalid operand +#CHECK: lxd %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: lxd %f2, 0 + + lxd %f0, -1 + lxd %f0, 4096 + lxd %f2, 0 + +#CHECK: error: invalid operand +#CHECK: lxdb %f0, -1 +#CHECK: error: invalid operand +#CHECK: lxdb %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: lxdb %f2, 0 + + lxdb %f0, -1 + lxdb %f0, 4096 + lxdb %f2, 0 + +#CHECK: error: invalid register pair +#CHECK: lxdbr %f2, %f0 + + lxdbr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: lxdr %f2, %f0 + + lxdr %f2, %f0 + +#CHECK: error: invalid operand +#CHECK: lxdtr %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: lxdtr %f0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: lxdtr %f2, %f0, 0 + + lxdtr %f0, %f0, -1 + lxdtr %f0, %f0, 16 + lxdtr %f2, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: lxe %f0, -1 +#CHECK: error: invalid operand +#CHECK: lxe %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: lxe %f2, 0 + + lxe %f0, -1 + lxe %f0, 4096 + lxe %f2, 0 + +#CHECK: error: invalid operand +#CHECK: lxeb %f0, -1 +#CHECK: error: invalid operand +#CHECK: lxeb %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: lxeb %f2, 0 + + lxeb %f0, -1 + lxeb %f0, 4096 + lxeb %f2, 0 + +#CHECK: error: invalid register pair +#CHECK: lxebr %f2, %f0 + + lxebr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: lxer %f2, %f0 + + lxer %f2, %f0 + +#CHECK: error: invalid register pair #CHECK: lxr %f0, %f2 #CHECK: error: invalid register pair #CHECK: lxr %f2, %f0 @@ -3224,6 +3800,14 @@ m %r1, 0 #CHECK: error: invalid operand +#CHECK: mad %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mad %f0, %f0, 4096 + + mad %f0, %f0, -1 + mad %f0, %f0, 4096 + +#CHECK: error: invalid operand #CHECK: madb %f0, %f0, -1 #CHECK: error: invalid operand #CHECK: madb %f0, %f0, 4096 @@ -3232,6 +3816,14 @@ madb %f0, %f0, 4096 #CHECK: error: invalid operand +#CHECK: mae %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mae %f0, %f0, 4096 + + mae %f0, %f0, -1 + mae %f0, %f0, 4096 + +#CHECK: error: invalid operand #CHECK: maeb %f0, %f0, -1 #CHECK: error: invalid operand #CHECK: maeb %f0, %f0, 4096 @@ -3240,6 +3832,38 @@ maeb %f0, %f0, 4096 #CHECK: error: invalid operand +#CHECK: may %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: may %f0, %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: may %f2, %f0, 0 + + may %f0, %f0, -1 + may %f0, %f0, 4096 + may %f2, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: mayh %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mayh %f0, %f0, 4096 + + mayh %f0, %f0, -1 + mayh %f0, %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: mayl %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mayl %f0, %f0, 4096 + + mayl %f0, %f0, -1 + mayl %f0, %f0, 4096 + +#CHECK: error: invalid register pair +#CHECK: mayr %f2, %f0, %f0 + + mayr %f2, %f0, %f0 + +#CHECK: error: invalid operand #CHECK: mc -1, 0 #CHECK: error: invalid operand #CHECK: mc 4096, 0 @@ -3257,6 +3881,14 @@ mc 0, 256 #CHECK: error: invalid operand +#CHECK: md %f0, -1 +#CHECK: error: invalid operand +#CHECK: md %f0, 4096 + + md %f0, -1 + md %f0, 4096 + +#CHECK: error: invalid operand #CHECK: mdb %f0, -1 #CHECK: error: invalid operand #CHECK: mdb %f0, 4096 @@ -3265,6 +3897,14 @@ mdb %f0, 4096 #CHECK: error: invalid operand +#CHECK: mde %f0, -1 +#CHECK: error: invalid operand +#CHECK: mde %f0, 4096 + + mde %f0, -1 + mde %f0, 4096 + +#CHECK: error: invalid operand #CHECK: mdeb %f0, -1 #CHECK: error: invalid operand #CHECK: mdeb %f0, 4096 @@ -3272,6 +3912,27 @@ mdeb %f0, -1 mdeb %f0, 4096 +#CHECK: error: instruction requires: fp-extension +#CHECK: mdtra %f0, %f0, %f0, 0 + + mdtra %f0, %f0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: me %f0, -1 +#CHECK: error: invalid operand +#CHECK: me %f0, 4096 + + me %f0, -1 + me %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: mee %f0, -1 +#CHECK: error: invalid operand +#CHECK: mee %f0, 4096 + + mee %f0, -1 + mee %f0, 4096 + #CHECK: error: invalid operand #CHECK: meeb %f0, -1 #CHECK: error: invalid operand @@ -3428,6 +4089,14 @@ ms %r0, 4096 #CHECK: error: invalid operand +#CHECK: msd %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: msd %f0, %f0, 4096 + + msd %f0, %f0, -1 + msd %f0, %f0, 4096 + +#CHECK: error: invalid operand #CHECK: msdb %f0, %f0, -1 #CHECK: error: invalid operand #CHECK: msdb %f0, %f0, 4096 @@ -3436,6 +4105,14 @@ msdb %f0, %f0, 4096 #CHECK: error: invalid operand +#CHECK: mse %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mse %f0, %f0, 4096 + + mse %f0, %f0, -1 + mse %f0, %f0, 4096 + +#CHECK: error: invalid operand #CHECK: mseb %f0, %f0, -1 #CHECK: error: invalid operand #CHECK: mseb %f0, %f0, 4096 @@ -3871,6 +4548,17 @@ mxbr %f2, %f0 #CHECK: error: invalid register pair +#CHECK: mxd %f2, 0 +#CHECK: error: invalid operand +#CHECK: mxd %f0, -1 +#CHECK: error: invalid operand +#CHECK: mxd %f0, 4096 + + mxd %f2, 0 + mxd %f0, -1 + mxd %f0, 4096 + +#CHECK: error: invalid register pair #CHECK: mxdb %f2, 0 #CHECK: error: invalid operand #CHECK: mxdb %f0, -1 @@ -3886,6 +4574,67 @@ mxdbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: mxdr %f2, %f0 + + mxdr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: mxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: mxr %f2, %f0 + + mxr %f0, %f2 + mxr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: mxtr %f0, %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: mxtr %f0, %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: mxtr %f2, %f0, %f0 + + mxtr %f0, %f0, %f2 + mxtr %f0, %f2, %f0 + mxtr %f2, %f0, %f0 + +#CHECK: error: instruction requires: fp-extension +#CHECK: mxtra %f0, %f0, %f0, 0 + + mxtra %f0, %f0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: my %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: my %f0, %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: my %f2, %f0, 0 + + my %f0, %f0, -1 + my %f0, %f0, 4096 + my %f2, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: myh %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: myh %f0, %f0, 4096 + + myh %f0, %f0, -1 + myh %f0, %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: myl %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: myl %f0, %f0, 4096 + + myl %f0, %f0, -1 + myl %f0, %f0, 4096 + +#CHECK: error: invalid register pair +#CHECK: myr %f2, %f0, %f0 + + myr %f2, %f0, %f0 + #CHECK: error: invalid operand #CHECK: n %r0, -1 #CHECK: error: invalid operand @@ -4413,6 +5162,31 @@ pr %r0 #CHECK: error: invalid operand +#CHECK: qadtr %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: qadtr %f0, %f0, %f0, 16 + + qadtr %f0, %f0, %f0, -1 + qadtr %f0, %f0, %f0, 16 + +#CHECK: error: invalid operand +#CHECK: qaxtr %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: qaxtr %f0, %f0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: qaxtr %f0, %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: qaxtr %f0, %f2, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: qaxtr %f2, %f0, %f0, 0 + + qaxtr %f0, %f0, %f0, -1 + qaxtr %f0, %f0, %f0, 16 + qaxtr %f0, %f0, %f2, 0 + qaxtr %f0, %f2, %f0, 0 + qaxtr %f2, %f0, %f0, 0 + +#CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,-1 #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,64 @@ -4511,6 +5285,31 @@ rosbg %r0,%r0,256,0,0 #CHECK: error: invalid operand +#CHECK: rrdtr %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: rrdtr %f0, %f0, %f0, 16 + + rrdtr %f0, %f0, %f0, -1 + rrdtr %f0, %f0, %f0, 16 + +#CHECK: error: invalid operand +#CHECK: rrxtr %f0, %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: rrxtr %f0, %f0, %f0, 16 +#CHECK: error: invalid register pair +#CHECK: rrxtr %f0, %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: rrxtr %f0, %f2, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: rrxtr %f2, %f0, %f0, 0 + + rrxtr %f0, %f0, %f0, -1 + rrxtr %f0, %f0, %f0, 16 + rrxtr %f0, %f0, %f2, 0 + rrxtr %f0, %f2, %f0, 0 + rrxtr %f2, %f0, %f0, 0 + +#CHECK: error: invalid operand #CHECK: rxsbg %r0,%r0,0,0,-1 #CHECK: error: invalid operand #CHECK: rxsbg %r0,%r0,0,0,64 @@ -4539,6 +5338,14 @@ s %r0, 4096 #CHECK: error: invalid operand +#CHECK: sd %f0, -1 +#CHECK: error: invalid operand +#CHECK: sd %f0, 4096 + + sd %f0, -1 + sd %f0, 4096 + +#CHECK: error: invalid operand #CHECK: sdb %f0, -1 #CHECK: error: invalid operand #CHECK: sdb %f0, 4096 @@ -4546,6 +5353,19 @@ sdb %f0, -1 sdb %f0, 4096 +#CHECK: error: instruction requires: fp-extension +#CHECK: sdtra %f0, %f0, %f0, 0 + + sdtra %f0, %f0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: se %f0, -1 +#CHECK: error: invalid operand +#CHECK: se %f0, 4096 + + se %f0, -1 + se %f0, 4096 + #CHECK: error: invalid operand #CHECK: seb %f0, -1 #CHECK: error: invalid operand @@ -4683,6 +5503,14 @@ sldl %r0,0(%r1,%r2) #CHECK: error: invalid operand +#CHECK: sldt %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: sldt %f0, %f0, 4096 + + sldt %f0, %f0, -1 + sldt %f0, %f0, 4096 + +#CHECK: error: invalid operand #CHECK: slfi %r0, -1 #CHECK: error: invalid operand #CHECK: slfi %r0, (1 << 32) @@ -4758,6 +5586,20 @@ slrk %r2,%r3,%r4 #CHECK: error: invalid operand +#CHECK: slxt %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: slxt %f0, %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: slxt %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: slxt %f2, %f0, 0 + + slxt %f0, %f0, -1 + slxt %f0, %f0, 4096 + slxt %f0, %f2, 0 + slxt %f2, %f0, 0 + +#CHECK: error: invalid operand #CHECK: sly %r0, -524289 #CHECK: error: invalid operand #CHECK: sly %r0, 524288 @@ -4819,6 +5661,14 @@ sp 0(-), 0(1) #CHECK: error: invalid operand +#CHECK: sqd %f0, -1 +#CHECK: error: invalid operand +#CHECK: sqd %f0, 4096 + + sqd %f0, -1 + sqd %f0, 4096 + +#CHECK: error: invalid operand #CHECK: sqdb %f0, -1 #CHECK: error: invalid operand #CHECK: sqdb %f0, 4096 @@ -4827,6 +5677,14 @@ sqdb %f0, 4096 #CHECK: error: invalid operand +#CHECK: sqe %f0, -1 +#CHECK: error: invalid operand +#CHECK: sqe %f0, 4096 + + sqe %f0, -1 + sqe %f0, 4096 + +#CHECK: error: invalid operand #CHECK: sqeb %f0, -1 #CHECK: error: invalid operand #CHECK: sqeb %f0, 4096 @@ -4842,6 +5700,14 @@ sqxbr %f0, %f2 sqxbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: sqxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: sqxr %f2, %f0 + + sqxr %f0, %f2 + sqxr %f2, %f0 + #CHECK: error: invalid operand #CHECK: sra %r0,-1 #CHECK: error: invalid operand @@ -4909,6 +5775,14 @@ srdl %r0,0(%r0) srdl %r0,0(%r1,%r2) +#CHECK: error: invalid operand +#CHECK: srdt %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: srdt %f0, %f0, 4096 + + srdt %f0, %f0, -1 + srdt %f0, %f0, 4096 + #CHECK: error: instruction requires: distinct-ops #CHECK: srk %r2,%r3,%r4 @@ -5025,6 +5899,20 @@ srp 0(-), 0, 0 #CHECK: error: invalid operand +#CHECK: srxt %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: srxt %f0, %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: srxt %f0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: srxt %f2, %f0, 0 + + srxt %f0, %f0, -1 + srxt %f0, %f0, 4096 + srxt %f0, %f2, 0 + srxt %f2, %f0, 0 + +#CHECK: error: invalid operand #CHECK: st %r0, -1 #CHECK: error: invalid operand #CHECK: st %r0, 4096 @@ -5326,6 +6214,22 @@ sty %r0, -524289 sty %r0, 524288 +#CHECK: error: invalid operand +#CHECK: su %f0, -1 +#CHECK: error: invalid operand +#CHECK: su %f0, 4096 + + su %f0, -1 + su %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: sw %f0, -1 +#CHECK: error: invalid operand +#CHECK: sw %f0, 4096 + + sw %f0, -1 + sw %f0, 4096 + #CHECK: error: invalid register pair #CHECK: sxbr %f0, %f2 #CHECK: error: invalid register pair @@ -5334,6 +6238,30 @@ sxbr %f0, %f2 sxbr %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: sxr %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: sxr %f2, %f0 + + sxr %f0, %f2 + sxr %f2, %f0 + +#CHECK: error: invalid register pair +#CHECK: sxtr %f0, %f0, %f2 +#CHECK: error: invalid register pair +#CHECK: sxtr %f0, %f2, %f0 +#CHECK: error: invalid register pair +#CHECK: sxtr %f2, %f0, %f0 + + sxtr %f0, %f0, %f2 + sxtr %f0, %f2, %f0 + sxtr %f2, %f0, %f0 + +#CHECK: error: instruction requires: fp-extension +#CHECK: sxtra %f0, %f0, %f0, 0 + + sxtra %f0, %f0, %f0, 0 + #CHECK: error: invalid operand #CHECK: sy %r0, -524289 #CHECK: error: invalid operand @@ -5343,6 +6271,22 @@ sy %r0, 524288 #CHECK: error: invalid operand +#CHECK: tbdr %f0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: tbdr %f0, 16, %f0 + + tbdr %f0, -1, %f0 + tbdr %f0, 16, %f0 + +#CHECK: error: invalid operand +#CHECK: tbedr %f0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: tbedr %f0, 16, %f0 + + tbedr %f0, -1, %f0 + tbedr %f0, 16, %f0 + +#CHECK: error: invalid operand #CHECK: tcdb %f0, -1 #CHECK: error: invalid operand #CHECK: tcdb %f0, 4096 @@ -5367,6 +6311,60 @@ tcxb %f0, 4096 #CHECK: error: invalid operand +#CHECK: tdcdt %f0, -1 +#CHECK: error: invalid operand +#CHECK: tdcdt %f0, 4096 + + tdcdt %f0, -1 + tdcdt %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: tdcet %f0, -1 +#CHECK: error: invalid operand +#CHECK: tdcet %f0, 4096 + + tdcet %f0, -1 + tdcet %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: tdcxt %f0, -1 +#CHECK: error: invalid operand +#CHECK: tdcxt %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: tdcxt %f2, 0 + + tdcxt %f0, -1 + tdcxt %f0, 4096 + tdcxt %f2, 0 + +#CHECK: error: invalid operand +#CHECK: tdgdt %f0, -1 +#CHECK: error: invalid operand +#CHECK: tdgdt %f0, 4096 + + tdgdt %f0, -1 + tdgdt %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: tdget %f0, -1 +#CHECK: error: invalid operand +#CHECK: tdget %f0, 4096 + + tdget %f0, -1 + tdget %f0, 4096 + +#CHECK: error: invalid operand +#CHECK: tdgxt %f0, -1 +#CHECK: error: invalid operand +#CHECK: tdgxt %f0, 4096 +#CHECK: error: invalid register pair +#CHECK: tdgxt %f2, 0 + + tdgxt %f0, -1 + tdgxt %f0, 4096 + tdgxt %f2, 0 + +#CHECK: error: invalid operand #CHECK: tm -1, 0 #CHECK: error: invalid operand #CHECK: tm 4096, 0 diff --git a/test/MC/SystemZ/insn-good-z13.s b/test/MC/SystemZ/insn-good-z13.s index cbfcfa9a89af9..6a4beff7638cb 100644 --- a/test/MC/SystemZ/insn-good-z13.s +++ b/test/MC/SystemZ/insn-good-z13.s @@ -4,6 +4,86 @@ # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch11 -show-encoding %s \ # RUN: | FileCheck %s +#CHECK: cdpt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xae] +#CHECK: cdpt %f15, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0xae] +#CHECK: cdpt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xae] +#CHECK: cdpt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xae] +#CHECK: cdpt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xae] +#CHECK: cdpt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xae] +#CHECK: cdpt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xae] +#CHECK: cdpt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xae] +#CHECK: cdpt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xae] + + cdpt %f0, 0(1), 0 + cdpt %f15, 0(1), 0 + cdpt %f0, 0(1), 15 + cdpt %f0, 0(1,%r1), 0 + cdpt %f0, 0(1,%r15), 0 + cdpt %f0, 4095(1,%r1), 0 + cdpt %f0, 4095(1,%r15), 0 + cdpt %f0, 0(256,%r1), 0 + cdpt %f0, 0(256,%r15), 0 + +#CHECK: cpdt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xac] +#CHECK: cpdt %f15, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0xac] +#CHECK: cpdt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xac] +#CHECK: cpdt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xac] +#CHECK: cpdt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xac] +#CHECK: cpdt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xac] +#CHECK: cpdt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xac] +#CHECK: cpdt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xac] +#CHECK: cpdt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xac] + + cpdt %f0, 0(1), 0 + cpdt %f15, 0(1), 0 + cpdt %f0, 0(1), 15 + cpdt %f0, 0(1,%r1), 0 + cpdt %f0, 0(1,%r15), 0 + cpdt %f0, 4095(1,%r1), 0 + cpdt %f0, 4095(1,%r15), 0 + cpdt %f0, 0(256,%r1), 0 + cpdt %f0, 0(256,%r15), 0 + +#CHECK: cpxt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xad] +#CHECK: cpxt %f13, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0xad] +#CHECK: cpxt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xad] +#CHECK: cpxt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xad] +#CHECK: cpxt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xad] +#CHECK: cpxt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xad] +#CHECK: cpxt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xad] +#CHECK: cpxt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xad] +#CHECK: cpxt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xad] + + cpxt %f0, 0(1), 0 + cpxt %f13, 0(1), 0 + cpxt %f0, 0(1), 15 + cpxt %f0, 0(1,%r1), 0 + cpxt %f0, 0(1,%r15), 0 + cpxt %f0, 4095(1,%r1), 0 + cpxt %f0, 4095(1,%r15), 0 + cpxt %f0, 0(256,%r1), 0 + cpxt %f0, 0(256,%r15), 0 + +#CHECK: cxpt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xaf] +#CHECK: cxpt %f13, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0xaf] +#CHECK: cxpt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xaf] +#CHECK: cxpt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xaf] +#CHECK: cxpt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xaf] +#CHECK: cxpt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xaf] +#CHECK: cxpt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xaf] +#CHECK: cxpt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xaf] +#CHECK: cxpt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xaf] + + cxpt %f0, 0(1), 0 + cxpt %f13, 0(1), 0 + cxpt %f0, 0(1), 15 + cxpt %f0, 0(1,%r1), 0 + cxpt %f0, 0(1,%r15), 0 + cxpt %f0, 4095(1,%r1), 0 + cxpt %f0, 4095(1,%r15), 0 + cxpt %f0, 0(256,%r1), 0 + cxpt %f0, 0(256,%r15), 0 + #CHECK: lcbb %r0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x27] #CHECK: lcbb %r0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x27] #CHECK: lcbb %r0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x27] diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s index 02c473c11a4a9..31d257d7448d2 100644 --- a/test/MC/SystemZ/insn-good-z196.s +++ b/test/MC/SystemZ/insn-good-z196.s @@ -2,6 +2,20 @@ # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch9 -show-encoding %s | FileCheck %s +#CHECK: adtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd2,0x00,0x00] +#CHECK: adtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd2,0x0f,0x00] +#CHECK: adtra %f0, %f0, %f15, 0 # encoding: [0xb3,0xd2,0xf0,0x00] +#CHECK: adtra %f0, %f15, %f0, 0 # encoding: [0xb3,0xd2,0x00,0x0f] +#CHECK: adtra %f15, %f0, %f0, 0 # encoding: [0xb3,0xd2,0x00,0xf0] +#CHECK: adtra %f7, %f8, %f9, 10 # encoding: [0xb3,0xd2,0x9a,0x78] + + adtra %f0, %f0, %f0, 0 + adtra %f0, %f0, %f0, 15 + adtra %f0, %f0, %f15, 0 + adtra %f0, %f15, %f0, 0 + adtra %f15, %f0, %f0, 0 + adtra %f7, %f8, %f9, 10 + #CHECK: aghik %r0, %r0, -32768 # encoding: [0xec,0x00,0x80,0x00,0x00,0xd9] #CHECK: aghik %r0, %r0, -1 # encoding: [0xec,0x00,0xff,0xff,0x00,0xd9] #CHECK: aghik %r0, %r0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0xd9] @@ -136,6 +150,20 @@ ark %r15,%r0,%r0 ark %r7,%r8,%r9 +#CHECK: axtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xda,0x00,0x00] +#CHECK: axtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xda,0x0f,0x00] +#CHECK: axtra %f0, %f0, %f13, 0 # encoding: [0xb3,0xda,0xd0,0x00] +#CHECK: axtra %f0, %f13, %f0, 0 # encoding: [0xb3,0xda,0x00,0x0d] +#CHECK: axtra %f13, %f0, %f0, 0 # encoding: [0xb3,0xda,0x00,0xd0] +#CHECK: axtra %f8, %f8, %f8, 8 # encoding: [0xb3,0xda,0x88,0x88] + + axtra %f0, %f0, %f0, 0 + axtra %f0, %f0, %f0, 15 + axtra %f0, %f0, %f13, 0 + axtra %f0, %f13, %f0, 0 + axtra %f13, %f0, %f0, 0 + axtra %f8, %f8, %f8, 8 + #CHECK: brcth %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xcc,0x06,A,A,A,A] #CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL brcth %r0, -0x100000000 @@ -187,6 +215,20 @@ cdfbra %f4, 5, %r6, 7 cdfbra %f15, 0, %r0, 0 +#CHECK: cdftr %f0, 0, %r0, 0 # encoding: [0xb9,0x51,0x00,0x00] +#CHECK: cdftr %f0, 0, %r0, 15 # encoding: [0xb9,0x51,0x0f,0x00] +#CHECK: cdftr %f0, 0, %r15, 0 # encoding: [0xb9,0x51,0x00,0x0f] +#CHECK: cdftr %f0, 15, %r0, 0 # encoding: [0xb9,0x51,0xf0,0x00] +#CHECK: cdftr %f4, 5, %r6, 7 # encoding: [0xb9,0x51,0x57,0x46] +#CHECK: cdftr %f15, 0, %r0, 0 # encoding: [0xb9,0x51,0x00,0xf0] + + cdftr %f0, 0, %r0, 0 + cdftr %f0, 0, %r0, 15 + cdftr %f0, 0, %r15, 0 + cdftr %f0, 15, %r0, 0 + cdftr %f4, 5, %r6, 7 + cdftr %f15, 0, %r0, 0 + #CHECK: cdgbra %f0, 0, %r0, 0 # encoding: [0xb3,0xa5,0x00,0x00] #CHECK: cdgbra %f0, 0, %r0, 15 # encoding: [0xb3,0xa5,0x0f,0x00] #CHECK: cdgbra %f0, 0, %r15, 0 # encoding: [0xb3,0xa5,0x00,0x0f] @@ -201,6 +243,20 @@ cdgbra %f4, 5, %r6, 7 cdgbra %f15, 0, %r0, 0 +#CHECK: cdgtra %f0, 0, %r0, 0 # encoding: [0xb3,0xf1,0x00,0x00] +#CHECK: cdgtra %f0, 0, %r0, 15 # encoding: [0xb3,0xf1,0x0f,0x00] +#CHECK: cdgtra %f0, 0, %r15, 0 # encoding: [0xb3,0xf1,0x00,0x0f] +#CHECK: cdgtra %f0, 15, %r0, 0 # encoding: [0xb3,0xf1,0xf0,0x00] +#CHECK: cdgtra %f4, 5, %r6, 7 # encoding: [0xb3,0xf1,0x57,0x46] +#CHECK: cdgtra %f15, 0, %r0, 0 # encoding: [0xb3,0xf1,0x00,0xf0] + + cdgtra %f0, 0, %r0, 0 + cdgtra %f0, 0, %r0, 15 + cdgtra %f0, 0, %r15, 0 + cdgtra %f0, 15, %r0, 0 + cdgtra %f4, 5, %r6, 7 + cdgtra %f15, 0, %r0, 0 + #CHECK: cdlfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x91,0x00,0x00] #CHECK: cdlfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x91,0x0f,0x00] #CHECK: cdlfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x91,0x00,0x0f] @@ -215,6 +271,20 @@ cdlfbr %f4, 5, %r6, 7 cdlfbr %f15, 0, %r0, 0 +#CHECK: cdlftr %f0, 0, %r0, 0 # encoding: [0xb9,0x53,0x00,0x00] +#CHECK: cdlftr %f0, 0, %r0, 15 # encoding: [0xb9,0x53,0x0f,0x00] +#CHECK: cdlftr %f0, 0, %r15, 0 # encoding: [0xb9,0x53,0x00,0x0f] +#CHECK: cdlftr %f0, 15, %r0, 0 # encoding: [0xb9,0x53,0xf0,0x00] +#CHECK: cdlftr %f4, 5, %r6, 7 # encoding: [0xb9,0x53,0x57,0x46] +#CHECK: cdlftr %f15, 0, %r0, 0 # encoding: [0xb9,0x53,0x00,0xf0] + + cdlftr %f0, 0, %r0, 0 + cdlftr %f0, 0, %r0, 15 + cdlftr %f0, 0, %r15, 0 + cdlftr %f0, 15, %r0, 0 + cdlftr %f4, 5, %r6, 7 + cdlftr %f15, 0, %r0, 0 + #CHECK: cdlgbr %f0, 0, %r0, 0 # encoding: [0xb3,0xa1,0x00,0x00] #CHECK: cdlgbr %f0, 0, %r0, 15 # encoding: [0xb3,0xa1,0x0f,0x00] #CHECK: cdlgbr %f0, 0, %r15, 0 # encoding: [0xb3,0xa1,0x00,0x0f] @@ -229,6 +299,20 @@ cdlgbr %f4, 5, %r6, 7 cdlgbr %f15, 0, %r0, 0 +#CHECK: cdlgtr %f0, 0, %r0, 0 # encoding: [0xb9,0x52,0x00,0x00] +#CHECK: cdlgtr %f0, 0, %r0, 15 # encoding: [0xb9,0x52,0x0f,0x00] +#CHECK: cdlgtr %f0, 0, %r15, 0 # encoding: [0xb9,0x52,0x00,0x0f] +#CHECK: cdlgtr %f0, 15, %r0, 0 # encoding: [0xb9,0x52,0xf0,0x00] +#CHECK: cdlgtr %f4, 5, %r6, 7 # encoding: [0xb9,0x52,0x57,0x46] +#CHECK: cdlgtr %f15, 0, %r0, 0 # encoding: [0xb9,0x52,0x00,0xf0] + + cdlgtr %f0, 0, %r0, 0 + cdlgtr %f0, 0, %r0, 15 + cdlgtr %f0, 0, %r15, 0 + cdlgtr %f0, 15, %r0, 0 + cdlgtr %f4, 5, %r6, 7 + cdlgtr %f15, 0, %r0, 0 + #CHECK: cefbra %f0, 0, %r0, 0 # encoding: [0xb3,0x94,0x00,0x00] #CHECK: cefbra %f0, 0, %r0, 15 # encoding: [0xb3,0x94,0x0f,0x00] #CHECK: cefbra %f0, 0, %r15, 0 # encoding: [0xb3,0x94,0x00,0x0f] @@ -299,6 +383,20 @@ cfdbra %r4, 5, %f6, 7 cfdbra %r15, 0, %f0, 0 +#CHECK: cfdtr %r0, 0, %f0, 0 # encoding: [0xb9,0x41,0x00,0x00] +#CHECK: cfdtr %r0, 0, %f0, 15 # encoding: [0xb9,0x41,0x0f,0x00] +#CHECK: cfdtr %r0, 0, %f15, 0 # encoding: [0xb9,0x41,0x00,0x0f] +#CHECK: cfdtr %r0, 15, %f0, 0 # encoding: [0xb9,0x41,0xf0,0x00] +#CHECK: cfdtr %r4, 5, %f6, 7 # encoding: [0xb9,0x41,0x57,0x46] +#CHECK: cfdtr %r15, 0, %f0, 0 # encoding: [0xb9,0x41,0x00,0xf0] + + cfdtr %r0, 0, %f0, 0 + cfdtr %r0, 0, %f0, 15 + cfdtr %r0, 0, %f15, 0 + cfdtr %r0, 15, %f0, 0 + cfdtr %r4, 5, %f6, 7 + cfdtr %r15, 0, %f0, 0 + #CHECK: cfebra %r0, 0, %f0, 0 # encoding: [0xb3,0x98,0x00,0x00] #CHECK: cfebra %r0, 0, %f0, 15 # encoding: [0xb3,0x98,0x0f,0x00] #CHECK: cfebra %r0, 0, %f15, 0 # encoding: [0xb3,0x98,0x00,0x0f] @@ -327,6 +425,20 @@ cfxbra %r7, 5, %f8, 9 cfxbra %r15, 0, %f0, 0 +#CHECK: cfxtr %r0, 0, %f0, 0 # encoding: [0xb9,0x49,0x00,0x00] +#CHECK: cfxtr %r0, 0, %f0, 15 # encoding: [0xb9,0x49,0x0f,0x00] +#CHECK: cfxtr %r0, 0, %f13, 0 # encoding: [0xb9,0x49,0x00,0x0d] +#CHECK: cfxtr %r0, 15, %f0, 0 # encoding: [0xb9,0x49,0xf0,0x00] +#CHECK: cfxtr %r7, 5, %f8, 9 # encoding: [0xb9,0x49,0x59,0x78] +#CHECK: cfxtr %r15, 0, %f0, 0 # encoding: [0xb9,0x49,0x00,0xf0] + + cfxtr %r0, 0, %f0, 0 + cfxtr %r0, 0, %f0, 15 + cfxtr %r0, 0, %f13, 0 + cfxtr %r0, 15, %f0, 0 + cfxtr %r7, 5, %f8, 9 + cfxtr %r15, 0, %f0, 0 + #CHECK: cgdbra %r0, 0, %f0, 0 # encoding: [0xb3,0xa9,0x00,0x00] #CHECK: cgdbra %r0, 0, %f0, 15 # encoding: [0xb3,0xa9,0x0f,0x00] #CHECK: cgdbra %r0, 0, %f15, 0 # encoding: [0xb3,0xa9,0x00,0x0f] @@ -341,6 +453,20 @@ cgdbra %r4, 5, %f6, 7 cgdbra %r15, 0, %f0, 0 +#CHECK: cgdtra %r0, 0, %f0, 0 # encoding: [0xb3,0xe1,0x00,0x00] +#CHECK: cgdtra %r0, 0, %f0, 15 # encoding: [0xb3,0xe1,0x0f,0x00] +#CHECK: cgdtra %r0, 0, %f15, 0 # encoding: [0xb3,0xe1,0x00,0x0f] +#CHECK: cgdtra %r0, 15, %f0, 0 # encoding: [0xb3,0xe1,0xf0,0x00] +#CHECK: cgdtra %r4, 5, %f6, 7 # encoding: [0xb3,0xe1,0x57,0x46] +#CHECK: cgdtra %r15, 0, %f0, 0 # encoding: [0xb3,0xe1,0x00,0xf0] + + cgdtra %r0, 0, %f0, 0 + cgdtra %r0, 0, %f0, 15 + cgdtra %r0, 0, %f15, 0 + cgdtra %r0, 15, %f0, 0 + cgdtra %r4, 5, %f6, 7 + cgdtra %r15, 0, %f0, 0 + #CHECK: cgebra %r0, 0, %f0, 0 # encoding: [0xb3,0xa8,0x00,0x00] #CHECK: cgebra %r0, 0, %f0, 15 # encoding: [0xb3,0xa8,0x0f,0x00] #CHECK: cgebra %r0, 0, %f15, 0 # encoding: [0xb3,0xa8,0x00,0x0f] @@ -369,6 +495,20 @@ cgxbra %r7, 5, %f8, 9 cgxbra %r15, 0, %f0, 0 +#CHECK: cgxtra %r0, 0, %f0, 0 # encoding: [0xb3,0xe9,0x00,0x00] +#CHECK: cgxtra %r0, 0, %f0, 15 # encoding: [0xb3,0xe9,0x0f,0x00] +#CHECK: cgxtra %r0, 0, %f13, 0 # encoding: [0xb3,0xe9,0x00,0x0d] +#CHECK: cgxtra %r0, 15, %f0, 0 # encoding: [0xb3,0xe9,0xf0,0x00] +#CHECK: cgxtra %r7, 5, %f8, 9 # encoding: [0xb3,0xe9,0x59,0x78] +#CHECK: cgxtra %r15, 0, %f0, 0 # encoding: [0xb3,0xe9,0x00,0xf0] + + cgxtra %r0, 0, %f0, 0 + cgxtra %r0, 0, %f0, 15 + cgxtra %r0, 0, %f13, 0 + cgxtra %r0, 15, %f0, 0 + cgxtra %r7, 5, %f8, 9 + cgxtra %r15, 0, %f0, 0 + #CHECK: chf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xcd] #CHECK: chf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xcd] #CHECK: chf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xcd] @@ -419,6 +559,20 @@ clfdbr %r4, 5, %f6, 7 clfdbr %r15, 0, %f0, 0 +#CHECK: clfdtr %r0, 0, %f0, 0 # encoding: [0xb9,0x43,0x00,0x00] +#CHECK: clfdtr %r0, 0, %f0, 15 # encoding: [0xb9,0x43,0x0f,0x00] +#CHECK: clfdtr %r0, 0, %f15, 0 # encoding: [0xb9,0x43,0x00,0x0f] +#CHECK: clfdtr %r0, 15, %f0, 0 # encoding: [0xb9,0x43,0xf0,0x00] +#CHECK: clfdtr %r4, 5, %f6, 7 # encoding: [0xb9,0x43,0x57,0x46] +#CHECK: clfdtr %r15, 0, %f0, 0 # encoding: [0xb9,0x43,0x00,0xf0] + + clfdtr %r0, 0, %f0, 0 + clfdtr %r0, 0, %f0, 15 + clfdtr %r0, 0, %f15, 0 + clfdtr %r0, 15, %f0, 0 + clfdtr %r4, 5, %f6, 7 + clfdtr %r15, 0, %f0, 0 + #CHECK: clfebr %r0, 0, %f0, 0 # encoding: [0xb3,0x9c,0x00,0x00] #CHECK: clfebr %r0, 0, %f0, 15 # encoding: [0xb3,0x9c,0x0f,0x00] #CHECK: clfebr %r0, 0, %f15, 0 # encoding: [0xb3,0x9c,0x00,0x0f] @@ -447,6 +601,20 @@ clfxbr %r7, 5, %f8, 9 clfxbr %r15, 0, %f0, 0 +#CHECK: clfxtr %r0, 0, %f0, 0 # encoding: [0xb9,0x4b,0x00,0x00] +#CHECK: clfxtr %r0, 0, %f0, 15 # encoding: [0xb9,0x4b,0x0f,0x00] +#CHECK: clfxtr %r0, 0, %f13, 0 # encoding: [0xb9,0x4b,0x00,0x0d] +#CHECK: clfxtr %r0, 15, %f0, 0 # encoding: [0xb9,0x4b,0xf0,0x00] +#CHECK: clfxtr %r7, 5, %f8, 9 # encoding: [0xb9,0x4b,0x59,0x78] +#CHECK: clfxtr %r15, 0, %f0, 0 # encoding: [0xb9,0x4b,0x00,0xf0] + + clfxtr %r0, 0, %f0, 0 + clfxtr %r0, 0, %f0, 15 + clfxtr %r0, 0, %f13, 0 + clfxtr %r0, 15, %f0, 0 + clfxtr %r7, 5, %f8, 9 + clfxtr %r15, 0, %f0, 0 + #CHECK: clgdbr %r0, 0, %f0, 0 # encoding: [0xb3,0xad,0x00,0x00] #CHECK: clgdbr %r0, 0, %f0, 15 # encoding: [0xb3,0xad,0x0f,0x00] #CHECK: clgdbr %r0, 0, %f15, 0 # encoding: [0xb3,0xad,0x00,0x0f] @@ -461,6 +629,20 @@ clgdbr %r4, 5, %f6, 7 clgdbr %r15, 0, %f0, 0 +#CHECK: clgdtr %r0, 0, %f0, 0 # encoding: [0xb9,0x42,0x00,0x00] +#CHECK: clgdtr %r0, 0, %f0, 15 # encoding: [0xb9,0x42,0x0f,0x00] +#CHECK: clgdtr %r0, 0, %f15, 0 # encoding: [0xb9,0x42,0x00,0x0f] +#CHECK: clgdtr %r0, 15, %f0, 0 # encoding: [0xb9,0x42,0xf0,0x00] +#CHECK: clgdtr %r4, 5, %f6, 7 # encoding: [0xb9,0x42,0x57,0x46] +#CHECK: clgdtr %r15, 0, %f0, 0 # encoding: [0xb9,0x42,0x00,0xf0] + + clgdtr %r0, 0, %f0, 0 + clgdtr %r0, 0, %f0, 15 + clgdtr %r0, 0, %f15, 0 + clgdtr %r0, 15, %f0, 0 + clgdtr %r4, 5, %f6, 7 + clgdtr %r15, 0, %f0, 0 + #CHECK: clgebr %r0, 0, %f0, 0 # encoding: [0xb3,0xac,0x00,0x00] #CHECK: clgebr %r0, 0, %f0, 15 # encoding: [0xb3,0xac,0x0f,0x00] #CHECK: clgebr %r0, 0, %f15, 0 # encoding: [0xb3,0xac,0x00,0x0f] @@ -489,6 +671,20 @@ clgxbr %r7, 5, %f8, 9 clgxbr %r15, 0, %f0, 0 +#CHECK: clgxtr %r0, 0, %f0, 0 # encoding: [0xb9,0x4a,0x00,0x00] +#CHECK: clgxtr %r0, 0, %f0, 15 # encoding: [0xb9,0x4a,0x0f,0x00] +#CHECK: clgxtr %r0, 0, %f13, 0 # encoding: [0xb9,0x4a,0x00,0x0d] +#CHECK: clgxtr %r0, 15, %f0, 0 # encoding: [0xb9,0x4a,0xf0,0x00] +#CHECK: clgxtr %r7, 5, %f8, 9 # encoding: [0xb9,0x4a,0x59,0x78] +#CHECK: clgxtr %r15, 0, %f0, 0 # encoding: [0xb9,0x4a,0x00,0xf0] + + clgxtr %r0, 0, %f0, 0 + clgxtr %r0, 0, %f0, 15 + clgxtr %r0, 0, %f13, 0 + clgxtr %r0, 15, %f0, 0 + clgxtr %r7, 5, %f8, 9 + clgxtr %r15, 0, %f0, 0 + #CHECK: clhf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xcf] #CHECK: clhf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xcf] #CHECK: clhf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xcf] @@ -535,6 +731,20 @@ cxfbra %f4, 5, %r9, 10 cxfbra %f13, 0, %r0, 0 +#CHECK: cxftr %f0, 0, %r0, 0 # encoding: [0xb9,0x59,0x00,0x00] +#CHECK: cxftr %f0, 0, %r0, 15 # encoding: [0xb9,0x59,0x0f,0x00] +#CHECK: cxftr %f0, 0, %r15, 0 # encoding: [0xb9,0x59,0x00,0x0f] +#CHECK: cxftr %f0, 15, %r0, 0 # encoding: [0xb9,0x59,0xf0,0x00] +#CHECK: cxftr %f4, 5, %r9, 10 # encoding: [0xb9,0x59,0x5a,0x49] +#CHECK: cxftr %f13, 0, %r0, 0 # encoding: [0xb9,0x59,0x00,0xd0] + + cxftr %f0, 0, %r0, 0 + cxftr %f0, 0, %r0, 15 + cxftr %f0, 0, %r15, 0 + cxftr %f0, 15, %r0, 0 + cxftr %f4, 5, %r9, 10 + cxftr %f13, 0, %r0, 0 + #CHECK: cxgbra %f0, 0, %r0, 0 # encoding: [0xb3,0xa6,0x00,0x00] #CHECK: cxgbra %f0, 0, %r0, 15 # encoding: [0xb3,0xa6,0x0f,0x00] #CHECK: cxgbra %f0, 0, %r15, 0 # encoding: [0xb3,0xa6,0x00,0x0f] @@ -549,6 +759,20 @@ cxgbra %f4, 5, %r9, 10 cxgbra %f13, 0, %r0, 0 +#CHECK: cxgtra %f0, 0, %r0, 0 # encoding: [0xb3,0xf9,0x00,0x00] +#CHECK: cxgtra %f0, 0, %r0, 15 # encoding: [0xb3,0xf9,0x0f,0x00] +#CHECK: cxgtra %f0, 0, %r15, 0 # encoding: [0xb3,0xf9,0x00,0x0f] +#CHECK: cxgtra %f0, 15, %r0, 0 # encoding: [0xb3,0xf9,0xf0,0x00] +#CHECK: cxgtra %f4, 5, %r9, 10 # encoding: [0xb3,0xf9,0x5a,0x49] +#CHECK: cxgtra %f13, 0, %r0, 0 # encoding: [0xb3,0xf9,0x00,0xd0] + + cxgtra %f0, 0, %r0, 0 + cxgtra %f0, 0, %r0, 15 + cxgtra %f0, 0, %r15, 0 + cxgtra %f0, 15, %r0, 0 + cxgtra %f4, 5, %r9, 10 + cxgtra %f13, 0, %r0, 0 + #CHECK: cxlfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x92,0x00,0x00] #CHECK: cxlfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x92,0x0f,0x00] #CHECK: cxlfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x92,0x00,0x0f] @@ -563,6 +787,20 @@ cxlfbr %f4, 5, %r9, 10 cxlfbr %f13, 0, %r0, 0 +#CHECK: cxlftr %f0, 0, %r0, 0 # encoding: [0xb9,0x5b,0x00,0x00] +#CHECK: cxlftr %f0, 0, %r0, 15 # encoding: [0xb9,0x5b,0x0f,0x00] +#CHECK: cxlftr %f0, 0, %r15, 0 # encoding: [0xb9,0x5b,0x00,0x0f] +#CHECK: cxlftr %f0, 15, %r0, 0 # encoding: [0xb9,0x5b,0xf0,0x00] +#CHECK: cxlftr %f4, 5, %r9, 10 # encoding: [0xb9,0x5b,0x5a,0x49] +#CHECK: cxlftr %f13, 0, %r0, 0 # encoding: [0xb9,0x5b,0x00,0xd0] + + cxlftr %f0, 0, %r0, 0 + cxlftr %f0, 0, %r0, 15 + cxlftr %f0, 0, %r15, 0 + cxlftr %f0, 15, %r0, 0 + cxlftr %f4, 5, %r9, 10 + cxlftr %f13, 0, %r0, 0 + #CHECK: cxlgbr %f0, 0, %r0, 0 # encoding: [0xb3,0xa2,0x00,0x00] #CHECK: cxlgbr %f0, 0, %r0, 15 # encoding: [0xb3,0xa2,0x0f,0x00] #CHECK: cxlgbr %f0, 0, %r15, 0 # encoding: [0xb3,0xa2,0x00,0x0f] @@ -577,6 +815,48 @@ cxlgbr %f4, 5, %r9, 10 cxlgbr %f13, 0, %r0, 0 +#CHECK: cxlgtr %f0, 0, %r0, 0 # encoding: [0xb9,0x5a,0x00,0x00] +#CHECK: cxlgtr %f0, 0, %r0, 15 # encoding: [0xb9,0x5a,0x0f,0x00] +#CHECK: cxlgtr %f0, 0, %r15, 0 # encoding: [0xb9,0x5a,0x00,0x0f] +#CHECK: cxlgtr %f0, 15, %r0, 0 # encoding: [0xb9,0x5a,0xf0,0x00] +#CHECK: cxlgtr %f4, 5, %r9, 10 # encoding: [0xb9,0x5a,0x5a,0x49] +#CHECK: cxlgtr %f13, 0, %r0, 0 # encoding: [0xb9,0x5a,0x00,0xd0] + + cxlgtr %f0, 0, %r0, 0 + cxlgtr %f0, 0, %r0, 15 + cxlgtr %f0, 0, %r15, 0 + cxlgtr %f0, 15, %r0, 0 + cxlgtr %f4, 5, %r9, 10 + cxlgtr %f13, 0, %r0, 0 + +#CHECK: ddtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd1,0x00,0x00] +#CHECK: ddtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd1,0x0f,0x00] +#CHECK: ddtra %f0, %f0, %f15, 0 # encoding: [0xb3,0xd1,0xf0,0x00] +#CHECK: ddtra %f0, %f15, %f0, 0 # encoding: [0xb3,0xd1,0x00,0x0f] +#CHECK: ddtra %f15, %f0, %f0, 0 # encoding: [0xb3,0xd1,0x00,0xf0] +#CHECK: ddtra %f7, %f8, %f9, 10 # encoding: [0xb3,0xd1,0x9a,0x78] + + ddtra %f0, %f0, %f0, 0 + ddtra %f0, %f0, %f0, 15 + ddtra %f0, %f0, %f15, 0 + ddtra %f0, %f15, %f0, 0 + ddtra %f15, %f0, %f0, 0 + ddtra %f7, %f8, %f9, 10 + +#CHECK: dxtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd9,0x00,0x00] +#CHECK: dxtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd9,0x0f,0x00] +#CHECK: dxtra %f0, %f0, %f13, 0 # encoding: [0xb3,0xd9,0xd0,0x00] +#CHECK: dxtra %f0, %f13, %f0, 0 # encoding: [0xb3,0xd9,0x00,0x0d] +#CHECK: dxtra %f13, %f0, %f0, 0 # encoding: [0xb3,0xd9,0x00,0xd0] +#CHECK: dxtra %f8, %f8, %f8, 8 # encoding: [0xb3,0xd9,0x88,0x88] + + dxtra %f0, %f0, %f0, 0 + dxtra %f0, %f0, %f0, 15 + dxtra %f0, %f0, %f13, 0 + dxtra %f0, %f13, %f0, 0 + dxtra %f13, %f0, %f0, 0 + dxtra %f8, %f8, %f8, 8 + #CHECK: fidbra %f0, 0, %f0, 0 # encoding: [0xb3,0x5f,0x00,0x00] #CHECK: fidbra %f0, 0, %f0, 15 # encoding: [0xb3,0x5f,0x0f,0x00] #CHECK: fidbra %f0, 0, %f15, 0 # encoding: [0xb3,0x5f,0x00,0x0f] @@ -1285,6 +1565,34 @@ lpdg %r2, 0(%r1), 1(%r15) lpdg %r2, 0(%r1), 4095(%r15) +#CHECK: mdtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd0,0x00,0x00] +#CHECK: mdtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd0,0x0f,0x00] +#CHECK: mdtra %f0, %f0, %f15, 0 # encoding: [0xb3,0xd0,0xf0,0x00] +#CHECK: mdtra %f0, %f15, %f0, 0 # encoding: [0xb3,0xd0,0x00,0x0f] +#CHECK: mdtra %f15, %f0, %f0, 0 # encoding: [0xb3,0xd0,0x00,0xf0] +#CHECK: mdtra %f7, %f8, %f9, 10 # encoding: [0xb3,0xd0,0x9a,0x78] + + mdtra %f0, %f0, %f0, 0 + mdtra %f0, %f0, %f0, 15 + mdtra %f0, %f0, %f15, 0 + mdtra %f0, %f15, %f0, 0 + mdtra %f15, %f0, %f0, 0 + mdtra %f7, %f8, %f9, 10 + +#CHECK: mxtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd8,0x00,0x00] +#CHECK: mxtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd8,0x0f,0x00] +#CHECK: mxtra %f0, %f0, %f13, 0 # encoding: [0xb3,0xd8,0xd0,0x00] +#CHECK: mxtra %f0, %f13, %f0, 0 # encoding: [0xb3,0xd8,0x00,0x0d] +#CHECK: mxtra %f13, %f0, %f0, 0 # encoding: [0xb3,0xd8,0x00,0xd0] +#CHECK: mxtra %f8, %f8, %f8, 8 # encoding: [0xb3,0xd8,0x88,0x88] + + mxtra %f0, %f0, %f0, 0 + mxtra %f0, %f0, %f0, 15 + mxtra %f0, %f0, %f13, 0 + mxtra %f0, %f13, %f0, 0 + mxtra %f13, %f0, %f0, 0 + mxtra %f8, %f8, %f8, 8 + #CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00] #CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00] #CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f] @@ -1379,6 +1687,20 @@ risblg %r15,%r0,0,0,0 risblg %r4,%r5,6,7,8 +#CHECK: sdtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd3,0x00,0x00] +#CHECK: sdtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd3,0x0f,0x00] +#CHECK: sdtra %f0, %f0, %f15, 0 # encoding: [0xb3,0xd3,0xf0,0x00] +#CHECK: sdtra %f0, %f15, %f0, 0 # encoding: [0xb3,0xd3,0x00,0x0f] +#CHECK: sdtra %f15, %f0, %f0, 0 # encoding: [0xb3,0xd3,0x00,0xf0] +#CHECK: sdtra %f7, %f8, %f9, 10 # encoding: [0xb3,0xd3,0x9a,0x78] + + sdtra %f0, %f0, %f0, 0 + sdtra %f0, %f0, %f0, 15 + sdtra %f0, %f0, %f15, 0 + sdtra %f0, %f15, %f0, 0 + sdtra %f15, %f0, %f0, 0 + sdtra %f7, %f8, %f9, 10 + #CHECK: sgrk %r0, %r0, %r0 # encoding: [0xb9,0xe9,0x00,0x00] #CHECK: sgrk %r0, %r0, %r15 # encoding: [0xb9,0xe9,0xf0,0x00] #CHECK: sgrk %r0, %r15, %r0 # encoding: [0xb9,0xe9,0x00,0x0f] @@ -1731,6 +2053,20 @@ stocgnp %r1,2(%r3) stocgno %r1,2(%r3) +#CHECK: sxtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xdb,0x00,0x00] +#CHECK: sxtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xdb,0x0f,0x00] +#CHECK: sxtra %f0, %f0, %f13, 0 # encoding: [0xb3,0xdb,0xd0,0x00] +#CHECK: sxtra %f0, %f13, %f0, 0 # encoding: [0xb3,0xdb,0x00,0x0d] +#CHECK: sxtra %f13, %f0, %f0, 0 # encoding: [0xb3,0xdb,0x00,0xd0] +#CHECK: sxtra %f8, %f8, %f8, 8 # encoding: [0xb3,0xdb,0x88,0x88] + + sxtra %f0, %f0, %f0, 0 + sxtra %f0, %f0, %f0, 15 + sxtra %f0, %f0, %f13, 0 + sxtra %f0, %f13, %f0, 0 + sxtra %f13, %f0, %f0, 0 + sxtra %f8, %f8, %f8, 8 + #CHECK: xgrk %r0, %r0, %r0 # encoding: [0xb9,0xe7,0x00,0x00] #CHECK: xgrk %r0, %r0, %r15 # encoding: [0xb9,0xe7,0xf0,0x00] #CHECK: xgrk %r0, %r15, %r0 # encoding: [0xb9,0xe7,0x00,0x0f] diff --git a/test/MC/SystemZ/insn-good-zEC12.s b/test/MC/SystemZ/insn-good-zEC12.s index 275d68d8a619a..2fe6c46ad908b 100644 --- a/test/MC/SystemZ/insn-good-zEC12.s +++ b/test/MC/SystemZ/insn-good-zEC12.s @@ -114,6 +114,26 @@ bprp 8, branch, target@plt bprp 9, branch@plt, target@plt +#CHECK: cdzt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xaa] +#CHECK: cdzt %f15, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0xaa] +#CHECK: cdzt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xaa] +#CHECK: cdzt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xaa] +#CHECK: cdzt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xaa] +#CHECK: cdzt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xaa] +#CHECK: cdzt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xaa] +#CHECK: cdzt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xaa] +#CHECK: cdzt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xaa] + + cdzt %f0, 0(1), 0 + cdzt %f15, 0(1), 0 + cdzt %f0, 0(1), 15 + cdzt %f0, 0(1,%r1), 0 + cdzt %f0, 0(1,%r15), 0 + cdzt %f0, 4095(1,%r1), 0 + cdzt %f0, 4095(1,%r15), 0 + cdzt %f0, 0(256,%r1), 0 + cdzt %f0, 0(256,%r15), 0 + #CHECK: clt %r0, 12, -524288 # encoding: [0xeb,0x0c,0x00,0x00,0x80,0x23] #CHECK: clt %r0, 12, -1 # encoding: [0xeb,0x0c,0x0f,0xff,0xff,0x23] #CHECK: clt %r0, 12, 0 # encoding: [0xeb,0x0c,0x00,0x00,0x00,0x23] @@ -178,6 +198,66 @@ clgtnl %r0, 0(%r15) clgtnh %r0, 0(%r15) +#CHECK: cxzt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xab] +#CHECK: cxzt %f13, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0xab] +#CHECK: cxzt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xab] +#CHECK: cxzt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xab] +#CHECK: cxzt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xab] +#CHECK: cxzt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xab] +#CHECK: cxzt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xab] +#CHECK: cxzt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xab] +#CHECK: cxzt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xab] + + cxzt %f0, 0(1), 0 + cxzt %f13, 0(1), 0 + cxzt %f0, 0(1), 15 + cxzt %f0, 0(1,%r1), 0 + cxzt %f0, 0(1,%r15), 0 + cxzt %f0, 4095(1,%r1), 0 + cxzt %f0, 4095(1,%r15), 0 + cxzt %f0, 0(256,%r1), 0 + cxzt %f0, 0(256,%r15), 0 + +#CHECK: czdt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xa8] +#CHECK: czdt %f15, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0xa8] +#CHECK: czdt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xa8] +#CHECK: czdt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xa8] +#CHECK: czdt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xa8] +#CHECK: czdt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xa8] +#CHECK: czdt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xa8] +#CHECK: czdt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xa8] +#CHECK: czdt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xa8] + + czdt %f0, 0(1), 0 + czdt %f15, 0(1), 0 + czdt %f0, 0(1), 15 + czdt %f0, 0(1,%r1), 0 + czdt %f0, 0(1,%r15), 0 + czdt %f0, 4095(1,%r1), 0 + czdt %f0, 4095(1,%r15), 0 + czdt %f0, 0(256,%r1), 0 + czdt %f0, 0(256,%r15), 0 + +#CHECK: czxt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xa9] +#CHECK: czxt %f13, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0xa9] +#CHECK: czxt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xa9] +#CHECK: czxt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xa9] +#CHECK: czxt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xa9] +#CHECK: czxt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xa9] +#CHECK: czxt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xa9] +#CHECK: czxt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xa9] +#CHECK: czxt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xa9] + + czxt %f0, 0(1), 0 + czxt %f13, 0(1), 0 + czxt %f0, 0(1), 15 + czxt %f0, 0(1,%r1), 0 + czxt %f0, 0(1,%r15), 0 + czxt %f0, 4095(1,%r1), 0 + czxt %f0, 4095(1,%r15), 0 + czxt %f0, 0(256,%r1), 0 + czxt %f0, 0(256,%r15), 0 + #CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00] #CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0] #CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70] diff --git a/test/MC/SystemZ/insn-good.s b/test/MC/SystemZ/insn-good.s index a6228f23c8f8e..73162e4eea712 100644 --- a/test/MC/SystemZ/insn-good.s +++ b/test/MC/SystemZ/insn-good.s @@ -17,6 +17,22 @@ a %r0, 4095(%r15,%r1) a %r15, 0 +#CHECK: ad %f0, 0 # encoding: [0x6a,0x00,0x00,0x00] +#CHECK: ad %f0, 4095 # encoding: [0x6a,0x00,0x0f,0xff] +#CHECK: ad %f0, 0(%r1) # encoding: [0x6a,0x00,0x10,0x00] +#CHECK: ad %f0, 0(%r15) # encoding: [0x6a,0x00,0xf0,0x00] +#CHECK: ad %f0, 4095(%r1,%r15) # encoding: [0x6a,0x01,0xff,0xff] +#CHECK: ad %f0, 4095(%r15,%r1) # encoding: [0x6a,0x0f,0x1f,0xff] +#CHECK: ad %f15, 0 # encoding: [0x6a,0xf0,0x00,0x00] + + ad %f0, 0 + ad %f0, 4095 + ad %f0, 0(%r1) + ad %f0, 0(%r15) + ad %f0, 4095(%r1,%r15) + ad %f0, 4095(%r15,%r1) + ad %f15, 0 + #CHECK: adb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1a] #CHECK: adb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1a] #CHECK: adb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1a] @@ -43,6 +59,44 @@ adbr %f7, %f8 adbr %f15, %f0 +#CHECK: adr %f0, %f0 # encoding: [0x2a,0x00] +#CHECK: adr %f0, %f15 # encoding: [0x2a,0x0f] +#CHECK: adr %f7, %f8 # encoding: [0x2a,0x78] +#CHECK: adr %f15, %f0 # encoding: [0x2a,0xf0] + + adr %f0, %f0 + adr %f0, %f15 + adr %f7, %f8 + adr %f15, %f0 + +#CHECK: adtr %f0, %f0, %f0 # encoding: [0xb3,0xd2,0x00,0x00] +#CHECK: adtr %f0, %f0, %f15 # encoding: [0xb3,0xd2,0xf0,0x00] +#CHECK: adtr %f0, %f15, %f0 # encoding: [0xb3,0xd2,0x00,0x0f] +#CHECK: adtr %f15, %f0, %f0 # encoding: [0xb3,0xd2,0x00,0xf0] +#CHECK: adtr %f7, %f8, %f9 # encoding: [0xb3,0xd2,0x90,0x78] + + adtr %f0, %f0, %f0 + adtr %f0, %f0, %f15 + adtr %f0, %f15, %f0 + adtr %f15, %f0, %f0 + adtr %f7, %f8, %f9 + +#CHECK: ae %f0, 0 # encoding: [0x7a,0x00,0x00,0x00] +#CHECK: ae %f0, 4095 # encoding: [0x7a,0x00,0x0f,0xff] +#CHECK: ae %f0, 0(%r1) # encoding: [0x7a,0x00,0x10,0x00] +#CHECK: ae %f0, 0(%r15) # encoding: [0x7a,0x00,0xf0,0x00] +#CHECK: ae %f0, 4095(%r1,%r15) # encoding: [0x7a,0x01,0xff,0xff] +#CHECK: ae %f0, 4095(%r15,%r1) # encoding: [0x7a,0x0f,0x1f,0xff] +#CHECK: ae %f15, 0 # encoding: [0x7a,0xf0,0x00,0x00] + + ae %f0, 0 + ae %f0, 4095 + ae %f0, 0(%r1) + ae %f0, 0(%r15) + ae %f0, 4095(%r1,%r15) + ae %f0, 4095(%r15,%r1) + ae %f15, 0 + #CHECK: aeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0a] #CHECK: aeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0a] #CHECK: aeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0a] @@ -69,6 +123,16 @@ aebr %f7, %f8 aebr %f15, %f0 +#CHECK: aer %f0, %f0 # encoding: [0x3a,0x00] +#CHECK: aer %f0, %f15 # encoding: [0x3a,0x0f] +#CHECK: aer %f7, %f8 # encoding: [0x3a,0x78] +#CHECK: aer %f15, %f0 # encoding: [0x3a,0xf0] + + aer %f0, %f0 + aer %f0, %f15 + aer %f7, %f8 + aer %f15, %f0 + #CHECK: afi %r0, -2147483648 # encoding: [0xc2,0x09,0x80,0x00,0x00,0x00] #CHECK: afi %r0, -1 # encoding: [0xc2,0x09,0xff,0xff,0xff,0xff] #CHECK: afi %r0, 0 # encoding: [0xc2,0x09,0x00,0x00,0x00,0x00] @@ -571,6 +635,58 @@ asi 524287(%r1), 42 asi 524287(%r15), 42 +#CHECK: au %f0, 0 # encoding: [0x7e,0x00,0x00,0x00] +#CHECK: au %f0, 4095 # encoding: [0x7e,0x00,0x0f,0xff] +#CHECK: au %f0, 0(%r1) # encoding: [0x7e,0x00,0x10,0x00] +#CHECK: au %f0, 0(%r15) # encoding: [0x7e,0x00,0xf0,0x00] +#CHECK: au %f0, 4095(%r1,%r15) # encoding: [0x7e,0x01,0xff,0xff] +#CHECK: au %f0, 4095(%r15,%r1) # encoding: [0x7e,0x0f,0x1f,0xff] +#CHECK: au %f15, 0 # encoding: [0x7e,0xf0,0x00,0x00] + + au %f0, 0 + au %f0, 4095 + au %f0, 0(%r1) + au %f0, 0(%r15) + au %f0, 4095(%r1,%r15) + au %f0, 4095(%r15,%r1) + au %f15, 0 + +#CHECK: aur %f0, %f0 # encoding: [0x3e,0x00] +#CHECK: aur %f0, %f15 # encoding: [0x3e,0x0f] +#CHECK: aur %f7, %f8 # encoding: [0x3e,0x78] +#CHECK: aur %f15, %f0 # encoding: [0x3e,0xf0] + + aur %f0, %f0 + aur %f0, %f15 + aur %f7, %f8 + aur %f15, %f0 + +#CHECK: aw %f0, 0 # encoding: [0x6e,0x00,0x00,0x00] +#CHECK: aw %f0, 4095 # encoding: [0x6e,0x00,0x0f,0xff] +#CHECK: aw %f0, 0(%r1) # encoding: [0x6e,0x00,0x10,0x00] +#CHECK: aw %f0, 0(%r15) # encoding: [0x6e,0x00,0xf0,0x00] +#CHECK: aw %f0, 4095(%r1,%r15) # encoding: [0x6e,0x01,0xff,0xff] +#CHECK: aw %f0, 4095(%r15,%r1) # encoding: [0x6e,0x0f,0x1f,0xff] +#CHECK: aw %f15, 0 # encoding: [0x6e,0xf0,0x00,0x00] + + aw %f0, 0 + aw %f0, 4095 + aw %f0, 0(%r1) + aw %f0, 0(%r15) + aw %f0, 4095(%r1,%r15) + aw %f0, 4095(%r15,%r1) + aw %f15, 0 + +#CHECK: awr %f0, %f0 # encoding: [0x2e,0x00] +#CHECK: awr %f0, %f15 # encoding: [0x2e,0x0f] +#CHECK: awr %f7, %f8 # encoding: [0x2e,0x78] +#CHECK: awr %f15, %f0 # encoding: [0x2e,0xf0] + + awr %f0, %f0 + awr %f0, %f15 + awr %f7, %f8 + awr %f15, %f0 + #CHECK: axbr %f0, %f0 # encoding: [0xb3,0x4a,0x00,0x00] #CHECK: axbr %f0, %f13 # encoding: [0xb3,0x4a,0x00,0x0d] #CHECK: axbr %f8, %f8 # encoding: [0xb3,0x4a,0x00,0x88] @@ -581,6 +697,28 @@ axbr %f8, %f8 axbr %f13, %f0 +#CHECK: axr %f0, %f0 # encoding: [0x36,0x00] +#CHECK: axr %f0, %f13 # encoding: [0x36,0x0d] +#CHECK: axr %f8, %f8 # encoding: [0x36,0x88] +#CHECK: axr %f13, %f0 # encoding: [0x36,0xd0] + + axr %f0, %f0 + axr %f0, %f13 + axr %f8, %f8 + axr %f13, %f0 + +#CHECK: axtr %f0, %f0, %f0 # encoding: [0xb3,0xda,0x00,0x00] +#CHECK: axtr %f0, %f0, %f13 # encoding: [0xb3,0xda,0xd0,0x00] +#CHECK: axtr %f0, %f13, %f0 # encoding: [0xb3,0xda,0x00,0x0d] +#CHECK: axtr %f13, %f0, %f0 # encoding: [0xb3,0xda,0x00,0xd0] +#CHECK: axtr %f8, %f8, %f8 # encoding: [0xb3,0xda,0x80,0x88] + + axtr %f0, %f0, %f0 + axtr %f0, %f0, %f13 + axtr %f0, %f13, %f0 + axtr %f13, %f0, %f0 + axtr %f8, %f8, %f8 + #CHECK: ay %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5a] #CHECK: ay %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5a] #CHECK: ay %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5a] @@ -1885,6 +2023,22 @@ c %r0, 4095(%r15,%r1) c %r15, 0 +#CHECK: cd %f0, 0 # encoding: [0x69,0x00,0x00,0x00] +#CHECK: cd %f0, 4095 # encoding: [0x69,0x00,0x0f,0xff] +#CHECK: cd %f0, 0(%r1) # encoding: [0x69,0x00,0x10,0x00] +#CHECK: cd %f0, 0(%r15) # encoding: [0x69,0x00,0xf0,0x00] +#CHECK: cd %f0, 4095(%r1,%r15) # encoding: [0x69,0x01,0xff,0xff] +#CHECK: cd %f0, 4095(%r15,%r1) # encoding: [0x69,0x0f,0x1f,0xff] +#CHECK: cd %f15, 0 # encoding: [0x69,0xf0,0x00,0x00] + + cd %f0, 0 + cd %f0, 4095 + cd %f0, 0(%r1) + cd %f0, 0(%r15) + cd %f0, 4095(%r1,%r15) + cd %f0, 4095(%r15,%r1) + cd %f15, 0 + #CHECK: cdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x19] #CHECK: cdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x19] #CHECK: cdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x19] @@ -1923,6 +2077,18 @@ cdfbr %f7, %r8 cdfbr %f15, %r15 +#CHECK: cdfr %f0, %r0 # encoding: [0xb3,0xb5,0x00,0x00] +#CHECK: cdfr %f0, %r15 # encoding: [0xb3,0xb5,0x00,0x0f] +#CHECK: cdfr %f15, %r0 # encoding: [0xb3,0xb5,0x00,0xf0] +#CHECK: cdfr %f7, %r8 # encoding: [0xb3,0xb5,0x00,0x78] +#CHECK: cdfr %f15, %r15 # encoding: [0xb3,0xb5,0x00,0xff] + + cdfr %f0, %r0 + cdfr %f0, %r15 + cdfr %f15, %r0 + cdfr %f7, %r8 + cdfr %f15, %r15 + #CHECK: cdgbr %f0, %r0 # encoding: [0xb3,0xa5,0x00,0x00] #CHECK: cdgbr %f0, %r15 # encoding: [0xb3,0xa5,0x00,0x0f] #CHECK: cdgbr %f15, %r0 # encoding: [0xb3,0xa5,0x00,0xf0] @@ -1935,6 +2101,40 @@ cdgbr %f7, %r8 cdgbr %f15, %r15 +#CHECK: cdgr %f0, %r0 # encoding: [0xb3,0xc5,0x00,0x00] +#CHECK: cdgr %f0, %r15 # encoding: [0xb3,0xc5,0x00,0x0f] +#CHECK: cdgr %f15, %r0 # encoding: [0xb3,0xc5,0x00,0xf0] +#CHECK: cdgr %f7, %r8 # encoding: [0xb3,0xc5,0x00,0x78] +#CHECK: cdgr %f15, %r15 # encoding: [0xb3,0xc5,0x00,0xff] + + cdgr %f0, %r0 + cdgr %f0, %r15 + cdgr %f15, %r0 + cdgr %f7, %r8 + cdgr %f15, %r15 + +#CHECK: cdgtr %f0, %r0 # encoding: [0xb3,0xf1,0x00,0x00] +#CHECK: cdgtr %f0, %r15 # encoding: [0xb3,0xf1,0x00,0x0f] +#CHECK: cdgtr %f15, %r0 # encoding: [0xb3,0xf1,0x00,0xf0] +#CHECK: cdgtr %f7, %r8 # encoding: [0xb3,0xf1,0x00,0x78] +#CHECK: cdgtr %f15, %r15 # encoding: [0xb3,0xf1,0x00,0xff] + + cdgtr %f0, %r0 + cdgtr %f0, %r15 + cdgtr %f15, %r0 + cdgtr %f7, %r8 + cdgtr %f15, %r15 + +#CHECK: cdr %f0, %f0 # encoding: [0x29,0x00] +#CHECK: cdr %f0, %f15 # encoding: [0x29,0x0f] +#CHECK: cdr %f7, %f8 # encoding: [0x29,0x78] +#CHECK: cdr %f15, %f0 # encoding: [0x29,0xf0] + + cdr %f0, %f0 + cdr %f0, %f15 + cdr %f7, %f8 + cdr %f15, %f0 + #CHECK: cds %r0, %r0, 0 # encoding: [0xbb,0x00,0x00,0x00] #CHECK: cds %r0, %r0, 4095 # encoding: [0xbb,0x00,0x0f,0xff] #CHECK: cds %r0, %r0, 0(%r1) # encoding: [0xbb,0x00,0x10,0x00] @@ -1977,6 +2177,18 @@ cdsg %r0, %r14, 0 cdsg %r14, %r0, 0 +#CHECK: cdstr %f0, %r0 # encoding: [0xb3,0xf3,0x00,0x00] +#CHECK: cdstr %f0, %r15 # encoding: [0xb3,0xf3,0x00,0x0f] +#CHECK: cdstr %f15, %r0 # encoding: [0xb3,0xf3,0x00,0xf0] +#CHECK: cdstr %f7, %r8 # encoding: [0xb3,0xf3,0x00,0x78] +#CHECK: cdstr %f15, %r15 # encoding: [0xb3,0xf3,0x00,0xff] + + cdstr %f0, %r0 + cdstr %f0, %r15 + cdstr %f15, %r0 + cdstr %f7, %r8 + cdstr %f15, %r15 + #CHECK: cdsy %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x31] #CHECK: cdsy %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x31] #CHECK: cdsy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x31] @@ -2001,6 +2213,44 @@ cdsy %r0, %r14, 0 cdsy %r14, %r0, 0 +#CHECK: cdtr %f0, %f0 # encoding: [0xb3,0xe4,0x00,0x00] +#CHECK: cdtr %f0, %f15 # encoding: [0xb3,0xe4,0x00,0x0f] +#CHECK: cdtr %f7, %f8 # encoding: [0xb3,0xe4,0x00,0x78] +#CHECK: cdtr %f15, %f0 # encoding: [0xb3,0xe4,0x00,0xf0] + + cdtr %f0, %f0 + cdtr %f0, %f15 + cdtr %f7, %f8 + cdtr %f15, %f0 + +#CHECK: cdutr %f0, %r0 # encoding: [0xb3,0xf2,0x00,0x00] +#CHECK: cdutr %f0, %r15 # encoding: [0xb3,0xf2,0x00,0x0f] +#CHECK: cdutr %f15, %r0 # encoding: [0xb3,0xf2,0x00,0xf0] +#CHECK: cdutr %f7, %r8 # encoding: [0xb3,0xf2,0x00,0x78] +#CHECK: cdutr %f15, %r15 # encoding: [0xb3,0xf2,0x00,0xff] + + cdutr %f0, %r0 + cdutr %f0, %r15 + cdutr %f15, %r0 + cdutr %f7, %r8 + cdutr %f15, %r15 + +#CHECK: ce %f0, 0 # encoding: [0x79,0x00,0x00,0x00] +#CHECK: ce %f0, 4095 # encoding: [0x79,0x00,0x0f,0xff] +#CHECK: ce %f0, 0(%r1) # encoding: [0x79,0x00,0x10,0x00] +#CHECK: ce %f0, 0(%r15) # encoding: [0x79,0x00,0xf0,0x00] +#CHECK: ce %f0, 4095(%r1,%r15) # encoding: [0x79,0x01,0xff,0xff] +#CHECK: ce %f0, 4095(%r15,%r1) # encoding: [0x79,0x0f,0x1f,0xff] +#CHECK: ce %f15, 0 # encoding: [0x79,0xf0,0x00,0x00] + + ce %f0, 0 + ce %f0, 4095 + ce %f0, 0(%r1) + ce %f0, 0(%r15) + ce %f0, 4095(%r1,%r15) + ce %f0, 4095(%r15,%r1) + ce %f15, 0 + #CHECK: ceb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x09] #CHECK: ceb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x09] #CHECK: ceb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x09] @@ -2027,6 +2277,16 @@ cebr %f7, %f8 cebr %f15, %f0 +#CHECK: cedtr %f0, %f0 # encoding: [0xb3,0xf4,0x00,0x00] +#CHECK: cedtr %f0, %f15 # encoding: [0xb3,0xf4,0x00,0x0f] +#CHECK: cedtr %f7, %f8 # encoding: [0xb3,0xf4,0x00,0x78] +#CHECK: cedtr %f15, %f0 # encoding: [0xb3,0xf4,0x00,0xf0] + + cedtr %f0, %f0 + cedtr %f0, %f15 + cedtr %f7, %f8 + cedtr %f15, %f0 + #CHECK: cefbr %f0, %r0 # encoding: [0xb3,0x94,0x00,0x00] #CHECK: cefbr %f0, %r15 # encoding: [0xb3,0x94,0x00,0x0f] #CHECK: cefbr %f15, %r0 # encoding: [0xb3,0x94,0x00,0xf0] @@ -2039,6 +2299,18 @@ cefbr %f7, %r8 cefbr %f15, %r15 +#CHECK: cefr %f0, %r0 # encoding: [0xb3,0xb4,0x00,0x00] +#CHECK: cefr %f0, %r15 # encoding: [0xb3,0xb4,0x00,0x0f] +#CHECK: cefr %f15, %r0 # encoding: [0xb3,0xb4,0x00,0xf0] +#CHECK: cefr %f7, %r8 # encoding: [0xb3,0xb4,0x00,0x78] +#CHECK: cefr %f15, %r15 # encoding: [0xb3,0xb4,0x00,0xff] + + cefr %f0, %r0 + cefr %f0, %r15 + cefr %f15, %r0 + cefr %f7, %r8 + cefr %f15, %r15 + #CHECK: cegbr %f0, %r0 # encoding: [0xb3,0xa4,0x00,0x00] #CHECK: cegbr %f0, %r15 # encoding: [0xb3,0xa4,0x00,0x0f] #CHECK: cegbr %f15, %r0 # encoding: [0xb3,0xa4,0x00,0xf0] @@ -2051,6 +2323,38 @@ cegbr %f7, %r8 cegbr %f15, %r15 +#CHECK: cegr %f0, %r0 # encoding: [0xb3,0xc4,0x00,0x00] +#CHECK: cegr %f0, %r15 # encoding: [0xb3,0xc4,0x00,0x0f] +#CHECK: cegr %f15, %r0 # encoding: [0xb3,0xc4,0x00,0xf0] +#CHECK: cegr %f7, %r8 # encoding: [0xb3,0xc4,0x00,0x78] +#CHECK: cegr %f15, %r15 # encoding: [0xb3,0xc4,0x00,0xff] + + cegr %f0, %r0 + cegr %f0, %r15 + cegr %f15, %r0 + cegr %f7, %r8 + cegr %f15, %r15 + +#CHECK: cer %f0, %f0 # encoding: [0x39,0x00] +#CHECK: cer %f0, %f15 # encoding: [0x39,0x0f] +#CHECK: cer %f7, %f8 # encoding: [0x39,0x78] +#CHECK: cer %f15, %f0 # encoding: [0x39,0xf0] + + cer %f0, %f0 + cer %f0, %f15 + cer %f7, %f8 + cer %f15, %f0 + +#CHECK: cextr %f0, %f0 # encoding: [0xb3,0xfc,0x00,0x00] +#CHECK: cextr %f0, %f13 # encoding: [0xb3,0xfc,0x00,0x0d] +#CHECK: cextr %f8, %f8 # encoding: [0xb3,0xfc,0x00,0x88] +#CHECK: cextr %f13, %f0 # encoding: [0xb3,0xfc,0x00,0xd0] + + cextr %f0, %f0 + cextr %f0, %f13 + cextr %f8, %f8 + cextr %f13, %f0 + #CHECK: cfc 0 # encoding: [0xb2,0x1a,0x00,0x00] #CHECK: cfc 0(%r1) # encoding: [0xb2,0x1a,0x10,0x00] #CHECK: cfc 0(%r15) # encoding: [0xb2,0x1a,0xf0,0x00] @@ -2077,6 +2381,18 @@ cfdbr %r4, 5, %f6 cfdbr %r15, 0, %f0 +#CHECK: cfdr %r0, 0, %f0 # encoding: [0xb3,0xb9,0x00,0x00] +#CHECK: cfdr %r0, 0, %f15 # encoding: [0xb3,0xb9,0x00,0x0f] +#CHECK: cfdr %r0, 15, %f0 # encoding: [0xb3,0xb9,0xf0,0x00] +#CHECK: cfdr %r4, 5, %f6 # encoding: [0xb3,0xb9,0x50,0x46] +#CHECK: cfdr %r15, 0, %f0 # encoding: [0xb3,0xb9,0x00,0xf0] + + cfdr %r0, 0, %f0 + cfdr %r0, 0, %f15 + cfdr %r0, 15, %f0 + cfdr %r4, 5, %f6 + cfdr %r15, 0, %f0 + #CHECK: cfebr %r0, 0, %f0 # encoding: [0xb3,0x98,0x00,0x00] #CHECK: cfebr %r0, 0, %f15 # encoding: [0xb3,0x98,0x00,0x0f] #CHECK: cfebr %r0, 15, %f0 # encoding: [0xb3,0x98,0xf0,0x00] @@ -2089,6 +2405,18 @@ cfebr %r4, 5, %f6 cfebr %r15, 0, %f0 +#CHECK: cfer %r0, 0, %f0 # encoding: [0xb3,0xb8,0x00,0x00] +#CHECK: cfer %r0, 0, %f15 # encoding: [0xb3,0xb8,0x00,0x0f] +#CHECK: cfer %r0, 15, %f0 # encoding: [0xb3,0xb8,0xf0,0x00] +#CHECK: cfer %r4, 5, %f6 # encoding: [0xb3,0xb8,0x50,0x46] +#CHECK: cfer %r15, 0, %f0 # encoding: [0xb3,0xb8,0x00,0xf0] + + cfer %r0, 0, %f0 + cfer %r0, 0, %f15 + cfer %r0, 15, %f0 + cfer %r4, 5, %f6 + cfer %r15, 0, %f0 + #CHECK: cfi %r0, -2147483648 # encoding: [0xc2,0x0d,0x80,0x00,0x00,0x00] #CHECK: cfi %r0, -1 # encoding: [0xc2,0x0d,0xff,0xff,0xff,0xff] #CHECK: cfi %r0, 0 # encoding: [0xc2,0x0d,0x00,0x00,0x00,0x00] @@ -2115,6 +2443,18 @@ cfxbr %r4, 5, %f8 cfxbr %r15, 0, %f0 +#CHECK: cfxr %r0, 0, %f0 # encoding: [0xb3,0xba,0x00,0x00] +#CHECK: cfxr %r0, 0, %f13 # encoding: [0xb3,0xba,0x00,0x0d] +#CHECK: cfxr %r0, 15, %f0 # encoding: [0xb3,0xba,0xf0,0x00] +#CHECK: cfxr %r4, 5, %f8 # encoding: [0xb3,0xba,0x50,0x48] +#CHECK: cfxr %r15, 0, %f0 # encoding: [0xb3,0xba,0x00,0xf0] + + cfxr %r0, 0, %f0 + cfxr %r0, 0, %f13 + cfxr %r0, 15, %f0 + cfxr %r4, 5, %f8 + cfxr %r15, 0, %f0 + #CHECK: cg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x20] #CHECK: cg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x20] #CHECK: cg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x20] @@ -2149,6 +2489,30 @@ cgdbr %r4, 5, %f6 cgdbr %r15, 0, %f0 +#CHECK: cgdr %r0, 0, %f0 # encoding: [0xb3,0xc9,0x00,0x00] +#CHECK: cgdr %r0, 0, %f15 # encoding: [0xb3,0xc9,0x00,0x0f] +#CHECK: cgdr %r0, 15, %f0 # encoding: [0xb3,0xc9,0xf0,0x00] +#CHECK: cgdr %r4, 5, %f6 # encoding: [0xb3,0xc9,0x50,0x46] +#CHECK: cgdr %r15, 0, %f0 # encoding: [0xb3,0xc9,0x00,0xf0] + + cgdr %r0, 0, %f0 + cgdr %r0, 0, %f15 + cgdr %r0, 15, %f0 + cgdr %r4, 5, %f6 + cgdr %r15, 0, %f0 + +#CHECK: cgdtr %r0, 0, %f0 # encoding: [0xb3,0xe1,0x00,0x00] +#CHECK: cgdtr %r0, 0, %f15 # encoding: [0xb3,0xe1,0x00,0x0f] +#CHECK: cgdtr %r0, 15, %f0 # encoding: [0xb3,0xe1,0xf0,0x00] +#CHECK: cgdtr %r4, 5, %f6 # encoding: [0xb3,0xe1,0x50,0x46] +#CHECK: cgdtr %r15, 0, %f0 # encoding: [0xb3,0xe1,0x00,0xf0] + + cgdtr %r0, 0, %f0 + cgdtr %r0, 0, %f15 + cgdtr %r0, 15, %f0 + cgdtr %r4, 5, %f6 + cgdtr %r15, 0, %f0 + #CHECK: cgebr %r0, 0, %f0 # encoding: [0xb3,0xa8,0x00,0x00] #CHECK: cgebr %r0, 0, %f15 # encoding: [0xb3,0xa8,0x00,0x0f] #CHECK: cgebr %r0, 15, %f0 # encoding: [0xb3,0xa8,0xf0,0x00] @@ -2161,6 +2525,18 @@ cgebr %r4, 5, %f6 cgebr %r15, 0, %f0 +#CHECK: cger %r0, 0, %f0 # encoding: [0xb3,0xc8,0x00,0x00] +#CHECK: cger %r0, 0, %f15 # encoding: [0xb3,0xc8,0x00,0x0f] +#CHECK: cger %r0, 15, %f0 # encoding: [0xb3,0xc8,0xf0,0x00] +#CHECK: cger %r4, 5, %f6 # encoding: [0xb3,0xc8,0x50,0x46] +#CHECK: cger %r15, 0, %f0 # encoding: [0xb3,0xc8,0x00,0xf0] + + cger %r0, 0, %f0 + cger %r0, 0, %f15 + cger %r0, 15, %f0 + cger %r4, 5, %f6 + cger %r15, 0, %f0 + #CHECK: cgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x30] #CHECK: cgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x30] #CHECK: cgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x30] @@ -3063,6 +3439,30 @@ cgxbr %r4, 5, %f8 cgxbr %r15, 0, %f0 +#CHECK: cgxr %r0, 0, %f0 # encoding: [0xb3,0xca,0x00,0x00] +#CHECK: cgxr %r0, 0, %f13 # encoding: [0xb3,0xca,0x00,0x0d] +#CHECK: cgxr %r0, 15, %f0 # encoding: [0xb3,0xca,0xf0,0x00] +#CHECK: cgxr %r4, 5, %f8 # encoding: [0xb3,0xca,0x50,0x48] +#CHECK: cgxr %r15, 0, %f0 # encoding: [0xb3,0xca,0x00,0xf0] + + cgxr %r0, 0, %f0 + cgxr %r0, 0, %f13 + cgxr %r0, 15, %f0 + cgxr %r4, 5, %f8 + cgxr %r15, 0, %f0 + +#CHECK: cgxtr %r0, 0, %f0 # encoding: [0xb3,0xe9,0x00,0x00] +#CHECK: cgxtr %r0, 0, %f13 # encoding: [0xb3,0xe9,0x00,0x0d] +#CHECK: cgxtr %r0, 15, %f0 # encoding: [0xb3,0xe9,0xf0,0x00] +#CHECK: cgxtr %r4, 5, %f8 # encoding: [0xb3,0xe9,0x50,0x48] +#CHECK: cgxtr %r15, 0, %f0 # encoding: [0xb3,0xe9,0x00,0xf0] + + cgxtr %r0, 0, %f0 + cgxtr %r0, 0, %f13 + cgxtr %r0, 15, %f0 + cgxtr %r4, 5, %f8 + cgxtr %r15, 0, %f0 + #CHECK: ch %r0, 0 # encoding: [0x49,0x00,0x00,0x00] #CHECK: ch %r0, 4095 # encoding: [0x49,0x00,0x0f,0xff] #CHECK: ch %r0, 0(%r1) # encoding: [0x49,0x00,0x10,0x00] @@ -5857,6 +6257,18 @@ cs %r0, %r15, 0 cs %r15, %r0, 0 +#CHECK: csdtr %r0, %f0, 0 # encoding: [0xb3,0xe3,0x00,0x00] +#CHECK: csdtr %r0, %f15, 0 # encoding: [0xb3,0xe3,0x00,0x0f] +#CHECK: csdtr %r0, %f0, 15 # encoding: [0xb3,0xe3,0x0f,0x00] +#CHECK: csdtr %r4, %f5, 6 # encoding: [0xb3,0xe3,0x06,0x45] +#CHECK: csdtr %r15, %f0, 0 # encoding: [0xb3,0xe3,0x00,0xf0] + + csdtr %r0, %f0, 0 + csdtr %r0, %f15, 0 + csdtr %r0, %f0, 15 + csdtr %r4, %f5, 6 + csdtr %r15, %f0, 0 + #CHECK: csg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x30] #CHECK: csg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x30] #CHECK: csg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x30] @@ -5895,6 +6307,18 @@ csst 0(%r1), 1(%r15), %r2 csst 0(%r1), 4095(%r15), %r2 +#CHECK: csxtr %r0, %f0, 0 # encoding: [0xb3,0xeb,0x00,0x00] +#CHECK: csxtr %r0, %f13, 0 # encoding: [0xb3,0xeb,0x00,0x0d] +#CHECK: csxtr %r0, %f0, 15 # encoding: [0xb3,0xeb,0x0f,0x00] +#CHECK: csxtr %r4, %f5, 6 # encoding: [0xb3,0xeb,0x06,0x45] +#CHECK: csxtr %r14, %f0, 0 # encoding: [0xb3,0xeb,0x00,0xe0] + + csxtr %r0, %f0, 0 + csxtr %r0, %f13, 0 + csxtr %r0, %f0, 15 + csxtr %r4, %f5, 6 + csxtr %r14, %f0, 0 + #CHECK: csy %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x14] #CHECK: csy %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x14] #CHECK: csy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x14] @@ -5995,6 +6419,18 @@ cu42 %r14, %r0 cu42 %r6, %r8 +#CHECK: cudtr %r0, %f0 # encoding: [0xb3,0xe2,0x00,0x00] +#CHECK: cudtr %r0, %f15 # encoding: [0xb3,0xe2,0x00,0x0f] +#CHECK: cudtr %r15, %f0 # encoding: [0xb3,0xe2,0x00,0xf0] +#CHECK: cudtr %r7, %f8 # encoding: [0xb3,0xe2,0x00,0x78] +#CHECK: cudtr %r15, %f15 # encoding: [0xb3,0xe2,0x00,0xff] + + cudtr %r0, %f0 + cudtr %r0, %f15 + cudtr %r15, %f0 + cudtr %r7, %f8 + cudtr %r15, %f15 + #CHECK: cuse %r0, %r8 # encoding: [0xb2,0x57,0x00,0x08] #CHECK: cuse %r0, %r14 # encoding: [0xb2,0x57,0x00,0x0e] #CHECK: cuse %r14, %r0 # encoding: [0xb2,0x57,0x00,0xe0] @@ -6033,6 +6469,18 @@ cuutf %r4, %r12, 0 cuutf %r4, %r12, 15 +#CHECK: cuxtr %r0, %f0 # encoding: [0xb3,0xea,0x00,0x00] +#CHECK: cuxtr %r0, %f13 # encoding: [0xb3,0xea,0x00,0x0d] +#CHECK: cuxtr %r14, %f0 # encoding: [0xb3,0xea,0x00,0xe0] +#CHECK: cuxtr %r6, %f8 # encoding: [0xb3,0xea,0x00,0x68] +#CHECK: cuxtr %r14, %f13 # encoding: [0xb3,0xea,0x00,0xed] + + cuxtr %r0, %f0 + cuxtr %r0, %f13 + cuxtr %r14, %f0 + cuxtr %r6, %f8 + cuxtr %r14, %f13 + #CHECK: cvb %r0, 0 # encoding: [0x4f,0x00,0x00,0x00] #CHECK: cvb %r0, 4095 # encoding: [0x4f,0x00,0x0f,0xff] #CHECK: cvb %r0, 0(%r1) # encoding: [0x4f,0x00,0x10,0x00] @@ -6175,6 +6623,18 @@ cxfbr %f8, %r7 cxfbr %f13, %r15 +#CHECK: cxfr %f0, %r0 # encoding: [0xb3,0xb6,0x00,0x00] +#CHECK: cxfr %f0, %r15 # encoding: [0xb3,0xb6,0x00,0x0f] +#CHECK: cxfr %f13, %r0 # encoding: [0xb3,0xb6,0x00,0xd0] +#CHECK: cxfr %f8, %r7 # encoding: [0xb3,0xb6,0x00,0x87] +#CHECK: cxfr %f13, %r15 # encoding: [0xb3,0xb6,0x00,0xdf] + + cxfr %f0, %r0 + cxfr %f0, %r15 + cxfr %f13, %r0 + cxfr %f8, %r7 + cxfr %f13, %r15 + #CHECK: cxgbr %f0, %r0 # encoding: [0xb3,0xa6,0x00,0x00] #CHECK: cxgbr %f0, %r15 # encoding: [0xb3,0xa6,0x00,0x0f] #CHECK: cxgbr %f13, %r0 # encoding: [0xb3,0xa6,0x00,0xd0] @@ -6187,6 +6647,74 @@ cxgbr %f8, %r7 cxgbr %f13, %r15 +#CHECK: cxgr %f0, %r0 # encoding: [0xb3,0xc6,0x00,0x00] +#CHECK: cxgr %f0, %r15 # encoding: [0xb3,0xc6,0x00,0x0f] +#CHECK: cxgr %f13, %r0 # encoding: [0xb3,0xc6,0x00,0xd0] +#CHECK: cxgr %f8, %r7 # encoding: [0xb3,0xc6,0x00,0x87] +#CHECK: cxgr %f13, %r15 # encoding: [0xb3,0xc6,0x00,0xdf] + + cxgr %f0, %r0 + cxgr %f0, %r15 + cxgr %f13, %r0 + cxgr %f8, %r7 + cxgr %f13, %r15 + +#CHECK: cxgtr %f0, %r0 # encoding: [0xb3,0xf9,0x00,0x00] +#CHECK: cxgtr %f0, %r15 # encoding: [0xb3,0xf9,0x00,0x0f] +#CHECK: cxgtr %f13, %r0 # encoding: [0xb3,0xf9,0x00,0xd0] +#CHECK: cxgtr %f8, %r7 # encoding: [0xb3,0xf9,0x00,0x87] +#CHECK: cxgtr %f13, %r15 # encoding: [0xb3,0xf9,0x00,0xdf] + + cxgtr %f0, %r0 + cxgtr %f0, %r15 + cxgtr %f13, %r0 + cxgtr %f8, %r7 + cxgtr %f13, %r15 + +#CHECK: cxr %f0, %f0 # encoding: [0xb3,0x69,0x00,0x00] +#CHECK: cxr %f0, %f13 # encoding: [0xb3,0x69,0x00,0x0d] +#CHECK: cxr %f8, %f8 # encoding: [0xb3,0x69,0x00,0x88] +#CHECK: cxr %f13, %f0 # encoding: [0xb3,0x69,0x00,0xd0] + + cxr %f0, %f0 + cxr %f0, %f13 + cxr %f8, %f8 + cxr %f13, %f0 + +#CHECK: cxstr %f0, %r0 # encoding: [0xb3,0xfb,0x00,0x00] +#CHECK: cxstr %f0, %r14 # encoding: [0xb3,0xfb,0x00,0x0e] +#CHECK: cxstr %f13, %r0 # encoding: [0xb3,0xfb,0x00,0xd0] +#CHECK: cxstr %f8, %r6 # encoding: [0xb3,0xfb,0x00,0x86] +#CHECK: cxstr %f13, %r14 # encoding: [0xb3,0xfb,0x00,0xde] + + cxstr %f0, %r0 + cxstr %f0, %r14 + cxstr %f13, %r0 + cxstr %f8, %r6 + cxstr %f13, %r14 + +#CHECK: cxtr %f0, %f0 # encoding: [0xb3,0xec,0x00,0x00] +#CHECK: cxtr %f0, %f13 # encoding: [0xb3,0xec,0x00,0x0d] +#CHECK: cxtr %f8, %f8 # encoding: [0xb3,0xec,0x00,0x88] +#CHECK: cxtr %f13, %f0 # encoding: [0xb3,0xec,0x00,0xd0] + + cxtr %f0, %f0 + cxtr %f0, %f13 + cxtr %f8, %f8 + cxtr %f13, %f0 + +#CHECK: cxutr %f0, %r0 # encoding: [0xb3,0xfa,0x00,0x00] +#CHECK: cxutr %f0, %r14 # encoding: [0xb3,0xfa,0x00,0x0e] +#CHECK: cxutr %f13, %r0 # encoding: [0xb3,0xfa,0x00,0xd0] +#CHECK: cxutr %f8, %r6 # encoding: [0xb3,0xfa,0x00,0x86] +#CHECK: cxutr %f13, %r14 # encoding: [0xb3,0xfa,0x00,0xde] + + cxutr %f0, %r0 + cxutr %f0, %r14 + cxutr %f13, %r0 + cxutr %f8, %r6 + cxutr %f13, %r14 + #CHECK: cy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x59] #CHECK: cy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x59] #CHECK: cy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x59] @@ -6225,6 +6753,22 @@ d %r0, 4095(%r15,%r1) d %r14, 0 +#CHECK: dd %f0, 0 # encoding: [0x6d,0x00,0x00,0x00] +#CHECK: dd %f0, 4095 # encoding: [0x6d,0x00,0x0f,0xff] +#CHECK: dd %f0, 0(%r1) # encoding: [0x6d,0x00,0x10,0x00] +#CHECK: dd %f0, 0(%r15) # encoding: [0x6d,0x00,0xf0,0x00] +#CHECK: dd %f0, 4095(%r1,%r15) # encoding: [0x6d,0x01,0xff,0xff] +#CHECK: dd %f0, 4095(%r15,%r1) # encoding: [0x6d,0x0f,0x1f,0xff] +#CHECK: dd %f15, 0 # encoding: [0x6d,0xf0,0x00,0x00] + + dd %f0, 0 + dd %f0, 4095 + dd %f0, 0(%r1) + dd %f0, 0(%r15) + dd %f0, 4095(%r1,%r15) + dd %f0, 4095(%r15,%r1) + dd %f15, 0 + #CHECK: ddb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1d] #CHECK: ddb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1d] #CHECK: ddb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1d] @@ -6251,6 +6795,44 @@ ddbr %f7, %f8 ddbr %f15, %f0 +#CHECK: ddr %f0, %f0 # encoding: [0x2d,0x00] +#CHECK: ddr %f0, %f15 # encoding: [0x2d,0x0f] +#CHECK: ddr %f7, %f8 # encoding: [0x2d,0x78] +#CHECK: ddr %f15, %f0 # encoding: [0x2d,0xf0] + + ddr %f0, %f0 + ddr %f0, %f15 + ddr %f7, %f8 + ddr %f15, %f0 + +#CHECK: ddtr %f0, %f0, %f0 # encoding: [0xb3,0xd1,0x00,0x00] +#CHECK: ddtr %f0, %f0, %f15 # encoding: [0xb3,0xd1,0xf0,0x00] +#CHECK: ddtr %f0, %f15, %f0 # encoding: [0xb3,0xd1,0x00,0x0f] +#CHECK: ddtr %f15, %f0, %f0 # encoding: [0xb3,0xd1,0x00,0xf0] +#CHECK: ddtr %f7, %f8, %f9 # encoding: [0xb3,0xd1,0x90,0x78] + + ddtr %f0, %f0, %f0 + ddtr %f0, %f0, %f15 + ddtr %f0, %f15, %f0 + ddtr %f15, %f0, %f0 + ddtr %f7, %f8, %f9 + +#CHECK: de %f0, 0 # encoding: [0x7d,0x00,0x00,0x00] +#CHECK: de %f0, 4095 # encoding: [0x7d,0x00,0x0f,0xff] +#CHECK: de %f0, 0(%r1) # encoding: [0x7d,0x00,0x10,0x00] +#CHECK: de %f0, 0(%r15) # encoding: [0x7d,0x00,0xf0,0x00] +#CHECK: de %f0, 4095(%r1,%r15) # encoding: [0x7d,0x01,0xff,0xff] +#CHECK: de %f0, 4095(%r15,%r1) # encoding: [0x7d,0x0f,0x1f,0xff] +#CHECK: de %f15, 0 # encoding: [0x7d,0xf0,0x00,0x00] + + de %f0, 0 + de %f0, 4095 + de %f0, 0(%r1) + de %f0, 0(%r15) + de %f0, 4095(%r1,%r15) + de %f0, 4095(%r15,%r1) + de %f15, 0 + #CHECK: deb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0d] #CHECK: deb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0d] #CHECK: deb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0d] @@ -6277,6 +6859,16 @@ debr %f7, %f8 debr %f15, %f0 +#CHECK: der %f0, %f0 # encoding: [0x3d,0x00] +#CHECK: der %f0, %f15 # encoding: [0x3d,0x0f] +#CHECK: der %f7, %f8 # encoding: [0x3d,0x78] +#CHECK: der %f15, %f0 # encoding: [0x3d,0xf0] + + der %f0, %f0 + der %f0, %f15 + der %f7, %f8 + der %f15, %f0 + #CHECK: didbr %f0, %f0, %f0, 0 # encoding: [0xb3,0x5b,0x00,0x00] #CHECK: didbr %f0, %f0, %f0, 15 # encoding: [0xb3,0x5b,0x0f,0x00] #CHECK: didbr %f0, %f0, %f15, 0 # encoding: [0xb3,0x5b,0x00,0x0f] @@ -6483,6 +7075,28 @@ dxbr %f8, %f8 dxbr %f13, %f0 +#CHECK: dxr %f0, %f0 # encoding: [0xb2,0x2d,0x00,0x00] +#CHECK: dxr %f0, %f13 # encoding: [0xb2,0x2d,0x00,0x0d] +#CHECK: dxr %f8, %f8 # encoding: [0xb2,0x2d,0x00,0x88] +#CHECK: dxr %f13, %f0 # encoding: [0xb2,0x2d,0x00,0xd0] + + dxr %f0, %f0 + dxr %f0, %f13 + dxr %f8, %f8 + dxr %f13, %f0 + +#CHECK: dxtr %f0, %f0, %f0 # encoding: [0xb3,0xd9,0x00,0x00] +#CHECK: dxtr %f0, %f0, %f13 # encoding: [0xb3,0xd9,0xd0,0x00] +#CHECK: dxtr %f0, %f13, %f0 # encoding: [0xb3,0xd9,0x00,0x0d] +#CHECK: dxtr %f13, %f0, %f0 # encoding: [0xb3,0xd9,0x00,0xd0] +#CHECK: dxtr %f8, %f8, %f8 # encoding: [0xb3,0xd9,0x80,0x88] + + dxtr %f0, %f0, %f0 + dxtr %f0, %f0, %f13 + dxtr %f0, %f13, %f0 + dxtr %f13, %f0, %f0 + dxtr %f8, %f8, %f8 + #CHECK: ear %r0, %a0 # encoding: [0xb2,0x4f,0x00,0x00] #CHECK: ear %r0, %a15 # encoding: [0xb2,0x4f,0x00,0x0f] #CHECK: ear %r15, %a0 # encoding: [0xb2,0x4f,0x00,0xf0] @@ -6589,6 +7203,26 @@ edmk 0(256,%r1), 0 edmk 0(256,%r15), 0 +#CHECK: eedtr %f0, %f9 # encoding: [0xb3,0xe5,0x00,0x09] +#CHECK: eedtr %f0, %f15 # encoding: [0xb3,0xe5,0x00,0x0f] +#CHECK: eedtr %f15, %f0 # encoding: [0xb3,0xe5,0x00,0xf0] +#CHECK: eedtr %f15, %f9 # encoding: [0xb3,0xe5,0x00,0xf9] + + eedtr %f0,%f9 + eedtr %f0,%f15 + eedtr %f15,%f0 + eedtr %f15,%f9 + +#CHECK: eextr %f0, %f8 # encoding: [0xb3,0xed,0x00,0x08] +#CHECK: eextr %f0, %f13 # encoding: [0xb3,0xed,0x00,0x0d] +#CHECK: eextr %f13, %f0 # encoding: [0xb3,0xed,0x00,0xd0] +#CHECK: eextr %f13, %f9 # encoding: [0xb3,0xed,0x00,0xd9] + + eextr %f0,%f8 + eextr %f0,%f13 + eextr %f13,%f0 + eextr %f13,%f9 + #CHECK: efpc %r0 # encoding: [0xb3,0x8c,0x00,0x00] #CHECK: efpc %r1 # encoding: [0xb3,0x8c,0x00,0x10] #CHECK: efpc %r15 # encoding: [0xb3,0x8c,0x00,0xf0] @@ -6607,6 +7241,26 @@ epsw %r15, %r0 epsw %r15, %r8 +#CHECK: esdtr %f0, %f9 # encoding: [0xb3,0xe7,0x00,0x09] +#CHECK: esdtr %f0, %f15 # encoding: [0xb3,0xe7,0x00,0x0f] +#CHECK: esdtr %f15, %f0 # encoding: [0xb3,0xe7,0x00,0xf0] +#CHECK: esdtr %f15, %f9 # encoding: [0xb3,0xe7,0x00,0xf9] + + esdtr %f0,%f9 + esdtr %f0,%f15 + esdtr %f15,%f0 + esdtr %f15,%f9 + +#CHECK: esxtr %f0, %f8 # encoding: [0xb3,0xef,0x00,0x08] +#CHECK: esxtr %f0, %f13 # encoding: [0xb3,0xef,0x00,0x0d] +#CHECK: esxtr %f13, %f0 # encoding: [0xb3,0xef,0x00,0xd0] +#CHECK: esxtr %f13, %f9 # encoding: [0xb3,0xef,0x00,0xd9] + + esxtr %f0,%f8 + esxtr %f0,%f13 + esxtr %f13,%f0 + esxtr %f13,%f9 + #CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00] #CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff] #CHECK: ex %r0, 0(%r1) # encoding: [0x44,0x00,0x10,0x00] @@ -6672,6 +7326,30 @@ fidbr %f4, 5, %f6 fidbr %f15, 0, %f0 +#CHECK: fidr %f0, %f0 # encoding: [0xb3,0x7f,0x00,0x00] +#CHECK: fidr %f0, %f15 # encoding: [0xb3,0x7f,0x00,0x0f] +#CHECK: fidr %f4, %f6 # encoding: [0xb3,0x7f,0x00,0x46] +#CHECK: fidr %f15, %f0 # encoding: [0xb3,0x7f,0x00,0xf0] + + fidr %f0, %f0 + fidr %f0, %f15 + fidr %f4, %f6 + fidr %f15, %f0 + +#CHECK: fidtr %f0, 0, %f0, 0 # encoding: [0xb3,0xd7,0x00,0x00] +#CHECK: fidtr %f0, 0, %f0, 15 # encoding: [0xb3,0xd7,0x0f,0x00] +#CHECK: fidtr %f0, 0, %f15, 0 # encoding: [0xb3,0xd7,0x00,0x0f] +#CHECK: fidtr %f0, 15, %f0, 0 # encoding: [0xb3,0xd7,0xf0,0x00] +#CHECK: fidtr %f4, 5, %f6, 7 # encoding: [0xb3,0xd7,0x57,0x46] +#CHECK: fidtr %f15, 0, %f0, 0 # encoding: [0xb3,0xd7,0x00,0xf0] + + fidtr %f0, 0, %f0, 0 + fidtr %f0, 0, %f0, 15 + fidtr %f0, 0, %f15, 0 + fidtr %f0, 15, %f0, 0 + fidtr %f4, 5, %f6, 7 + fidtr %f15, 0, %f0, 0 + #CHECK: fiebr %f0, 0, %f0 # encoding: [0xb3,0x57,0x00,0x00] #CHECK: fiebr %f0, 0, %f15 # encoding: [0xb3,0x57,0x00,0x0f] #CHECK: fiebr %f0, 15, %f0 # encoding: [0xb3,0x57,0xf0,0x00] @@ -6684,6 +7362,16 @@ fiebr %f4, 5, %f6 fiebr %f15, 0, %f0 +#CHECK: fier %f0, %f0 # encoding: [0xb3,0x77,0x00,0x00] +#CHECK: fier %f0, %f15 # encoding: [0xb3,0x77,0x00,0x0f] +#CHECK: fier %f4, %f6 # encoding: [0xb3,0x77,0x00,0x46] +#CHECK: fier %f15, %f0 # encoding: [0xb3,0x77,0x00,0xf0] + + fier %f0, %f0 + fier %f0, %f15 + fier %f4, %f6 + fier %f15, %f0 + #CHECK: fixbr %f0, 0, %f0 # encoding: [0xb3,0x47,0x00,0x00] #CHECK: fixbr %f0, 0, %f13 # encoding: [0xb3,0x47,0x00,0x0d] #CHECK: fixbr %f0, 15, %f0 # encoding: [0xb3,0x47,0xf0,0x00] @@ -6696,6 +7384,30 @@ fixbr %f4, 5, %f8 fixbr %f13, 0, %f0 +#CHECK: fixr %f0, %f0 # encoding: [0xb3,0x67,0x00,0x00] +#CHECK: fixr %f0, %f13 # encoding: [0xb3,0x67,0x00,0x0d] +#CHECK: fixr %f4, %f8 # encoding: [0xb3,0x67,0x00,0x48] +#CHECK: fixr %f13, %f0 # encoding: [0xb3,0x67,0x00,0xd0] + + fixr %f0, %f0 + fixr %f0, %f13 + fixr %f4, %f8 + fixr %f13, %f0 + +#CHECK: fixtr %f0, 0, %f0, 0 # encoding: [0xb3,0xdf,0x00,0x00] +#CHECK: fixtr %f0, 0, %f0, 15 # encoding: [0xb3,0xdf,0x0f,0x00] +#CHECK: fixtr %f0, 0, %f13, 0 # encoding: [0xb3,0xdf,0x00,0x0d] +#CHECK: fixtr %f0, 15, %f0, 0 # encoding: [0xb3,0xdf,0xf0,0x00] +#CHECK: fixtr %f4, 5, %f8, 9 # encoding: [0xb3,0xdf,0x59,0x48] +#CHECK: fixtr %f13, 0, %f0, 0 # encoding: [0xb3,0xdf,0x00,0xd0] + + fixtr %f0, 0, %f0, 0 + fixtr %f0, 0, %f0, 15 + fixtr %f0, 0, %f13, 0 + fixtr %f0, 15, %f0, 0 + fixtr %f4, 5, %f8, 9 + fixtr %f13, 0, %f0, 0 + #CHECK: flogr %r0, %r0 # encoding: [0xb9,0x83,0x00,0x00] #CHECK: flogr %r0, %r15 # encoding: [0xb9,0x83,0x00,0x0f] #CHECK: flogr %r10, %r9 # encoding: [0xb9,0x83,0x00,0xa9] @@ -6706,6 +7418,26 @@ flogr %r10, %r9 flogr %r14, %r0 +#CHECK: hdr %f0, %f0 # encoding: [0x24,0x00] +#CHECK: hdr %f0, %f15 # encoding: [0x24,0x0f] +#CHECK: hdr %f7, %f8 # encoding: [0x24,0x78] +#CHECK: hdr %f15, %f0 # encoding: [0x24,0xf0] + + hdr %f0, %f0 + hdr %f0, %f15 + hdr %f7, %f8 + hdr %f15, %f0 + +#CHECK: her %f0, %f0 # encoding: [0x34,0x00] +#CHECK: her %f0, %f15 # encoding: [0x34,0x0f] +#CHECK: her %f7, %f8 # encoding: [0x34,0x78] +#CHECK: her %f15, %f0 # encoding: [0x34,0xf0] + + her %f0, %f0 + her %f0, %f15 + her %f7, %f8 + her %f15, %f0 + #CHECK: ic %r0, 0 # encoding: [0x43,0x00,0x00,0x00] #CHECK: ic %r0, 4095 # encoding: [0x43,0x00,0x0f,0xff] #CHECK: ic %r0, 0(%r1) # encoding: [0x43,0x00,0x10,0x00] @@ -6804,6 +7536,34 @@ icy %r0, 524287(%r15,%r1) icy %r15, 0 +#CHECK: iedtr %f0, %f0, %f0 # encoding: [0xb3,0xf6,0x00,0x00] +#CHECK: iedtr %f0, %f0, %f15 # encoding: [0xb3,0xf6,0x00,0x0f] +#CHECK: iedtr %f0, %f15, %f0 # encoding: [0xb3,0xf6,0xf0,0x00] +#CHECK: iedtr %f15, %f0, %f0 # encoding: [0xb3,0xf6,0x00,0xf0] +#CHECK: iedtr %f1, %f2, %f3 # encoding: [0xb3,0xf6,0x20,0x13] +#CHECK: iedtr %f15, %f15, %f15 # encoding: [0xb3,0xf6,0xf0,0xff] + + iedtr %f0, %f0, %f0 + iedtr %f0, %f0, %f15 + iedtr %f0, %f15, %f0 + iedtr %f15, %f0, %f0 + iedtr %f1, %f2, %f3 + iedtr %f15, %f15, %f15 + +#CHECK: iextr %f0, %f0, %f0 # encoding: [0xb3,0xfe,0x00,0x00] +#CHECK: iextr %f0, %f0, %f13 # encoding: [0xb3,0xfe,0x00,0x0d] +#CHECK: iextr %f0, %f13, %f0 # encoding: [0xb3,0xfe,0xd0,0x00] +#CHECK: iextr %f13, %f0, %f0 # encoding: [0xb3,0xfe,0x00,0xd0] +#CHECK: iextr %f1, %f8, %f4 # encoding: [0xb3,0xfe,0x80,0x14] +#CHECK: iextr %f13, %f13, %f13 # encoding: [0xb3,0xfe,0xd0,0xdd] + + iextr %f0, %f0, %f0 + iextr %f0, %f0, %f13 + iextr %f0, %f13, %f0 + iextr %f13, %f0, %f0 + iextr %f1, %f8, %f4 + iextr %f13, %f13, %f13 + #CHECK: iihf %r0, 0 # encoding: [0xc0,0x08,0x00,0x00,0x00,0x00] #CHECK: iihf %r0, 4294967295 # encoding: [0xc0,0x08,0xff,0xff,0xff,0xff] #CHECK: iihf %r15, 0 # encoding: [0xc0,0xf8,0x00,0x00,0x00,0x00] @@ -6894,6 +7654,16 @@ kdbr %f7, %f8 kdbr %f15, %f0 +#CHECK: kdtr %f0, %f0 # encoding: [0xb3,0xe0,0x00,0x00] +#CHECK: kdtr %f0, %f15 # encoding: [0xb3,0xe0,0x00,0x0f] +#CHECK: kdtr %f7, %f8 # encoding: [0xb3,0xe0,0x00,0x78] +#CHECK: kdtr %f15, %f0 # encoding: [0xb3,0xe0,0x00,0xf0] + + kdtr %f0, %f0 + kdtr %f0, %f15 + kdtr %f7, %f8 + kdtr %f15, %f0 + #CHECK: keb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x08] #CHECK: keb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x08] #CHECK: keb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x08] @@ -6980,6 +7750,16 @@ kxbr %f8, %f8 kxbr %f13, %f0 +#CHECK: kxtr %f0, %f0 # encoding: [0xb3,0xe8,0x00,0x00] +#CHECK: kxtr %f0, %f13 # encoding: [0xb3,0xe8,0x00,0x0d] +#CHECK: kxtr %f8, %f8 # encoding: [0xb3,0xe8,0x00,0x88] +#CHECK: kxtr %f13, %f0 # encoding: [0xb3,0xe8,0x00,0xd0] + + kxtr %f0, %f0 + kxtr %f0, %f13 + kxtr %f8, %f8 + kxtr %f13, %f0 + #CHECK: l %r0, 0 # encoding: [0x58,0x00,0x00,0x00] #CHECK: l %r0, 4095 # encoding: [0x58,0x00,0x0f,0xff] #CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00] @@ -7199,6 +7979,16 @@ lcdbr %f15,%f0 lcdbr %f15,%f9 +#CHECK: lcdr %f0, %f9 # encoding: [0x23,0x09] +#CHECK: lcdr %f0, %f15 # encoding: [0x23,0x0f] +#CHECK: lcdr %f15, %f0 # encoding: [0x23,0xf0] +#CHECK: lcdr %f15, %f9 # encoding: [0x23,0xf9] + + lcdr %f0,%f9 + lcdr %f0,%f15 + lcdr %f15,%f0 + lcdr %f15,%f9 + #CHECK: lcebr %f0, %f9 # encoding: [0xb3,0x03,0x00,0x09] #CHECK: lcebr %f0, %f15 # encoding: [0xb3,0x03,0x00,0x0f] #CHECK: lcebr %f15, %f0 # encoding: [0xb3,0x03,0x00,0xf0] @@ -7209,6 +7999,16 @@ lcebr %f15,%f0 lcebr %f15,%f9 +#CHECK: lcer %f0, %f9 # encoding: [0x33,0x09] +#CHECK: lcer %f0, %f15 # encoding: [0x33,0x0f] +#CHECK: lcer %f15, %f0 # encoding: [0x33,0xf0] +#CHECK: lcer %f15, %f9 # encoding: [0x33,0xf9] + + lcer %f0,%f9 + lcer %f0,%f15 + lcer %f15,%f0 + lcer %f15,%f9 + #CHECK: lcgfr %r0, %r0 # encoding: [0xb9,0x13,0x00,0x00] #CHECK: lcgfr %r0, %r15 # encoding: [0xb9,0x13,0x00,0x0f] #CHECK: lcgfr %r15, %r0 # encoding: [0xb9,0x13,0x00,0xf0] @@ -7249,6 +8049,16 @@ lcxbr %f13,%f0 lcxbr %f13,%f9 +#CHECK: lcxr %f0, %f8 # encoding: [0xb3,0x63,0x00,0x08] +#CHECK: lcxr %f0, %f13 # encoding: [0xb3,0x63,0x00,0x0d] +#CHECK: lcxr %f13, %f0 # encoding: [0xb3,0x63,0x00,0xd0] +#CHECK: lcxr %f13, %f9 # encoding: [0xb3,0x63,0x00,0xd9] + + lcxr %f0,%f8 + lcxr %f0,%f13 + lcxr %f13,%f0 + lcxr %f13,%f9 + #CHECK: ld %f0, 0 # encoding: [0x68,0x00,0x00,0x00] #CHECK: ld %f0, 4095 # encoding: [0x68,0x00,0x0f,0xff] #CHECK: ld %f0, 0(%r1) # encoding: [0x68,0x00,0x10,0x00] @@ -7265,6 +8075,22 @@ ld %f0, 4095(%r15,%r1) ld %f15, 0 +#CHECK: lde %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x24] +#CHECK: lde %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x24] +#CHECK: lde %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x24] +#CHECK: lde %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x24] +#CHECK: lde %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x24] +#CHECK: lde %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x24] +#CHECK: lde %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x24] + + lde %f0, 0 + lde %f0, 4095 + lde %f0, 0(%r1) + lde %f0, 0(%r15) + lde %f0, 4095(%r1,%r15) + lde %f0, 4095(%r15,%r1) + lde %f15, 0 + #CHECK: ldeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x04] #CHECK: ldeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x04] #CHECK: ldeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x04] @@ -7289,6 +8115,24 @@ ldebr %f7, %f8 ldebr %f15, %f0 +#CHECK: lder %f0, %f15 # encoding: [0xb3,0x24,0x00,0x0f] +#CHECK: lder %f7, %f8 # encoding: [0xb3,0x24,0x00,0x78] +#CHECK: lder %f15, %f0 # encoding: [0xb3,0x24,0x00,0xf0] + + lder %f0, %f15 + lder %f7, %f8 + lder %f15, %f0 + +#CHECK: ldetr %f0, %f0, 15 # encoding: [0xb3,0xd4,0x0f,0x00] +#CHECK: ldetr %f0, %f15, 0 # encoding: [0xb3,0xd4,0x00,0x0f] +#CHECK: ldetr %f7, %f8, 9 # encoding: [0xb3,0xd4,0x09,0x78] +#CHECK: ldetr %f15, %f0, 0 # encoding: [0xb3,0xd4,0x00,0xf0] + + ldetr %f0, %f0, 15 + ldetr %f0, %f15, 0 + ldetr %f7, %f8, 9 + ldetr %f15, %f0, 0 + #CHECK: ldgr %f0, %r0 # encoding: [0xb3,0xc1,0x00,0x00] #CHECK: ldgr %f0, %r15 # encoding: [0xb3,0xc1,0x00,0x0f] #CHECK: ldgr %f15, %r0 # encoding: [0xb3,0xc1,0x00,0xf0] @@ -7323,6 +8167,32 @@ ldxbr %f13, %f0 ldxbr %f13, %f13 +#CHECK: ldxr %f0, %f0 # encoding: [0x25,0x00] +#CHECK: ldxr %f0, %f13 # encoding: [0x25,0x0d] +#CHECK: ldxr %f7, %f8 # encoding: [0x25,0x78] +#CHECK: ldxr %f15, %f0 # encoding: [0x25,0xf0] +#CHECK: ldxr %f15, %f13 # encoding: [0x25,0xfd] + + ldxr %f0, %f0 + ldxr %f0, %f13 + ldxr %f7, %f8 + ldxr %f15, %f0 + ldxr %f15, %f13 + +#CHECK: ldxtr %f0, 0, %f0, 0 # encoding: [0xb3,0xdd,0x00,0x00] +#CHECK: ldxtr %f0, 0, %f0, 15 # encoding: [0xb3,0xdd,0x0f,0x00] +#CHECK: ldxtr %f0, 0, %f13, 0 # encoding: [0xb3,0xdd,0x00,0x0d] +#CHECK: ldxtr %f0, 15, %f0, 0 # encoding: [0xb3,0xdd,0xf0,0x00] +#CHECK: ldxtr %f4, 5, %f8, 9 # encoding: [0xb3,0xdd,0x59,0x48] +#CHECK: ldxtr %f13, 0, %f0, 0 # encoding: [0xb3,0xdd,0x00,0xd0] + + ldxtr %f0, 0, %f0, 0 + ldxtr %f0, 0, %f0, 15 + ldxtr %f0, 0, %f13, 0 + ldxtr %f0, 15, %f0, 0 + ldxtr %f4, 5, %f8, 9 + ldxtr %f13, 0, %f0, 0 + #CHECK: ldy %f0, -524288 # encoding: [0xed,0x00,0x00,0x00,0x80,0x65] #CHECK: ldy %f0, -1 # encoding: [0xed,0x00,0x0f,0xff,0xff,0x65] #CHECK: ldy %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x65] @@ -7373,6 +8243,32 @@ ledbr %f15, %f0 ledbr %f15, %f15 +#CHECK: ledr %f0, %f0 # encoding: [0x35,0x00] +#CHECK: ledr %f0, %f15 # encoding: [0x35,0x0f] +#CHECK: ledr %f7, %f8 # encoding: [0x35,0x78] +#CHECK: ledr %f15, %f0 # encoding: [0x35,0xf0] +#CHECK: ledr %f15, %f15 # encoding: [0x35,0xff] + + ledr %f0, %f0 + ledr %f0, %f15 + ledr %f7, %f8 + ledr %f15, %f0 + ledr %f15, %f15 + +#CHECK: ledtr %f0, 0, %f0, 0 # encoding: [0xb3,0xd5,0x00,0x00] +#CHECK: ledtr %f0, 0, %f0, 15 # encoding: [0xb3,0xd5,0x0f,0x00] +#CHECK: ledtr %f0, 0, %f15, 0 # encoding: [0xb3,0xd5,0x00,0x0f] +#CHECK: ledtr %f0, 15, %f0, 0 # encoding: [0xb3,0xd5,0xf0,0x00] +#CHECK: ledtr %f4, 5, %f6, 7 # encoding: [0xb3,0xd5,0x57,0x46] +#CHECK: ledtr %f15, 0, %f0, 0 # encoding: [0xb3,0xd5,0x00,0xf0] + + ledtr %f0, 0, %f0, 0 + ledtr %f0, 0, %f0, 15 + ledtr %f0, 0, %f15, 0 + ledtr %f0, 15, %f0, 0 + ledtr %f4, 5, %f6, 7 + ledtr %f15, 0, %f0, 0 + #CHECK: ler %f0, %f9 # encoding: [0x38,0x09] #CHECK: ler %f0, %f15 # encoding: [0x38,0x0f] #CHECK: ler %f15, %f0 # encoding: [0x38,0xf0] @@ -7395,6 +8291,18 @@ lexbr %f13, %f0 lexbr %f13, %f13 +#CHECK: lexr %f0, %f0 # encoding: [0xb3,0x66,0x00,0x00] +#CHECK: lexr %f0, %f13 # encoding: [0xb3,0x66,0x00,0x0d] +#CHECK: lexr %f7, %f8 # encoding: [0xb3,0x66,0x00,0x78] +#CHECK: lexr %f15, %f0 # encoding: [0xb3,0x66,0x00,0xf0] +#CHECK: lexr %f15, %f13 # encoding: [0xb3,0x66,0x00,0xfd] + + lexr %f0, %f0 + lexr %f0, %f13 + lexr %f7, %f8 + lexr %f15, %f0 + lexr %f15, %f13 + #CHECK: ley %f0, -524288 # encoding: [0xed,0x00,0x00,0x00,0x80,0x64] #CHECK: ley %f0, -1 # encoding: [0xed,0x00,0x0f,0xff,0xff,0x64] #CHECK: ley %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x64] @@ -8303,6 +9211,16 @@ lndbr %f15,%f0 lndbr %f15,%f9 +#CHECK: lndr %f0, %f9 # encoding: [0x21,0x09] +#CHECK: lndr %f0, %f15 # encoding: [0x21,0x0f] +#CHECK: lndr %f15, %f0 # encoding: [0x21,0xf0] +#CHECK: lndr %f15, %f9 # encoding: [0x21,0xf9] + + lndr %f0,%f9 + lndr %f0,%f15 + lndr %f15,%f0 + lndr %f15,%f9 + #CHECK: lnebr %f0, %f9 # encoding: [0xb3,0x01,0x00,0x09] #CHECK: lnebr %f0, %f15 # encoding: [0xb3,0x01,0x00,0x0f] #CHECK: lnebr %f15, %f0 # encoding: [0xb3,0x01,0x00,0xf0] @@ -8313,6 +9231,16 @@ lnebr %f15,%f0 lnebr %f15,%f9 +#CHECK: lner %f0, %f9 # encoding: [0x31,0x09] +#CHECK: lner %f0, %f15 # encoding: [0x31,0x0f] +#CHECK: lner %f15, %f0 # encoding: [0x31,0xf0] +#CHECK: lner %f15, %f9 # encoding: [0x31,0xf9] + + lner %f0,%f9 + lner %f0,%f15 + lner %f15,%f0 + lner %f15,%f9 + #CHECK: lngfr %r0, %r0 # encoding: [0xb9,0x11,0x00,0x00] #CHECK: lngfr %r0, %r15 # encoding: [0xb9,0x11,0x00,0x0f] #CHECK: lngfr %r15, %r0 # encoding: [0xb9,0x11,0x00,0xf0] @@ -8353,6 +9281,16 @@ lnxbr %f13,%f0 lnxbr %f13,%f9 +#CHECK: lnxr %f0, %f8 # encoding: [0xb3,0x61,0x00,0x08] +#CHECK: lnxr %f0, %f13 # encoding: [0xb3,0x61,0x00,0x0d] +#CHECK: lnxr %f13, %f0 # encoding: [0xb3,0x61,0x00,0xd0] +#CHECK: lnxr %f13, %f9 # encoding: [0xb3,0x61,0x00,0xd9] + + lnxr %f0,%f8 + lnxr %f0,%f13 + lnxr %f13,%f0 + lnxr %f13,%f9 + #CHECK: lpdbr %f0, %f9 # encoding: [0xb3,0x10,0x00,0x09] #CHECK: lpdbr %f0, %f15 # encoding: [0xb3,0x10,0x00,0x0f] #CHECK: lpdbr %f15, %f0 # encoding: [0xb3,0x10,0x00,0xf0] @@ -8363,6 +9301,16 @@ lpdbr %f15,%f0 lpdbr %f15,%f9 +#CHECK: lpdr %f0, %f9 # encoding: [0x20,0x09] +#CHECK: lpdr %f0, %f15 # encoding: [0x20,0x0f] +#CHECK: lpdr %f15, %f0 # encoding: [0x20,0xf0] +#CHECK: lpdr %f15, %f9 # encoding: [0x20,0xf9] + + lpdr %f0,%f9 + lpdr %f0,%f15 + lpdr %f15,%f0 + lpdr %f15,%f9 + #CHECK: lpebr %f0, %f9 # encoding: [0xb3,0x00,0x00,0x09] #CHECK: lpebr %f0, %f15 # encoding: [0xb3,0x00,0x00,0x0f] #CHECK: lpebr %f15, %f0 # encoding: [0xb3,0x00,0x00,0xf0] @@ -8373,6 +9321,16 @@ lpebr %f15,%f0 lpebr %f15,%f9 +#CHECK: lper %f0, %f9 # encoding: [0x30,0x09] +#CHECK: lper %f0, %f15 # encoding: [0x30,0x0f] +#CHECK: lper %f15, %f0 # encoding: [0x30,0xf0] +#CHECK: lper %f15, %f9 # encoding: [0x30,0xf9] + + lper %f0,%f9 + lper %f0,%f15 + lper %f15,%f0 + lper %f15,%f9 + #CHECK: lpgfr %r0, %r0 # encoding: [0xb9,0x10,0x00,0x00] #CHECK: lpgfr %r0, %r15 # encoding: [0xb9,0x10,0x00,0x0f] #CHECK: lpgfr %r15, %r0 # encoding: [0xb9,0x10,0x00,0xf0] @@ -8435,6 +9393,16 @@ lpxbr %f13,%f0 lpxbr %f13,%f9 +#CHECK: lpxr %f0, %f8 # encoding: [0xb3,0x60,0x00,0x08] +#CHECK: lpxr %f0, %f13 # encoding: [0xb3,0x60,0x00,0x0d] +#CHECK: lpxr %f13, %f0 # encoding: [0xb3,0x60,0x00,0xd0] +#CHECK: lpxr %f13, %f9 # encoding: [0xb3,0x60,0x00,0xd9] + + lpxr %f0,%f8 + lpxr %f0,%f13 + lpxr %f13,%f0 + lpxr %f13,%f9 + #CHECK: lr %r0, %r9 # encoding: [0x18,0x09] #CHECK: lr %r0, %r15 # encoding: [0x18,0x0f] #CHECK: lr %r15, %r0 # encoding: [0x18,0xf0] @@ -8445,6 +9413,30 @@ lr %r15,%r0 lr %r15,%r9 +#CHECK: lrdr %f0, %f0 # encoding: [0x25,0x00] +#CHECK: lrdr %f0, %f13 # encoding: [0x25,0x0d] +#CHECK: lrdr %f7, %f8 # encoding: [0x25,0x78] +#CHECK: lrdr %f15, %f0 # encoding: [0x25,0xf0] +#CHECK: lrdr %f15, %f13 # encoding: [0x25,0xfd] + + lrdr %f0, %f0 + lrdr %f0, %f13 + lrdr %f7, %f8 + lrdr %f15, %f0 + lrdr %f15, %f13 + +#CHECK: lrer %f0, %f0 # encoding: [0x35,0x00] +#CHECK: lrer %f0, %f15 # encoding: [0x35,0x0f] +#CHECK: lrer %f7, %f8 # encoding: [0x35,0x78] +#CHECK: lrer %f15, %f0 # encoding: [0x35,0xf0] +#CHECK: lrer %f15, %f15 # encoding: [0x35,0xff] + + lrer %f0, %f0 + lrer %f0, %f15 + lrer %f7, %f8 + lrer %f15, %f0 + lrer %f15, %f15 + #CHECK: lrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0d,A,A,A,A] #CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL lrl %r0, -0x100000000 @@ -8604,6 +9596,26 @@ ltdbr %f15,%f0 ltdbr %f15,%f9 +#CHECK: ltdr %f0, %f9 # encoding: [0x22,0x09] +#CHECK: ltdr %f0, %f15 # encoding: [0x22,0x0f] +#CHECK: ltdr %f15, %f0 # encoding: [0x22,0xf0] +#CHECK: ltdr %f15, %f9 # encoding: [0x22,0xf9] + + ltdr %f0,%f9 + ltdr %f0,%f15 + ltdr %f15,%f0 + ltdr %f15,%f9 + +#CHECK: ltdtr %f0, %f9 # encoding: [0xb3,0xd6,0x00,0x09] +#CHECK: ltdtr %f0, %f15 # encoding: [0xb3,0xd6,0x00,0x0f] +#CHECK: ltdtr %f15, %f0 # encoding: [0xb3,0xd6,0x00,0xf0] +#CHECK: ltdtr %f15, %f9 # encoding: [0xb3,0xd6,0x00,0xf9] + + ltdtr %f0,%f9 + ltdtr %f0,%f15 + ltdtr %f15,%f0 + ltdtr %f15,%f9 + #CHECK: ltebr %f0, %f9 # encoding: [0xb3,0x02,0x00,0x09] #CHECK: ltebr %f0, %f15 # encoding: [0xb3,0x02,0x00,0x0f] #CHECK: ltebr %f15, %f0 # encoding: [0xb3,0x02,0x00,0xf0] @@ -8614,6 +9626,16 @@ ltebr %f15,%f0 ltebr %f15,%f9 +#CHECK: lter %f0, %f9 # encoding: [0x32,0x09] +#CHECK: lter %f0, %f15 # encoding: [0x32,0x0f] +#CHECK: lter %f15, %f0 # encoding: [0x32,0xf0] +#CHECK: lter %f15, %f9 # encoding: [0x32,0xf9] + + lter %f0,%f9 + lter %f0,%f15 + lter %f15,%f0 + lter %f15,%f9 + #CHECK: ltg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x02] #CHECK: ltg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x02] #CHECK: ltg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x02] @@ -8698,6 +9720,136 @@ ltxbr %f13,%f0 ltxbr %f13,%f9 +#CHECK: ltxr %f0, %f9 # encoding: [0xb3,0x62,0x00,0x09] +#CHECK: ltxr %f0, %f13 # encoding: [0xb3,0x62,0x00,0x0d] +#CHECK: ltxr %f13, %f0 # encoding: [0xb3,0x62,0x00,0xd0] +#CHECK: ltxr %f13, %f9 # encoding: [0xb3,0x62,0x00,0xd9] + + ltxr %f0,%f9 + ltxr %f0,%f13 + ltxr %f13,%f0 + ltxr %f13,%f9 + +#CHECK: ltxtr %f0, %f9 # encoding: [0xb3,0xde,0x00,0x09] +#CHECK: ltxtr %f0, %f13 # encoding: [0xb3,0xde,0x00,0x0d] +#CHECK: ltxtr %f13, %f0 # encoding: [0xb3,0xde,0x00,0xd0] +#CHECK: ltxtr %f13, %f9 # encoding: [0xb3,0xde,0x00,0xd9] + + ltxtr %f0,%f9 + ltxtr %f0,%f13 + ltxtr %f13,%f0 + ltxtr %f13,%f9 + +#CHECK: lxd %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x25] +#CHECK: lxd %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x25] +#CHECK: lxd %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x25] +#CHECK: lxd %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x25] +#CHECK: lxd %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x25] +#CHECK: lxd %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x25] + + lxd %f0, 0 + lxd %f0, 4095 + lxd %f0, 0(%r1) + lxd %f0, 0(%r15) + lxd %f0, 4095(%r1,%r15) + lxd %f0, 4095(%r15,%r1) + lxd %f13, 0 + +#CHECK: lxdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x05] +#CHECK: lxdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x05] +#CHECK: lxdb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x05] +#CHECK: lxdb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x05] +#CHECK: lxdb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x05] +#CHECK: lxdb %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x05] + + lxdb %f0, 0 + lxdb %f0, 4095 + lxdb %f0, 0(%r1) + lxdb %f0, 0(%r15) + lxdb %f0, 4095(%r1,%r15) + lxdb %f0, 4095(%r15,%r1) + lxdb %f13, 0 + +#CHECK: lxdbr %f0, %f8 # encoding: [0xb3,0x05,0x00,0x08] +#CHECK: lxdbr %f0, %f13 # encoding: [0xb3,0x05,0x00,0x0d] +#CHECK: lxdbr %f13, %f0 # encoding: [0xb3,0x05,0x00,0xd0] +#CHECK: lxdbr %f13, %f15 # encoding: [0xb3,0x05,0x00,0xdf] + + lxdbr %f0,%f8 + lxdbr %f0,%f13 + lxdbr %f13,%f0 + lxdbr %f13,%f15 + +#CHECK: lxdr %f0, %f8 # encoding: [0xb3,0x25,0x00,0x08] +#CHECK: lxdr %f0, %f13 # encoding: [0xb3,0x25,0x00,0x0d] +#CHECK: lxdr %f13, %f0 # encoding: [0xb3,0x25,0x00,0xd0] +#CHECK: lxdr %f13, %f15 # encoding: [0xb3,0x25,0x00,0xdf] + + lxdr %f0,%f8 + lxdr %f0,%f13 + lxdr %f13,%f0 + lxdr %f13,%f15 + +#CHECK: lxdtr %f0, %f0, 15 # encoding: [0xb3,0xdc,0x0f,0x00] +#CHECK: lxdtr %f0, %f15, 0 # encoding: [0xb3,0xdc,0x00,0x0f] +#CHECK: lxdtr %f5, %f8, 9 # encoding: [0xb3,0xdc,0x09,0x58] +#CHECK: lxdtr %f13, %f0, 0 # encoding: [0xb3,0xdc,0x00,0xd0] + + lxdtr %f0, %f0, 15 + lxdtr %f0, %f15, 0 + lxdtr %f5, %f8, 9 + lxdtr %f13, %f0, 0 + +#CHECK: lxe %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x26] +#CHECK: lxe %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x26] +#CHECK: lxe %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x26] +#CHECK: lxe %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x26] +#CHECK: lxe %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x26] +#CHECK: lxe %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x26] + + lxe %f0, 0 + lxe %f0, 4095 + lxe %f0, 0(%r1) + lxe %f0, 0(%r15) + lxe %f0, 4095(%r1,%r15) + lxe %f0, 4095(%r15,%r1) + lxe %f13, 0 + +#CHECK: lxeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x06] +#CHECK: lxeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x06] +#CHECK: lxeb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x06] +#CHECK: lxeb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x06] +#CHECK: lxeb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x06] +#CHECK: lxeb %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x06] + + lxeb %f0, 0 + lxeb %f0, 4095 + lxeb %f0, 0(%r1) + lxeb %f0, 0(%r15) + lxeb %f0, 4095(%r1,%r15) + lxeb %f0, 4095(%r15,%r1) + lxeb %f13, 0 + +#CHECK: lxebr %f0, %f8 # encoding: [0xb3,0x06,0x00,0x08] +#CHECK: lxebr %f0, %f13 # encoding: [0xb3,0x06,0x00,0x0d] +#CHECK: lxebr %f13, %f0 # encoding: [0xb3,0x06,0x00,0xd0] +#CHECK: lxebr %f13, %f15 # encoding: [0xb3,0x06,0x00,0xdf] + + lxebr %f0,%f8 + lxebr %f0,%f13 + lxebr %f13,%f0 + lxebr %f13,%f15 + +#CHECK: lxer %f0, %f8 # encoding: [0xb3,0x26,0x00,0x08] +#CHECK: lxer %f0, %f13 # encoding: [0xb3,0x26,0x00,0x0d] +#CHECK: lxer %f13, %f0 # encoding: [0xb3,0x26,0x00,0xd0] +#CHECK: lxer %f13, %f15 # encoding: [0xb3,0x26,0x00,0xdf] + + lxer %f0,%f8 + lxer %f0,%f13 + lxer %f13,%f0 + lxer %f13,%f15 + #CHECK: lxr %f0, %f8 # encoding: [0xb3,0x65,0x00,0x08] #CHECK: lxr %f0, %f13 # encoding: [0xb3,0x65,0x00,0x0d] #CHECK: lxr %f13, %f0 # encoding: [0xb3,0x65,0x00,0xd0] @@ -8770,6 +9922,26 @@ m %r0, 4095(%r15,%r1) m %r14, 0 +#CHECK: mad %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3e] +#CHECK: mad %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3e] +#CHECK: mad %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x3e] +#CHECK: mad %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x3e] +#CHECK: mad %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x3e] +#CHECK: mad %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x3e] +#CHECK: mad %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x3e] +#CHECK: mad %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x3e] +#CHECK: mad %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x3e] + + mad %f0, %f0, 0 + mad %f0, %f0, 4095 + mad %f0, %f0, 0(%r1) + mad %f0, %f0, 0(%r15) + mad %f0, %f0, 4095(%r1,%r15) + mad %f0, %f0, 4095(%r15,%r1) + mad %f0, %f15, 0 + mad %f15, %f0, 0 + mad %f15, %f15, 0 + #CHECK: madb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1e] #CHECK: madb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1e] #CHECK: madb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1e] @@ -8804,6 +9976,40 @@ madbr %f7, %f8, %f9 madbr %f15, %f15, %f15 +#CHECK: madr %f0, %f0, %f0 # encoding: [0xb3,0x3e,0x00,0x00] +#CHECK: madr %f0, %f0, %f15 # encoding: [0xb3,0x3e,0x00,0x0f] +#CHECK: madr %f0, %f15, %f0 # encoding: [0xb3,0x3e,0x00,0xf0] +#CHECK: madr %f15, %f0, %f0 # encoding: [0xb3,0x3e,0xf0,0x00] +#CHECK: madr %f7, %f8, %f9 # encoding: [0xb3,0x3e,0x70,0x89] +#CHECK: madr %f15, %f15, %f15 # encoding: [0xb3,0x3e,0xf0,0xff] + + madr %f0, %f0, %f0 + madr %f0, %f0, %f15 + madr %f0, %f15, %f0 + madr %f15, %f0, %f0 + madr %f7, %f8, %f9 + madr %f15, %f15, %f15 + +#CHECK: mae %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x2e] +#CHECK: mae %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x2e] +#CHECK: mae %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x2e] +#CHECK: mae %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x2e] +#CHECK: mae %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x2e] +#CHECK: mae %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x2e] +#CHECK: mae %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x2e] +#CHECK: mae %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x2e] +#CHECK: mae %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x2e] + + mae %f0, %f0, 0 + mae %f0, %f0, 4095 + mae %f0, %f0, 0(%r1) + mae %f0, %f0, 0(%r15) + mae %f0, %f0, 4095(%r1,%r15) + mae %f0, %f0, 4095(%r15,%r1) + mae %f0, %f15, 0 + mae %f15, %f0, 0 + mae %f15, %f15, 0 + #CHECK: maeb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0e] #CHECK: maeb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0e] #CHECK: maeb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0e] @@ -8838,6 +10044,122 @@ maebr %f7, %f8, %f9 maebr %f15, %f15, %f15 +#CHECK: maer %f0, %f0, %f0 # encoding: [0xb3,0x2e,0x00,0x00] +#CHECK: maer %f0, %f0, %f15 # encoding: [0xb3,0x2e,0x00,0x0f] +#CHECK: maer %f0, %f15, %f0 # encoding: [0xb3,0x2e,0x00,0xf0] +#CHECK: maer %f15, %f0, %f0 # encoding: [0xb3,0x2e,0xf0,0x00] +#CHECK: maer %f7, %f8, %f9 # encoding: [0xb3,0x2e,0x70,0x89] +#CHECK: maer %f15, %f15, %f15 # encoding: [0xb3,0x2e,0xf0,0xff] + + maer %f0, %f0, %f0 + maer %f0, %f0, %f15 + maer %f0, %f15, %f0 + maer %f15, %f0, %f0 + maer %f7, %f8, %f9 + maer %f15, %f15, %f15 + +#CHECK: may %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3a] +#CHECK: may %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3a] +#CHECK: may %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x3a] +#CHECK: may %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x3a] +#CHECK: may %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x3a] +#CHECK: may %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x3a] +#CHECK: may %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x3a] +#CHECK: may %f13, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0x3a] +#CHECK: may %f13, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xd0,0x3a] + + may %f0, %f0, 0 + may %f0, %f0, 4095 + may %f0, %f0, 0(%r1) + may %f0, %f0, 0(%r15) + may %f0, %f0, 4095(%r1,%r15) + may %f0, %f0, 4095(%r15,%r1) + may %f0, %f15, 0 + may %f13, %f0, 0 + may %f13, %f15, 0 + +#CHECK: mayh %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3c] +#CHECK: mayh %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3c] +#CHECK: mayh %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x3c] +#CHECK: mayh %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x3c] +#CHECK: mayh %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x3c] +#CHECK: mayh %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x3c] +#CHECK: mayh %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x3c] +#CHECK: mayh %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x3c] +#CHECK: mayh %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x3c] + + mayh %f0, %f0, 0 + mayh %f0, %f0, 4095 + mayh %f0, %f0, 0(%r1) + mayh %f0, %f0, 0(%r15) + mayh %f0, %f0, 4095(%r1,%r15) + mayh %f0, %f0, 4095(%r15,%r1) + mayh %f0, %f15, 0 + mayh %f15, %f0, 0 + mayh %f15, %f15, 0 + +#CHECK: mayhr %f0, %f0, %f0 # encoding: [0xb3,0x3c,0x00,0x00] +#CHECK: mayhr %f0, %f0, %f15 # encoding: [0xb3,0x3c,0x00,0x0f] +#CHECK: mayhr %f0, %f15, %f0 # encoding: [0xb3,0x3c,0x00,0xf0] +#CHECK: mayhr %f15, %f0, %f0 # encoding: [0xb3,0x3c,0xf0,0x00] +#CHECK: mayhr %f7, %f8, %f9 # encoding: [0xb3,0x3c,0x70,0x89] +#CHECK: mayhr %f15, %f15, %f15 # encoding: [0xb3,0x3c,0xf0,0xff] + + mayhr %f0, %f0, %f0 + mayhr %f0, %f0, %f15 + mayhr %f0, %f15, %f0 + mayhr %f15, %f0, %f0 + mayhr %f7, %f8, %f9 + mayhr %f15, %f15, %f15 + +#CHECK: mayl %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x38] +#CHECK: mayl %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x38] +#CHECK: mayl %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x38] +#CHECK: mayl %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x38] +#CHECK: mayl %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x38] +#CHECK: mayl %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x38] +#CHECK: mayl %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x38] +#CHECK: mayl %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x38] +#CHECK: mayl %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x38] + + mayl %f0, %f0, 0 + mayl %f0, %f0, 4095 + mayl %f0, %f0, 0(%r1) + mayl %f0, %f0, 0(%r15) + mayl %f0, %f0, 4095(%r1,%r15) + mayl %f0, %f0, 4095(%r15,%r1) + mayl %f0, %f15, 0 + mayl %f15, %f0, 0 + mayl %f15, %f15, 0 + +#CHECK: maylr %f0, %f0, %f0 # encoding: [0xb3,0x38,0x00,0x00] +#CHECK: maylr %f0, %f0, %f15 # encoding: [0xb3,0x38,0x00,0x0f] +#CHECK: maylr %f0, %f15, %f0 # encoding: [0xb3,0x38,0x00,0xf0] +#CHECK: maylr %f15, %f0, %f0 # encoding: [0xb3,0x38,0xf0,0x00] +#CHECK: maylr %f7, %f8, %f9 # encoding: [0xb3,0x38,0x70,0x89] +#CHECK: maylr %f15, %f15, %f15 # encoding: [0xb3,0x38,0xf0,0xff] + + maylr %f0, %f0, %f0 + maylr %f0, %f0, %f15 + maylr %f0, %f15, %f0 + maylr %f15, %f0, %f0 + maylr %f7, %f8, %f9 + maylr %f15, %f15, %f15 + +#CHECK: mayr %f0, %f0, %f0 # encoding: [0xb3,0x3a,0x00,0x00] +#CHECK: mayr %f0, %f0, %f15 # encoding: [0xb3,0x3a,0x00,0x0f] +#CHECK: mayr %f0, %f15, %f0 # encoding: [0xb3,0x3a,0x00,0xf0] +#CHECK: mayr %f13, %f0, %f0 # encoding: [0xb3,0x3a,0xd0,0x00] +#CHECK: mayr %f5, %f8, %f9 # encoding: [0xb3,0x3a,0x50,0x89] +#CHECK: mayr %f13, %f15, %f15 # encoding: [0xb3,0x3a,0xd0,0xff] + + mayr %f0, %f0, %f0 + mayr %f0, %f0, %f15 + mayr %f0, %f15, %f0 + mayr %f13, %f0, %f0 + mayr %f5, %f8, %f9 + mayr %f13, %f15, %f15 + #CHECK: mc 0, 0 # encoding: [0xaf,0x00,0x00,0x00] #CHECK: mc 4095, 0 # encoding: [0xaf,0x00,0x0f,0xff] #CHECK: mc 0, 255 # encoding: [0xaf,0xff,0x00,0x00] @@ -8854,6 +10176,22 @@ mc 4095(%r1), 42 mc 4095(%r15), 42 +#CHECK: md %f0, 0 # encoding: [0x6c,0x00,0x00,0x00] +#CHECK: md %f0, 4095 # encoding: [0x6c,0x00,0x0f,0xff] +#CHECK: md %f0, 0(%r1) # encoding: [0x6c,0x00,0x10,0x00] +#CHECK: md %f0, 0(%r15) # encoding: [0x6c,0x00,0xf0,0x00] +#CHECK: md %f0, 4095(%r1,%r15) # encoding: [0x6c,0x01,0xff,0xff] +#CHECK: md %f0, 4095(%r15,%r1) # encoding: [0x6c,0x0f,0x1f,0xff] +#CHECK: md %f15, 0 # encoding: [0x6c,0xf0,0x00,0x00] + + md %f0, 0 + md %f0, 4095 + md %f0, 0(%r1) + md %f0, 0(%r15) + md %f0, 4095(%r1,%r15) + md %f0, 4095(%r15,%r1) + md %f15, 0 + #CHECK: mdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1c] #CHECK: mdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1c] #CHECK: mdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1c] @@ -8880,6 +10218,22 @@ mdbr %f7, %f8 mdbr %f15, %f0 +#CHECK: mde %f0, 0 # encoding: [0x7c,0x00,0x00,0x00] +#CHECK: mde %f0, 4095 # encoding: [0x7c,0x00,0x0f,0xff] +#CHECK: mde %f0, 0(%r1) # encoding: [0x7c,0x00,0x10,0x00] +#CHECK: mde %f0, 0(%r15) # encoding: [0x7c,0x00,0xf0,0x00] +#CHECK: mde %f0, 4095(%r1,%r15) # encoding: [0x7c,0x01,0xff,0xff] +#CHECK: mde %f0, 4095(%r15,%r1) # encoding: [0x7c,0x0f,0x1f,0xff] +#CHECK: mde %f15, 0 # encoding: [0x7c,0xf0,0x00,0x00] + + mde %f0, 0 + mde %f0, 4095 + mde %f0, 0(%r1) + mde %f0, 0(%r15) + mde %f0, 4095(%r1,%r15) + mde %f0, 4095(%r15,%r1) + mde %f15, 0 + #CHECK: mdeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0c] #CHECK: mdeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0c] #CHECK: mdeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0c] @@ -8906,6 +10260,70 @@ mdebr %f7, %f8 mdebr %f15, %f0 +#CHECK: mder %f0, %f0 # encoding: [0x3c,0x00] +#CHECK: mder %f0, %f15 # encoding: [0x3c,0x0f] +#CHECK: mder %f7, %f8 # encoding: [0x3c,0x78] +#CHECK: mder %f15, %f0 # encoding: [0x3c,0xf0] + + mder %f0, %f0 + mder %f0, %f15 + mder %f7, %f8 + mder %f15, %f0 + +#CHECK: mdr %f0, %f0 # encoding: [0x2c,0x00] +#CHECK: mdr %f0, %f15 # encoding: [0x2c,0x0f] +#CHECK: mdr %f7, %f8 # encoding: [0x2c,0x78] +#CHECK: mdr %f15, %f0 # encoding: [0x2c,0xf0] + + mdr %f0, %f0 + mdr %f0, %f15 + mdr %f7, %f8 + mdr %f15, %f0 + +#CHECK: mdtr %f0, %f0, %f0 # encoding: [0xb3,0xd0,0x00,0x00] +#CHECK: mdtr %f0, %f0, %f15 # encoding: [0xb3,0xd0,0xf0,0x00] +#CHECK: mdtr %f0, %f15, %f0 # encoding: [0xb3,0xd0,0x00,0x0f] +#CHECK: mdtr %f15, %f0, %f0 # encoding: [0xb3,0xd0,0x00,0xf0] +#CHECK: mdtr %f7, %f8, %f9 # encoding: [0xb3,0xd0,0x90,0x78] + + mdtr %f0, %f0, %f0 + mdtr %f0, %f0, %f15 + mdtr %f0, %f15, %f0 + mdtr %f15, %f0, %f0 + mdtr %f7, %f8, %f9 + +#CHECK: me %f0, 0 # encoding: [0x7c,0x00,0x00,0x00] +#CHECK: me %f0, 4095 # encoding: [0x7c,0x00,0x0f,0xff] +#CHECK: me %f0, 0(%r1) # encoding: [0x7c,0x00,0x10,0x00] +#CHECK: me %f0, 0(%r15) # encoding: [0x7c,0x00,0xf0,0x00] +#CHECK: me %f0, 4095(%r1,%r15) # encoding: [0x7c,0x01,0xff,0xff] +#CHECK: me %f0, 4095(%r15,%r1) # encoding: [0x7c,0x0f,0x1f,0xff] +#CHECK: me %f15, 0 # encoding: [0x7c,0xf0,0x00,0x00] + + me %f0, 0 + me %f0, 4095 + me %f0, 0(%r1) + me %f0, 0(%r15) + me %f0, 4095(%r1,%r15) + me %f0, 4095(%r15,%r1) + me %f15, 0 + +#CHECK: mee %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x37] +#CHECK: mee %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x37] +#CHECK: mee %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x37] +#CHECK: mee %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x37] +#CHECK: mee %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x37] +#CHECK: mee %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x37] +#CHECK: mee %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x37] + + mee %f0, 0 + mee %f0, 4095 + mee %f0, 0(%r1) + mee %f0, 0(%r15) + mee %f0, 4095(%r1,%r15) + mee %f0, 4095(%r15,%r1) + mee %f15, 0 + #CHECK: meeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x17] #CHECK: meeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x17] #CHECK: meeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x17] @@ -8932,6 +10350,26 @@ meebr %f7, %f8 meebr %f15, %f0 +#CHECK: meer %f0, %f0 # encoding: [0xb3,0x37,0x00,0x00] +#CHECK: meer %f0, %f15 # encoding: [0xb3,0x37,0x00,0x0f] +#CHECK: meer %f7, %f8 # encoding: [0xb3,0x37,0x00,0x78] +#CHECK: meer %f15, %f0 # encoding: [0xb3,0x37,0x00,0xf0] + + meer %f0, %f0 + meer %f0, %f15 + meer %f7, %f8 + meer %f15, %f0 + +#CHECK: mer %f0, %f0 # encoding: [0x3c,0x00] +#CHECK: mer %f0, %f15 # encoding: [0x3c,0x0f] +#CHECK: mer %f7, %f8 # encoding: [0x3c,0x78] +#CHECK: mer %f15, %f0 # encoding: [0x3c,0xf0] + + mer %f0, %f0 + mer %f0, %f15 + mer %f7, %f8 + mer %f15, %f0 + #CHECK: mfy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5c] #CHECK: mfy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5c] #CHECK: mfy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5c] @@ -9140,6 +10578,26 @@ ms %r0, 4095(%r15,%r1) ms %r15, 0 +#CHECK: msd %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3f] +#CHECK: msd %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3f] +#CHECK: msd %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x3f] +#CHECK: msd %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x3f] +#CHECK: msd %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x3f] +#CHECK: msd %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x3f] +#CHECK: msd %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x3f] +#CHECK: msd %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x3f] +#CHECK: msd %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x3f] + + msd %f0, %f0, 0 + msd %f0, %f0, 4095 + msd %f0, %f0, 0(%r1) + msd %f0, %f0, 0(%r15) + msd %f0, %f0, 4095(%r1,%r15) + msd %f0, %f0, 4095(%r15,%r1) + msd %f0, %f15, 0 + msd %f15, %f0, 0 + msd %f15, %f15, 0 + #CHECK: msdb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1f] #CHECK: msdb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1f] #CHECK: msdb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1f] @@ -9174,6 +10632,40 @@ msdbr %f7, %f8, %f9 msdbr %f15, %f15, %f15 +#CHECK: msdr %f0, %f0, %f0 # encoding: [0xb3,0x3f,0x00,0x00] +#CHECK: msdr %f0, %f0, %f15 # encoding: [0xb3,0x3f,0x00,0x0f] +#CHECK: msdr %f0, %f15, %f0 # encoding: [0xb3,0x3f,0x00,0xf0] +#CHECK: msdr %f15, %f0, %f0 # encoding: [0xb3,0x3f,0xf0,0x00] +#CHECK: msdr %f7, %f8, %f9 # encoding: [0xb3,0x3f,0x70,0x89] +#CHECK: msdr %f15, %f15, %f15 # encoding: [0xb3,0x3f,0xf0,0xff] + + msdr %f0, %f0, %f0 + msdr %f0, %f0, %f15 + msdr %f0, %f15, %f0 + msdr %f15, %f0, %f0 + msdr %f7, %f8, %f9 + msdr %f15, %f15, %f15 + +#CHECK: mse %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x2f] +#CHECK: mse %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x2f] +#CHECK: mse %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x2f] +#CHECK: mse %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x2f] +#CHECK: mse %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x2f] +#CHECK: mse %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x2f] +#CHECK: mse %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x2f] +#CHECK: mse %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x2f] +#CHECK: mse %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x2f] + + mse %f0, %f0, 0 + mse %f0, %f0, 4095 + mse %f0, %f0, 0(%r1) + mse %f0, %f0, 0(%r15) + mse %f0, %f0, 4095(%r1,%r15) + mse %f0, %f0, 4095(%r15,%r1) + mse %f0, %f15, 0 + mse %f15, %f0, 0 + mse %f15, %f15, 0 + #CHECK: mseb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0f] #CHECK: mseb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0f] #CHECK: mseb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0f] @@ -9208,6 +10700,20 @@ msebr %f7, %f8, %f9 msebr %f15, %f15, %f15 +#CHECK: mser %f0, %f0, %f0 # encoding: [0xb3,0x2f,0x00,0x00] +#CHECK: mser %f0, %f0, %f15 # encoding: [0xb3,0x2f,0x00,0x0f] +#CHECK: mser %f0, %f15, %f0 # encoding: [0xb3,0x2f,0x00,0xf0] +#CHECK: mser %f15, %f0, %f0 # encoding: [0xb3,0x2f,0xf0,0x00] +#CHECK: mser %f7, %f8, %f9 # encoding: [0xb3,0x2f,0x70,0x89] +#CHECK: mser %f15, %f15, %f15 # encoding: [0xb3,0x2f,0xf0,0xff] + + mser %f0, %f0, %f0 + mser %f0, %f0, %f15 + mser %f0, %f15, %f0 + mser %f15, %f0, %f0 + mser %f7, %f8, %f9 + mser %f15, %f15, %f15 + #CHECK: msfi %r0, -2147483648 # encoding: [0xc2,0x01,0x80,0x00,0x00,0x00] #CHECK: msfi %r0, -1 # encoding: [0xc2,0x01,0xff,0xff,0xff,0xff] #CHECK: msfi %r0, 0 # encoding: [0xc2,0x01,0x00,0x00,0x00,0x00] @@ -9672,6 +11178,22 @@ mxbr %f8, %f5 mxbr %f13, %f13 +#CHECK: mxd %f0, 0 # encoding: [0x67,0x00,0x00,0x00] +#CHECK: mxd %f0, 4095 # encoding: [0x67,0x00,0x0f,0xff] +#CHECK: mxd %f0, 0(%r1) # encoding: [0x67,0x00,0x10,0x00] +#CHECK: mxd %f0, 0(%r15) # encoding: [0x67,0x00,0xf0,0x00] +#CHECK: mxd %f0, 4095(%r1,%r15) # encoding: [0x67,0x01,0xff,0xff] +#CHECK: mxd %f0, 4095(%r15,%r1) # encoding: [0x67,0x0f,0x1f,0xff] +#CHECK: mxd %f13, 0 # encoding: [0x67,0xd0,0x00,0x00] + + mxd %f0, 0 + mxd %f0, 4095 + mxd %f0, 0(%r1) + mxd %f0, 0(%r15) + mxd %f0, 4095(%r1,%r15) + mxd %f0, 4095(%r15,%r1) + mxd %f13, 0 + #CHECK: mxdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x07] #CHECK: mxdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x07] #CHECK: mxdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x07] @@ -9698,6 +11220,140 @@ mxdbr %f8, %f8 mxdbr %f13, %f0 +#CHECK: mxdr %f0, %f0 # encoding: [0x27,0x00] +#CHECK: mxdr %f0, %f15 # encoding: [0x27,0x0f] +#CHECK: mxdr %f8, %f8 # encoding: [0x27,0x88] +#CHECK: mxdr %f13, %f0 # encoding: [0x27,0xd0] + + mxdr %f0, %f0 + mxdr %f0, %f15 + mxdr %f8, %f8 + mxdr %f13, %f0 + +#CHECK: mxr %f0, %f0 # encoding: [0x26,0x00] +#CHECK: mxr %f0, %f13 # encoding: [0x26,0x0d] +#CHECK: mxr %f8, %f5 # encoding: [0x26,0x85] +#CHECK: mxr %f13, %f13 # encoding: [0x26,0xdd] + + mxr %f0, %f0 + mxr %f0, %f13 + mxr %f8, %f5 + mxr %f13, %f13 + +#CHECK: mxtr %f0, %f0, %f0 # encoding: [0xb3,0xd8,0x00,0x00] +#CHECK: mxtr %f0, %f0, %f13 # encoding: [0xb3,0xd8,0xd0,0x00] +#CHECK: mxtr %f0, %f13, %f0 # encoding: [0xb3,0xd8,0x00,0x0d] +#CHECK: mxtr %f13, %f0, %f0 # encoding: [0xb3,0xd8,0x00,0xd0] +#CHECK: mxtr %f8, %f8, %f8 # encoding: [0xb3,0xd8,0x80,0x88] + + mxtr %f0, %f0, %f0 + mxtr %f0, %f0, %f13 + mxtr %f0, %f13, %f0 + mxtr %f13, %f0, %f0 + mxtr %f8, %f8, %f8 + +#CHECK: my %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3b] +#CHECK: my %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3b] +#CHECK: my %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x3b] +#CHECK: my %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x3b] +#CHECK: my %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x3b] +#CHECK: my %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x3b] +#CHECK: my %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x3b] +#CHECK: my %f13, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0x3b] +#CHECK: my %f13, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xd0,0x3b] + + my %f0, %f0, 0 + my %f0, %f0, 4095 + my %f0, %f0, 0(%r1) + my %f0, %f0, 0(%r15) + my %f0, %f0, 4095(%r1,%r15) + my %f0, %f0, 4095(%r15,%r1) + my %f0, %f15, 0 + my %f13, %f0, 0 + my %f13, %f15, 0 + +#CHECK: myh %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3d] +#CHECK: myh %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3d] +#CHECK: myh %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x3d] +#CHECK: myh %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x3d] +#CHECK: myh %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x3d] +#CHECK: myh %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x3d] +#CHECK: myh %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x3d] +#CHECK: myh %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x3d] +#CHECK: myh %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x3d] + + myh %f0, %f0, 0 + myh %f0, %f0, 4095 + myh %f0, %f0, 0(%r1) + myh %f0, %f0, 0(%r15) + myh %f0, %f0, 4095(%r1,%r15) + myh %f0, %f0, 4095(%r15,%r1) + myh %f0, %f15, 0 + myh %f15, %f0, 0 + myh %f15, %f15, 0 + +#CHECK: myhr %f0, %f0, %f0 # encoding: [0xb3,0x3d,0x00,0x00] +#CHECK: myhr %f0, %f0, %f15 # encoding: [0xb3,0x3d,0x00,0x0f] +#CHECK: myhr %f0, %f15, %f0 # encoding: [0xb3,0x3d,0x00,0xf0] +#CHECK: myhr %f15, %f0, %f0 # encoding: [0xb3,0x3d,0xf0,0x00] +#CHECK: myhr %f7, %f8, %f9 # encoding: [0xb3,0x3d,0x70,0x89] +#CHECK: myhr %f15, %f15, %f15 # encoding: [0xb3,0x3d,0xf0,0xff] + + myhr %f0, %f0, %f0 + myhr %f0, %f0, %f15 + myhr %f0, %f15, %f0 + myhr %f15, %f0, %f0 + myhr %f7, %f8, %f9 + myhr %f15, %f15, %f15 + +#CHECK: myl %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x39] +#CHECK: myl %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x39] +#CHECK: myl %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x39] +#CHECK: myl %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x39] +#CHECK: myl %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x39] +#CHECK: myl %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x39] +#CHECK: myl %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x39] +#CHECK: myl %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x39] +#CHECK: myl %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x39] + + myl %f0, %f0, 0 + myl %f0, %f0, 4095 + myl %f0, %f0, 0(%r1) + myl %f0, %f0, 0(%r15) + myl %f0, %f0, 4095(%r1,%r15) + myl %f0, %f0, 4095(%r15,%r1) + myl %f0, %f15, 0 + myl %f15, %f0, 0 + myl %f15, %f15, 0 + +#CHECK: mylr %f0, %f0, %f0 # encoding: [0xb3,0x39,0x00,0x00] +#CHECK: mylr %f0, %f0, %f15 # encoding: [0xb3,0x39,0x00,0x0f] +#CHECK: mylr %f0, %f15, %f0 # encoding: [0xb3,0x39,0x00,0xf0] +#CHECK: mylr %f15, %f0, %f0 # encoding: [0xb3,0x39,0xf0,0x00] +#CHECK: mylr %f7, %f8, %f9 # encoding: [0xb3,0x39,0x70,0x89] +#CHECK: mylr %f15, %f15, %f15 # encoding: [0xb3,0x39,0xf0,0xff] + + mylr %f0, %f0, %f0 + mylr %f0, %f0, %f15 + mylr %f0, %f15, %f0 + mylr %f15, %f0, %f0 + mylr %f7, %f8, %f9 + mylr %f15, %f15, %f15 + +#CHECK: myr %f0, %f0, %f0 # encoding: [0xb3,0x3b,0x00,0x00] +#CHECK: myr %f0, %f0, %f15 # encoding: [0xb3,0x3b,0x00,0x0f] +#CHECK: myr %f0, %f15, %f0 # encoding: [0xb3,0x3b,0x00,0xf0] +#CHECK: myr %f13, %f0, %f0 # encoding: [0xb3,0x3b,0xd0,0x00] +#CHECK: myr %f5, %f8, %f9 # encoding: [0xb3,0x3b,0x50,0x89] +#CHECK: myr %f13, %f15, %f15 # encoding: [0xb3,0x3b,0xd0,0xff] + + myr %f0, %f0, %f0 + myr %f0, %f0, %f15 + myr %f0, %f15, %f0 + myr %f13, %f0, %f0 + myr %f5, %f8, %f9 + myr %f13, %f15, %f15 + #CHECK: n %r0, 0 # encoding: [0x54,0x00,0x00,0x00] #CHECK: n %r0, 4095 # encoding: [0x54,0x00,0x0f,0xff] #CHECK: n %r0, 0(%r1) # encoding: [0x54,0x00,0x10,0x00] @@ -10193,6 +11849,9 @@ pfdrl 7, frob@PLT pfdrl 8, frob@PLT +#CHECK: pfpo # encoding: [0x01,0x0a] + pfpo + #CHECK: pka 0, 0(1) # encoding: [0xe9,0x00,0x00,0x00,0x00,0x00] #CHECK: pka 0, 0(1,%r1) # encoding: [0xe9,0x00,0x00,0x00,0x10,0x00] #CHECK: pka 0, 0(1,%r15) # encoding: [0xe9,0x00,0x00,0x00,0xf0,0x00] @@ -10262,6 +11921,34 @@ #CHECK: pr # encoding: [0x01,0x01] pr +#CHECK: qadtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xf5,0x00,0x00] +#CHECK: qadtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xf5,0x0f,0x00] +#CHECK: qadtr %f0, %f0, %f15, 0 # encoding: [0xb3,0xf5,0x00,0x0f] +#CHECK: qadtr %f0, %f15, %f0, 0 # encoding: [0xb3,0xf5,0xf0,0x00] +#CHECK: qadtr %f4, %f5, %f6, 7 # encoding: [0xb3,0xf5,0x57,0x46] +#CHECK: qadtr %f15, %f0, %f0, 0 # encoding: [0xb3,0xf5,0x00,0xf0] + + qadtr %f0, %f0, %f0, 0 + qadtr %f0, %f0, %f0, 15 + qadtr %f0, %f0, %f15, 0 + qadtr %f0, %f15, %f0, 0 + qadtr %f4, %f5, %f6, 7 + qadtr %f15, %f0, %f0, 0 + +#CHECK: qaxtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xfd,0x00,0x00] +#CHECK: qaxtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xfd,0x0f,0x00] +#CHECK: qaxtr %f0, %f0, %f13, 0 # encoding: [0xb3,0xfd,0x00,0x0d] +#CHECK: qaxtr %f0, %f13, %f0, 0 # encoding: [0xb3,0xfd,0xd0,0x00] +#CHECK: qaxtr %f8, %f8, %f8, 8 # encoding: [0xb3,0xfd,0x88,0x88] +#CHECK: qaxtr %f13, %f0, %f0, 0 # encoding: [0xb3,0xfd,0x00,0xd0] + + qaxtr %f0, %f0, %f0, 0 + qaxtr %f0, %f0, %f0, 15 + qaxtr %f0, %f0, %f13, 0 + qaxtr %f0, %f13, %f0, 0 + qaxtr %f8, %f8, %f8, 8 + qaxtr %f13, %f0, %f0, 0 + #CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55] #CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55] #CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] @@ -10362,6 +12049,34 @@ rosbg %r15,%r0,0,0,0 rosbg %r4,%r5,6,7,8 +#CHECK: rrdtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xf7,0x00,0x00] +#CHECK: rrdtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xf7,0x0f,0x00] +#CHECK: rrdtr %f0, %f0, %f15, 0 # encoding: [0xb3,0xf7,0x00,0x0f] +#CHECK: rrdtr %f0, %f15, %f0, 0 # encoding: [0xb3,0xf7,0xf0,0x00] +#CHECK: rrdtr %f4, %f5, %f6, 7 # encoding: [0xb3,0xf7,0x57,0x46] +#CHECK: rrdtr %f15, %f0, %f0, 0 # encoding: [0xb3,0xf7,0x00,0xf0] + + rrdtr %f0, %f0, %f0, 0 + rrdtr %f0, %f0, %f0, 15 + rrdtr %f0, %f0, %f15, 0 + rrdtr %f0, %f15, %f0, 0 + rrdtr %f4, %f5, %f6, 7 + rrdtr %f15, %f0, %f0, 0 + +#CHECK: rrxtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xff,0x00,0x00] +#CHECK: rrxtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xff,0x0f,0x00] +#CHECK: rrxtr %f0, %f0, %f13, 0 # encoding: [0xb3,0xff,0x00,0x0d] +#CHECK: rrxtr %f0, %f13, %f0, 0 # encoding: [0xb3,0xff,0xd0,0x00] +#CHECK: rrxtr %f8, %f8, %f8, 8 # encoding: [0xb3,0xff,0x88,0x88] +#CHECK: rrxtr %f13, %f0, %f0, 0 # encoding: [0xb3,0xff,0x00,0xd0] + + rrxtr %f0, %f0, %f0, 0 + rrxtr %f0, %f0, %f0, 15 + rrxtr %f0, %f0, %f13, 0 + rrxtr %f0, %f13, %f0, 0 + rrxtr %f8, %f8, %f8, 8 + rrxtr %f13, %f0, %f0, 0 + #CHECK: rxsbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x57] #CHECK: rxsbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x57] #CHECK: rxsbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x57] @@ -10414,6 +12129,22 @@ sar %a7, %r8 sar %a15, %r15 +#CHECK: sd %f0, 0 # encoding: [0x6b,0x00,0x00,0x00] +#CHECK: sd %f0, 4095 # encoding: [0x6b,0x00,0x0f,0xff] +#CHECK: sd %f0, 0(%r1) # encoding: [0x6b,0x00,0x10,0x00] +#CHECK: sd %f0, 0(%r15) # encoding: [0x6b,0x00,0xf0,0x00] +#CHECK: sd %f0, 4095(%r1,%r15) # encoding: [0x6b,0x01,0xff,0xff] +#CHECK: sd %f0, 4095(%r15,%r1) # encoding: [0x6b,0x0f,0x1f,0xff] +#CHECK: sd %f15, 0 # encoding: [0x6b,0xf0,0x00,0x00] + + sd %f0, 0 + sd %f0, 4095 + sd %f0, 0(%r1) + sd %f0, 0(%r15) + sd %f0, 4095(%r1,%r15) + sd %f0, 4095(%r15,%r1) + sd %f15, 0 + #CHECK: sdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1b] #CHECK: sdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1b] #CHECK: sdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1b] @@ -10440,6 +12171,44 @@ sdbr %f7, %f8 sdbr %f15, %f0 +#CHECK: sdr %f0, %f0 # encoding: [0x2b,0x00] +#CHECK: sdr %f0, %f15 # encoding: [0x2b,0x0f] +#CHECK: sdr %f7, %f8 # encoding: [0x2b,0x78] +#CHECK: sdr %f15, %f0 # encoding: [0x2b,0xf0] + + sdr %f0, %f0 + sdr %f0, %f15 + sdr %f7, %f8 + sdr %f15, %f0 + +#CHECK: sdtr %f0, %f0, %f0 # encoding: [0xb3,0xd3,0x00,0x00] +#CHECK: sdtr %f0, %f0, %f15 # encoding: [0xb3,0xd3,0xf0,0x00] +#CHECK: sdtr %f0, %f15, %f0 # encoding: [0xb3,0xd3,0x00,0x0f] +#CHECK: sdtr %f15, %f0, %f0 # encoding: [0xb3,0xd3,0x00,0xf0] +#CHECK: sdtr %f7, %f8, %f9 # encoding: [0xb3,0xd3,0x90,0x78] + + sdtr %f0, %f0, %f0 + sdtr %f0, %f0, %f15 + sdtr %f0, %f15, %f0 + sdtr %f15, %f0, %f0 + sdtr %f7, %f8, %f9 + +#CHECK: se %f0, 0 # encoding: [0x7b,0x00,0x00,0x00] +#CHECK: se %f0, 4095 # encoding: [0x7b,0x00,0x0f,0xff] +#CHECK: se %f0, 0(%r1) # encoding: [0x7b,0x00,0x10,0x00] +#CHECK: se %f0, 0(%r15) # encoding: [0x7b,0x00,0xf0,0x00] +#CHECK: se %f0, 4095(%r1,%r15) # encoding: [0x7b,0x01,0xff,0xff] +#CHECK: se %f0, 4095(%r15,%r1) # encoding: [0x7b,0x0f,0x1f,0xff] +#CHECK: se %f15, 0 # encoding: [0x7b,0xf0,0x00,0x00] + + se %f0, 0 + se %f0, 4095 + se %f0, 0(%r1) + se %f0, 0(%r15) + se %f0, 4095(%r1,%r15) + se %f0, 4095(%r15,%r1) + se %f15, 0 + #CHECK: seb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0b] #CHECK: seb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0b] #CHECK: seb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0b] @@ -10466,6 +12235,16 @@ sebr %f7, %f8 sebr %f15, %f0 +#CHECK: ser %f0, %f0 # encoding: [0x3b,0x00] +#CHECK: ser %f0, %f15 # encoding: [0x3b,0x0f] +#CHECK: ser %f7, %f8 # encoding: [0x3b,0x78] +#CHECK: ser %f15, %f0 # encoding: [0x3b,0xf0] + + ser %f0, %f0 + ser %f0, %f15 + ser %f7, %f8 + ser %f15, %f0 + #CHECK: sfasr %r0 # encoding: [0xb3,0x85,0x00,0x00] #CHECK: sfasr %r1 # encoding: [0xb3,0x85,0x00,0x10] #CHECK: sfasr %r15 # encoding: [0xb3,0x85,0x00,0xf0] @@ -10744,6 +12523,26 @@ sldl %r0,4095(%r1) sldl %r0,4095(%r15) +#CHECK: sldt %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x40] +#CHECK: sldt %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x40] +#CHECK: sldt %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x40] +#CHECK: sldt %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x40] +#CHECK: sldt %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x40] +#CHECK: sldt %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x40] +#CHECK: sldt %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x40] +#CHECK: sldt %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x40] +#CHECK: sldt %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x40] + + sldt %f0, %f0, 0 + sldt %f0, %f0, 4095 + sldt %f0, %f0, 0(%r1) + sldt %f0, %f0, 0(%r15) + sldt %f0, %f0, 4095(%r1,%r15) + sldt %f0, %f0, 4095(%r15,%r1) + sldt %f0, %f15, 0 + sldt %f15, %f0, 0 + sldt %f15, %f15, 0 + #CHECK: slfi %r0, 0 # encoding: [0xc2,0x05,0x00,0x00,0x00,0x00] #CHECK: slfi %r0, 4294967295 # encoding: [0xc2,0x05,0xff,0xff,0xff,0xff] #CHECK: slfi %r15, 0 # encoding: [0xc2,0xf5,0x00,0x00,0x00,0x00] @@ -10878,6 +12677,26 @@ slr %r15,%r0 slr %r7,%r8 +#CHECK: slxt %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x48] +#CHECK: slxt %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x48] +#CHECK: slxt %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x48] +#CHECK: slxt %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x48] +#CHECK: slxt %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x48] +#CHECK: slxt %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x48] +#CHECK: slxt %f0, %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x48] +#CHECK: slxt %f13, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0x48] +#CHECK: slxt %f13, %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0xd0,0x48] + + slxt %f0, %f0, 0 + slxt %f0, %f0, 4095 + slxt %f0, %f0, 0(%r1) + slxt %f0, %f0, 0(%r15) + slxt %f0, %f0, 4095(%r1,%r15) + slxt %f0, %f0, 4095(%r15,%r1) + slxt %f0, %f13, 0 + slxt %f13, %f0, 0 + slxt %f13, %f13, 0 + #CHECK: sly %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5f] #CHECK: sly %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5f] #CHECK: sly %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5f] @@ -10938,6 +12757,22 @@ spm %r1 spm %r15 +#CHECK: sqd %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x35] +#CHECK: sqd %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x35] +#CHECK: sqd %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x35] +#CHECK: sqd %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x35] +#CHECK: sqd %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x35] +#CHECK: sqd %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x35] +#CHECK: sqd %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x35] + + sqd %f0, 0 + sqd %f0, 4095 + sqd %f0, 0(%r1) + sqd %f0, 0(%r15) + sqd %f0, 4095(%r1,%r15) + sqd %f0, 4095(%r15,%r1) + sqd %f15, 0 + #CHECK: sqdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x15] #CHECK: sqdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x15] #CHECK: sqdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x15] @@ -10964,6 +12799,32 @@ sqdbr %f7, %f8 sqdbr %f15, %f0 +#CHECK: sqdr %f0, %f0 # encoding: [0xb2,0x44,0x00,0x00] +#CHECK: sqdr %f0, %f15 # encoding: [0xb2,0x44,0x00,0x0f] +#CHECK: sqdr %f7, %f8 # encoding: [0xb2,0x44,0x00,0x78] +#CHECK: sqdr %f15, %f0 # encoding: [0xb2,0x44,0x00,0xf0] + + sqdr %f0, %f0 + sqdr %f0, %f15 + sqdr %f7, %f8 + sqdr %f15, %f0 + +#CHECK: sqe %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x34] +#CHECK: sqe %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x34] +#CHECK: sqe %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x34] +#CHECK: sqe %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x34] +#CHECK: sqe %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x34] +#CHECK: sqe %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x34] +#CHECK: sqe %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x34] + + sqe %f0, 0 + sqe %f0, 4095 + sqe %f0, 0(%r1) + sqe %f0, 0(%r15) + sqe %f0, 4095(%r1,%r15) + sqe %f0, 4095(%r15,%r1) + sqe %f15, 0 + #CHECK: sqeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x14] #CHECK: sqeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x14] #CHECK: sqeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x14] @@ -10990,6 +12851,16 @@ sqebr %f7, %f8 sqebr %f15, %f0 +#CHECK: sqer %f0, %f0 # encoding: [0xb2,0x45,0x00,0x00] +#CHECK: sqer %f0, %f15 # encoding: [0xb2,0x45,0x00,0x0f] +#CHECK: sqer %f7, %f8 # encoding: [0xb2,0x45,0x00,0x78] +#CHECK: sqer %f15, %f0 # encoding: [0xb2,0x45,0x00,0xf0] + + sqer %f0, %f0 + sqer %f0, %f15 + sqer %f7, %f8 + sqer %f15, %f0 + #CHECK: sqxbr %f0, %f0 # encoding: [0xb3,0x16,0x00,0x00] #CHECK: sqxbr %f0, %f13 # encoding: [0xb3,0x16,0x00,0x0d] #CHECK: sqxbr %f8, %f8 # encoding: [0xb3,0x16,0x00,0x88] @@ -11000,6 +12871,16 @@ sqxbr %f8, %f8 sqxbr %f13, %f0 +#CHECK: sqxr %f0, %f0 # encoding: [0xb3,0x36,0x00,0x00] +#CHECK: sqxr %f0, %f13 # encoding: [0xb3,0x36,0x00,0x0d] +#CHECK: sqxr %f8, %f8 # encoding: [0xb3,0x36,0x00,0x88] +#CHECK: sqxr %f13, %f0 # encoding: [0xb3,0x36,0x00,0xd0] + + sqxr %f0, %f0 + sqxr %f0, %f13 + sqxr %f8, %f8 + sqxr %f13, %f0 + #CHECK: sr %r0, %r0 # encoding: [0x1b,0x00] #CHECK: sr %r0, %r15 # encoding: [0x1b,0x0f] #CHECK: sr %r15, %r0 # encoding: [0x1b,0xf0] @@ -11090,6 +12971,26 @@ srdl %r0,4095(%r1) srdl %r0,4095(%r15) +#CHECK: srdt %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x41] +#CHECK: srdt %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x41] +#CHECK: srdt %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x41] +#CHECK: srdt %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x41] +#CHECK: srdt %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x41] +#CHECK: srdt %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x41] +#CHECK: srdt %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x41] +#CHECK: srdt %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x41] +#CHECK: srdt %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x41] + + srdt %f0, %f0, 0 + srdt %f0, %f0, 4095 + srdt %f0, %f0, 0(%r1) + srdt %f0, %f0, 0(%r15) + srdt %f0, %f0, 4095(%r1,%r15) + srdt %f0, %f0, 4095(%r15,%r1) + srdt %f0, %f15, 0 + srdt %f15, %f0, 0 + srdt %f15, %f15, 0 + #CHECK: srl %r0, 0 # encoding: [0x88,0x00,0x00,0x00] #CHECK: srl %r7, 0 # encoding: [0x88,0x70,0x00,0x00] #CHECK: srl %r15, 0 # encoding: [0x88,0xf0,0x00,0x00] @@ -11210,6 +13111,26 @@ srstu %r15,%r0 srstu %r7,%r8 +#CHECK: srxt %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x49] +#CHECK: srxt %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x49] +#CHECK: srxt %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x49] +#CHECK: srxt %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x49] +#CHECK: srxt %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x49] +#CHECK: srxt %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x49] +#CHECK: srxt %f0, %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x49] +#CHECK: srxt %f13, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0x49] +#CHECK: srxt %f13, %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0xd0,0x49] + + srxt %f0, %f0, 0 + srxt %f0, %f0, 4095 + srxt %f0, %f0, 0(%r1) + srxt %f0, %f0, 0(%r15) + srxt %f0, %f0, 4095(%r1,%r15) + srxt %f0, %f0, 4095(%r15,%r1) + srxt %f0, %f13, 0 + srxt %f13, %f0, 0 + srxt %f13, %f13, 0 + #CHECK: st %r0, 0 # encoding: [0x50,0x00,0x00,0x00] #CHECK: st %r0, 4095 # encoding: [0x50,0x00,0x0f,0xff] #CHECK: st %r0, 0(%r1) # encoding: [0x50,0x00,0x10,0x00] @@ -11929,6 +13850,32 @@ sty %r0, 524287(%r15,%r1) sty %r15, 0 +#CHECK: su %f0, 0 # encoding: [0x7f,0x00,0x00,0x00] +#CHECK: su %f0, 4095 # encoding: [0x7f,0x00,0x0f,0xff] +#CHECK: su %f0, 0(%r1) # encoding: [0x7f,0x00,0x10,0x00] +#CHECK: su %f0, 0(%r15) # encoding: [0x7f,0x00,0xf0,0x00] +#CHECK: su %f0, 4095(%r1,%r15) # encoding: [0x7f,0x01,0xff,0xff] +#CHECK: su %f0, 4095(%r15,%r1) # encoding: [0x7f,0x0f,0x1f,0xff] +#CHECK: su %f15, 0 # encoding: [0x7f,0xf0,0x00,0x00] + + su %f0, 0 + su %f0, 4095 + su %f0, 0(%r1) + su %f0, 0(%r15) + su %f0, 4095(%r1,%r15) + su %f0, 4095(%r15,%r1) + su %f15, 0 + +#CHECK: sur %f0, %f0 # encoding: [0x3f,0x00] +#CHECK: sur %f0, %f15 # encoding: [0x3f,0x0f] +#CHECK: sur %f7, %f8 # encoding: [0x3f,0x78] +#CHECK: sur %f15, %f0 # encoding: [0x3f,0xf0] + + sur %f0, %f0 + sur %f0, %f15 + sur %f7, %f8 + sur %f15, %f0 + #CHECK: svc 0 # encoding: [0x0a,0x00] #CHECK: svc 3 # encoding: [0x0a,0x03] #CHECK: svc 128 # encoding: [0x0a,0x80] @@ -11939,6 +13886,32 @@ svc 128 svc 0xff +#CHECK: sw %f0, 0 # encoding: [0x6f,0x00,0x00,0x00] +#CHECK: sw %f0, 4095 # encoding: [0x6f,0x00,0x0f,0xff] +#CHECK: sw %f0, 0(%r1) # encoding: [0x6f,0x00,0x10,0x00] +#CHECK: sw %f0, 0(%r15) # encoding: [0x6f,0x00,0xf0,0x00] +#CHECK: sw %f0, 4095(%r1,%r15) # encoding: [0x6f,0x01,0xff,0xff] +#CHECK: sw %f0, 4095(%r15,%r1) # encoding: [0x6f,0x0f,0x1f,0xff] +#CHECK: sw %f15, 0 # encoding: [0x6f,0xf0,0x00,0x00] + + sw %f0, 0 + sw %f0, 4095 + sw %f0, 0(%r1) + sw %f0, 0(%r15) + sw %f0, 4095(%r1,%r15) + sw %f0, 4095(%r15,%r1) + sw %f15, 0 + +#CHECK: swr %f0, %f0 # encoding: [0x2f,0x00] +#CHECK: swr %f0, %f15 # encoding: [0x2f,0x0f] +#CHECK: swr %f7, %f8 # encoding: [0x2f,0x78] +#CHECK: swr %f15, %f0 # encoding: [0x2f,0xf0] + + swr %f0, %f0 + swr %f0, %f15 + swr %f7, %f8 + swr %f15, %f0 + #CHECK: sxbr %f0, %f0 # encoding: [0xb3,0x4b,0x00,0x00] #CHECK: sxbr %f0, %f13 # encoding: [0xb3,0x4b,0x00,0x0d] #CHECK: sxbr %f8, %f8 # encoding: [0xb3,0x4b,0x00,0x88] @@ -11949,6 +13922,28 @@ sxbr %f8, %f8 sxbr %f13, %f0 +#CHECK: sxr %f0, %f0 # encoding: [0x37,0x00] +#CHECK: sxr %f0, %f13 # encoding: [0x37,0x0d] +#CHECK: sxr %f8, %f8 # encoding: [0x37,0x88] +#CHECK: sxr %f13, %f0 # encoding: [0x37,0xd0] + + sxr %f0, %f0 + sxr %f0, %f13 + sxr %f8, %f8 + sxr %f13, %f0 + +#CHECK: sxtr %f0, %f0, %f0 # encoding: [0xb3,0xdb,0x00,0x00] +#CHECK: sxtr %f0, %f0, %f13 # encoding: [0xb3,0xdb,0xd0,0x00] +#CHECK: sxtr %f0, %f13, %f0 # encoding: [0xb3,0xdb,0x00,0x0d] +#CHECK: sxtr %f13, %f0, %f0 # encoding: [0xb3,0xdb,0x00,0xd0] +#CHECK: sxtr %f8, %f8, %f8 # encoding: [0xb3,0xdb,0x80,0x88] + + sxtr %f0, %f0, %f0 + sxtr %f0, %f0, %f13 + sxtr %f0, %f13, %f0 + sxtr %f13, %f0, %f0 + sxtr %f8, %f8, %f8 + #CHECK: sy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5b] #CHECK: sy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5b] #CHECK: sy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5b] @@ -11975,6 +13970,30 @@ tam +#CHECK: tbdr %f0, 0, %f0 # encoding: [0xb3,0x51,0x00,0x00] +#CHECK: tbdr %f0, 0, %f15 # encoding: [0xb3,0x51,0x00,0x0f] +#CHECK: tbdr %f0, 15, %f0 # encoding: [0xb3,0x51,0xf0,0x00] +#CHECK: tbdr %f4, 5, %f6 # encoding: [0xb3,0x51,0x50,0x46] +#CHECK: tbdr %f15, 0, %f0 # encoding: [0xb3,0x51,0x00,0xf0] + + tbdr %f0, 0, %f0 + tbdr %f0, 0, %f15 + tbdr %f0, 15, %f0 + tbdr %f4, 5, %f6 + tbdr %f15, 0, %f0 + +#CHECK: tbedr %f0, 0, %f0 # encoding: [0xb3,0x50,0x00,0x00] +#CHECK: tbedr %f0, 0, %f15 # encoding: [0xb3,0x50,0x00,0x0f] +#CHECK: tbedr %f0, 15, %f0 # encoding: [0xb3,0x50,0xf0,0x00] +#CHECK: tbedr %f4, 5, %f6 # encoding: [0xb3,0x50,0x50,0x46] +#CHECK: tbedr %f15, 0, %f0 # encoding: [0xb3,0x50,0x00,0xf0] + + tbedr %f0, 0, %f0 + tbedr %f0, 0, %f15 + tbedr %f0, 15, %f0 + tbedr %f4, 5, %f6 + tbedr %f15, 0, %f0 + #CHECK: tcdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x11] #CHECK: tcdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x11] #CHECK: tcdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x11] @@ -12023,6 +14042,122 @@ tcxb %f0, 4095(%r15,%r1) tcxb %f13, 0 +#CHECK: tdcdt %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x54] +#CHECK: tdcdt %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x54] +#CHECK: tdcdt %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x54] +#CHECK: tdcdt %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x54] +#CHECK: tdcdt %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x54] +#CHECK: tdcdt %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x54] +#CHECK: tdcdt %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x54] + + tdcdt %f0, 0 + tdcdt %f0, 4095 + tdcdt %f0, 0(%r1) + tdcdt %f0, 0(%r15) + tdcdt %f0, 4095(%r1,%r15) + tdcdt %f0, 4095(%r15,%r1) + tdcdt %f15, 0 + +#CHECK: tdcet %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x50] +#CHECK: tdcet %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x50] +#CHECK: tdcet %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x50] +#CHECK: tdcet %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x50] +#CHECK: tdcet %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x50] +#CHECK: tdcet %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x50] +#CHECK: tdcet %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x50] + + tdcet %f0, 0 + tdcet %f0, 4095 + tdcet %f0, 0(%r1) + tdcet %f0, 0(%r15) + tdcet %f0, 4095(%r1,%r15) + tdcet %f0, 4095(%r15,%r1) + tdcet %f15, 0 + +#CHECK: tdcxt %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x58] +#CHECK: tdcxt %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x58] +#CHECK: tdcxt %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x58] +#CHECK: tdcxt %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x58] +#CHECK: tdcxt %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x58] +#CHECK: tdcxt %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x58] +#CHECK: tdcxt %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x58] + + tdcxt %f0, 0 + tdcxt %f0, 4095 + tdcxt %f0, 0(%r1) + tdcxt %f0, 0(%r15) + tdcxt %f0, 4095(%r1,%r15) + tdcxt %f0, 4095(%r15,%r1) + tdcxt %f13, 0 + +#CHECK: tdgdt %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x55] +#CHECK: tdgdt %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x55] +#CHECK: tdgdt %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x55] +#CHECK: tdgdt %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x55] +#CHECK: tdgdt %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x55] +#CHECK: tdgdt %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x55] +#CHECK: tdgdt %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x55] + + tdgdt %f0, 0 + tdgdt %f0, 4095 + tdgdt %f0, 0(%r1) + tdgdt %f0, 0(%r15) + tdgdt %f0, 4095(%r1,%r15) + tdgdt %f0, 4095(%r15,%r1) + tdgdt %f15, 0 + +#CHECK: tdget %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x51] +#CHECK: tdget %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x51] +#CHECK: tdget %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x51] +#CHECK: tdget %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x51] +#CHECK: tdget %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x51] +#CHECK: tdget %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x51] +#CHECK: tdget %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x51] + + tdget %f0, 0 + tdget %f0, 4095 + tdget %f0, 0(%r1) + tdget %f0, 0(%r15) + tdget %f0, 4095(%r1,%r15) + tdget %f0, 4095(%r15,%r1) + tdget %f15, 0 + +#CHECK: tdgxt %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x59] +#CHECK: tdgxt %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x59] +#CHECK: tdgxt %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x59] +#CHECK: tdgxt %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x59] +#CHECK: tdgxt %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x59] +#CHECK: tdgxt %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x59] +#CHECK: tdgxt %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x59] + + tdgxt %f0, 0 + tdgxt %f0, 4095 + tdgxt %f0, 0(%r1) + tdgxt %f0, 0(%r15) + tdgxt %f0, 4095(%r1,%r15) + tdgxt %f0, 4095(%r15,%r1) + tdgxt %f13, 0 + +#CHECK: thder %f0, %f9 # encoding: [0xb3,0x58,0x00,0x09] +#CHECK: thder %f0, %f15 # encoding: [0xb3,0x58,0x00,0x0f] +#CHECK: thder %f15, %f0 # encoding: [0xb3,0x58,0x00,0xf0] +#CHECK: thder %f15, %f9 # encoding: [0xb3,0x58,0x00,0xf9] + + thder %f0,%f9 + thder %f0,%f15 + thder %f15,%f0 + thder %f15,%f9 + +#CHECK: thdr %f0, %f9 # encoding: [0xb3,0x59,0x00,0x09] +#CHECK: thdr %f0, %f15 # encoding: [0xb3,0x59,0x00,0x0f] +#CHECK: thdr %f15, %f0 # encoding: [0xb3,0x59,0x00,0xf0] +#CHECK: thdr %f15, %f9 # encoding: [0xb3,0x59,0x00,0xf9] + + thdr %f0,%f9 + thdr %f0,%f15 + thdr %f15,%f0 + thdr %f15,%f9 + #CHECK: tm 0, 0 # encoding: [0x91,0x00,0x00,0x00] #CHECK: tm 4095, 0 # encoding: [0x91,0x00,0x0f,0xff] #CHECK: tm 0, 255 # encoding: [0x91,0xff,0x00,0x00] diff --git a/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll b/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll deleted file mode 100644 index a7f414b8694b9..0000000000000 --- a/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll +++ /dev/null @@ -1,26 +0,0 @@ -; REQUIRES: asserts -; RUN: opt < %s -loop-vectorize -force-vector-interleave=1 -S -debug-only=loop-vectorize 2>&1 | FileCheck %s - -target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" -target triple = "aarch64--linux-gnu" - -; CHECK-LABEL: all_scalar -; CHECK: LV: Found scalar instruction: %i.next = add nuw nsw i64 %i, 2 -; CHECK: LV: Found an estimated cost of 2 for VF 2 For instruction: %i.next = add nuw nsw i64 %i, 2 -; CHECK: LV: Not considering vector loop of width 2 because it will not generate any vector instructions -; -define void @all_scalar(i64* %a, i64 %n) { -entry: - br label %for.body - -for.body: - %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] - %tmp0 = getelementptr i64, i64* %a, i64 %i - store i64 0, i64* %tmp0, align 1 - %i.next = add nuw nsw i64 %i, 2 - %cond = icmp eq i64 %i.next, %n - br i1 %cond, label %for.end, label %for.body - -for.end: - ret void -} |