diff options
Diffstat (limited to 'test')
19 files changed, 493 insertions, 149 deletions
diff --git a/test/Analysis/ValueTracking/select-pattern.ll b/test/Analysis/ValueTracking/select-pattern.ll new file mode 100644 index 0000000000000..455df00ef1218 --- /dev/null +++ b/test/Analysis/ValueTracking/select-pattern.ll @@ -0,0 +1,46 @@ +; RUN: opt -simplifycfg < %s -S | FileCheck %s + +; The dead code would cause a select that had itself +; as an operand to be analyzed. This would then cause +; infinite recursion and eventual crash. + +define void @PR36045(i1 %t, i32* %b) { +; CHECK-LABEL: @PR36045( +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + br i1 %t, label %if, label %end + +if: + br i1 %t, label %unreach, label %pre + +unreach: + unreachable + +pre: + %p = phi i32 [ 70, %if ], [ %sel, %for ] + br label %for + +for: + %cmp = icmp sgt i32 %p, 8 + %add = add i32 %p, 2 + %sel = select i1 %cmp, i32 %p, i32 %add + %cmp21 = icmp ult i32 %sel, 21 + br i1 %cmp21, label %pre, label %for.end + +for.end: + br i1 %t, label %unreach2, label %then12 + +then12: + store i32 0, i32* %b + br label %unreach2 + +unreach2: + %spec = phi i32 [ %sel, %for.end ], [ 42, %then12 ] + unreachable + +end: + ret void +} + diff --git a/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll new file mode 100644 index 0000000000000..faaa725486f16 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=aarch64_be-- %s -o /dev/null -debug-only=isel -O0 2>&1 | FileCheck %s +; REQUIRES: asserts + +; This test uses big endian in order to force an abort since it's not currently supported for GISel. +; The purpose is to check that we don't fall back to FastISel. Checking the pass structure is insufficient +; because the FastISel is set up in the SelectionDAGISel, so it doesn't appear on the pass structure. + +; CHECK-NOT: Enabling fast-ise +define void @empty() { + ret void +} diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll new file mode 100644 index 0000000000000..9bda39c9fca7f --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll @@ -0,0 +1,14 @@ +; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s + +@g = global i16 0, align 2 +declare void @bar(i32) + +; Check that only one load is generated. We fall back to +define hidden void @foo() { +; CHECK-NOT: ldrh +; CHECK: ldrsh + %1 = load volatile i16, i16* @g, align 2 + %2 = sext i16 %1 to i32 + call void @bar(i32 %2) + ret void +} diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir index 4ed84ed79bbaa..c3ed3316ad317 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir @@ -75,7 +75,7 @@ body: | ; CHECK: %w0 = COPY [[C]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00 ; CHECK: %x0 = COPY [[C1]](s64) - ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT half 0xH0000 + ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) ; CHECK: %w0 = COPY [[ANYEXT]](s32) diff --git a/test/CodeGen/AArch64/dllimport.ll b/test/CodeGen/AArch64/dllimport.ll index fad049a54cd22..281c847a39a56 100644 --- a/test/CodeGen/AArch64/dllimport.ll +++ b/test/CodeGen/AArch64/dllimport.ll @@ -1,4 +1,6 @@ -; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype asm -o - %s | FileCheck %s +; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,DAG-ISEL +; RUN: llc -mtriple aarch64-unknown-windows-msvc -fast-isel -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,FAST-ISEL +; RUN: llc -mtriple aarch64-unknown-windows-msvc -O0 -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,GLOBAL-ISEL,GLOBAL-ISEL-FALLBACK @var = external dllimport global i32 @ext = external global i32 @@ -23,7 +25,11 @@ define i32 @get_ext() { ; CHECK-LABEL: get_ext ; CHECK: adrp x8, ext -; CHECK: ldr w0, [x8, ext] +; DAG-ISEL: ldr w0, [x8, ext] +; FAST-ISEL: add x8, x8, ext +; FAST-ISEL: ldr w0, [x8] +; GLOBAL-ISEL-FALLBACK: add x8, x8, ext +; GLOBAL-ISEL-FALLBACK: ldr w0, [x8] ; CHECK: ret define i32* @get_var_pointer() { @@ -31,8 +37,8 @@ define i32* @get_var_pointer() { } ; CHECK-LABEL: get_var_pointer -; CHECK: adrp x0, __imp_var -; CHECK: ldr x0, [x0, __imp_var] +; CHECK: adrp [[REG1:x[0-9]+]], __imp_var +; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]], __imp_var] ; CHECK: ret define i32 @call_external() { @@ -51,4 +57,6 @@ define i32 @call_internal() { } ; CHECK-LABEL: call_internal -; CHECK: b internal +; DAG-ISEL: b internal +; FAST-ISEL: b internal +; GLOBAL-ISEL: bl internal diff --git a/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir b/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir new file mode 100644 index 0000000000000..fc19173a176b9 --- /dev/null +++ b/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir @@ -0,0 +1,26 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple aarch64-apple-ios -run-pass regallocfast -o - %s | FileCheck %s +# This test used to crash the fast register alloc. +# Basically, when a basic block has liveins, the fast regalloc +# was deferencing the begin iterator of this block. However, +# when this block is empty and it will just crashed! +--- +name: crashing +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: crashing + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: %x0, %x1 + ; CHECK: bb.1: + ; CHECK: renamable %w0 = MOVi32imm -1 + ; CHECK: RET_ReallyLR implicit killed %w0 + bb.1: + liveins: %x0, %x1 + + bb.2: + %0:gpr32 = MOVi32imm -1 + %w0 = COPY %0 + RET_ReallyLR implicit %w0 + +... diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll index d6b0628956a02..fabed795c5686 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll @@ -234,6 +234,23 @@ define amdgpu_ps void @wqm(float %a) { ret void } +; This checks that we use the 64-bit encoding when the operand is a SGPR. +; SI-LABEL: {{^}}test_sgpr: +; SI: v_cmpx_ge_f32_e64 +define amdgpu_ps void @test_sgpr(float inreg %a) #0 { + %c = fcmp ole float %a, 1.000000e+00 + call void @llvm.amdgcn.kill(i1 %c) #1 + ret void +} + +; SI-LABEL: {{^}}test_non_inline_imm_sgpr: +; SI-NOT: v_cmpx_ge_f32_e64 +define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 { + %c = fcmp ole float %a, 1.500000e+00 + call void @llvm.amdgcn.kill(i1 %c) #1 + ret void +} + declare void @llvm.amdgcn.kill(i1) #0 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 declare i1 @llvm.amdgcn.wqm.vote(i1) diff --git a/test/CodeGen/AMDGPU/multilevel-break.ll b/test/CodeGen/AMDGPU/multilevel-break.ll index 5b556f12f0d6d..8cc02d497098b 100644 --- a/test/CodeGen/AMDGPU/multilevel-break.ll +++ b/test/CodeGen/AMDGPU/multilevel-break.ll @@ -66,10 +66,9 @@ ENDIF: ; preds = %LOOP ; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop( ; OPT: llvm.amdgcn.break -; OPT: llvm.amdgcn.break +; OPT: llvm.amdgcn.loop ; OPT: llvm.amdgcn.if.break ; OPT: llvm.amdgcn.if.break -; OPT: llvm.amdgcn.loop ; OPT: llvm.amdgcn.end.cf ; GCN-LABEL: {{^}}multi_if_break_loop: diff --git a/test/CodeGen/AMDGPU/nested-loop-conditions.ll b/test/CodeGen/AMDGPU/nested-loop-conditions.ll index 96d2841e685f4..672549c8ea636 100644 --- a/test/CodeGen/AMDGPU/nested-loop-conditions.ll +++ b/test/CodeGen/AMDGPU/nested-loop-conditions.ll @@ -124,100 +124,55 @@ bb23: ; preds = %bb10 ; Earlier version of above, before a run of the structurizer. ; IR-LABEL: @nested_loop_conditions( -; IR: %tmp1235 = icmp slt i32 %tmp1134, 9 -; IR: br i1 %tmp1235, label %bb14.lr.ph, label %Flow - -; IR: bb14.lr.ph: -; IR: br label %bb14 - -; IR: Flow3: -; IR: call void @llvm.amdgcn.end.cf(i64 %18) -; IR: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %17) -; IR: %1 = extractvalue { i1, i64 } %0, 0 -; IR: %2 = extractvalue { i1, i64 } %0, 1 -; IR: br i1 %1, label %bb4.bb13_crit_edge, label %Flow4 - -; IR: bb4.bb13_crit_edge: -; IR: br label %Flow4 - -; IR: Flow4: -; IR: %3 = phi i1 [ true, %bb4.bb13_crit_edge ], [ false, %Flow3 ] -; IR: call void @llvm.amdgcn.end.cf(i64 %2) -; IR: br label %Flow - -; IR: bb13: -; IR: br label %bb31 - -; IR: Flow: -; IR: %4 = phi i1 [ %3, %Flow4 ], [ true, %bb ] -; IR: %5 = call { i1, i64 } @llvm.amdgcn.if(i1 %4) -; IR: %6 = extractvalue { i1, i64 } %5, 0 -; IR: %7 = extractvalue { i1, i64 } %5, 1 -; IR: br i1 %6, label %bb13, label %bb31 - -; IR: bb14: -; IR: %phi.broken = phi i64 [ %18, %Flow2 ], [ 0, %bb14.lr.ph ] -; IR: %tmp1037 = phi i32 [ %tmp1033, %bb14.lr.ph ], [ %16, %Flow2 ] -; IR: %tmp936 = phi <4 x i32> [ %tmp932, %bb14.lr.ph ], [ %15, %Flow2 ] -; IR: %tmp15 = icmp eq i32 %tmp1037, 1 -; IR: %8 = xor i1 %tmp15, true -; IR: %9 = call { i1, i64 } @llvm.amdgcn.if(i1 %8) -; IR: %10 = extractvalue { i1, i64 } %9, 0 -; IR: %11 = extractvalue { i1, i64 } %9, 1 -; IR: br i1 %10, label %bb31.loopexit, label %Flow1 +; IR: Flow7: +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %17) +; IR-NEXT: %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %15) +; IR-NEXT: %1 = extractvalue { i1, i64 } %0, 0 +; IR-NEXT: %2 = extractvalue { i1, i64 } %0, 1 +; IR-NEXT: br i1 %1, label %bb4.bb13_crit_edge, label %Flow8 ; IR: Flow1: -; IR: %12 = call { i1, i64 } @llvm.amdgcn.else(i64 %11) -; IR: %13 = extractvalue { i1, i64 } %12, 0 -; IR: %14 = extractvalue { i1, i64 } %12, 1 -; IR: br i1 %13, label %bb16, label %Flow2 - -; IR: bb16: -; IR: %tmp17 = bitcast i64 %tmp3 to <2 x i32> -; IR: br label %bb18 +; IR-NEXT: %loop.phi = phi i64 [ %loop.phi9, %Flow6 ], [ %phi.broken, %bb14 ] +; IR-NEXT: %13 = phi <4 x i32> [ %29, %Flow6 ], [ undef, %bb14 ] +; IR-NEXT: %14 = phi i32 [ %30, %Flow6 ], [ undef, %bb14 ] +; IR-NEXT: %15 = phi i1 [ %31, %Flow6 ], [ false, %bb14 ] +; IR-NEXT: %16 = phi i1 [ false, %Flow6 ], [ %8, %bb14 ] +; IR-NEXT: %17 = call i64 @llvm.amdgcn.else.break(i64 %11, i64 %loop.phi) +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %11) +; IR-NEXT: %18 = call i1 @llvm.amdgcn.loop(i64 %17) +; IR-NEXT: br i1 %18, label %Flow7, label %bb14 ; IR: Flow2: -; IR: %loop.phi = phi i64 [ %21, %bb21 ], [ %phi.broken, %Flow1 ] -; IR: %15 = phi <4 x i32> [ %tmp9, %bb21 ], [ undef, %Flow1 ] -; IR: %16 = phi i32 [ %tmp10, %bb21 ], [ undef, %Flow1 ] -; IR: %17 = phi i1 [ %20, %bb21 ], [ false, %Flow1 ] -; IR: %18 = call i64 @llvm.amdgcn.else.break(i64 %14, i64 %loop.phi) -; IR: call void @llvm.amdgcn.end.cf(i64 %14) -; IR: %19 = call i1 @llvm.amdgcn.loop(i64 %18) -; IR: br i1 %19, label %Flow3, label %bb14 - -; IR: bb18: -; IR: %tmp19 = load volatile i32, i32 addrspace(1)* undef -; IR: %tmp20 = icmp slt i32 %tmp19, 9 -; IR: br i1 %tmp20, label %bb21, label %bb18 +; IR-NEXT: %loop.phi10 = phi i64 [ %loop.phi11, %Flow5 ], [ %12, %bb16 ] +; IR-NEXT: %19 = phi <4 x i32> [ %29, %Flow5 ], [ undef, %bb16 ] +; IR-NEXT: %20 = phi i32 [ %30, %Flow5 ], [ undef, %bb16 ] +; IR-NEXT: %21 = phi i1 [ %31, %Flow5 ], [ false, %bb16 ] +; IR-NEXT: %22 = phi i1 [ false, %Flow5 ], [ false, %bb16 ] +; IR-NEXT: %23 = phi i1 [ false, %Flow5 ], [ %8, %bb16 ] +; IR-NEXT: %24 = call { i1, i64 } @llvm.amdgcn.if(i1 %23) +; IR-NEXT: %25 = extractvalue { i1, i64 } %24, 0 +; IR-NEXT: %26 = extractvalue { i1, i64 } %24, 1 +; IR-NEXT: br i1 %25, label %bb21, label %Flow3 ; IR: bb21: -; IR: %tmp22 = extractelement <2 x i32> %tmp17, i64 1 -; IR: %tmp23 = lshr i32 %tmp22, 16 -; IR: %tmp24 = select i1 undef, i32 undef, i32 %tmp23 -; IR: %tmp25 = uitofp i32 %tmp24 to float -; IR: %tmp26 = fmul float %tmp25, 0x3EF0001000000000 -; IR: %tmp27 = fsub float %tmp26, undef -; IR: %tmp28 = fcmp olt float %tmp27, 5.000000e-01 -; IR: %tmp29 = select i1 %tmp28, i64 1, i64 2 -; IR: %tmp30 = extractelement <4 x i32> %tmp936, i64 %tmp29 -; IR: %tmp7 = zext i32 %tmp30 to i64 -; IR: %tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %tmp7 -; IR: %tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16 -; IR: %tmp10 = extractelement <4 x i32> %tmp9, i64 0 -; IR: %tmp11 = load volatile i32, i32 addrspace(1)* undef -; IR: %tmp12 = icmp slt i32 %tmp11, 9 -; IR: %20 = xor i1 %tmp12, true -; IR: %21 = call i64 @llvm.amdgcn.if.break(i1 %20, i64 %phi.broken) -; IR: br label %Flow2 +; IR: %tmp12 = icmp slt i32 %tmp11, 9 +; IR-NEXT: %27 = xor i1 %tmp12, true +; IR-NEXT: %28 = call i64 @llvm.amdgcn.if.break(i1 %27, i64 %phi.broken) +; IR-NEXT: br label %Flow3 -; IR: bb31.loopexit: -; IR: br label %Flow1 +; IR: Flow3: +; IR-NEXT: %loop.phi11 = phi i64 [ %phi.broken, %bb21 ], [ %phi.broken, %Flow2 ] +; IR-NEXT: %loop.phi9 = phi i64 [ %28, %bb21 ], [ %loop.phi10, %Flow2 ] +; IR-NEXT: %29 = phi <4 x i32> [ %tmp9, %bb21 ], [ %19, %Flow2 ] +; IR-NEXT: %30 = phi i32 [ %tmp10, %bb21 ], [ %20, %Flow2 ] +; IR-NEXT: %31 = phi i1 [ %27, %bb21 ], [ %21, %Flow2 ] +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %26) +; IR-NEXT: br i1 %22, label %bb31.loopexit, label %Flow4 ; IR: bb31: -; IR: call void @llvm.amdgcn.end.cf(i64 %7) -; IR: store volatile i32 0, i32 addrspace(1)* undef -; IR: ret void +; IR-NEXT: call void @llvm.amdgcn.end.cf(i64 %7) +; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef +; IR-NEXT: ret void ; GCN-LABEL: {{^}}nested_loop_conditions: diff --git a/test/CodeGen/X86/pr34592.ll b/test/CodeGen/X86/pr34592.ll new file mode 100644 index 0000000000000..09dfade1ee536 --- /dev/null +++ b/test/CodeGen/X86/pr34592.ll @@ -0,0 +1,74 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 -O0 | FileCheck %s + +define <16 x i64> @pluto(<16 x i64> %arg, <16 x i64> %arg1, <16 x i64> %arg2, <16 x i64> %arg3, <16 x i64> %arg4) { +; CHECK-LABEL: pluto: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: pushq %rbp +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset %rbp, -16 +; CHECK-NEXT: movq %rsp, %rbp +; CHECK-NEXT: .cfi_def_cfa_register %rbp +; CHECK-NEXT: andq $-32, %rsp +; CHECK-NEXT: subq $352, %rsp # imm = 0x160 +; CHECK-NEXT: vmovaps 240(%rbp), %ymm8 +; CHECK-NEXT: vmovaps 208(%rbp), %ymm9 +; CHECK-NEXT: vmovaps 176(%rbp), %ymm10 +; CHECK-NEXT: vmovaps 144(%rbp), %ymm11 +; CHECK-NEXT: vmovaps 112(%rbp), %ymm12 +; CHECK-NEXT: vmovaps 80(%rbp), %ymm13 +; CHECK-NEXT: vmovaps 48(%rbp), %ymm14 +; CHECK-NEXT: vmovaps 16(%rbp), %ymm15 +; CHECK-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,18446744071562067968,18446744071562067968] +; CHECK-NEXT: vblendvpd %ymm0, %ymm2, %ymm6, %ymm0 +; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; CHECK-NEXT: vpblendd {{.*#+}} ymm6 = ymm2[0,1],ymm13[2,3],ymm2[4,5,6,7] +; CHECK-NEXT: vpblendd {{.*#+}} ymm8 = ymm2[0,1],ymm8[2,3,4,5,6,7] +; CHECK-NEXT: vmovaps {{.*#+}} ymm13 = [18446744071562067968,18446744071562067968,0,0] +; CHECK-NEXT: vblendvpd %ymm13, %ymm9, %ymm6, %ymm6 +; CHECK-NEXT: vpblendd {{.*#+}} ymm9 = ymm0[0,1,2,3],ymm11[4,5],ymm0[6,7] +; CHECK-NEXT: vpermq {{.*#+}} ymm9 = ymm9[3,2,2,1] +; CHECK-NEXT: vmovaps %xmm6, %xmm11 +; CHECK-NEXT: # implicit-def: %ymm13 +; CHECK-NEXT: vinserti128 $1, %xmm11, %ymm13, %ymm13 +; CHECK-NEXT: vpblendd {{.*#+}} ymm9 = ymm9[0,1,2,3],ymm13[4,5],ymm9[6,7] +; CHECK-NEXT: vmovaps %xmm0, %xmm11 +; CHECK-NEXT: # implicit-def: %ymm0 +; CHECK-NEXT: vinserti128 $1, %xmm11, %ymm0, %ymm0 +; CHECK-NEXT: vpblendd {{.*#+}} ymm8 = ymm8[0,1,2,3],ymm7[4,5],ymm8[6,7] +; CHECK-NEXT: vpermq {{.*#+}} ymm13 = ymm8[2,0,2,3] +; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm13[0,1,2,3],ymm0[4,5,6,7] +; CHECK-NEXT: vpblendd {{.*#+}} ymm2 = ymm7[0,1,2,3],ymm2[4,5],ymm7[6,7] +; CHECK-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,0,2,3] +; CHECK-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3],ymm5[4,5],ymm6[6,7] +; CHECK-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,1,1,2] +; CHECK-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm6[4,5,6,7] +; CHECK-NEXT: vpermq {{.*#+}} ymm6 = ymm8[2,1,1,3] +; CHECK-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[0,1,0,1,4,5,4,5] +; CHECK-NEXT: vpblendd {{.*#+}} ymm5 = ymm6[0,1,2,3,4,5],ymm5[6,7] +; CHECK-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm9, %ymm0 +; CHECK-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm5, %ymm1 +; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm5 # 32-byte Reload +; CHECK-NEXT: vmovaps %ymm2, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm5, %ymm2 +; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm6 # 32-byte Reload +; CHECK-NEXT: vmovaps %ymm3, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm6, %ymm3 +; CHECK-NEXT: vmovaps %ymm15, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm12, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm10, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm4, {{[0-9]+}}(%rsp) # 32-byte Spill +; CHECK-NEXT: vmovaps %ymm14, (%rsp) # 32-byte Spill +; CHECK-NEXT: movq %rbp, %rsp +; CHECK-NEXT: popq %rbp +; CHECK-NEXT: retq +bb: + %tmp = select <16 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <16 x i64> %arg, <16 x i64> %arg1 + %tmp5 = select <16 x i1> <i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x i64> %arg2, <16 x i64> zeroinitializer + %tmp6 = select <16 x i1> <i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true>, <16 x i64> %arg3, <16 x i64> %tmp5 + %tmp7 = shufflevector <16 x i64> %tmp, <16 x i64> %tmp6, <16 x i32> <i32 11, i32 18, i32 24, i32 9, i32 14, i32 29, i32 29, i32 6, i32 14, i32 28, i32 8, i32 9, i32 22, i32 12, i32 25, i32 6> + ret <16 x i64> %tmp7 +} diff --git a/test/MC/X86/eval-fill.s b/test/MC/X86/eval-fill.s new file mode 100644 index 0000000000000..f09166ee0f122 --- /dev/null +++ b/test/MC/X86/eval-fill.s @@ -0,0 +1,17 @@ +// RUN: llvm-mc -filetype=obj %s -o - -triple x86_64-pc-linux | llvm-readobj -s | FileCheck %s + +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 4092 + + .globl foo +foo: + .space 4 +bar: + .space 4092 - (bar - foo) diff --git a/test/MC/X86/x86-32-coverage.s b/test/MC/X86/x86-32-coverage.s index 03be55fa4beb9..09e147fd1627c 100644 --- a/test/MC/X86/x86-32-coverage.s +++ b/test/MC/X86/x86-32-coverage.s @@ -10774,3 +10774,9 @@ btcl $4, (%eax) // CHECK: clzero // CHECK: encoding: [0x0f,0x01,0xfc] clzero + +// CHECK: lock addl %esi, (%edi) +// INTEL: lock add dword ptr [edi], esi +// CHECK: encoding: [0xf0,0x01,0x37] + lock add %esi, (%edi) + diff --git a/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll b/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll new file mode 100644 index 0000000000000..5c126e3f47681 --- /dev/null +++ b/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll @@ -0,0 +1,39 @@ +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-scei-ps4" + +%struct.CFVS = type { %struct.Vec } +%struct.Vec = type { i8 } +%struct.S = type { i8 } + +@_ZN4CFVSD1Ev = alias void (%struct.CFVS*), void (%struct.CFVS*)* @_ZN4CFVSD2Ev + +define void @_ZN4CFVSD2Ev(%struct.CFVS* %this) unnamed_addr align 2 !dbg !8 { +entry: + %this.addr = alloca %struct.CFVS*, align 8 + store %struct.CFVS* %this, %struct.CFVS** %this.addr, align 8 + %this1 = load %struct.CFVS*, %struct.CFVS** %this.addr, align 8 + %m_val = getelementptr inbounds %struct.CFVS, %struct.CFVS* %this1, i32 0, i32 0 + ret void +} + +declare dereferenceable(1) %struct.S* @_Z3Getv() + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5, !6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 6.0.0 (trunk 321360) (llvm/trunk 321359)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "bz188598-b.cpp", directory: "") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 2} +!6 = !{i32 7, !"PIC Level", i32 2} +!8 = distinct !DISubprogram(name: "~CFVS", linkageName: "_ZN4CFVSD2Ev", scope: !9, file: !1, line: 2, type: !28, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: false, unit: !0, declaration: !27, variables: !2) +!9 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "CFVS", file: !10, line: 7, size: 8, elements: !11, identifier: "_ZTS4CFVS") +!10 = !DIFile(filename: "./bz188598.h", directory: "") +!11 = !{!35} +!27 = !DISubprogram(name: "~CFVS", scope: !9, file: !10, line: 8, type: !28, isLocal: false, isDefinition: false, scopeLine: 8, flags: DIFlagPrototyped, isOptimized: false) +!28 = !DISubroutineType(types: !29) +!29 = !{null, !30} +!30 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!35 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) diff --git a/test/ThinLTO/X86/dicompositetype-unique-alias.ll b/test/ThinLTO/X86/dicompositetype-unique-alias.ll new file mode 100644 index 0000000000000..28c363d611109 --- /dev/null +++ b/test/ThinLTO/X86/dicompositetype-unique-alias.ll @@ -0,0 +1,62 @@ +; RUN: opt -module-summary -o %t1.bc %s +; RUN: opt -module-summary -o %t2.bc %S/Inputs/dicompositetype-unique-alias.ll +; RUN: llvm-lto --thinlto-action=run %t1.bc %t2.bc -thinlto-save-temps=%t3. +; RUN: llvm-dis %t3.0.3.imported.bc -o - | FileCheck %s +; RUN: llvm-lto2 run %t1.bc %t2.bc -o %t --save-temps \ +; RUN: -r %t1.bc,_ZN1CD2Ev,pl \ +; RUN: -r %t1.bc,_ZN4CFVSD1Ev,l \ +; RUN: -r %t1.bc,_ZN4CFVSD2Ev,l \ +; RUN: -r %t1.bc,_Z3Getv,l \ +; RUN: -r %t2.bc,_ZN4CFVSD1Ev,pl \ +; RUN: -r %t2.bc,_ZN4CFVSD2Ev,pl \ +; RUN: -r %t2.bc,_Z3Getv,l +; RUN: llvm-dis %t.1.3.import.bc -o - | FileCheck %s + +; Only llvm-lto2 adds the dso_local keyword, hence the {{.*}} +; CHECK: define available_externally{{.*}} void @_ZN4CFVSD1Ev + +; Confirm that we only have a single DICompositeType after importing +; both an alias and its aliasee, since ODR Type Uniquing is enabled. +; CHECK: DICompositeType +; CHECK-NOT: DICompositeType + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-scei-ps4" + +%class.C = type <{ i32 (...)**, %class.A, %struct.CFVS, [6 x i8] }> +%class.A = type { %struct.Vec } +%struct.Vec = type { i8 } +%struct.CFVS = type { %struct.Vec } +%struct.S = type { i8 } + +define void @_ZN1CD2Ev(%class.C* %this) unnamed_addr align 2 { +entry: + %this.addr = alloca %class.C*, align 8 + %this1 = load %class.C*, %class.C** %this.addr, align 8 + %m = getelementptr inbounds %class.C, %class.C* %this1, i32 0, i32 2 + call void @_ZN4CFVSD1Ev(%struct.CFVS* %m), !dbg !50 + call void @_ZN4CFVSD2Ev(%struct.CFVS* %m), !dbg !50 + ret void +} + +declare void @_ZN4CFVSD1Ev(%struct.CFVS*) unnamed_addr +declare void @_ZN4CFVSD2Ev(%struct.CFVS*) unnamed_addr + +declare dereferenceable(1) %struct.S* @_Z3Getv() + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5, !6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 6.0.0 (trunk 321360) (llvm/trunk 321359)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "bz188598-a.cpp", directory: ".") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 2} +!6 = !{i32 7, !"PIC Level", i32 2} +!8 = distinct !DISubprogram(name: "~C", linkageName: "_ZN1CD2Ev", scope: !1, file: !1, line: 9, type: !47, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!47 = !DISubroutineType(types: !48) +!48 = !{!55} +!50 = !DILocation(line: 9, scope: !51) +!51 = distinct !DILexicalBlock(scope: !8, file: !1, line: 9) +!55 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) diff --git a/test/Transforms/CallSiteSplitting/callsite-no-splitting.ll b/test/Transforms/CallSiteSplitting/callsite-no-splitting.ll index ca41bd6fc5e1b..25b4cb23be605 100644 --- a/test/Transforms/CallSiteSplitting/callsite-no-splitting.ll +++ b/test/Transforms/CallSiteSplitting/callsite-no-splitting.ll @@ -16,3 +16,27 @@ Tail: %r = call i32 @callee(i32* %a, i32 %v, i32 %p) ret i32 %r } + +define void @fn1(i16 %p1) { +entry: + ret void +} + +define void @fn2() { + ret void + +; Unreachable code below + +for.inc: ; preds = %for.inc + br i1 undef, label %for.end6, label %for.inc + +for.end6: ; preds = %for.inc + br i1 undef, label %lor.rhs, label %lor.end + +lor.rhs: ; preds = %for.end6 + br label %lor.end + +lor.end: ; preds = %for.end6, %lor.rhs + call void @fn1(i16 0) + ret void +} diff --git a/test/Transforms/InstCombine/minmax-fold.ll b/test/Transforms/InstCombine/minmax-fold.ll index 933aac7e23f2a..bf54204df080b 100644 --- a/test/Transforms/InstCombine/minmax-fold.ll +++ b/test/Transforms/InstCombine/minmax-fold.ll @@ -899,3 +899,24 @@ define i32 @common_factor_umax_extra_use_both(i32 %a, i32 %b, i32 %c) { ret i32 %max_abc } +; This would assert. Don't assume that earlier min/max types match a possible later min/max. + +define float @not_min_of_min(i8 %i, float %x) { +; CHECK-LABEL: @not_min_of_min( +; CHECK-NEXT: [[CMP1_INV:%.*]] = fcmp fast oge float [[X:%.*]], 1.000000e+00 +; CHECK-NEXT: [[MIN1:%.*]] = select i1 [[CMP1_INV]], float 1.000000e+00, float [[X]] +; CHECK-NEXT: [[CMP2_INV:%.*]] = fcmp fast oge float [[X]], 2.000000e+00 +; CHECK-NEXT: [[MIN2:%.*]] = select i1 [[CMP2_INV]], float 2.000000e+00, float [[X]] +; CHECK-NEXT: [[CMP3:%.*]] = icmp ult i8 [[I:%.*]], 16 +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP3]], float [[MIN1]], float [[MIN2]] +; CHECK-NEXT: ret float [[R]] +; + %cmp1 = fcmp fast ult float %x, 1.0 + %min1 = select i1 %cmp1, float %x, float 1.0 + %cmp2 = fcmp fast ult float %x, 2.0 + %min2 = select i1 %cmp2, float %x, float 2.0 + %cmp3 = icmp ult i8 %i, 16 + %r = select i1 %cmp3, float %min1, float %min2 + ret float %r +} + diff --git a/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll b/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll index 9cddffdd17951..5b5ea676baec9 100644 --- a/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll +++ b/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s diff --git a/test/Transforms/StructurizeCFG/bug36015.ll b/test/Transforms/StructurizeCFG/bug36015.ll new file mode 100644 index 0000000000000..24b9c9cdde2d6 --- /dev/null +++ b/test/Transforms/StructurizeCFG/bug36015.ll @@ -0,0 +1,53 @@ +; RUN: opt -S -structurizecfg %s | FileCheck %s + +; r321751 introduced a bug where control flow branching from if to exit was +; not handled properly and instead ended up in an infinite loop. +define void @bug36015(i32 %cmp0, i32 %count) { +entry: + br label %loop.outer + +loop.outer: + %ctr.loop.outer = phi i32 [ 0, %entry ], [ %ctr.else, %else ] + call void @foo(i32 0) + br label %loop.inner + +loop.inner: + %ctr.loop.inner = phi i32 [ %ctr.loop.outer, %loop.outer ], [ %ctr.if, %if ] + call void @foo(i32 1) + %cond.inner = icmp eq i32 %cmp0, %ctr.loop.inner + br i1 %cond.inner, label %if, label %else + +; CHECK: if: +; CHECK: %0 = xor i1 %cond.if, true +; CHECK: br label %Flow +if: + %ctr.if = add i32 %ctr.loop.inner, 1 + call void @foo(i32 2) + %cond.if = icmp slt i32 %ctr.if, %count + br i1 %cond.if, label %loop.inner, label %exit + +; CHECK: Flow: +; CHECK: %2 = phi i1 [ %0, %if ], [ true, %loop.inner ] +; CHECK: %3 = phi i1 [ false, %if ], [ true, %loop.inner ] +; CHECK: br i1 %2, label %Flow1, label %loop.inner + +; CHECK: Flow1: +; CHECK: br i1 %3, label %else, label %Flow2 + +; CHECK: else: +; CHECK: br label %Flow2 +else: + %ctr.else = add i32 %ctr.loop.inner, 1 + call void @foo(i32 3) + %cond.else = icmp slt i32 %ctr.else, %count + br i1 %cond.else, label %loop.outer, label %exit + +; CHECK: Flow2: +; CHECK: %6 = phi i1 [ %4, %else ], [ true, %Flow1 ] +; CHECK: br i1 %6, label %exit, label %loop.outer + +exit: + ret void +} + +declare void @foo(i32) diff --git a/test/Transforms/StructurizeCFG/nested-loop-order.ll b/test/Transforms/StructurizeCFG/nested-loop-order.ll index 7b5bd5acb6298..58634d0d37db8 100644 --- a/test/Transforms/StructurizeCFG/nested-loop-order.ll +++ b/test/Transforms/StructurizeCFG/nested-loop-order.ll @@ -1,76 +1,32 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -structurizecfg %s -o - | FileCheck %s define void @main(float addrspace(1)* %out) { -; CHECK-LABEL: @main( -; CHECK-NEXT: main_body: -; CHECK-NEXT: br label [[LOOP_OUTER:%.*]] -; CHECK: LOOP.outer: -; CHECK-NEXT: [[TEMP8_0_PH:%.*]] = phi float [ 0.000000e+00, [[MAIN_BODY:%.*]] ], [ [[TMP13:%.*]], [[FLOW3:%.*]] ] -; CHECK-NEXT: [[TEMP4_0_PH:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP12:%.*]], [[FLOW3]] ] -; CHECK-NEXT: br label [[LOOP:%.*]] -; CHECK: LOOP: -; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ undef, [[LOOP_OUTER]] ], [ [[TMP12]], [[FLOW:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = phi float [ undef, [[LOOP_OUTER]] ], [ [[TMP13]], [[FLOW]] ] -; CHECK-NEXT: [[TEMP4_0:%.*]] = phi i32 [ [[TEMP4_0_PH]], [[LOOP_OUTER]] ], [ [[TMP15:%.*]], [[FLOW]] ] -; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TEMP4_0]], 1 -; CHECK-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP20]], 3 -; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP22]], true -; CHECK-NEXT: br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]] -; CHECK: Flow2: -; CHECK-NEXT: [[TMP3:%.*]] = phi float [ [[TEMP8_0_PH]], [[IF29:%.*]] ], [ [[TMP9:%.*]], [[FLOW1:%.*]] ] -; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[TMP20]], [[IF29]] ], [ undef, [[FLOW1]] ] -; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ [[TMP32:%.*]], [[IF29]] ], [ true, [[FLOW1]] ] -; CHECK-NEXT: br label [[FLOW]] -; CHECK: Flow3: -; CHECK-NEXT: br i1 [[TMP16:%.*]], label [[ENDLOOP:%.*]], label [[LOOP_OUTER]] -; CHECK: ENDLOOP: -; CHECK-NEXT: [[TEMP8_1:%.*]] = phi float [ [[TMP14:%.*]], [[FLOW3]] ] -; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[TMP20]], 3 -; CHECK-NEXT: [[DOT45:%.*]] = select i1 [[TMP23]], float 0.000000e+00, float 1.000000e+00 -; CHECK-NEXT: store float [[DOT45]], float addrspace(1)* [[OUT:%.*]] -; CHECK-NEXT: ret void -; CHECK: ENDIF: -; CHECK-NEXT: [[TMP31:%.*]] = icmp sgt i32 [[TMP20]], 1 -; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[TMP31]], true -; CHECK-NEXT: br i1 [[TMP6]], label [[ENDIF28:%.*]], label [[FLOW1]] -; CHECK: Flow1: -; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP20]], [[ENDIF28]] ], [ [[TMP0]], [[ENDIF]] ] -; CHECK-NEXT: [[TMP8:%.*]] = phi float [ [[TMP35:%.*]], [[ENDIF28]] ], [ [[TMP1]], [[ENDIF]] ] -; CHECK-NEXT: [[TMP9]] = phi float [ [[TMP35]], [[ENDIF28]] ], [ [[TEMP8_0_PH]], [[ENDIF]] ] -; CHECK-NEXT: [[TMP10:%.*]] = phi i1 [ [[TMP36:%.*]], [[ENDIF28]] ], [ true, [[ENDIF]] ] -; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[ENDIF28]] ], [ true, [[ENDIF]] ] -; CHECK-NEXT: br i1 [[TMP11]], label [[IF29]], label [[FLOW2:%.*]] -; CHECK: IF29: -; CHECK-NEXT: [[TMP32]] = icmp sgt i32 [[TMP20]], 2 -; CHECK-NEXT: br label [[FLOW2]] -; CHECK: Flow: -; CHECK-NEXT: [[TMP12]] = phi i32 [ [[TMP7]], [[FLOW2]] ], [ [[TMP0]], [[LOOP]] ] -; CHECK-NEXT: [[TMP13]] = phi float [ [[TMP8]], [[FLOW2]] ], [ [[TMP1]], [[LOOP]] ] -; CHECK-NEXT: [[TMP14]] = phi float [ [[TMP3]], [[FLOW2]] ], [ [[TEMP8_0_PH]], [[LOOP]] ] -; CHECK-NEXT: [[TMP15]] = phi i32 [ [[TMP4]], [[FLOW2]] ], [ undef, [[LOOP]] ] -; CHECK-NEXT: [[TMP16]] = phi i1 [ [[TMP10]], [[FLOW2]] ], [ true, [[LOOP]] ] -; CHECK-NEXT: [[TMP17:%.*]] = phi i1 [ [[TMP5]], [[FLOW2]] ], [ true, [[LOOP]] ] -; CHECK-NEXT: br i1 [[TMP17]], label [[FLOW3]], label [[LOOP]] -; CHECK: ENDIF28: -; CHECK-NEXT: [[TMP35]] = fadd float [[TEMP8_0_PH]], 1.000000e+00 -; CHECK-NEXT: [[TMP36]] = icmp sgt i32 [[TMP20]], 2 -; CHECK-NEXT: br label [[FLOW1]] -; + +; CHECK: main_body: +; CHECK: br label %LOOP.outer main_body: br label %LOOP.outer +; CHECK: LOOP.outer: +; CHECK: br label %LOOP LOOP.outer: ; preds = %ENDIF28, %main_body %temp8.0.ph = phi float [ 0.000000e+00, %main_body ], [ %tmp35, %ENDIF28 ] %temp4.0.ph = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ] br label %LOOP +; CHECK: LOOP: +; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow LOOP: ; preds = %IF29, %LOOP.outer %temp4.0 = phi i32 [ %temp4.0.ph, %LOOP.outer ], [ %tmp20, %IF29 ] %tmp20 = add i32 %temp4.0, 1 %tmp22 = icmp sgt i32 %tmp20, 3 br i1 %tmp22, label %ENDLOOP, label %ENDIF +; CHECK: Flow3 +; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer + +; CHECK: ENDLOOP: +; CHECK: ret void ENDLOOP: ; preds = %ENDIF28, %IF29, %LOOP %temp8.1 = phi float [ %temp8.0.ph, %LOOP ], [ %temp8.0.ph, %IF29 ], [ %tmp35, %ENDIF28 ] %tmp23 = icmp eq i32 %tmp20, 3 @@ -78,14 +34,29 @@ ENDLOOP: ; preds = %ENDIF28, %IF29, %LO store float %.45, float addrspace(1)* %out ret void +; CHECK: ENDIF: +; CHECK: br i1 %tmp31, label %IF29, label %Flow1 ENDIF: ; preds = %LOOP %tmp31 = icmp sgt i32 %tmp20, 1 br i1 %tmp31, label %IF29, label %ENDIF28 +; CHECK: Flow: +; CHECK: br i1 %{{[0-9]+}}, label %Flow2, label %LOOP + +; CHECK: IF29: +; CHECK: br label %Flow1 IF29: ; preds = %ENDIF %tmp32 = icmp sgt i32 %tmp20, 2 br i1 %tmp32, label %ENDLOOP, label %LOOP +; CHECK: Flow1: +; CHECK: br label %Flow + +; CHECK: Flow2: +; CHECK: br i1 %{{[0-9]+}}, label %ENDIF28, label %Flow3 + +; CHECK: ENDIF28: +; CHECK: br label %Flow3 ENDIF28: ; preds = %ENDIF %tmp35 = fadd float %temp8.0.ph, 1.0 %tmp36 = icmp sgt i32 %tmp20, 2 |