diff options
Diffstat (limited to 'usr.sbin/cxgbtool/reg_defs_t3b.c')
| -rw-r--r-- | usr.sbin/cxgbtool/reg_defs_t3b.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/usr.sbin/cxgbtool/reg_defs_t3b.c b/usr.sbin/cxgbtool/reg_defs_t3b.c index 539742ce3c9cb..cd85d840a1dd1 100644 --- a/usr.sbin/cxgbtool/reg_defs_t3b.c +++ b/usr.sbin/cxgbtool/reg_defs_t3b.c @@ -150,7 +150,7 @@ struct reg_info t3b_sge3_regs[] = { { "DrbPriThrsh", 0, 16 }, { "SG_DEBUG_INDEX", 0x78, 0 }, { "SG_DEBUG_DATA", 0x7c, 0 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_pcix1_regs[] = { @@ -222,7 +222,7 @@ struct reg_info t3b_pcix1_regs[] = { { "WakeUp0", 2, 1 }, { "SleepMode1", 1, 1 }, { "SleepMode0", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_pcie0_regs[] = { @@ -376,7 +376,7 @@ struct reg_info t3b_pcie0_regs[] = { { "BeaconDetect", 2, 1 }, { "RxDetect", 1, 1 }, { "TxIdleDetect", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_t3dbg_regs[] = { @@ -557,7 +557,7 @@ struct reg_info t3b_t3dbg_regs[] = { { "BSEnLane1", 4, 1 }, { "BSInSelLane0", 1, 2 }, { "BSEnLane0", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_mc7_pmrx_regs[] = { @@ -678,7 +678,7 @@ struct reg_info t3b_mc7_pmrx_regs[] = { { "PE", 2, 15 }, { "UE", 1, 1 }, { "CE", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_mc7_pmtx_regs[] = { @@ -799,7 +799,7 @@ struct reg_info t3b_mc7_pmtx_regs[] = { { "PE", 2, 15 }, { "UE", 1, 1 }, { "CE", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_mc7_cm_regs[] = { @@ -920,7 +920,7 @@ struct reg_info t3b_mc7_cm_regs[] = { { "PE", 2, 15 }, { "UE", 1, 1 }, { "CE", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_cim_regs[] = { @@ -1047,7 +1047,7 @@ struct reg_info t3b_cim_regs[] = { { "PILADbgWrPtr", 0, 9 }, { "CIM_PO_LA_DEBUGDATA", 0x2e8, 0 }, { "CIM_PI_LA_DEBUGDATA", 0x2ec, 0 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_tp1_regs[] = { @@ -1453,7 +1453,7 @@ struct reg_info t3b_tp1_regs[] = { { "TP_EMBED_OP_FIELD3", 0x4f4, 0 }, { "TP_EMBED_OP_FIELD4", 0x4f8, 0 }, { "TP_EMBED_OP_FIELD5", 0x4fc, 0 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_ulp2_rx_regs[] = { @@ -1497,7 +1497,7 @@ struct reg_info t3b_ulp2_rx_regs[] = { { "ULPRX_RQ_ULIMIT", 0x538, 0 }, { "ULPRX_PBL_LLIMIT", 0x53c, 0 }, { "ULPRX_PBL_ULIMIT", 0x540, 0 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_ulp2_tx_regs[] = { @@ -1525,7 +1525,7 @@ struct reg_info t3b_ulp2_tx_regs[] = { { "ULPTX_DMA_WEIGHT", 0x5ac, 0 }, { "D1_WEIGHT", 16, 16 }, { "D0_WEIGHT", 0, 16 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_pm1_rx_regs[] = { @@ -1569,7 +1569,7 @@ struct reg_info t3b_pm1_rx_regs[] = { { "ocspi1_ofifo2x_Tx_framing_error", 6, 1 }, { "iespi_par_error", 3, 3 }, { "ocspi_par_error", 0, 3 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_pm1_tx_regs[] = { @@ -1613,7 +1613,7 @@ struct reg_info t3b_pm1_tx_regs[] = { { "oespi1_ofifo2x_Tx_framing_error", 6, 1 }, { "icspi_par_error", 3, 3 }, { "oespi_par_error", 0, 3 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_mps0_regs[] = { @@ -1655,7 +1655,7 @@ struct reg_info t3b_mps0_regs[] = { { "RXTpParErr", 4, 2 }, { "TX1TpParErr", 2, 2 }, { "TX0TpParErr", 0, 2 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_cpl_switch_regs[] = { @@ -1686,7 +1686,7 @@ struct reg_info t3b_cpl_switch_regs[] = { { "cpl_map_tbl_idx", 0, 8 }, { "CPL_MAP_TBL_DATA", 0x65c, 0 }, { "cpl_map_tbl_data", 0, 8 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_smb0_regs[] = { @@ -1752,7 +1752,7 @@ struct reg_info t3b_smb0_regs[] = { { "DebugDataL", 0, 16 }, { "SMB_DEBUG_LA", 0x69c, 0 }, { "DebugLAReqAddr", 0, 10 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_i2cm0_regs[] = { @@ -1765,7 +1765,7 @@ struct reg_info t3b_i2cm0_regs[] = { { "Ack", 30, 1 }, { "Cont", 1, 1 }, { "Op", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_mi1_regs[] = { @@ -1784,7 +1784,7 @@ struct reg_info t3b_mi1_regs[] = { { "Busy", 31, 1 }, { "Inc", 2, 1 }, { "Op", 0, 2 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_jm1_regs[] = { @@ -1797,7 +1797,7 @@ struct reg_info t3b_jm1_regs[] = { { "JM_OP", 0x6cc, 0 }, { "Busy", 31, 1 }, { "Cnt", 0, 5 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_sf1_regs[] = { @@ -1807,7 +1807,7 @@ struct reg_info t3b_sf1_regs[] = { { "Cont", 3, 1 }, { "ByteCnt", 1, 2 }, { "Op", 0, 1 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_pl3_regs[] = { @@ -1917,7 +1917,7 @@ struct reg_info t3b_pl3_regs[] = { { "PL_CLI", 0x6f8, 0 }, { "PL_LCK", 0x6fc, 0 }, { "Lck", 0, 2 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_mc5a_regs[] = { @@ -2100,7 +2100,7 @@ struct reg_info t3b_mc5a_regs[] = { { "ReadCmd", 0, 20 }, { "MC5_DB_MASK_WRITE_CMD", 0x7fc, 0 }, { "MaskWr", 0, 16 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_xgmac0_0_regs[] = { @@ -2464,7 +2464,7 @@ struct reg_info t3b_xgmac0_0_regs[] = { { "XGM_RX_SPI4_SOP_EOP_CNT", 0x9ac, 0 }, { "RxSPI4SopCnt", 16, 16 }, { "RxSPI4EopCnt", 0, 16 }, - { NULL } + { NULL, 0, 0 } }; struct reg_info t3b_xgmac0_1_regs[] = { @@ -2828,5 +2828,5 @@ struct reg_info t3b_xgmac0_1_regs[] = { { "XGM_RX_SPI4_SOP_EOP_CNT", 0xbac, 0 }, { "RxSPI4SopCnt", 16, 16 }, { "RxSPI4EopCnt", 0, 16 }, - { NULL } + { NULL, 0, 0 } }; |