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* libpmc: add support for POWER8/9 PMCsLeandro Lupori2020-11-051-0/+20
| | | | | | | | | | | This change adds support for POWER8/9 performance counters. Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D26113 Notes: svn path=/head/; revision=367391
* Add support for Cortex-A76/Neoverse-N1 to hwpmcAndrew Turner2020-08-121-0/+22
| | | | | | | | | | | | | | This adds support for the Cortex-A76 and Neoverse-N1 PMU counters to pmc. While here add more PMCR_IDCODE values and check the implementers code is correct before setting the PMU type. Reviewed by: bz, emaste (looks reasonable to me) Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D25959 Notes: svn path=/head/; revision=364153
* Add support for BERI statcounters.Ruslan Bukin2019-09-181-0/+19
| | | | | | | | | | | | | | | | | | | | BERI stands for Bluespec Extensible RISC Implementation, based on MIPS. BERI has not implemented standard MIPS perfomance monitoring counters, instead it provides statistical counters. BERI statcounters have a several limitations: - They can't be written - They don't support start/stop operation - None of hardware interrupt is provided on a counter overflow. So make it separate to hwpmc_mips module and support process/system counting mode only. Sponsored by: DARPA, AFRL Notes: svn path=/head/; revision=352487
* Revert r336773: it removed too much.Warner Losh2018-07-271-0/+44
| | | | | | | | | | r336773 removed all things xscale. However, some things xscale are really armv5. Revert that entirely. A more modest removal will follow. Noticed by: andrew@ Notes: svn path=/head/; revision=336783
* Remove xscale supportWarner Losh2018-07-271-44/+0
| | | | | | | | | | | | | The OLD XSCALE stuff hasn't been useful in a while. The original committer (cognet@) was the only one that had boards for it. He's blessed this removal. Newer XSCALE (GUMSTIX) is for hardware that's quite old. After discussion on arm@, it was clear there was no support for keeping it. Differential Review: https://reviews.freebsd.org/D16313 Notes: svn path=/head/; revision=336773
* hwpmc: add summary command and further metadata extensionsMatt Macy2018-06-061-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | metadata changes: - log pmc sample rate with pmcallocate - log proc flags with thread / process logging to identify user vs kernel threads fixes: - use log cpuid to translate event id to event name Implement rudimentary summary command to track sample counts by thread and process name within a pmc log. % make -j4 buildkernel >& /dev/null & % sudo pmcstat -S unhalted_core_cycles -S llc-misses -O foo sleep 15 % pmc summary foo cpu_clk_unhalted.thread_p_any: idle: 138108207162 clang-6.0: 105336158004 sh: 72340108510 make: 8642012963 kernel: 7754011631 longest_lat_cache.miss: clang-6.0: 87502625 sh: 40901227 make: 5500165 kernel: 3300099 awk: 2000060 % pmc summary -f ~/foo idx: 278 name: cpu_clk_unhalted.thread_p_any rate: 2000003 idle: 69054 clang-6.0: 52668 sh: 36170 make: 4321 kernel: 3877 hwpmc: proc(7445): 3319 awk: 1289 xargs: 357 rand_harvestq: 181 mtree: 102 intr: 53 zfskern: 31 usb: 7 pagedaemon: 4 ntpd: 3 syslogd: 1 acpi_thermal: 1 logger: 1 syncer: 1 snmptrapd: 1 sleep: 1 idx: 17 name: longest_lat_cache.miss rate: 100003 clang-6.0: 875 sh: 409 make: 55 kernel: 33 awk: 20 hwpmc: proc(7445): 14 xargs: 9 idle: 8 intr: 3 zfskern: 2 Notes: svn path=/head/; revision=334701
* libpmc: improve arg checkingMatt Macy2018-06-041-7/+12
| | | | Notes: svn path=/head/; revision=334639
* libpmc: Intel doesn't require runtime counter table initMatt Macy2018-06-011-0/+3
| | | | Notes: svn path=/head/; revision=334463
* hwpmc: remove unused pre-table driven bits for intelMatt Macy2018-05-311-2097/+1
| | | | | | | | | | | | | | | | | | | Intel now provides comprehensive tables for all performance counters and the various valid configuration permutations as text .json files. Libpmc has been converted to use these and hwpmc_core has been greatly simplified by moving to passthrough of the table values. The one gotcha is that said tables don't support pentium pro and and pentium IV. There's very few users of hwpmc on _amd64_ kernels on new hardware. It is unlikely that anyone is doing low level optimization on 15 year old Intel hardware. Nonetheless, if someone feels strongly enough to populate the corresponding tables for p4 and ppro I will reinstate the files in to the build. Code for the K8 counters and !x86 architectures remains unchanged. Notes: svn path=/head/; revision=334456
* libpmc: squelch valgrind warningsMatt Macy2018-05-301-1/+2
| | | | Notes: svn path=/head/; revision=334371
* pmc_annotate: adhere to the APIEric van Gyzen2018-05-291-1/+2
| | | | | | | | | | If the 'mode' parameter was invalid, pmc_annotate() would return EINVAL instead of setting errno and returning -1. Sponsored by: Dell EMC Notes: svn path=/head/; revision=334351
* libpmc: don't return -1 on success in pmc_allocateMatt Macy2018-05-291-1/+1
| | | | Notes: svn path=/head/; revision=334349
* libpmc: don't leak string in error case eitherMatt Macy2018-05-291-4/+5
| | | | | | | Reported by: vangyzen@ Notes: svn path=/head/; revision=334347
* libpmc: free allocated string on return from pmc_allocateMatt Macy2018-05-291-0/+1
| | | | | | | | Reported by: Coverity CID: 1391359 Notes: svn path=/head/; revision=334345
* pmc(3)/hwpmc(4): update supported Intel processors to rely fully on theMatt Macy2018-05-261-9/+21
| | | | | | | | | | | | | | | | | | vendor provided pmu-events tables and sundry cleanups. The vendor pmu-events tables provide counter descriptions, default sample rates, event, umask, and flag values for all the counter configuration permutations. Using this gives us: - much simpler kernel code for the MD component - helpful long and short event descriptions - simpler user code - sample rates that won't overload the system Update man page with newer sample types and remove unused sample type. Notes: svn path=/head/; revision=334244
* Revert r334242 "pmc(3)/hwpmc(4): update supported Intel processors to rely ↵Matt Macy2018-05-261-21/+9
| | | | | | | | | fully on the" because of squash commit messages Notes: svn path=/head/; revision=334243
* pmc(3)/hwpmc(4): update supported Intel processors to rely fully on theMatt Macy2018-05-261-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vendor provided pmu-events tables and sundry cleanups. The vendor pmu-events tables provide counter descriptions, default sample rates, event, umask, and flag values for all the counter configuration permutations. Using this gives us: - much simpler kernel code for the MD component - helpful long and short event descriptions - simpler user code - sample rates that won't overload the system Update man page with newer sample types and remove unused sample type. Squashed commit of the following: commit 4459d43eff815bec08ccc5533dbe5de846f03128 Author: Matt Macy <mmacy@mattmacy.io> Date: Sat May 26 00:06:31 2018 -0700 libpmc: fix pmu function signatures for non amd64 commit a2cb8bbc586c65d41f9b291430a2261ec67b59fe Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 22:38:11 2018 -0700 pmcstat: fix indentation of usage commit f686954b15ff56a833ac80404898977cb80a265b Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 22:19:49 2018 -0700 pmclog(3): add callchain and pmcallocatedyn, remove pcsample commit 73e13a0d2e9498c81c150d14d022050cee7511bb Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 22:19:00 2018 -0700 pmclog.h: GC pcsample field commit 3e93ffd65da641fa657539dad3c48e281f8b5798 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 22:05:57 2018 -0700 hwpmc: make Intel core CPUs use external event tables commit 634f5fae1e1644ac324003136c66cd9c619d1c93 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 22:00:06 2018 -0700 pmclog: update log record types, bump PMC_MAJOR - explicitly make log record types a multiple of 8 bytes - hook in pmu event types for pmc_allocate records - remove references to no longer PCSAMPLE record commit 83d84fcd2d65bdf6ddcb2e155a22f0cfa2a9c225 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 21:52:10 2018 -0700 libpmc: add support for having vendor table driven pmc_allocate commit 9e6ad63c40c2fce8404847ace5078ca6cb33a736 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 19:11:33 2018 -0700 hwpmc_core: add accessors for EVSEL & UMASK, make IAP_UMASK useful to user commit 859dceb93daa6419a48c794db99b6758e5b041c9 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 19:09:45 2018 -0700 pmcstat: update usage and man page as well as make -L consistent with pmccontrol commit 79c7d8597e28c2eb13f5f9113e65ec2792ca57b1 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 18:07:03 2018 -0700 pmu_util: add support for all current intel event keywords commit d8089c7f6a6c8527f38324252b1ffb47004694c6 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 17:45:00 2018 -0700 add description for new arguments commit 058336740bab53c62ec88a3a026ea848cf3878c6 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 17:38:15 2018 -0700 libpmc: move pmu_events table and pmu_utils out of libpmcstat so that they can be used by pmc_allocate commit 049b66b382e2f833c3f47bc8df9e750cb265709f Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 16:12:41 2018 -0700 pmcstat: hook pmu_events counter description utility routines in commit f5e01e7b37a691dc045e1aa16b3ebdd162515de8 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 16:11:59 2018 -0700 pmu_events: add utility routines for listing counters and their descriptions commit cba4d4f8907f772279f86f18f915e0d74d33ac56 Author: Matt Macy <mmacy@mattmacy.io> Date: Fri May 25 16:09:50 2018 -0700 pmu-events: expand out skylake regex to simplify string matches Notes: svn path=/head/; revision=334242
* Replace the PMC class struct copy with an explicit memcpy()Justin Hibbits2018-01-131-1/+2
| | | | | | | | | | | | | This should be effectively a nop for all archs, but for some reason the codegen difference on the PowerPC 970 is such that the struct assignment doesn't work (unless a printf() using one of the elements in the copied struct follows it), while the memcpy() succeeds. On all archs the memcpy() should be expanded to an inline copy, since the copy is bounded to ~16 bytes. MFC after: 3 weeks Notes: svn path=/head/; revision=327911
* lib: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-261-0/+2
| | | | | | | | | | | | | | | Mainly focus on files that use BSD 2-Clause license, however the tool I was using mis-identified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Notes: svn path=/head/; revision=326219
* Skylake server core PMC support for hwpmc(4).Konstantin Belousov2017-09-061-1/+23
| | | | | | | | | | | Reviewed by: emaste Sponsored by: The FreeBSD Foundation Hardware provided by: Intel MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D12221 Notes: svn path=/head/; revision=323230
* Minor style changes to make forthcoming code stand out less.Konstantin Belousov2017-09-061-5/+6
| | | | | | | | | | Reviewed by: emaste Sponsored by: The FreeBSD Foundation MFC after: 2 weeks X-Differential revision: https://reviews.freebsd.org/D12221 Notes: svn path=/head/; revision=323229
* lib: minor spelling fixes in comments.Pedro F. Giffuni2016-05-011-1/+1
| | | | | | | No functional change. Notes: svn path=/head/; revision=298896
* Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's ↵Randall Stewart2015-11-301-1/+117
| | | | | | | | | | | | | | | have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc. Notes: svn path=/head/; revision=291494
* For the Cortex-A8 use the a8 and not the a9 events table.Bjoern A. Zeeb2015-10-141-1/+1
| | | | | | | | | MFC after: 2 weeks Sponsored by: DARPA/AFRL Differential Revision: https://reviews.freebsd.org/D3882 Notes: svn path=/head/; revision=289317
* o Rework ARMv7 events list using aliases - same way as we have for arm64.Ruslan Bukin2015-06-101-10/+53
| | | | | | | o Extend it with Cortex A9-specific events. Notes: svn path=/head/; revision=284218
* Use fixed enum values for PMC_CLASSES().John Baldwin2015-05-191-5/+12
| | | | | | | | | | | | This removes one of the frequent causes of ABI breakage when new CPU types are added to hwpmc(4). Differential Revision: https://reviews.freebsd.org/D2586 Reviewed by: davide, emaste, gnn (earlier version) MFC after: 2 weeks Notes: svn path=/head/; revision=283120
* Add Performance Monitoring Counters support for AArch64.Ruslan Bukin2015-05-191-0/+77
| | | | | | | | | | | | | Family-common and CPU-specific counters implemented. Supported CPUs: ARM Cortex A53/57/72. Reviewed by: andrew, bz, emaste, gnn, jhb Sponsored by: ARM Limited Differential Revision: https://reviews.freebsd.org/D2555 Notes: svn path=/head/; revision=283112
* Implement hwpmc(4) for Freescale e500 core.Justin Hibbits2015-04-181-2/+22
| | | | | | | | | | | This supports e500v1, e500v2, and e500mc. Tested only on e500v2, but the performance counters are identical across all, with e500mc having some additional events. Relnotes: Yes Notes: svn path=/head/; revision=281713
* Add support for the MIPS74K SoC family performance counters events.Adrian Chadd2015-04-051-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These are similar to the mips24k performance counters - some are available on perfcnt0/3, some are available on perfcnt1/4. However, the events aren't all the same. * Add the events, named the same as from Linux oprofile. * Verify they're the same as "MIPS32(R) 74KTM Processor Core Family Software User's Manual"; Document Number: MD00519; Revision 01.05. * Rename INSTRUCTIONS to something else, so it doesn't clash with the alias INSTRUCTIONS. I'll try to tidy this up later; there are a few other aliases to add and shuffle around. Tested: * QCA9558 SoC (AP135 board) - MIPS74Kc core (no FPU.) * make universe; where it didn't fail for other reasons. TODO: * It'd be nice to support the four performance counters in at least this hardware, rather than just two. Reviewed by: bsdimp ("looks good; don't break world".) Notes: svn path=/head/; revision=281098
* Use the correct event table for Haswell Xeon eventsRyan Stone2015-03-101-1/+1
| | | | | | | | | Differential Revision: https://reviews.freebsd.org/D1588 MFC after: 1 month Sponsored by: Sandvine Inc. Notes: svn path=/head/; revision=279833
* Add ARMv7 performance monitoring counters.Ruslan Bukin2015-01-281-0/+42
| | | | | | | | | Differential Revision: https://reviews.freebsd.org/D1687 Reviewed by: rpaulo Sponsored by: DARPA, AFRL Notes: svn path=/head/; revision=277835
* Update the hwpmc driver to have the new type HASWELL_XEON. AlsoRandall Stewart2015-01-141-1/+24
| | | | | | | | | | | | | | | | | | go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc. Notes: svn path=/head/; revision=277177
* For Xeon 7500 and 48XX (Nehalem EX and Westmere EX) variants of theKonstantin Belousov2014-06-041-1/+45
| | | | | | | | | | | | | | | | | Core i7 and Westmere processors, the uncore PMC subsystem is completely different from the uncore PMC on smaller versions of CPUs. Disable existing uncore hwpmc code for EX, otherwise non-existing MSRs are accessed. The cores PMCs seems to be identical for non-EX and EX, according to the SDM. Reviewed by: davide, fabient Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Notes: svn path=/head/; revision=267062
* Update hwpmc to support core events for Atom Silvermont microarchitecture.Hiren Panchasara2014-03-201-0/+22
| | | | | | | | | | (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks Notes: svn path=/head/; revision=263446
* Add hwpmc(4) support for the PowerPC 970 class processors, direct events.Justin Hibbits2014-02-011-10/+32
| | | | | | | | | | | | | | This also fixes asserts on removal of the module for the mpc74xx. The PowerPC 970 processors have two different types of events: direct events and indirect events. Thus far only direct events are supported. I included some documentation in the driver on how indirect events work, but support is for the future. MFC after: 1 month Notes: svn path=/head/; revision=261342
* Update hwpmc to support Haswell class processors.Sean Bruno2013-03-281-0/+62
| | | | | | | | | | | | | | | 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks Notes: svn path=/head/; revision=248842
* Update hwpmc to support the Xeon class of Ivybridge processors.Sean Bruno2013-01-311-1/+22
| | | | | | | | | | | | | | | | | case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks Notes: svn path=/head/; revision=246166
* Fix a few warnings from newer clang 3.2 in libpmc, about comparing enumDimitry Andric2012-11-051-2/+2
| | | | | | | | | | | pmc_event values against integer constants which fall outside the enum range. Reviewed by: fabient, sbruno MFC after: 3 days Notes: svn path=/head/; revision=242622
* Cleanup and rename some variables in libpmc and hwpmc.Sean Bruno2012-10-241-1/+1
| | | | | | | | | | Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ sbruno@ Obtained from: Yahoo! Inc. MFC after: 2 weeks Notes: svn path=/head/; revision=241974
* Update hwpmc to support the Xeon class of Sandybridge processors.Sean Bruno2012-10-191-3/+24
| | | | | | | | | | | | | | | | | (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks Notes: svn path=/head/; revision=241738
* Add Intel Ivy Bridge support to hwpmc(9).Fabien Thomas2012-09-061-8/+67
| | | | | | | | | | | | | Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan Notes: svn path=/head/; revision=240164
* Add software PMC support.Fabien Thomas2012-03-281-26/+92
| | | | | | | | | | | | | | | | New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month Notes: svn path=/head/; revision=233628
* Add Octeon-related parts to libpmcOleksandr Tymoshenko2012-03-231-0/+21
| | | | Notes: svn path=/head/; revision=233335
* Make reusable part of code have mips prefix, not mips24Oleksandr Tymoshenko2012-03-221-9/+10
| | | | Notes: svn path=/head/; revision=233320
* - Add support for the Intel Sandy Bridge microarchitecture (both core and ↵Davide Italiano2012-03-011-0/+36
| | | | | | | | | | | | | | uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks Notes: svn path=/head/; revision=232366
* Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).Justin Hibbits2011-12-241-0/+62
| | | | | | | | | | Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE Notes: svn path=/head/; revision=228869
* In lib/libpmc/libpmc.c, struct pmc_cputype_map's pm_cputype field shouldDimitry Andric2011-12-161-1/+1
| | | | | | | | | be of type 'enum pmc_cputype', not 'enum pmc_class'. MFC after: 1 week Notes: svn path=/head/; revision=228557
* Add a flush of the current PMC log buffer before displaying the next top.Fabien Thomas2011-10-181-0/+6
| | | | | | | | | | | As the underlying block is 4KB if the PMC throughput is low the measurement will be reported on the next tick. pmcstat(8) use the modified flush API to reclaim current buffer before displaying next top. MFC after: 1 month Notes: svn path=/head/; revision=226514
* Fix invalid class removal when IAF is not the last class.Fabien Thomas2010-09-051-4/+4
| | | | | | | | | Keep IAF class with 0 PMC and change the alias in libpmc to IAP. MFC after: 1 week Notes: svn path=/head/; revision=212224
* When configuring hwpmc to use the EXT_SNOOP event, only send a default ↵Ryan Stone2010-05-011-1/+8
| | | | | | | | | | cachestate qualifier on the Atom processor. Other Intel processors do not accept a cachestate qualifier and currently hwpmc will return EINVAL if you try to use the EXT_SNOOP event on those processors Approved by: jkoshy (mentor) MFC after: 2 weeks Notes: svn path=/head/; revision=207482
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