From 7e6cd705f344de2f9f08475a0fa2ef9191f88dd0 Mon Sep 17 00:00:00 2001 From: cvs2svn Date: Mon, 20 Mar 2000 08:47:53 +0000 Subject: This commit was manufactured by cvs2svn to create tag 'RELENG_4_0_0_RELEASE'. This commit was manufactured to restore the state of the 4.0-RELEASE image. Releases prior to 5.3-RELEASE are omitting the secure/ and crypto/ subdirs. --- COPYRIGHT | 2 +- Makefile | 2 +- Makefile.inc1 | 2 +- Makefile.upgrade | 2 +- README | 2 +- UPDATING | 2 +- bin/Makefile | 2 +- bin/Makefile.inc | 2 +- bin/cat/Makefile | 2 +- bin/cat/cat.1 | 2 +- bin/cat/cat.c | 2 +- bin/chio/Makefile | 2 +- bin/chio/chio.1 | 2 +- bin/chio/chio.c | 2 +- bin/chio/defs.h | 2 +- bin/chio/pathnames.h | 2 +- bin/chmod/Makefile | 2 +- bin/chmod/chmod.1 | 2 +- bin/chmod/chmod.c | 2 +- bin/cp/Makefile | 2 +- bin/cp/cp.1 | 2 +- bin/cp/cp.c | 2 +- bin/cp/extern.h | 2 +- bin/cp/utils.c | 2 +- bin/csh/Makefile | 2 +- bin/csh/USD.doc/Makefile | 2 +- bin/csh/USD.doc/csh.1 | 2 +- bin/csh/USD.doc/csh.2 | 2 +- bin/csh/USD.doc/csh.3 | 2 +- bin/csh/USD.doc/csh.4 | 2 +- bin/csh/USD.doc/csh.a | 2 +- bin/csh/USD.doc/csh.g | 2 +- bin/csh/USD.doc/tabs | 2 +- bin/csh/alloc.c | 2 +- bin/csh/char.c | 2 +- bin/csh/char.h | 2 +- bin/csh/const.c | 2 +- bin/csh/csh.1 | 2 +- bin/csh/csh.c | 2 +- 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lib/libc_r/uthread/uthread_attr_getdetachstate.c | 2 +- lib/libc_r/uthread/uthread_attr_getinheritsched.c | 2 +- lib/libc_r/uthread/uthread_attr_getschedparam.c | 2 +- lib/libc_r/uthread/uthread_attr_getschedpolicy.c | 2 +- lib/libc_r/uthread/uthread_attr_getscope.c | 2 +- lib/libc_r/uthread/uthread_attr_getstackaddr.c | 2 +- lib/libc_r/uthread/uthread_attr_getstacksize.c | 2 +- lib/libc_r/uthread/uthread_attr_init.c | 2 +- .../uthread/uthread_attr_setcreatesuspend_np.c | 2 +- lib/libc_r/uthread/uthread_attr_setdetachstate.c | 2 +- lib/libc_r/uthread/uthread_attr_setinheritsched.c | 2 +- lib/libc_r/uthread/uthread_attr_setprio.c | 2 +- lib/libc_r/uthread/uthread_attr_setschedparam.c | 2 +- lib/libc_r/uthread/uthread_attr_setschedpolicy.c | 2 +- lib/libc_r/uthread/uthread_attr_setscope.c | 2 +- lib/libc_r/uthread/uthread_attr_setstackaddr.c | 2 +- lib/libc_r/uthread/uthread_attr_setstacksize.c | 2 +- lib/libc_r/uthread/uthread_autoinit.cc | 2 +- lib/libc_r/uthread/uthread_bind.c | 2 +- lib/libc_r/uthread/uthread_cancel.c | 2 +- lib/libc_r/uthread/uthread_clean.c | 2 +- lib/libc_r/uthread/uthread_close.c | 2 +- lib/libc_r/uthread/uthread_cond.c | 2 +- lib/libc_r/uthread/uthread_condattr_destroy.c | 2 +- lib/libc_r/uthread/uthread_condattr_init.c | 2 +- lib/libc_r/uthread/uthread_connect.c | 2 +- lib/libc_r/uthread/uthread_creat.c | 2 +- lib/libc_r/uthread/uthread_create.c | 2 +- lib/libc_r/uthread/uthread_detach.c | 2 +- lib/libc_r/uthread/uthread_dup.c | 2 +- lib/libc_r/uthread/uthread_dup2.c | 2 +- lib/libc_r/uthread/uthread_equal.c | 2 +- lib/libc_r/uthread/uthread_execve.c | 2 +- lib/libc_r/uthread/uthread_exit.c | 2 +- lib/libc_r/uthread/uthread_fchflags.c | 2 +- lib/libc_r/uthread/uthread_fchmod.c | 2 +- lib/libc_r/uthread/uthread_fchown.c | 2 +- lib/libc_r/uthread/uthread_fcntl.c | 2 +- lib/libc_r/uthread/uthread_fd.c | 2 +- lib/libc_r/uthread/uthread_file.c | 2 +- lib/libc_r/uthread/uthread_find_thread.c | 2 +- lib/libc_r/uthread/uthread_flock.c | 2 +- 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lib/libc_r/uthread/uthread_multi_np.c | 2 +- lib/libc_r/uthread/uthread_mutex.c | 2 +- lib/libc_r/uthread/uthread_mutex_prioceiling.c | 2 +- lib/libc_r/uthread/uthread_mutex_protocol.c | 2 +- lib/libc_r/uthread/uthread_mutexattr_destroy.c | 2 +- lib/libc_r/uthread/uthread_nanosleep.c | 2 +- lib/libc_r/uthread/uthread_once.c | 2 +- lib/libc_r/uthread/uthread_open.c | 2 +- lib/libc_r/uthread/uthread_pause.c | 2 +- lib/libc_r/uthread/uthread_pipe.c | 2 +- lib/libc_r/uthread/uthread_poll.c | 2 +- lib/libc_r/uthread/uthread_priority_queue.c | 2 +- lib/libc_r/uthread/uthread_read.c | 2 +- lib/libc_r/uthread/uthread_readv.c | 2 +- lib/libc_r/uthread/uthread_recvfrom.c | 2 +- lib/libc_r/uthread/uthread_recvmsg.c | 2 +- lib/libc_r/uthread/uthread_resume_np.c | 2 +- lib/libc_r/uthread/uthread_rwlock.c | 2 +- lib/libc_r/uthread/uthread_rwlockattr.c | 2 +- lib/libc_r/uthread/uthread_select.c | 2 +- lib/libc_r/uthread/uthread_self.c | 2 +- lib/libc_r/uthread/uthread_sem.c | 2 +- lib/libc_r/uthread/uthread_sendmsg.c | 2 +- lib/libc_r/uthread/uthread_sendto.c | 2 +- lib/libc_r/uthread/uthread_seterrno.c | 2 +- lib/libc_r/uthread/uthread_setprio.c | 2 +- lib/libc_r/uthread/uthread_setschedparam.c | 2 +- lib/libc_r/uthread/uthread_setsockopt.c | 2 +- lib/libc_r/uthread/uthread_shutdown.c | 2 +- lib/libc_r/uthread/uthread_sig.c | 2 +- lib/libc_r/uthread/uthread_sigaction.c | 2 +- lib/libc_r/uthread/uthread_sigblock.c | 2 +- lib/libc_r/uthread/uthread_sigmask.c | 2 +- lib/libc_r/uthread/uthread_signal.c | 2 +- lib/libc_r/uthread/uthread_sigpending.c | 2 +- lib/libc_r/uthread/uthread_sigprocmask.c | 2 +- lib/libc_r/uthread/uthread_sigsetmask.c | 2 +- lib/libc_r/uthread/uthread_sigsuspend.c | 2 +- lib/libc_r/uthread/uthread_sigwait.c | 2 +- lib/libc_r/uthread/uthread_single_np.c | 2 +- lib/libc_r/uthread/uthread_sleep.c | 2 +- lib/libc_r/uthread/uthread_socket.c | 2 +- lib/libc_r/uthread/uthread_socketpair.c | 2 +- lib/libc_r/uthread/uthread_spec.c | 2 +- lib/libc_r/uthread/uthread_spinlock.c | 2 +- lib/libc_r/uthread/uthread_suspend_np.c | 2 +- lib/libc_r/uthread/uthread_switch_np.c | 2 +- lib/libc_r/uthread/uthread_system.c | 2 +- lib/libc_r/uthread/uthread_tcdrain.c | 2 +- lib/libc_r/uthread/uthread_wait.c | 2 +- lib/libc_r/uthread/uthread_wait4.c | 2 +- lib/libc_r/uthread/uthread_waitpid.c | 2 +- lib/libc_r/uthread/uthread_write.c | 2 +- lib/libc_r/uthread/uthread_writev.c | 2 +- lib/libc_r/uthread/uthread_yield.c | 2 +- lib/libcalendar/Makefile | 2 +- lib/libcalendar/calendar.3 | 2 +- lib/libcalendar/calendar.c | 2 +- lib/libcalendar/calendar.h | 2 +- lib/libcalendar/easter.c | 2 +- lib/libcam/Makefile | 2 +- lib/libcam/cam.3 | 2 +- lib/libcam/cam_cdbparse.3 | 2 +- lib/libcam/camlib.c | 2 +- lib/libcam/camlib.h | 2 +- lib/libcam/scsi_cmdparse.c | 2 +- lib/libcom_err/Makefile | 2 +- lib/libcom_err/doc/Makefile | 2 +- lib/libcom_err/doc/com_err.texinfo | 2 +- lib/libcompat/4.1/ascftime.c | 2 +- lib/libcompat/4.1/cftime.3 | 2 +- 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+- lib/libdisk/disklabel.c | 2 +- lib/libdisk/libdisk.3 | 2 +- lib/libdisk/libdisk.h | 2 +- lib/libdisk/rules.c | 2 +- lib/libdisk/tst01.c | 2 +- lib/libdisk/write_disk.c | 2 +- lib/libedit/Makefile | 2 +- lib/libedit/editline.3 | 2 +- lib/libedit/editrc.5 | 2 +- lib/libfetch/Makefile | 2 +- lib/libfetch/common.c | 2 +- lib/libfetch/common.h | 2 +- lib/libfetch/fetch.3 | 2 +- lib/libfetch/fetch.c | 2 +- lib/libfetch/fetch.h | 2 +- lib/libfetch/fetch_err.et | 2 +- lib/libfetch/file.c | 2 +- lib/libfetch/ftp.c | 2 +- lib/libfetch/ftp.errors | 2 +- lib/libfetch/http.c | 2 +- lib/libfetch/http.errors | 2 +- lib/libform/Makefile | 2 +- lib/libftpio/Makefile | 2 +- lib/libftpio/ftp.errors | 2 +- lib/libftpio/ftpio.3 | 2 +- lib/libftpio/ftpio.c | 2 +- lib/libftpio/ftpio.h | 2 +- lib/libgnumalloc/Makefile | 2 +- lib/libio/Makefile | 2 +- lib/libio/alpha_sethae.c | 4 +- lib/libio/bwx.c | 2 +- lib/libio/io.c | 2 +- lib/libio/io.h | 2 +- lib/libio/swiz.c | 2 +- lib/libipsec/Makefile | 2 +- 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lib/msun/man/ieee.3 | 2 +- lib/msun/man/ieee_test.3 | 2 +- lib/msun/man/j0.3 | 2 +- lib/msun/man/lgamma.3 | 2 +- lib/msun/man/math.3 | 2 +- lib/msun/man/rint.3 | 2 +- lib/msun/man/sin.3 | 2 +- lib/msun/man/sinh.3 | 2 +- lib/msun/man/sqrt.3 | 2 +- lib/msun/man/tan.3 | 2 +- lib/msun/man/tanh.3 | 2 +- lib/msun/src/e_acos.c | 2 +- lib/msun/src/e_acosf.c | 2 +- lib/msun/src/e_acosh.c | 2 +- lib/msun/src/e_acoshf.c | 2 +- lib/msun/src/e_asin.c | 2 +- lib/msun/src/e_asinf.c | 2 +- lib/msun/src/e_atan2.c | 2 +- lib/msun/src/e_atan2f.c | 2 +- lib/msun/src/e_atanh.c | 2 +- lib/msun/src/e_atanhf.c | 2 +- lib/msun/src/e_cosh.c | 2 +- lib/msun/src/e_coshf.c | 2 +- lib/msun/src/e_exp.c | 2 +- lib/msun/src/e_expf.c | 2 +- lib/msun/src/e_fmod.c | 2 +- lib/msun/src/e_fmodf.c | 2 +- lib/msun/src/e_gamma.c | 2 +- lib/msun/src/e_gamma_r.c | 2 +- lib/msun/src/e_gammaf.c | 2 +- lib/msun/src/e_gammaf_r.c | 2 +- lib/msun/src/e_hypot.c | 2 +- lib/msun/src/e_hypotf.c | 2 +- lib/msun/src/e_j0.c | 2 +- lib/msun/src/e_j0f.c | 2 +- lib/msun/src/e_j1.c | 2 +- lib/msun/src/e_j1f.c | 2 +- lib/msun/src/e_jn.c | 2 +- lib/msun/src/e_jnf.c | 2 +- lib/msun/src/e_lgamma.c | 2 +- lib/msun/src/e_lgamma_r.c | 2 +- lib/msun/src/e_lgammaf.c | 2 +- lib/msun/src/e_lgammaf_r.c | 2 +- lib/msun/src/e_log.c | 2 +- lib/msun/src/e_log10.c | 2 +- lib/msun/src/e_log10f.c | 2 +- lib/msun/src/e_logf.c | 2 +- lib/msun/src/e_pow.c | 2 +- lib/msun/src/e_powf.c | 2 +- lib/msun/src/e_rem_pio2.c | 2 +- lib/msun/src/e_rem_pio2f.c | 2 +- lib/msun/src/e_remainder.c | 2 +- lib/msun/src/e_remainderf.c | 2 +- lib/msun/src/e_scalb.c | 2 +- lib/msun/src/e_scalbf.c | 2 +- lib/msun/src/e_sinh.c | 2 +- lib/msun/src/e_sinhf.c | 2 +- lib/msun/src/e_sqrt.c | 2 +- lib/msun/src/e_sqrtf.c | 2 +- lib/msun/src/get_hw_float.c | 2 +- lib/msun/src/k_cos.c | 2 +- lib/msun/src/k_cosf.c | 2 +- lib/msun/src/k_rem_pio2.c | 2 +- lib/msun/src/k_rem_pio2f.c | 2 +- lib/msun/src/k_sin.c | 2 +- lib/msun/src/k_sinf.c | 2 +- lib/msun/src/k_standard.c | 2 +- lib/msun/src/k_tan.c | 2 +- lib/msun/src/k_tanf.c | 2 +- lib/msun/src/math.h | 2 +- lib/msun/src/math_private.h | 2 +- lib/msun/src/s_asinh.c | 2 +- lib/msun/src/s_asinhf.c | 2 +- lib/msun/src/s_atan.c | 2 +- lib/msun/src/s_atanf.c | 2 +- lib/msun/src/s_cbrt.c | 2 +- lib/msun/src/s_cbrtf.c | 2 +- lib/msun/src/s_ceil.c | 2 +- lib/msun/src/s_ceilf.c | 2 +- lib/msun/src/s_copysign.c | 2 +- lib/msun/src/s_copysignf.c | 2 +- lib/msun/src/s_cos.c | 2 +- lib/msun/src/s_cosf.c | 2 +- lib/msun/src/s_erf.c | 2 +- lib/msun/src/s_erff.c | 2 +- lib/msun/src/s_expm1.c | 2 +- lib/msun/src/s_expm1f.c | 2 +- lib/msun/src/s_fabs.c | 2 +- lib/msun/src/s_fabsf.c | 2 +- lib/msun/src/s_finite.c | 2 +- lib/msun/src/s_finitef.c | 2 +- lib/msun/src/s_floor.c | 2 +- lib/msun/src/s_floorf.c | 2 +- lib/msun/src/s_frexp.c | 2 +- lib/msun/src/s_frexpf.c | 2 +- lib/msun/src/s_ilogb.c | 2 +- lib/msun/src/s_ilogbf.c | 2 +- lib/msun/src/s_isnan.c | 2 +- lib/msun/src/s_isnanf.c | 2 +- lib/msun/src/s_ldexp.c | 2 +- lib/msun/src/s_ldexpf.c | 2 +- lib/msun/src/s_lib_version.c | 2 +- lib/msun/src/s_log1p.c | 2 +- lib/msun/src/s_log1pf.c | 2 +- lib/msun/src/s_logb.c | 2 +- lib/msun/src/s_logbf.c | 2 +- lib/msun/src/s_matherr.c | 2 +- lib/msun/src/s_modf.c | 2 +- lib/msun/src/s_modff.c | 2 +- lib/msun/src/s_nextafter.c | 2 +- lib/msun/src/s_nextafterf.c | 2 +- lib/msun/src/s_rint.c | 2 +- lib/msun/src/s_rintf.c | 2 +- lib/msun/src/s_scalbn.c | 2 +- lib/msun/src/s_scalbnf.c | 2 +- lib/msun/src/s_significand.c | 2 +- lib/msun/src/s_significandf.c | 2 +- lib/msun/src/s_sin.c | 2 +- lib/msun/src/s_sinf.c | 2 +- lib/msun/src/s_tan.c | 2 +- lib/msun/src/s_tanf.c | 2 +- lib/msun/src/s_tanh.c | 2 +- lib/msun/src/s_tanhf.c | 2 +- lib/msun/src/w_acos.c | 2 +- lib/msun/src/w_acosf.c | 2 +- lib/msun/src/w_acosh.c | 2 +- lib/msun/src/w_acoshf.c | 2 +- lib/msun/src/w_asin.c | 2 +- lib/msun/src/w_asinf.c | 2 +- lib/msun/src/w_atan2.c | 2 +- lib/msun/src/w_atan2f.c | 2 +- lib/msun/src/w_atanh.c | 2 +- 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sys/cam/scsi/scsi_sa.h | 2 +- sys/cam/scsi/scsi_ses.c | 2 +- sys/cam/scsi/scsi_ses.h | 2 +- sys/cam/scsi/scsi_targ_bh.c | 2 +- sys/cam/scsi/scsi_target.c | 2 +- sys/cam/scsi/scsi_targetio.h | 2 +- sys/coda/cnode.h | 2 +- sys/coda/coda.h | 2 +- sys/coda/coda_fbsd.c | 2 +- sys/coda/coda_io.h | 2 +- sys/coda/coda_kernel.h | 2 +- sys/coda/coda_namecache.c | 2 +- sys/coda/coda_namecache.h | 2 +- sys/coda/coda_opstats.h | 2 +- sys/coda/coda_pioctl.h | 2 +- sys/coda/coda_psdev.c | 2 +- sys/coda/coda_psdev.h | 2 +- sys/coda/coda_subr.c | 2 +- sys/coda/coda_subr.h | 2 +- sys/coda/coda_venus.c | 2 +- sys/coda/coda_venus.h | 2 +- sys/coda/coda_vfsops.c | 2 +- sys/coda/coda_vfsops.h | 2 +- sys/coda/coda_vnops.c | 2 +- sys/coda/coda_vnops.h | 2 +- sys/conf/Makefile.alpha | 2 +- sys/conf/Makefile.i386 | 2 +- sys/conf/Makefile.pc98 | 2 +- sys/conf/files | 2 +- sys/conf/files.alpha | 2 +- sys/conf/files.i386 | 2 +- sys/conf/files.pc98 | 2 +- sys/conf/ldscript.alpha | 2 +- sys/conf/ldscript.i386 | 2 +- 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sys/crypto/cast128/cast128_subkey.h | 2 +- sys/crypto/des/des.h | 2 +- sys/crypto/des/des_3cbc.c | 2 +- sys/crypto/des/des_cbc.c | 2 +- sys/crypto/des/des_ecb.c | 2 +- sys/crypto/des/des_locl.h | 2 +- sys/crypto/des/des_setkey.c | 2 +- sys/crypto/des/podd.h | 2 +- sys/crypto/des/sk.h | 2 +- sys/crypto/des/spr.h | 2 +- sys/crypto/hmac_md5.c | 2 +- sys/crypto/hmac_md5.h | 2 +- sys/crypto/md5.c | 2 +- sys/crypto/md5.h | 2 +- sys/crypto/rc5/rc5.c | 2 +- sys/crypto/rc5/rc5.h | 2 +- sys/crypto/rc5/rc5_cbc.c | 2 +- sys/crypto/sha1.c | 2 +- sys/crypto/sha1.h | 2 +- sys/ddb/db_access.c | 2 +- sys/ddb/db_access.h | 2 +- sys/ddb/db_aout.c | 2 +- sys/ddb/db_break.c | 2 +- sys/ddb/db_break.h | 2 +- sys/ddb/db_command.c | 2 +- sys/ddb/db_command.h | 2 +- sys/ddb/db_examine.c | 2 +- sys/ddb/db_expr.c | 2 +- sys/ddb/db_input.c | 2 +- sys/ddb/db_kld.c | 2 +- sys/ddb/db_lex.c | 2 +- sys/ddb/db_lex.h | 2 +- sys/ddb/db_output.c | 2 +- sys/ddb/db_output.h | 2 +- sys/ddb/db_print.c | 2 +- sys/ddb/db_ps.c | 2 +- sys/ddb/db_run.c | 2 +- sys/ddb/db_sym.c | 2 +- sys/ddb/db_sym.h | 2 +- sys/ddb/db_sysctl.c | 2 +- sys/ddb/db_trap.c | 2 +- sys/ddb/db_variables.c | 2 +- sys/ddb/db_variables.h | 2 +- sys/ddb/db_watch.c | 2 +- sys/ddb/db_watch.h | 2 +- sys/ddb/db_write_cmd.c | 2 +- sys/ddb/ddb.h | 2 +- sys/dev/advansys/adv_eisa.c | 2 +- sys/dev/advansys/adv_isa.c | 2 +- sys/dev/advansys/adv_pci.c | 2 +- sys/dev/advansys/advansys.c | 2 +- sys/dev/advansys/advansys.h | 2 +- sys/dev/advansys/advlib.c | 2 +- sys/dev/advansys/advlib.h | 2 +- sys/dev/advansys/advmcode.c | 2 +- sys/dev/advansys/advmcode.h | 2 +- sys/dev/advansys/adw_pci.c | 2 +- sys/dev/advansys/adwcam.c | 2 +- sys/dev/advansys/adwlib.c | 2 +- sys/dev/advansys/adwlib.h | 2 +- sys/dev/advansys/adwmcode.c | 2 +- sys/dev/advansys/adwmcode.h | 2 +- sys/dev/advansys/adwvar.h | 2 +- sys/dev/aha/aha.c | 2 +- sys/dev/aha/aha_isa.c | 2 +- sys/dev/aha/aha_mca.c | 2 +- sys/dev/aha/ahareg.h | 2 +- sys/dev/ahb/ahb.c | 2 +- sys/dev/ahb/ahbreg.h | 2 +- sys/dev/aic/aic.c | 2 +- sys/dev/aic/aic6360reg.h | 2 +- sys/dev/aic/aic_isa.c | 2 +- sys/dev/aic/aic_pccard.c | 2 +- sys/dev/aic/aicvar.h | 2 +- sys/dev/aic7xxx/93cx6.c | 2 +- sys/dev/aic7xxx/93cx6.h | 2 +- sys/dev/aic7xxx/Makefile | 2 +- sys/dev/aic7xxx/ahc_eisa.c | 2 +- sys/dev/aic7xxx/ahc_pci.c | 2 +- sys/dev/aic7xxx/aic7xxx.c | 2 +- sys/dev/aic7xxx/aic7xxx.h | 2 +- sys/dev/aic7xxx/aic7xxx.reg | 2 +- sys/dev/aic7xxx/aic7xxx.seq | 2 +- sys/dev/aic7xxx/aicasm.c | 2 +- sys/dev/aic7xxx/aicasm.h | 2 +- sys/dev/aic7xxx/aicasm_gram.y | 2 +- sys/dev/aic7xxx/aicasm_scan.l | 2 +- sys/dev/aic7xxx/aicasm_symbol.c | 2 +- sys/dev/aic7xxx/aicasm_symbol.h | 2 +- sys/dev/aic7xxx/sequencer.h | 2 +- sys/dev/amr/amr.c | 2 +- sys/dev/amr/amr_disk.c | 2 +- sys/dev/amr/amr_pci.c | 2 +- sys/dev/amr/amrio.h | 2 +- sys/dev/amr/amrreg.h | 2 +- sys/dev/amr/amrvar.h | 2 +- sys/dev/an/if_aironet_ieee.h | 2 +- sys/dev/an/if_an.c | 4 +- sys/dev/an/if_an_isa.c | 2 +- sys/dev/an/if_an_pccard.c | 2 +- sys/dev/an/if_an_pci.c | 4 +- sys/dev/an/if_anreg.h | 2 +- sys/dev/ata/ata-all.c | 2 +- sys/dev/ata/ata-all.h | 2 +- sys/dev/ata/ata-disk.c | 2 +- sys/dev/ata/ata-disk.h | 2 +- sys/dev/ata/ata-dma.c | 2 +- sys/dev/ata/atapi-all.c | 2 +- sys/dev/ata/atapi-all.h | 2 +- sys/dev/ata/atapi-cd.c | 2 +- sys/dev/ata/atapi-cd.h | 2 +- sys/dev/ata/atapi-fd.c | 2 +- sys/dev/ata/atapi-fd.h | 2 +- sys/dev/ata/atapi-tape.c | 2 +- sys/dev/ata/atapi-tape.h | 2 +- sys/dev/bktr/CHANGELOG.TXT | 2 +- sys/dev/bktr/bktr_audio.c | 2 +- sys/dev/bktr/bktr_audio.h | 2 +- sys/dev/bktr/bktr_card.c | 2 +- sys/dev/bktr/bktr_card.h | 2 +- sys/dev/bktr/bktr_core.c | 2 +- sys/dev/bktr/bktr_core.h | 2 +- sys/dev/bktr/bktr_i2c.c | 2 +- sys/dev/bktr/bktr_i2c.h | 2 +- sys/dev/bktr/bktr_os.c | 2 +- sys/dev/bktr/bktr_os.h | 2 +- sys/dev/bktr/bktr_reg.h | 2 +- sys/dev/bktr/bktr_tuner.c | 2 +- sys/dev/bktr/bktr_tuner.h | 2 +- sys/dev/buslogic/bt.c | 2 +- sys/dev/buslogic/bt_eisa.c | 2 +- sys/dev/buslogic/bt_isa.c | 2 +- sys/dev/buslogic/bt_mca.c | 2 +- sys/dev/buslogic/bt_pci.c | 2 +- sys/dev/buslogic/btreg.h | 2 +- sys/dev/cardbus/Makefile.cardbusdevs | 2 +- sys/dev/cardbus/cardbus.c | 2 +- sys/dev/cardbus/cardbusdevs | 2 +- sys/dev/cardbus/cardbusdevs.h | 2 +- sys/dev/cardbus/cardbusdevs_data.h | 2 +- sys/dev/cardbus/cardbusreg.h | 2 +- sys/dev/cardbus/cardbusvar.h | 2 +- sys/dev/cardbus/devlist2h.awk | 2 +- sys/dev/cardbus/pccardcis.h | 2 +- sys/dev/ccd/ccd.c | 2 +- sys/dev/dec/mcclock.c | 2 +- sys/dev/dec/mcclock_if.m | 2 +- sys/dev/dpt/dpt.h | 2 +- sys/dev/dpt/dpt_control.c | 2 +- sys/dev/dpt/dpt_eisa.c | 2 +- sys/dev/dpt/dpt_pci.c | 2 +- sys/dev/dpt/dpt_pci.h | 2 +- sys/dev/dpt/dpt_scsi.c | 2 +- sys/dev/ed/if_ed.c | 2 +- sys/dev/ed/if_ed_isa.c | 2 +- sys/dev/ed/if_ed_pccard.c | 2 +- sys/dev/ed/if_ed_pci.c | 2 +- sys/dev/ed/if_edreg.h | 2 +- sys/dev/ed/if_edvar.h | 2 +- sys/dev/eisa/eisaconf.c | 2 +- sys/dev/eisa/eisaconf.h | 2 +- sys/dev/en/midway.c | 2 +- sys/dev/ep/if_ep.c | 2 +- sys/dev/ep/if_ep_eisa.c | 2 +- sys/dev/ep/if_ep_isa.c | 2 +- sys/dev/ep/if_ep_mca.c | 2 +- sys/dev/ep/if_ep_pccard.c | 2 +- sys/dev/ep/if_epreg.h | 2 +- sys/dev/ep/if_epvar.h | 2 +- sys/dev/ex/if_ex.c | 2 +- sys/dev/fb/fb.c | 2 +- sys/dev/fb/fbreg.h | 2 +- sys/dev/fb/splash.c | 2 +- sys/dev/fb/splashreg.h | 2 +- sys/dev/fb/vga.c | 2 +- sys/dev/fb/vgareg.h | 2 +- sys/dev/hea/eni.c | 4 +- sys/dev/hea/eni.h | 2 +- sys/dev/hea/eni_buffer.c | 4 +- sys/dev/hea/eni_globals.c | 4 +- sys/dev/hea/eni_if.c | 4 +- sys/dev/hea/eni_init.c | 4 +- sys/dev/hea/eni_intr.c | 4 +- sys/dev/hea/eni_receive.c | 4 +- sys/dev/hea/eni_stats.h | 2 +- sys/dev/hea/eni_suni.h | 2 +- sys/dev/hea/eni_transmit.c | 4 +- sys/dev/hea/eni_var.h | 2 +- sys/dev/hea/eni_vcm.c | 4 +- sys/dev/hfa/fore.h | 2 +- sys/dev/hfa/fore_aali.h | 2 +- sys/dev/hfa/fore_buffer.c | 4 +- sys/dev/hfa/fore_command.c | 4 +- sys/dev/hfa/fore_globals.c | 4 +- sys/dev/hfa/fore_if.c | 4 +- sys/dev/hfa/fore_include.h | 2 +- sys/dev/hfa/fore_init.c | 4 +- sys/dev/hfa/fore_intr.c | 4 +- sys/dev/hfa/fore_load.c | 4 +- sys/dev/hfa/fore_output.c | 4 +- sys/dev/hfa/fore_receive.c | 4 +- sys/dev/hfa/fore_slave.h | 2 +- sys/dev/hfa/fore_stats.c | 4 +- sys/dev/hfa/fore_stats.h | 2 +- sys/dev/hfa/fore_timer.c | 4 +- sys/dev/hfa/fore_transmit.c | 4 +- sys/dev/hfa/fore_var.h | 2 +- sys/dev/hfa/fore_vcm.c | 4 +- sys/dev/ida/ida.c | 2 +- sys/dev/ida/ida_disk.c | 2 +- sys/dev/ida/ida_eisa.c | 2 +- sys/dev/ida/ida_pci.c | 2 +- sys/dev/ida/idareg.h | 2 +- sys/dev/ida/idavar.h | 2 +- sys/dev/ie/if_ie.c | 2 +- sys/dev/ie/if_ie507.h | 2 +- sys/dev/ie/if_iereg.h | 2 +- sys/dev/iicbus/if_ic.c | 2 +- sys/dev/iicbus/iic.c | 2 +- sys/dev/iicbus/iicbb.c | 2 +- sys/dev/iicbus/iicbb_if.m | 2 +- sys/dev/iicbus/iicbus.c | 2 +- sys/dev/iicbus/iicbus.h | 2 +- sys/dev/iicbus/iicbus_if.m | 2 +- sys/dev/iicbus/iiconf.c | 2 +- sys/dev/iicbus/iiconf.h | 2 +- sys/dev/iicbus/iicsmb.c | 2 +- sys/dev/isp/MAINTAINER | 2 +- sys/dev/isp/asm_pci.h | 2 +- sys/dev/isp/isp.c | 2 +- sys/dev/isp/isp_freebsd.c | 2 +- sys/dev/isp/isp_freebsd.h | 2 +- sys/dev/isp/isp_inline.h | 2 +- sys/dev/isp/isp_target.c | 2 +- sys/dev/isp/isp_target.h | 2 +- sys/dev/isp/isp_tpublic.h | 2 +- sys/dev/isp/ispmbox.h | 2 +- sys/dev/isp/ispreg.h | 2 +- sys/dev/isp/ispvar.h | 2 +- sys/dev/kbd/atkbd.c | 2 +- sys/dev/kbd/atkbdc.c | 2 +- sys/dev/kbd/atkbdcreg.h | 2 +- sys/dev/kbd/atkbdreg.h | 2 +- sys/dev/kbd/kbd.c | 2 +- sys/dev/kbd/kbdreg.h | 2 +- sys/dev/kbd/kbdtables.h | 2 +- sys/dev/mca/mca_bus.c | 2 +- sys/dev/mca/mca_busreg.h | 2 +- sys/dev/mca/mca_busvar.h | 2 +- sys/dev/md/md.c | 2 +- sys/dev/mii/Makefile.miidevs | 2 +- sys/dev/mii/amphy.c | 4 +- sys/dev/mii/amphyreg.h | 2 +- sys/dev/mii/dcphy.c | 4 +- sys/dev/mii/devlist2h.awk | 2 +- sys/dev/mii/exphy.c | 2 +- sys/dev/mii/mii.c | 2 +- sys/dev/mii/mii.h | 2 +- sys/dev/mii/mii_physubr.c | 2 +- sys/dev/mii/miibus_if.m | 2 +- sys/dev/mii/miidevs | 2 +- sys/dev/mii/miidevs.h | 2 +- sys/dev/mii/miivar.h | 2 +- sys/dev/mii/mlphy.c | 2 +- sys/dev/mii/nsphy.c | 2 +- sys/dev/mii/nsphyreg.h | 2 +- sys/dev/mii/pnphy.c | 4 +- sys/dev/mii/rlphy.c | 4 +- sys/dev/mii/tlphy.c | 2 +- sys/dev/mii/tlphyreg.h | 2 +- sys/dev/mii/ukphy.c | 2 +- sys/dev/mii/ukphy_subr.c | 2 +- sys/dev/mlx/mlx.c | 2 +- sys/dev/mlx/mlx_disk.c | 2 +- sys/dev/mlx/mlx_pci.c | 2 +- sys/dev/mlx/mlxio.h | 2 +- sys/dev/mlx/mlxreg.h | 2 +- sys/dev/mlx/mlxvar.h | 2 +- sys/dev/pccard/Makefile.pccarddevs | 2 +- sys/dev/pccard/card_if.m | 2 +- sys/dev/pccard/devlist2h.awk | 2 +- sys/dev/pccard/files.pccard | 2 +- sys/dev/pccard/pccard.c | 2 +- sys/dev/pccard/pccard_cis.c | 2 +- sys/dev/pccard/pccard_cis_quirks.c | 2 +- sys/dev/pccard/pccardchip.h | 2 +- sys/dev/pccard/pccarddevs | 2 +- sys/dev/pccard/pccarddevs.h | 2 +- sys/dev/pccard/pccarddevs_data.h | 2 +- sys/dev/pccard/pccardreg.h | 2 +- sys/dev/pccard/pccardvar.h | 2 +- sys/dev/pccard/power_if.m | 2 +- sys/dev/pcic/i82365.c | 2 +- sys/dev/pcic/i82365_isa.c | 2 +- sys/dev/pcic/i82365reg.h | 2 +- sys/dev/pcic/i82365var.h | 2 +- sys/dev/pdq/if_fea.c | 2 +- sys/dev/pdq/if_fpa.c | 2 +- sys/dev/pdq/pdq.c | 2 +- sys/dev/pdq/pdq_ifsubr.c | 2 +- sys/dev/pdq/pdqreg.h | 2 +- sys/dev/pdq/pdqvar.h | 2 +- sys/dev/ppbus/if_plip.c | 2 +- sys/dev/ppbus/immio.c | 2 +- sys/dev/ppbus/lpbb.c | 2 +- sys/dev/ppbus/lpt.c | 2 +- sys/dev/ppbus/lpt.h | 2 +- sys/dev/ppbus/pcfclock.c | 2 +- sys/dev/ppbus/ppb_1284.c | 2 +- sys/dev/ppbus/ppb_1284.h | 2 +- sys/dev/ppbus/ppb_base.c | 2 +- sys/dev/ppbus/ppb_msq.c | 2 +- sys/dev/ppbus/ppb_msq.h | 2 +- sys/dev/ppbus/ppbconf.c | 2 +- sys/dev/ppbus/ppbconf.h | 2 +- sys/dev/ppbus/ppbio.h | 2 +- sys/dev/ppbus/ppbus_if.m | 2 +- sys/dev/ppbus/ppi.c | 2 +- sys/dev/ppbus/ppi.h | 2 +- sys/dev/ppbus/pps.c | 2 +- sys/dev/ppbus/vpo.c | 2 +- sys/dev/ppbus/vpoio.c | 2 +- sys/dev/ppbus/vpoio.h | 2 +- sys/dev/si/si.c | 2 +- sys/dev/si/si.h | 2 +- sys/dev/si/si2_z280.c | 2 +- sys/dev/si/si3_t225.c | 2 +- sys/dev/si/si_eisa.c | 2 +- sys/dev/si/si_isa.c | 2 +- sys/dev/si/si_pci.c | 2 +- sys/dev/si/sireg.h | 2 +- sys/dev/si/sivar.h | 2 +- sys/dev/smbus/smb.c | 2 +- sys/dev/smbus/smbconf.c | 2 +- sys/dev/smbus/smbconf.h | 2 +- sys/dev/smbus/smbus.c | 2 +- sys/dev/smbus/smbus.h | 2 +- sys/dev/smbus/smbus_if.m | 2 +- sys/dev/sn/if_sn.c | 2 +- sys/dev/sn/if_sn_isa.c | 2 +- sys/dev/sn/if_sn_pccard.c | 2 +- sys/dev/sn/if_snreg.h | 2 +- sys/dev/sn/if_snvar.h | 2 +- sys/dev/sound/chip.h | 2 +- sys/dev/sound/isa/ad1816.c | 2 +- sys/dev/sound/isa/ad1816.h | 2 +- sys/dev/sound/isa/es1888.c | 2 +- sys/dev/sound/isa/gusc.c | 2 +- sys/dev/sound/isa/mss.c | 2 +- sys/dev/sound/isa/mss.h | 2 +- sys/dev/sound/isa/sb.c | 2 +- sys/dev/sound/isa/sb.h | 2 +- sys/dev/sound/isa/sbc.c | 2 +- sys/dev/sound/pci/aureal.c | 2 +- sys/dev/sound/pci/aureal.h | 2 +- sys/dev/sound/pci/csa.c | 2 +- sys/dev/sound/pci/csaimg.h | 2 +- sys/dev/sound/pci/csapcm.c | 2 +- sys/dev/sound/pci/csareg.h | 2 +- sys/dev/sound/pci/csavar.h | 2 +- sys/dev/sound/pci/es137x.c | 2 +- sys/dev/sound/pci/es137x.h | 2 +- sys/dev/sound/pci/neomagic-coeff.h | 2 +- sys/dev/sound/pci/neomagic.c | 2 +- sys/dev/sound/pci/neomagic.h | 2 +- sys/dev/sound/pci/t4dwave.c | 2 +- sys/dev/sound/pci/t4dwave.h | 2 +- sys/dev/sound/pcm/ac97.c | 2 +- sys/dev/sound/pcm/ac97.h | 2 +- sys/dev/sound/pcm/channel.c | 2 +- sys/dev/sound/pcm/channel.h | 2 +- sys/dev/sound/pcm/datatypes.h | 2 +- sys/dev/sound/pcm/dsp.c | 2 +- sys/dev/sound/pcm/dsp.h | 2 +- sys/dev/sound/pcm/fake.c | 2 +- sys/dev/sound/pcm/feeder.c | 2 +- sys/dev/sound/pcm/mixer.c | 2 +- sys/dev/sound/pcm/mixer.h | 2 +- sys/dev/sound/pcm/sound.c | 2 +- sys/dev/sound/pcm/sound.h | 2 +- sys/dev/streams/streams.c | 2 +- sys/dev/sym/sym_conf.h | 2 +- sys/dev/sym/sym_defs.h | 2 +- sys/dev/sym/sym_hipd.c | 2 +- sys/dev/syscons/schistory.c | 2 +- sys/dev/syscons/scmouse.c | 2 +- sys/dev/syscons/scterm-dumb.c | 2 +- sys/dev/syscons/scterm-sc.c | 2 +- sys/dev/syscons/scterm.c | 2 +- sys/dev/syscons/sctermvar.h | 2 +- sys/dev/syscons/scvesactl.c | 2 +- sys/dev/syscons/scvgarndr.c | 2 +- sys/dev/syscons/scvidctl.c | 2 +- sys/dev/syscons/scvtb.c | 2 +- sys/dev/syscons/syscons.c | 2 +- sys/dev/syscons/syscons.h | 2 +- sys/dev/syscons/sysmouse.c | 2 +- sys/dev/usb/FILES | 2 +- sys/dev/usb/Makefile.usbdevs | 2 +- sys/dev/usb/devlist2h.awk | 2 +- sys/dev/usb/hid.c | 2 +- sys/dev/usb/hid.h | 2 +- sys/dev/usb/if_aue.c | 4 +- sys/dev/usb/if_auereg.h | 2 +- sys/dev/usb/if_cue.c | 4 +- sys/dev/usb/if_cuereg.h | 2 +- sys/dev/usb/if_kue.c | 4 +- sys/dev/usb/if_kuereg.h | 2 +- sys/dev/usb/kue_fw.h | 2 +- sys/dev/usb/ohci.c | 2 +- sys/dev/usb/ohcireg.h | 2 +- sys/dev/usb/ohcivar.h | 2 +- sys/dev/usb/ugen.c | 2 +- sys/dev/usb/uhci.c | 2 +- sys/dev/usb/uhcireg.h | 2 +- sys/dev/usb/uhcivar.h | 2 +- sys/dev/usb/uhid.c | 2 +- sys/dev/usb/uhub.c | 2 +- sys/dev/usb/ukbd.c | 2 +- sys/dev/usb/ulpt.c | 2 +- sys/dev/usb/umass.c | 2 +- sys/dev/usb/umodem.c | 2 +- sys/dev/usb/ums.c | 2 +- sys/dev/usb/usb.c | 2 +- sys/dev/usb/usb.h | 2 +- sys/dev/usb/usb_ethersubr.c | 4 +- sys/dev/usb/usb_ethersubr.h | 2 +- sys/dev/usb/usb_if.m | 2 +- sys/dev/usb/usb_mem.h | 2 +- sys/dev/usb/usb_port.h | 2 +- sys/dev/usb/usb_quirks.c | 2 +- sys/dev/usb/usb_quirks.h | 2 +- sys/dev/usb/usb_subr.c | 2 +- sys/dev/usb/usbcdc.h | 2 +- sys/dev/usb/usbdevs | 2 +- sys/dev/usb/usbdevs.h | 2 +- sys/dev/usb/usbdevs_data.h | 2 +- sys/dev/usb/usbdi.c | 2 +- sys/dev/usb/usbdi.h | 2 +- sys/dev/usb/usbdi_util.c | 2 +- sys/dev/usb/usbdi_util.h | 2 +- sys/dev/usb/usbdivar.h | 2 +- sys/dev/usb/usbhid.h | 2 +- sys/dev/vinum/COPYRIGHT | 2 +- sys/dev/vinum/makestatetext | 2 +- sys/dev/vinum/request.h | 2 +- sys/dev/vinum/statetexts.h | 2 +- sys/dev/vinum/vinum.c | 2 +- sys/dev/vinum/vinumconfig.c | 2 +- sys/dev/vinum/vinumdaemon.c | 2 +- sys/dev/vinum/vinumext.h | 2 +- sys/dev/vinum/vinumhdr.h | 2 +- sys/dev/vinum/vinuminterrupt.c | 2 +- sys/dev/vinum/vinumio.c | 2 +- sys/dev/vinum/vinumio.h | 2 +- sys/dev/vinum/vinumioctl.c | 2 +- sys/dev/vinum/vinumkw.h | 2 +- sys/dev/vinum/vinumlock.c | 2 +- sys/dev/vinum/vinummemory.c | 2 +- sys/dev/vinum/vinumparser.c | 2 +- sys/dev/vinum/vinumraid5.c | 2 +- sys/dev/vinum/vinumrequest.c | 2 +- sys/dev/vinum/vinumrevive.c | 2 +- sys/dev/vinum/vinumstate.c | 2 +- sys/dev/vinum/vinumstate.h | 2 +- sys/dev/vinum/vinumutil.c | 2 +- sys/dev/vinum/vinumvar.h | 2 +- sys/dev/vn/vn.c | 2 +- sys/dev/vx/if_vx.c | 2 +- sys/dev/vx/if_vx_eisa.c | 2 +- sys/dev/vx/if_vx_pci.c | 2 +- sys/dev/xe/if_xe.c | 2 +- sys/dev/xe/if_xereg.h | 2 +- sys/dev/xe/if_xevar.h | 2 +- sys/fs/hpfs/hpfs.h | 2 +- sys/fs/hpfs/hpfs_alsubr.c | 2 +- sys/fs/hpfs/hpfs_hash.c | 2 +- sys/fs/hpfs/hpfs_ioctl.h | 2 +- sys/fs/hpfs/hpfs_lookup.c | 2 +- sys/fs/hpfs/hpfs_subr.c | 2 +- sys/fs/hpfs/hpfs_subr.h | 2 +- sys/fs/hpfs/hpfs_vfsops.c | 2 +- sys/fs/hpfs/hpfs_vnops.c | 2 +- sys/fs/hpfs/hpfsmount.h | 2 +- sys/gnu/ext2fs/COPYRIGHT.INFO | 2 +- sys/gnu/ext2fs/ext2_fs.h | 2 +- sys/gnu/ext2fs/ext2_inode_cnv.c | 2 +- sys/gnu/ext2fs/ext2_lookup.c | 2 +- sys/gnu/ext2fs/ext2_readwrite.c | 2 +- sys/gnu/ext2fs/ext2_vfsops.c | 2 +- sys/gnu/ext2fs/ext2_vnops.c | 2 +- sys/gnu/ext2fs/i386-bitops.h | 2 +- sys/gnu/i386/fpemul/control_w.h | 2 +- sys/gnu/i386/fpemul/div_small.s | 2 +- sys/gnu/i386/fpemul/errors.c | 2 +- sys/gnu/i386/fpemul/exception.h | 2 +- sys/gnu/i386/fpemul/fpu_arith.c | 2 +- sys/gnu/i386/fpemul/fpu_asm.h | 2 +- sys/gnu/i386/fpemul/fpu_aux.c | 2 +- sys/gnu/i386/fpemul/fpu_emu.h | 2 +- sys/gnu/i386/fpemul/fpu_entry.c | 2 +- sys/gnu/i386/fpemul/fpu_etc.c | 2 +- sys/gnu/i386/fpemul/fpu_proto.h | 2 +- sys/gnu/i386/fpemul/fpu_system.h | 2 +- sys/gnu/i386/fpemul/fpu_trig.c | 2 +- sys/gnu/i386/fpemul/get_address.c | 2 +- sys/gnu/i386/fpemul/load_store.c | 2 +- sys/gnu/i386/fpemul/math_emu.h | 2 +- sys/gnu/i386/fpemul/poly_2xm1.c | 2 +- sys/gnu/i386/fpemul/poly_atan.c | 2 +- sys/gnu/i386/fpemul/poly_div.s | 2 +- sys/gnu/i386/fpemul/poly_l2.c | 2 +- sys/gnu/i386/fpemul/poly_mul64.s | 2 +- sys/gnu/i386/fpemul/poly_sin.c | 2 +- sys/gnu/i386/fpemul/poly_tan.c | 2 +- sys/gnu/i386/fpemul/polynomial.s | 2 +- sys/gnu/i386/fpemul/reg_add_sub.c | 2 +- sys/gnu/i386/fpemul/reg_compare.c | 2 +- sys/gnu/i386/fpemul/reg_constant.h | 2 +- sys/gnu/i386/fpemul/reg_div.s | 2 +- sys/gnu/i386/fpemul/reg_ld_str.c | 2 +- sys/gnu/i386/fpemul/reg_mul.c | 2 +- sys/gnu/i386/fpemul/reg_norm.s | 2 +- sys/gnu/i386/fpemul/reg_round.s | 2 +- sys/gnu/i386/fpemul/reg_u_add.s | 2 +- sys/gnu/i386/fpemul/reg_u_div.s | 2 +- sys/gnu/i386/fpemul/reg_u_mul.s | 2 +- sys/gnu/i386/fpemul/reg_u_sub.s | 2 +- sys/gnu/i386/fpemul/status_w.h | 2 +- sys/gnu/i386/fpemul/version.h | 2 +- sys/gnu/i386/fpemul/wm_shrx.s | 2 +- sys/gnu/i386/fpemul/wm_sqrt.s | 2 +- sys/gnu/i386/isa/dgb.c | 2 +- sys/gnu/i386/isa/dgm.c | 2 +- sys/gnu/i386/isa/dgmbios.h | 2 +- sys/gnu/i386/isa/dgmfep.h | 2 +- sys/gnu/i386/isa/dgmreg.h | 2 +- sys/gnu/i386/isa/dgreg.h | 2 +- sys/i386/Makefile | 2 +- sys/i386/apm/apm.c | 2 +- sys/i386/apm/apm.h | 2 +- sys/i386/bios/mca_machdep.c | 158 - sys/i386/bios/mca_machdep.h | 31 - sys/i386/boot/Makefile | 2 +- sys/i386/boot/Makefile.inc | 2 +- sys/i386/boot/biosboot/Makefile | 2 +- sys/i386/boot/biosboot/README.386BSD | 2 +- sys/i386/boot/biosboot/README.MACH | 2 +- sys/i386/boot/biosboot/README.serial | 2 +- sys/i386/boot/biosboot/asm.S | 2 +- sys/i386/boot/biosboot/asm.h | 2 +- sys/i386/boot/biosboot/bios.S | 2 +- sys/i386/boot/biosboot/boot.c | 2 +- sys/i386/boot/biosboot/boot.h | 2 +- sys/i386/boot/biosboot/boot2.S | 2 +- sys/i386/boot/biosboot/disk.c | 2 +- sys/i386/boot/biosboot/io.c | 2 +- sys/i386/boot/biosboot/probe_keyboard.c | 2 +- sys/i386/boot/biosboot/serial.S | 2 +- sys/i386/boot/biosboot/start.S | 2 +- sys/i386/boot/biosboot/sys.c | 2 +- sys/i386/boot/biosboot/table.c | 2 +- sys/i386/boot/cdboot/Makefile | 2 +- sys/i386/boot/cdboot/asm.S | 2 +- sys/i386/boot/cdboot/boot.c | 2 +- sys/i386/boot/cdboot/boot.h | 2 +- sys/i386/boot/cdboot/cdrom.c | 2 +- sys/i386/boot/cdboot/malloc.c | 2 +- sys/i386/boot/dosboot/Makefile | 2 +- sys/i386/boot/dosboot/ansi.h | 2 +- sys/i386/boot/dosboot/boot.c | 2 +- sys/i386/boot/dosboot/boot.h | 2 +- sys/i386/boot/dosboot/bootinfo.h | 2 +- sys/i386/boot/dosboot/cdefs.h | 2 +- sys/i386/boot/dosboot/dinode.h | 2 +- sys/i386/boot/dosboot/dir.h | 2 +- sys/i386/boot/dosboot/dirent.h | 2 +- sys/i386/boot/dosboot/disk.c | 2 +- sys/i386/boot/dosboot/disklabe.h | 2 +- sys/i386/boot/dosboot/endian.h | 2 +- sys/i386/boot/dosboot/exec.h | 2 +- sys/i386/boot/dosboot/fbsdboot.mak | 2 +- sys/i386/boot/dosboot/fs.h | 2 +- sys/i386/boot/dosboot/imgact.h | 2 +- sys/i386/boot/dosboot/inode.h | 2 +- sys/i386/boot/dosboot/mexec.h | 2 +- sys/i386/boot/dosboot/param.h | 2 +- sys/i386/boot/dosboot/quota.h | 2 +- sys/i386/boot/dosboot/reboot.h | 2 +- sys/i386/boot/dosboot/sys.c | 2 +- sys/i386/boot/dosboot/syslimit.h | 2 +- sys/i386/boot/dosboot/sysparam.h | 2 +- sys/i386/boot/dosboot/types.h | 2 +- sys/i386/boot/kzipboot/Makefile | 2 +- sys/i386/boot/netboot/3c509.c | 2 +- sys/i386/boot/netboot/Makefile | 2 +- sys/i386/boot/netboot/netboot.8 | 2 +- sys/i386/boot/rawboot/Makefile | 2 +- sys/i386/conf/GENERIC | 2 +- sys/i386/conf/LINT | 2 +- sys/i386/conf/NEWCARD | 2 +- sys/i386/i386/atomic.c | 2 +- sys/i386/i386/autoconf.c | 2 +- sys/i386/i386/bios.c | 2 +- sys/i386/i386/bioscall.s | 2 +- sys/i386/i386/busdma_machdep.c | 2 +- sys/i386/i386/db_disasm.c | 2 +- sys/i386/i386/db_interface.c | 2 +- sys/i386/i386/db_trace.c | 2 +- sys/i386/i386/elf_machdep.c | 2 +- sys/i386/i386/exception.s | 2 +- sys/i386/i386/genassym.c | 2 +- sys/i386/i386/globals.s | 2 +- sys/i386/i386/i686_mem.c | 2 +- sys/i386/i386/identcpu.c | 2 +- sys/i386/i386/in_cksum.c | 2 +- sys/i386/i386/initcpu.c | 2 +- sys/i386/i386/k6_mem.c | 2 +- sys/i386/i386/locore.s | 2 +- sys/i386/i386/machdep.c | 2 +- sys/i386/i386/math_emu.h | 2 +- sys/i386/i386/math_emulate.c | 2 +- sys/i386/i386/mem.c | 2 +- sys/i386/i386/mp_clock.c | 2 +- sys/i386/i386/mp_machdep.c | 2 +- sys/i386/i386/mpapic.c | 2 +- sys/i386/i386/mpboot.s | 2 +- sys/i386/i386/mplock.s | 2 +- sys/i386/i386/nexus.c | 2 +- sys/i386/i386/perfmon.c | 2 +- sys/i386/i386/pmap.c | 2 +- sys/i386/i386/procfs_machdep.c | 2 +- sys/i386/i386/simplelock.s | 2 +- sys/i386/i386/support.s | 2 +- sys/i386/i386/swtch.s | 2 +- sys/i386/i386/symbols.raw | 2 +- sys/i386/i386/sys_machdep.c | 2 +- sys/i386/i386/trap.c | 2 +- sys/i386/i386/userconfig.c | 4 +- sys/i386/i386/vm86.c | 2 +- sys/i386/i386/vm86bios.s | 2 +- sys/i386/i386/vm_machdep.c | 2 +- sys/i386/ibcs2/Makefile | 2 +- sys/i386/ibcs2/coff.h | 2 +- sys/i386/ibcs2/ibcs2_fcntl.c | 2 +- sys/i386/ibcs2/ibcs2_ioctl.c | 2 +- sys/i386/ibcs2/ibcs2_ipc.c | 2 +- sys/i386/ibcs2/ibcs2_ipc.h | 2 +- sys/i386/ibcs2/ibcs2_isc.c | 2 +- sys/i386/ibcs2/ibcs2_misc.c | 2 +- sys/i386/ibcs2/ibcs2_msg.c | 2 +- sys/i386/ibcs2/ibcs2_other.c | 2 +- sys/i386/ibcs2/ibcs2_poll.h | 2 +- sys/i386/ibcs2/ibcs2_signal.c | 2 +- sys/i386/ibcs2/ibcs2_signal.h | 2 +- sys/i386/ibcs2/ibcs2_stat.c | 2 +- sys/i386/ibcs2/ibcs2_sysvec.c | 2 +- sys/i386/ibcs2/ibcs2_util.c | 2 +- sys/i386/ibcs2/ibcs2_xenix.c | 2 +- sys/i386/ibcs2/imgact_coff.c | 2 +- sys/i386/ibcs2/syscalls.conf | 2 +- sys/i386/ibcs2/syscalls.isc | 2 +- sys/i386/ibcs2/syscalls.isc.conf | 2 +- sys/i386/ibcs2/syscalls.master | 2 +- sys/i386/ibcs2/syscalls.xenix | 2 +- sys/i386/ibcs2/syscalls.xenix.conf | 2 +- sys/i386/include/ansi.h | 2 +- sys/i386/include/apic.h | 2 +- sys/i386/include/apm_bios.h | 2 +- sys/i386/include/apm_segments.h | 2 +- sys/i386/include/asm.h | 2 +- sys/i386/include/asmacros.h | 2 +- sys/i386/include/asnames.h | 2 +- sys/i386/include/atomic.h | 2 +- sys/i386/include/bootinfo.h | 2 +- sys/i386/include/bus.h | 2 +- sys/i386/include/bus_memio.h | 2 +- sys/i386/include/bus_pio.h | 2 +- sys/i386/include/cdk.h | 2 +- sys/i386/include/clock.h | 2 +- sys/i386/include/comstats.h | 2 +- sys/i386/include/cpu.h | 2 +- sys/i386/include/cpufunc.h | 2 +- sys/i386/include/cputypes.h | 2 +- sys/i386/include/cronyx.h | 2 +- sys/i386/include/db_machdep.h | 2 +- sys/i386/include/elf.h | 2 +- sys/i386/include/endian.h | 2 +- sys/i386/include/exec.h | 2 +- sys/i386/include/float.h | 2 +- sys/i386/include/floatingpoint.h | 2 +- sys/i386/include/frame.h | 2 +- sys/i386/include/globaldata.h | 2 +- sys/i386/include/globals.h | 2 +- sys/i386/include/i4b_cause.h | 2 +- sys/i386/include/i4b_debug.h | 2 +- sys/i386/include/i4b_ioctl.h | 2 +- sys/i386/include/i4b_rbch_ioctl.h | 2 +- sys/i386/include/i4b_tel_ioctl.h | 2 +- sys/i386/include/i4b_trace.h | 2 +- sys/i386/include/ieeefp.h | 2 +- sys/i386/include/if_wavelan_ieee.h | 2 +- sys/i386/include/if_wl_wavelan.h | 2 +- sys/i386/include/iic.h | 2 +- sys/i386/include/in_cksum.h | 2 +- sys/i386/include/ioctl_bt848.h | 2 +- sys/i386/include/ioctl_ctx.h | 2 +- sys/i386/include/ioctl_fd.h | 2 +- sys/i386/include/ioctl_meteor.h | 2 +- sys/i386/include/ipl.h | 2 +- sys/i386/include/limits.h | 2 +- sys/i386/include/lock.h | 2 +- sys/i386/include/lpt.h | 2 +- sys/i386/include/md_var.h | 2 +- sys/i386/include/mouse.h | 2 +- sys/i386/include/mpapic.h | 2 +- sys/i386/include/mtpr.h | 2 +- sys/i386/include/npx.h | 2 +- sys/i386/include/param.h | 2 +- sys/i386/include/pc/bios.h | 2 +- sys/i386/include/pc/display.h | 2 +- sys/i386/include/pc/msdos.h | 2 +- sys/i386/include/pc/vesa.h | 2 +- sys/i386/include/pcaudioio.h | 2 +- sys/i386/include/pcb.h | 2 +- sys/i386/include/pcb_ext.h | 2 +- sys/i386/include/pcvt_ioctl.h | 2 +- sys/i386/include/perfmon.h | 2 +- sys/i386/include/pmap.h | 2 +- sys/i386/include/proc.h | 2 +- sys/i386/include/profile.h | 2 +- sys/i386/include/psl.h | 2 +- sys/i386/include/ptrace.h | 2 +- sys/i386/include/random.h | 2 +- sys/i386/include/reg.h | 2 +- sys/i386/include/reloc.h | 2 +- sys/i386/include/resource.h | 2 +- sys/i386/include/segments.h | 2 +- sys/i386/include/setjmp.h | 2 +- sys/i386/include/sigframe.h | 2 +- sys/i386/include/signal.h | 2 +- sys/i386/include/smb.h | 2 +- sys/i386/include/smp.h | 2 +- sys/i386/include/smptests.h | 2 +- sys/i386/include/speaker.h | 2 +- sys/i386/include/specialreg.h | 2 +- sys/i386/include/spigot.h | 2 +- sys/i386/include/stdarg.h | 2 +- sys/i386/include/sysarch.h | 2 +- sys/i386/include/trap.h | 2 +- sys/i386/include/tss.h | 2 +- sys/i386/include/types.h | 2 +- sys/i386/include/ucontext.h | 2 +- sys/i386/include/varargs.h | 2 +- sys/i386/include/vm86.h | 2 +- sys/i386/include/vmparam.h | 2 +- sys/i386/include/wtio.h | 2 +- sys/i386/isa/README.le | 2 +- sys/i386/isa/adv_isa.c | 2 +- sys/i386/isa/apic_ipl.h | 2 +- sys/i386/isa/apic_ipl.s | 2 +- sys/i386/isa/apic_vector.s | 2 +- sys/i386/isa/asc.c | 2 +- sys/i386/isa/ascreg.h | 2 +- sys/i386/isa/atapi.c | 2 +- sys/i386/isa/atapi.h | 2 +- sys/i386/isa/bs/bs.c | 2 +- sys/i386/isa/bs/bsfunc.c | 2 +- sys/i386/isa/bs/bsif.c | 2 +- sys/i386/isa/bs/bsif.h | 2 +- sys/i386/isa/clock.c | 2 +- sys/i386/isa/ctx.c | 2 +- sys/i386/isa/ctxreg.h | 2 +- sys/i386/isa/cx.c | 2 +- sys/i386/isa/cy.c | 2 +- sys/i386/isa/cyreg.h | 2 +- sys/i386/isa/elink.c | 2 +- sys/i386/isa/elink.h | 2 +- sys/i386/isa/gpib.c | 2 +- sys/i386/isa/gsc.c | 2 +- sys/i386/isa/ic/cd1400.h | 2 +- sys/i386/isa/ic/esp.h | 2 +- sys/i386/isa/ic/hd64570.h | 2 +- sys/i386/isa/ic/i8237.h | 2 +- sys/i386/isa/ic/i8251.h | 2 +- sys/i386/isa/ic/i82586.h | 2 +- sys/i386/isa/ic/lemac.h | 2 +- sys/i386/isa/ic/ns16550.h | 2 +- sys/i386/isa/ic/rsa.h | 2 +- sys/i386/isa/ic/scd1400.h | 2 +- sys/i386/isa/icu.h | 2 +- sys/i386/isa/icu_ipl.h | 2 +- sys/i386/isa/icu_ipl.s | 2 +- sys/i386/isa/icu_vector.s | 2 +- sys/i386/isa/if_ar.c | 2 +- sys/i386/isa/if_ar.h | 2 +- sys/i386/isa/if_arregs.h | 2 +- sys/i386/isa/if_cs.c | 2 +- sys/i386/isa/if_csreg.h | 2 +- sys/i386/isa/if_cx.c | 2 +- sys/i386/isa/if_el.c | 2 +- sys/i386/isa/if_elreg.h | 2 +- sys/i386/isa/if_fe.c | 2 +- sys/i386/isa/if_fereg.h | 2 +- sys/i386/isa/if_le.c | 2 +- sys/i386/isa/if_lnc.c | 2 +- sys/i386/isa/if_lnc.h | 2 +- sys/i386/isa/if_rdp.c | 2 +- sys/i386/isa/if_rdpreg.h | 2 +- sys/i386/isa/if_sr.c | 2 +- sys/i386/isa/if_sr.h | 2 +- sys/i386/isa/if_srregs.h | 2 +- sys/i386/isa/if_wi.c | 4 +- sys/i386/isa/if_wireg.h | 2 +- sys/i386/isa/if_wl.c | 2 +- sys/i386/isa/intr_machdep.c | 4 +- sys/i386/isa/intr_machdep.h | 2 +- sys/i386/isa/ipl.s | 2 +- sys/i386/isa/ipl_funcs.c | 2 +- sys/i386/isa/isa.c | 2 +- sys/i386/isa/isa.h | 2 +- sys/i386/isa/isa_compat.c | 2 +- sys/i386/isa/isa_compat.h | 2 +- sys/i386/isa/isa_device.h | 2 +- sys/i386/isa/isa_dma.c | 2 +- sys/i386/isa/isa_dma.h | 2 +- sys/i386/isa/istallion.c | 2 +- sys/i386/isa/labpc.c | 2 +- sys/i386/isa/loran.c | 2 +- sys/i386/isa/lptreg.h | 2 +- sys/i386/isa/matcd/matcd.c | 2 +- sys/i386/isa/mca_machdep.c | 2 +- sys/i386/isa/mca_machdep.h | 2 +- sys/i386/isa/mcd.c | 2 +- sys/i386/isa/mcdreg.h | 2 +- sys/i386/isa/mse.c | 2 +- sys/i386/isa/npx.c | 2 +- sys/i386/isa/pcaudio.c | 2 +- sys/i386/isa/pcf.c | 2 +- sys/i386/isa/pcibus.c | 2 +- sys/i386/isa/pcibus.h | 2 +- sys/i386/isa/pcvt/pcvt_conf.h | 2 +- sys/i386/isa/pcvt/pcvt_drv.c | 2 +- sys/i386/isa/pcvt/pcvt_ext.c | 2 +- sys/i386/isa/pcvt/pcvt_hdr.h | 2 +- sys/i386/isa/pcvt/pcvt_kbd.c | 2 +- sys/i386/isa/pcvt/pcvt_kbd.h | 2 +- sys/i386/isa/pcvt/pcvt_out.c | 2 +- sys/i386/isa/pcvt/pcvt_sup.c | 2 +- sys/i386/isa/pcvt/pcvt_tbl.h | 2 +- sys/i386/isa/pcvt/pcvt_vtf.c | 2 +- sys/i386/isa/prof_machdep.c | 2 +- sys/i386/isa/random_machdep.c | 2 +- sys/i386/isa/rc.c | 2 +- sys/i386/isa/rp.c | 2 +- sys/i386/isa/scd.c | 2 +- sys/i386/isa/scdreg.h | 2 +- sys/i386/isa/sound/ad1848.c | 2 +- sys/i386/isa/sound/cs4232.c | 2 +- sys/i386/isa/sound/dev_table.c | 2 +- sys/i386/isa/sound/gus_wave.c | 2 +- sys/i386/isa/sound/mmap_test.c | 2 +- sys/i386/isa/sound/opl3.c | 2 +- sys/i386/isa/sound/pas2_mixer.c | 2 +- sys/i386/isa/sound/pcm86.c | 2 +- sys/i386/isa/sound/sb16_dsp.c | 2 +- sys/i386/isa/sound/sb16_midi.c | 2 +- sys/i386/isa/sound/sb_dsp.c | 2 +- sys/i386/isa/sound/sbcard.h | 2 +- sys/i386/isa/sound/sound.doc | 2 +- sys/i386/isa/sound/sound_config.h | 2 +- sys/i386/isa/sound/soundcard.c | 2 +- sys/i386/isa/sound/sscape.c | 2 +- sys/i386/isa/spigot.c | 2 +- sys/i386/isa/spkr.c | 2 +- sys/i386/isa/stallion.c | 2 +- sys/i386/isa/timerreg.h | 2 +- sys/i386/isa/tw.c | 2 +- sys/i386/isa/vector.s | 2 +- sys/i386/isa/vesa.c | 2 +- sys/i386/isa/wd.c | 2 +- sys/i386/isa/wd_cd.c | 2 +- sys/i386/isa/wd_cd.h | 2 +- sys/i386/isa/wdreg.h | 2 +- sys/i386/isa/wfd.c | 2 +- sys/i386/isa/wst.c | 2 +- sys/i386/isa/wt.c | 2 +- sys/i386/isa/wtreg.h | 2 +- sys/i386/linux/Makefile | 2 +- sys/i386/linux/imgact_linux.c | 2 +- sys/i386/linux/linux.h | 2 +- sys/i386/linux/linux_dummy.c | 2 +- sys/i386/linux/linux_file.c | 2 +- sys/i386/linux/linux_genassym.c | 2 +- sys/i386/linux/linux_ioctl.c | 2 +- sys/i386/linux/linux_ioctl.h | 2 +- sys/i386/linux/linux_ipc.c | 2 +- sys/i386/linux/linux_locore.s | 2 +- sys/i386/linux/linux_mib.c | 2 +- sys/i386/linux/linux_mib.h | 2 +- sys/i386/linux/linux_misc.c | 2 +- sys/i386/linux/linux_proto.h | 2 +- sys/i386/linux/linux_signal.c | 2 +- sys/i386/linux/linux_socket.c | 2 +- sys/i386/linux/linux_stats.c | 2 +- sys/i386/linux/linux_syscall.h | 2 +- sys/i386/linux/linux_sysent.c | 2 +- sys/i386/linux/linux_sysvec.c | 2 +- sys/i386/linux/linux_util.c | 2 +- sys/i386/linux/linux_util.h | 2 +- sys/i386/linux/syscalls.conf | 2 +- sys/i386/linux/syscalls.master | 2 +- sys/i386/svr4/svr4_genassym.c | 2 +- sys/i386/svr4/svr4_locore.s | 2 +- sys/i386/svr4/svr4_machdep.c | 2 +- sys/i386/svr4/svr4_machdep.h | 2 +- sys/i4b/driver/i4b_bsdi_ibc.c | 2 +- sys/i4b/driver/i4b_ctl.c | 2 +- sys/i4b/driver/i4b_ipr.c | 2 +- sys/i4b/driver/i4b_isppp.c | 2 +- sys/i4b/driver/i4b_rbch.c | 2 +- sys/i4b/driver/i4b_tel.c | 2 +- sys/i4b/driver/i4b_trace.c | 2 +- sys/i4b/include/i4b_global.h | 2 +- sys/i4b/include/i4b_isdnq931.h | 2 +- sys/i4b/include/i4b_l1l2.h | 2 +- sys/i4b/include/i4b_l2l3.h | 2 +- sys/i4b/include/i4b_l3l4.h | 2 +- sys/i4b/include/i4b_mbuf.h | 2 +- sys/i4b/layer1/i4b_asuscom_ipac.c | 2 +- sys/i4b/layer1/i4b_avm_a1.c | 2 +- sys/i4b/layer1/i4b_avm_fritz_pci.c | 2 +- sys/i4b/layer1/i4b_avm_fritz_pcmcia.c | 2 +- sys/i4b/layer1/i4b_avm_fritz_pnp.c | 2 +- sys/i4b/layer1/i4b_bchan.c | 2 +- sys/i4b/layer1/i4b_ctx_s0P.c | 2 +- sys/i4b/layer1/i4b_drn_ngo.c | 2 +- sys/i4b/layer1/i4b_dynalink.c | 2 +- sys/i4b/layer1/i4b_elsa_isdnmc.c | 2 +- sys/i4b/layer1/i4b_elsa_mcall.c | 2 +- sys/i4b/layer1/i4b_elsa_pcc16.c | 2 +- sys/i4b/layer1/i4b_elsa_qs1i.c | 2 +- sys/i4b/layer1/i4b_elsa_qs1p.c | 2 +- sys/i4b/layer1/i4b_hscx.c | 2 +- sys/i4b/layer1/i4b_hscx.h | 2 +- sys/i4b/layer1/i4b_ipac.h | 2 +- sys/i4b/layer1/i4b_isac.c | 2 +- sys/i4b/layer1/i4b_isac.h | 2 +- sys/i4b/layer1/i4b_isic.c | 2 +- sys/i4b/layer1/i4b_isic_isa.c | 2 +- sys/i4b/layer1/i4b_isic_pcmcia.c | 2 +- sys/i4b/layer1/i4b_isic_pnp.c | 2 +- sys/i4b/layer1/i4b_itk_ix1.c | 2 +- sys/i4b/layer1/i4b_l1.c | 2 +- sys/i4b/layer1/i4b_l1.h | 2 +- sys/i4b/layer1/i4b_l1fsm.c | 2 +- sys/i4b/layer1/i4b_siemens_isurf.c | 2 +- sys/i4b/layer1/i4b_sws.c | 2 +- sys/i4b/layer1/i4b_tel_s016.c | 2 +- sys/i4b/layer1/i4b_tel_s0163.c | 2 +- sys/i4b/layer1/i4b_tel_s08.c | 2 +- sys/i4b/layer1/i4b_usr_sti.c | 2 +- sys/i4b/layer1/isa_isic.c | 2 +- sys/i4b/layer1/isapnp_isic.c | 2 +- sys/i4b/layer1/isic_supio.c | 2 +- sys/i4b/layer1/pci_isic.c | 2 +- sys/i4b/layer1/pci_isic.h | 2 +- sys/i4b/layer1/pcmcia_isic.c | 2 +- sys/i4b/layer1/pcmcia_isic.h | 2 +- sys/i4b/layer2/i4b_iframe.c | 2 +- sys/i4b/layer2/i4b_l2.c | 2 +- sys/i4b/layer2/i4b_l2.h | 2 +- sys/i4b/layer2/i4b_l2fsm.c | 2 +- sys/i4b/layer2/i4b_l2fsm.h | 2 +- sys/i4b/layer2/i4b_l2timer.c | 2 +- sys/i4b/layer2/i4b_lme.c | 2 +- sys/i4b/layer2/i4b_mbuf.c | 2 +- sys/i4b/layer2/i4b_sframe.c | 2 +- sys/i4b/layer2/i4b_tei.c | 2 +- sys/i4b/layer2/i4b_uframe.c | 2 +- sys/i4b/layer2/i4b_util.c | 2 +- sys/i4b/layer3/i4b_l2if.c | 2 +- sys/i4b/layer3/i4b_l3.h | 2 +- sys/i4b/layer3/i4b_l3fsm.c | 2 +- sys/i4b/layer3/i4b_l3fsm.h | 2 +- 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sys/net/net_osdep.h | 2 +- sys/net/netisr.h | 2 +- sys/net/pfkeyv2.h | 2 +- sys/net/ppp_comp.h | 2 +- sys/net/ppp_deflate.c | 2 +- sys/net/ppp_defs.h | 2 +- sys/net/ppp_tty.c | 2 +- sys/net/radix.c | 2 +- sys/net/radix.h | 2 +- sys/net/raw_cb.c | 2 +- sys/net/raw_cb.h | 2 +- sys/net/raw_usrreq.c | 2 +- sys/net/route.c | 2 +- sys/net/route.h | 2 +- sys/net/rtsock.c | 2 +- sys/net/slcompress.c | 2 +- sys/net/slcompress.h | 2 +- sys/net/slip.h | 2 +- sys/net/zlib.c | 2 +- sys/net/zlib.h | 2 +- sys/netatalk/aarp.h | 2 +- sys/netatalk/at_var.h | 2 +- sys/netatalk/ddp_input.c | 2 +- sys/netatalk/ddp_var.h | 2 +- sys/netatm/atm.h | 2 +- sys/netatm/atm_aal5.c | 4 +- sys/netatm/atm_cm.c | 4 +- sys/netatm/atm_cm.h | 2 +- sys/netatm/atm_device.c | 4 +- sys/netatm/atm_if.c | 4 +- sys/netatm/atm_if.h | 2 +- sys/netatm/atm_ioctl.h | 2 +- sys/netatm/atm_pcb.h | 2 +- sys/netatm/atm_proto.c | 4 +- sys/netatm/atm_sap.h | 2 +- sys/netatm/atm_sigmgr.h | 2 +- sys/netatm/atm_signal.c | 4 +- sys/netatm/atm_socket.c | 4 +- sys/netatm/atm_stack.h | 2 +- sys/netatm/atm_subr.c | 4 +- sys/netatm/atm_sys.h | 2 +- sys/netatm/atm_usrreq.c | 4 +- sys/netatm/atm_var.h | 2 +- sys/netatm/atm_vc.h | 2 +- sys/netatm/ipatm/ipatm.h | 2 +- sys/netatm/ipatm/ipatm_event.c | 4 +- sys/netatm/ipatm/ipatm_if.c | 4 +- sys/netatm/ipatm/ipatm_input.c | 4 +- sys/netatm/ipatm/ipatm_load.c | 4 +- sys/netatm/ipatm/ipatm_output.c | 4 +- sys/netatm/ipatm/ipatm_serv.h | 2 +- sys/netatm/ipatm/ipatm_usrreq.c | 4 +- sys/netatm/ipatm/ipatm_var.h | 2 +- sys/netatm/ipatm/ipatm_vcm.c | 4 +- sys/netatm/kern_include.h | 2 +- sys/netatm/port.h | 2 +- sys/netatm/queue.h | 2 +- sys/netatm/sigpvc/sigpvc_if.c | 4 +- sys/netatm/sigpvc/sigpvc_subr.c | 4 +- sys/netatm/sigpvc/sigpvc_var.h | 2 +- sys/netatm/spans/spans_arp.c | 4 +- sys/netatm/spans/spans_cls.c | 4 +- sys/netatm/spans/spans_cls.h | 2 +- sys/netatm/spans/spans_if.c | 4 +- sys/netatm/spans/spans_kxdr.c | 4 +- sys/netatm/spans/spans_msg.c | 4 +- sys/netatm/spans/spans_print.c | 4 +- sys/netatm/spans/spans_proto.c | 4 +- sys/netatm/spans/spans_subr.c | 4 +- sys/netatm/spans/spans_util.c | 4 +- sys/netatm/spans/spans_var.h | 2 +- sys/netatm/spans/spans_xdr.x | 4 +- sys/netatm/uni/q2110_sigaa.c | 4 +- sys/netatm/uni/q2110_sigcpcs.c | 4 +- sys/netatm/uni/q2110_subr.c | 4 +- sys/netatm/uni/qsaal1_sigaa.c | 4 +- sys/netatm/uni/qsaal1_sigcpcs.c | 4 +- sys/netatm/uni/qsaal1_subr.c | 4 +- sys/netatm/uni/sscf_uni.c | 4 +- sys/netatm/uni/sscf_uni.h | 2 +- sys/netatm/uni/sscf_uni_lower.c | 4 +- sys/netatm/uni/sscf_uni_upper.c | 4 +- sys/netatm/uni/sscf_uni_var.h | 2 +- sys/netatm/uni/sscop.c | 4 +- sys/netatm/uni/sscop.h | 2 +- sys/netatm/uni/sscop_lower.c | 4 +- sys/netatm/uni/sscop_misc.h | 2 +- sys/netatm/uni/sscop_pdu.c | 4 +- sys/netatm/uni/sscop_pdu.h | 2 +- sys/netatm/uni/sscop_sigaa.c | 4 +- sys/netatm/uni/sscop_sigcpcs.c | 4 +- sys/netatm/uni/sscop_subr.c | 4 +- sys/netatm/uni/sscop_timer.c | 4 +- sys/netatm/uni/sscop_upper.c | 4 +- sys/netatm/uni/sscop_var.h | 2 +- sys/netatm/uni/uni.h | 2 +- sys/netatm/uni/uni_load.c | 4 +- sys/netatm/uni/uniarp.c | 4 +- sys/netatm/uni/uniarp_cache.c | 4 +- sys/netatm/uni/uniarp_input.c | 4 +- sys/netatm/uni/uniarp_output.c | 4 +- sys/netatm/uni/uniarp_timer.c | 4 +- sys/netatm/uni/uniarp_vcm.c | 4 +- sys/netatm/uni/uniip.c | 4 +- sys/netatm/uni/uniip_var.h | 2 +- sys/netatm/uni/unisig.h | 2 +- sys/netatm/uni/unisig_decode.c | 4 +- sys/netatm/uni/unisig_decode.h | 2 +- sys/netatm/uni/unisig_encode.c | 4 +- sys/netatm/uni/unisig_if.c | 4 +- sys/netatm/uni/unisig_mbuf.c | 4 +- sys/netatm/uni/unisig_mbuf.h | 2 +- sys/netatm/uni/unisig_msg.c | 4 +- sys/netatm/uni/unisig_msg.h | 2 +- sys/netatm/uni/unisig_print.c | 4 +- sys/netatm/uni/unisig_print.h | 2 +- sys/netatm/uni/unisig_proto.c | 4 +- sys/netatm/uni/unisig_sigmgr_state.c | 4 +- sys/netatm/uni/unisig_subr.c | 4 +- sys/netatm/uni/unisig_util.c | 4 +- sys/netatm/uni/unisig_var.h | 2 +- sys/netatm/uni/unisig_vc_state.c | 4 +- sys/netgraph/NOTES | 2 +- sys/netgraph/netgraph.h | 2 +- sys/netgraph/ng_UI.c | 2 +- sys/netgraph/ng_UI.h | 2 +- sys/netgraph/ng_async.c | 2 +- sys/netgraph/ng_async.h | 2 +- sys/netgraph/ng_base.c | 2 +- sys/netgraph/ng_bpf.c | 2 +- sys/netgraph/ng_bpf.h | 2 +- sys/netgraph/ng_cisco.c | 2 +- sys/netgraph/ng_cisco.h | 2 +- sys/netgraph/ng_echo.c | 2 +- sys/netgraph/ng_echo.h | 2 +- sys/netgraph/ng_ether.h | 2 +- sys/netgraph/ng_frame_relay.c | 2 +- sys/netgraph/ng_frame_relay.h | 2 +- sys/netgraph/ng_hole.c | 2 +- sys/netgraph/ng_hole.h | 2 +- sys/netgraph/ng_iface.c | 2 +- sys/netgraph/ng_iface.h | 2 +- sys/netgraph/ng_ksocket.c | 2 +- sys/netgraph/ng_ksocket.h | 2 +- sys/netgraph/ng_lmi.c | 2 +- sys/netgraph/ng_lmi.h | 2 +- sys/netgraph/ng_message.h | 2 +- sys/netgraph/ng_parse.c | 2 +- sys/netgraph/ng_parse.h | 2 +- sys/netgraph/ng_ppp.c | 2 +- sys/netgraph/ng_ppp.h | 2 +- sys/netgraph/ng_pppoe.c | 2 +- sys/netgraph/ng_pppoe.h | 2 +- sys/netgraph/ng_pptpgre.c | 2 +- sys/netgraph/ng_pptpgre.h | 2 +- sys/netgraph/ng_rfc1490.c | 2 +- sys/netgraph/ng_rfc1490.h | 2 +- sys/netgraph/ng_sample.c | 2 +- sys/netgraph/ng_sample.h | 2 +- sys/netgraph/ng_socket.c | 2 +- sys/netgraph/ng_socket.h | 2 +- sys/netgraph/ng_socketvar.h | 2 +- sys/netgraph/ng_tee.c | 2 +- sys/netgraph/ng_tee.h | 2 +- sys/netgraph/ng_tty.c | 2 +- sys/netgraph/ng_tty.h | 2 +- sys/netgraph/ng_vjc.c | 2 +- sys/netgraph/ng_vjc.h | 2 +- sys/netinet/icmp6.h | 2 +- sys/netinet/icmp_var.h | 2 +- sys/netinet/if_atm.c | 2 +- sys/netinet/if_ether.c | 2 +- sys/netinet/if_ether.h | 2 +- sys/netinet/if_fddi.h | 2 +- sys/netinet/igmp.c | 2 +- sys/netinet/igmp.h | 2 +- sys/netinet/igmp_var.h | 2 +- sys/netinet/in.c | 2 +- sys/netinet/in.h | 2 +- sys/netinet/in_cksum.c | 2 +- sys/netinet/in_gif.c | 2 +- sys/netinet/in_gif.h | 2 +- sys/netinet/in_hostcache.c | 2 +- sys/netinet/in_hostcache.h | 2 +- sys/netinet/in_pcb.c | 2 +- sys/netinet/in_pcb.h | 2 +- sys/netinet/in_proto.c | 2 +- sys/netinet/in_rmx.c | 2 +- sys/netinet/in_systm.h | 2 +- sys/netinet/in_var.h | 2 +- sys/netinet/ip.h | 2 +- sys/netinet/ip6.h | 2 +- sys/netinet/ip_auth.c | 2 +- sys/netinet/ip_auth.h | 2 +- sys/netinet/ip_compat.h | 2 +- sys/netinet/ip_divert.c | 2 +- sys/netinet/ip_dummynet.c | 2 +- sys/netinet/ip_dummynet.h | 2 +- sys/netinet/ip_ecn.c | 2 +- sys/netinet/ip_ecn.h | 2 +- sys/netinet/ip_fil.c | 2 +- sys/netinet/ip_fil.h | 2 +- sys/netinet/ip_flow.c | 2 +- sys/netinet/ip_flow.h | 2 +- sys/netinet/ip_frag.c | 2 +- sys/netinet/ip_frag.h | 2 +- sys/netinet/ip_ftp_pxy.c | 2 +- sys/netinet/ip_fw.c | 2 +- sys/netinet/ip_fw.h | 2 +- sys/netinet/ip_icmp.c | 2 +- sys/netinet/ip_icmp.h | 2 +- sys/netinet/ip_input.c | 2 +- sys/netinet/ip_log.c | 2 +- sys/netinet/ip_mroute.c | 2 +- sys/netinet/ip_mroute.h | 2 +- sys/netinet/ip_nat.c | 2 +- sys/netinet/ip_nat.h | 2 +- sys/netinet/ip_output.c | 2 +- sys/netinet/ip_proxy.c | 2 +- sys/netinet/ip_proxy.h | 2 +- sys/netinet/ip_raudio_pxy.c | 2 +- sys/netinet/ip_rcmd_pxy.c | 2 +- sys/netinet/ip_state.c | 2 +- sys/netinet/ip_state.h | 2 +- sys/netinet/ip_var.h | 2 +- sys/netinet/ipl.h | 2 +- sys/netinet/ipprotosw.h | 2 +- sys/netinet/mlfk_ipl.c | 2 +- sys/netinet/raw_ip.c | 2 +- sys/netinet/tcp.h | 2 +- sys/netinet/tcp_debug.c | 2 +- sys/netinet/tcp_debug.h | 2 +- sys/netinet/tcp_fsm.h | 2 +- sys/netinet/tcp_input.c | 2 +- sys/netinet/tcp_output.c | 2 +- sys/netinet/tcp_seq.h | 2 +- sys/netinet/tcp_subr.c | 2 +- sys/netinet/tcp_timer.c | 2 +- sys/netinet/tcp_timer.h | 2 +- sys/netinet/tcp_usrreq.c | 2 +- sys/netinet/tcp_var.h | 2 +- sys/netinet/tcpip.h | 2 +- sys/netinet/udp.h | 2 +- sys/netinet/udp_usrreq.c | 2 +- sys/netinet/udp_var.h | 2 +- sys/netinet6/ah.h | 2 +- sys/netinet6/ah6.h | 2 +- sys/netinet6/ah_core.c | 2 +- sys/netinet6/ah_input.c | 2 +- sys/netinet6/ah_output.c | 2 +- sys/netinet6/dest6.c | 2 +- sys/netinet6/esp.h | 2 +- sys/netinet6/esp6.h | 2 +- sys/netinet6/esp_core.c | 2 +- sys/netinet6/esp_input.c | 2 +- sys/netinet6/esp_output.c | 2 +- sys/netinet6/frag6.c | 2 +- sys/netinet6/icmp6.c | 2 +- sys/netinet6/icmp6.h | 2 +- sys/netinet6/in6.c | 2 +- sys/netinet6/in6.h | 2 +- sys/netinet6/in6_cksum.c | 2 +- sys/netinet6/in6_gif.c | 2 +- sys/netinet6/in6_gif.h | 2 +- sys/netinet6/in6_ifattach.c | 2 +- sys/netinet6/in6_ifattach.h | 2 +- sys/netinet6/in6_pcb.c | 4 +- sys/netinet6/in6_pcb.h | 2 +- sys/netinet6/in6_prefix.c | 2 +- sys/netinet6/in6_prefix.h | 2 +- sys/netinet6/in6_proto.c | 2 +- sys/netinet6/in6_rmx.c | 2 +- sys/netinet6/in6_var.h | 2 +- sys/netinet6/ip6.h | 2 +- sys/netinet6/ip6_ecn.h | 2 +- sys/netinet6/ip6_forward.c | 2 +- sys/netinet6/ip6_fw.c | 2 +- sys/netinet6/ip6_fw.h | 2 +- sys/netinet6/ip6_input.c | 2 +- sys/netinet6/ip6_mroute.c | 2 +- sys/netinet6/ip6_mroute.h | 2 +- sys/netinet6/ip6_output.c | 2 +- sys/netinet6/ip6_var.h | 2 +- sys/netinet6/ip6protosw.h | 2 +- sys/netinet6/ipsec.c | 2 +- sys/netinet6/ipsec.h | 2 +- sys/netinet6/ipsec6.h | 2 +- sys/netinet6/mld6.c | 2 +- sys/netinet6/mld6_var.h | 2 +- sys/netinet6/nd6.c | 2 +- sys/netinet6/nd6.h | 2 +- sys/netinet6/nd6_nbr.c | 2 +- sys/netinet6/nd6_rtr.c | 2 +- sys/netinet6/pim6.h | 2 +- sys/netinet6/pim6_var.h | 2 +- sys/netinet6/raw_ip6.c | 2 +- sys/netinet6/route6.c | 2 +- sys/netinet6/tcp6_var.h | 4 +- sys/netinet6/udp6_usrreq.c | 2 +- sys/netinet6/udp6_var.h | 2 +- sys/netipx/ipx.c | 2 +- sys/netipx/ipx.h | 2 +- sys/netipx/ipx_cksum.c | 2 +- sys/netipx/ipx_if.h | 2 +- sys/netipx/ipx_input.c | 2 +- sys/netipx/ipx_ip.c | 2 +- sys/netipx/ipx_ip.h | 2 +- sys/netipx/ipx_outputfl.c | 2 +- sys/netipx/ipx_pcb.c | 2 +- sys/netipx/ipx_pcb.h | 2 +- sys/netipx/ipx_proto.c | 2 +- sys/netipx/ipx_tun.c | 2 +- sys/netipx/ipx_usrreq.c | 2 +- sys/netipx/ipx_var.h | 2 +- sys/netipx/spx.h | 2 +- sys/netipx/spx_debug.c | 2 +- sys/netipx/spx_debug.h | 2 +- sys/netipx/spx_timer.h | 2 +- sys/netipx/spx_usrreq.c | 2 +- sys/netipx/spx_var.h | 2 +- sys/netkey/key.c | 2 +- sys/netkey/key.h | 2 +- sys/netkey/key_debug.c | 2 +- sys/netkey/key_debug.h | 2 +- sys/netkey/key_var.h | 2 +- sys/netkey/keydb.h | 2 +- sys/netkey/keysock.c | 2 +- sys/netkey/keysock.h | 2 +- sys/netnatm/natm.c | 2 +- sys/netnatm/natm.h | 2 +- sys/netnatm/natm_proto.c | 2 +- sys/netncp/ncp.h | 2 +- sys/netncp/ncp_cfg.h | 2 +- sys/netncp/ncp_conn.c | 2 +- sys/netncp/ncp_conn.h | 2 +- sys/netncp/ncp_crypt.c | 2 +- sys/netncp/ncp_file.h | 2 +- sys/netncp/ncp_lib.h | 2 +- sys/netncp/ncp_login.c | 2 +- sys/netncp/ncp_mod.c | 2 +- sys/netncp/ncp_ncp.c | 2 +- sys/netncp/ncp_ncp.h | 2 +- sys/netncp/ncp_nls.c | 2 +- sys/netncp/ncp_nls.h | 2 +- sys/netncp/ncp_rcfile.h | 2 +- sys/netncp/ncp_rq.c | 2 +- sys/netncp/ncp_rq.h | 2 +- sys/netncp/ncp_sock.c | 2 +- sys/netncp/ncp_sock.h | 2 +- sys/netncp/ncp_subr.c | 2 +- sys/netncp/ncp_subr.h | 2 +- sys/netncp/ncp_user.h | 2 +- sys/netncp/nwerror.h | 2 +- sys/netns/idp.h | 2 +- sys/netns/idp_usrreq.c | 2 +- sys/netns/idp_var.h | 2 +- sys/netns/ns.c | 2 +- sys/netns/ns.h | 2 +- sys/netns/ns_cksum.c | 2 +- sys/netns/ns_error.c | 2 +- sys/netns/ns_error.h | 2 +- sys/netns/ns_if.h | 2 +- sys/netns/ns_input.c | 2 +- sys/netns/ns_ip.c | 2 +- sys/netns/ns_output.c | 2 +- sys/netns/ns_pcb.c | 2 +- sys/netns/ns_pcb.h | 2 +- sys/netns/ns_proto.c | 2 +- sys/netns/sp.h | 2 +- sys/netns/spidp.h | 2 +- sys/netns/spp_debug.c | 2 +- sys/netns/spp_debug.h | 2 +- sys/netns/spp_timer.h | 2 +- sys/netns/spp_usrreq.c | 2 +- sys/netns/spp_var.h | 2 +- sys/nfs/bootp_subr.c | 2 +- sys/nfs/krpc.h | 2 +- sys/nfs/krpc_subr.c | 2 +- sys/nfs/nfs.h | 2 +- sys/nfs/nfs_bio.c | 2 +- sys/nfs/nfs_node.c | 2 +- sys/nfs/nfs_nqlease.c | 2 +- sys/nfs/nfs_serv.c | 2 +- sys/nfs/nfs_socket.c | 2 +- sys/nfs/nfs_srvcache.c | 2 +- sys/nfs/nfs_subs.c | 2 +- sys/nfs/nfs_syscalls.c | 2 +- sys/nfs/nfs_vfsops.c | 2 +- sys/nfs/nfs_vnops.c | 2 +- sys/nfs/nfsdiskless.h | 2 +- sys/nfs/nfsm_subs.h | 2 +- sys/nfs/nfsmount.h | 2 +- sys/nfs/nfsnode.h | 2 +- sys/nfs/nfsproto.h | 2 +- sys/nfs/nfsrtt.h | 2 +- sys/nfs/nfsrvcache.h | 2 +- sys/nfs/nfsv2.h | 2 +- sys/nfs/nqnfs.h | 2 +- sys/nfs/rpcv2.h | 2 +- sys/nfs/xdr_subs.h | 2 +- sys/ntfs/ntfs.h | 2 +- sys/ntfs/ntfs_compr.c | 2 +- sys/ntfs/ntfs_compr.h | 2 +- sys/ntfs/ntfs_ihash.c | 2 +- sys/ntfs/ntfs_ihash.h | 2 +- sys/ntfs/ntfs_inode.h | 2 +- sys/ntfs/ntfs_subr.c | 2 +- sys/ntfs/ntfs_subr.h | 2 +- sys/ntfs/ntfs_vfsops.c | 2 +- sys/ntfs/ntfs_vfsops.h | 2 +- sys/ntfs/ntfs_vnops.c | 2 +- sys/ntfs/ntfsmount.h | 2 +- sys/nwfs/nwfs.h | 2 +- sys/nwfs/nwfs_io.c | 2 +- sys/nwfs/nwfs_ioctl.c | 2 +- sys/nwfs/nwfs_mount.h | 2 +- sys/nwfs/nwfs_node.c | 2 +- sys/nwfs/nwfs_node.h | 2 +- sys/nwfs/nwfs_subr.c | 2 +- sys/nwfs/nwfs_subr.h | 2 +- sys/nwfs/nwfs_vfsops.c | 2 +- sys/nwfs/nwfs_vnops.c | 2 +- sys/pc98/boot/Makefile | 2 +- sys/pc98/boot/Makefile.inc | 2 +- sys/pc98/boot/biosboot/Makefile | 2 +- sys/pc98/boot/biosboot/README.386BSD | 2 +- sys/pc98/boot/biosboot/README.MACH | 2 +- sys/pc98/boot/biosboot/README.serial | 2 +- sys/pc98/boot/biosboot/asm.S | 2 +- sys/pc98/boot/biosboot/asm.h | 2 +- sys/pc98/boot/biosboot/bios.S | 2 +- sys/pc98/boot/biosboot/boot.c | 2 +- sys/pc98/boot/biosboot/boot.h | 2 +- sys/pc98/boot/biosboot/disk.c | 2 +- sys/pc98/boot/biosboot/io.c | 2 +- sys/pc98/boot/biosboot/serial.S | 2 +- sys/pc98/boot/biosboot/start.S | 2 +- sys/pc98/boot/biosboot/sys.c | 2 +- sys/pc98/boot/biosboot/table.c | 2 +- sys/pc98/boot/kzipboot/Makefile | 2 +- sys/pc98/boot/netboot/3c509.c | 2 +- sys/pc98/boot/rawboot/Makefile | 2 +- sys/pc98/conf/GENERIC98 | 2 +- sys/pc98/i386/machdep.c | 2 +- sys/pc98/i386/userconfig.c | 4 +- sys/pc98/pc98/atapi.c | 2 +- sys/pc98/pc98/clock.c | 2 +- sys/pc98/pc98/diskslice_machdep.c | 2 +- sys/pc98/pc98/fd.c | 2 +- sys/pc98/pc98/fdreg.h | 2 +- sys/pc98/pc98/if_ed.c | 2 +- sys/pc98/pc98/if_ed98.h | 2 +- sys/pc98/pc98/isa_compat.c | 2 +- sys/pc98/pc98/isa_compat.h | 2 +- sys/pc98/pc98/isa_dma.c | 2 +- sys/pc98/pc98/mse.c | 2 +- sys/pc98/pc98/npx.c | 2 +- sys/pc98/pc98/olpt.c | 2 +- sys/pc98/pc98/pc98.h | 2 +- sys/pc98/pc98/pc98_machdep.c | 2 +- sys/pc98/pc98/pc98_machdep.h | 2 +- sys/pc98/pc98/pc98gdc.c | 2 +- sys/pc98/pc98/pc98kbd.c | 2 +- sys/pc98/pc98/pcaudio.c | 2 +- sys/pc98/pc98/ppc.c | 2 +- sys/pc98/pc98/ppcreg.h | 2 +- sys/pc98/pc98/sc_machdep.h | 2 +- sys/pc98/pc98/scgdcrndr.c | 2 +- sys/pc98/pc98/scterm-sck.c | 2 +- sys/pc98/pc98/scvtbpc98.c | 2 +- sys/pc98/pc98/sio.c | 2 +- sys/pc98/pc98/spkr.c | 2 +- sys/pc98/pc98/syscons.c | 2 +- sys/pc98/pc98/syscons_pc98.c | 2 +- sys/pc98/pc98/wd.c | 2 +- sys/pccard/cardinfo.h | 2 +- sys/pccard/driver.h | 2 +- sys/pccard/i82365.h | 2 +- sys/pccard/pccard.c | 2 +- sys/pccard/pccard_beep.c | 2 +- sys/pccard/pccard_nbk.c | 2 +- sys/pccard/pccard_nbk.h | 2 +- sys/pccard/pcic.c | 2 +- sys/pccard/pcic.h | 2 +- sys/pccard/slot.h | 2 +- sys/pci/adw_pci.c | 2 +- sys/pci/alpm.c | 2 +- sys/pci/amd.c | 2 +- sys/pci/cy_pci.c | 2 +- sys/pci/cy_pcireg.h | 2 +- sys/pci/dc21040reg.h | 2 +- sys/pci/ide_pci.c | 2 +- sys/pci/ide_pcireg.h | 2 +- sys/pci/if_ar_p.c | 2 +- sys/pci/if_dc.c | 4 +- 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+- sys/sys/syscall.mk | 2 +- sys/sys/sysctl.h | 2 +- sys/sys/sysent.h | 2 +- sys/sys/syslimits.h | 2 +- sys/sys/syslog.h | 2 +- sys/sys/sysproto.h | 2 +- sys/sys/systm.h | 2 +- sys/sys/termios.h | 2 +- sys/sys/time.h | 2 +- sys/sys/timeb.h | 2 +- sys/sys/timepps.h | 2 +- sys/sys/timers.h | 2 +- sys/sys/times.h | 2 +- sys/sys/timex.h | 2 +- sys/sys/tprintf.h | 2 +- sys/sys/tty.h | 2 +- sys/sys/ttychars.h | 2 +- sys/sys/ttycom.h | 2 +- sys/sys/ttydefaults.h | 2 +- sys/sys/ttydev.h | 2 +- sys/sys/types.h | 2 +- sys/sys/ucontext.h | 2 +- sys/sys/ucred.h | 2 +- sys/sys/uio.h | 2 +- sys/sys/un.h | 2 +- sys/sys/unistd.h | 2 +- sys/sys/unpcb.h | 2 +- sys/sys/user.h | 2 +- sys/sys/utsname.h | 2 +- sys/sys/vmmeter.h | 2 +- sys/sys/vnioctl.h | 2 +- sys/sys/vnode.h | 2 +- sys/sys/wait.h | 2 +- sys/sys/wormio.h | 2 +- sys/sys/xrpuio.h | 2 +- sys/ufs/ffs/README | 322 - sys/ufs/ffs/README.softupdates | 2 +- sys/ufs/ffs/ffs_alloc.c | 2 +- sys/ufs/ffs/ffs_balloc.c | 2 +- sys/ufs/ffs/ffs_extern.h | 2 +- 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+- sys/vm/vm.h | 2 +- sys/vm/vm_extern.h | 2 +- sys/vm/vm_fault.c | 2 +- sys/vm/vm_glue.c | 2 +- sys/vm/vm_init.c | 2 +- sys/vm/vm_kern.c | 2 +- sys/vm/vm_kern.h | 2 +- sys/vm/vm_map.c | 2 +- sys/vm/vm_map.h | 2 +- sys/vm/vm_meter.c | 2 +- sys/vm/vm_mmap.c | 2 +- sys/vm/vm_object.c | 2 +- sys/vm/vm_object.h | 2 +- sys/vm/vm_page.c | 2 +- sys/vm/vm_page.h | 2 +- sys/vm/vm_pageout.c | 2 +- sys/vm/vm_pageout.h | 2 +- sys/vm/vm_pager.c | 2 +- sys/vm/vm_pager.h | 2 +- sys/vm/vm_param.h | 2 +- sys/vm/vm_swap.c | 2 +- sys/vm/vm_unix.c | 2 +- sys/vm/vm_zone.c | 2 +- sys/vm/vm_zone.h | 2 +- sys/vm/vnode_pager.c | 2 +- sys/vm/vnode_pager.h | 2 +- tools/3.0-upgrade/cvt-wtmp.c | 2 +- tools/LibraryReport/LibraryReport.tcl | 2 +- tools/diag/README | 2 +- tools/diag/ac/ac | 2 +- tools/diag/httpd-error/httpd-error | 2 +- tools/install.sh | 2 +- tools/regression/README | 2 +- tools/regression/p1003_1b/Makefile | 2 +- tools/regression/p1003_1b/README | 2 +- tools/regression/p1003_1b/fifo.c | 2 +- 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tools/tools/upgrade/getosreldate.sh | 2 +- tools/tools/upgrade/move_aout_libs.sh | 2 +- usr.bin/Makefile | 2 +- usr.bin/apply/apply.1 | 2 +- usr.bin/apply/apply.c | 2 +- usr.bin/ar/Makefile | 2 +- usr.bin/ar/ar.1 | 2 +- usr.bin/ar/ar.1aout | 2 +- usr.bin/ar/ar.5 | 2 +- usr.bin/ar/ar.c | 2 +- usr.bin/at/Makefile | 2 +- usr.bin/at/at.c | 2 +- usr.bin/at/at.man | 2 +- usr.bin/at/panic.c | 2 +- usr.bin/at/parsetime.c | 2 +- usr.bin/at/perm.c | 2 +- usr.bin/at/privs.h | 2 +- usr.bin/banner/banner.6 | 2 +- usr.bin/banner/banner.c | 2 +- usr.bin/basename/basename.1 | 2 +- usr.bin/biff/biff.1 | 2 +- usr.bin/biff/biff.c | 2 +- usr.bin/brandelf/brandelf.1 | 2 +- usr.bin/brandelf/brandelf.c | 2 +- usr.bin/c89/c89.1 | 2 +- usr.bin/c89/c89.sh | 2 +- usr.bin/calendar/calendar.1 | 2 +- usr.bin/calendar/calendars/calendar.all | 2 +- usr.bin/calendar/calendars/calendar.birthday | 2 +- usr.bin/calendar/calendars/calendar.christian | 2 +- usr.bin/calendar/calendars/calendar.computer | 2 +- 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usr.bin/rpcgen/rpc_util.c | 2 +- usr.bin/rpcgen/rpcgen.1 | 2 +- usr.bin/rpcinfo/Makefile | 2 +- usr.bin/rpcinfo/rpcinfo.8 | 2 +- usr.bin/rpcinfo/rpcinfo.c | 2 +- usr.bin/rs/rs.1 | 2 +- usr.bin/rs/rs.c | 2 +- usr.bin/rsh/Makefile | 2 +- usr.bin/rsh/rsh.1 | 2 +- usr.bin/rsh/rsh.c | 2 +- usr.bin/rup/Makefile | 2 +- usr.bin/rup/rup.1 | 2 +- usr.bin/rup/rup.c | 2 +- usr.bin/ruptime/ruptime.1 | 2 +- usr.bin/ruptime/ruptime.c | 2 +- usr.bin/rusers/Makefile | 2 +- usr.bin/rusers/rusers.1 | 2 +- usr.bin/rusers/rusers.c | 2 +- usr.bin/rwall/Makefile | 2 +- usr.bin/rwall/rwall.1 | 2 +- usr.bin/rwall/rwall.c | 2 +- usr.bin/rwho/rwho.1 | 2 +- usr.bin/rwho/rwho.c | 2 +- usr.bin/sasc/sasc.1 | 2 +- usr.bin/sasc/sasc.c | 2 +- usr.bin/script/script.1 | 2 +- usr.bin/script/script.c | 2 +- usr.bin/sed/compile.c | 2 +- usr.bin/sed/main.c | 2 +- usr.bin/sed/misc.c | 2 +- usr.bin/sed/process.c | 2 +- usr.bin/sed/sed.1 | 2 +- usr.bin/shar/shar.1 | 2 +- usr.bin/showmount/showmount.8 | 2 +- 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usr.sbin/pppd/cbcp.c | 2 +- usr.sbin/pppd/ccp.c | 2 +- usr.sbin/pppd/ccp.h | 2 +- usr.sbin/pppd/chap.c | 2 +- usr.sbin/pppd/chap.h | 2 +- usr.sbin/pppd/chap_ms.c | 2 +- usr.sbin/pppd/chap_ms.h | 2 +- usr.sbin/pppd/demand.c | 2 +- usr.sbin/pppd/fsm.c | 2 +- usr.sbin/pppd/fsm.h | 2 +- usr.sbin/pppd/ipcp.c | 2 +- usr.sbin/pppd/ipcp.h | 2 +- usr.sbin/pppd/ipxcp.c | 2 +- usr.sbin/pppd/ipxcp.h | 2 +- usr.sbin/pppd/lcp.c | 2 +- usr.sbin/pppd/lcp.h | 2 +- usr.sbin/pppd/magic.c | 2 +- usr.sbin/pppd/magic.h | 2 +- usr.sbin/pppd/main.c | 2 +- usr.sbin/pppd/options.c | 2 +- usr.sbin/pppd/patchlevel.h | 2 +- usr.sbin/pppd/pathnames.h | 2 +- usr.sbin/pppd/pppd.8 | 2 +- usr.sbin/pppd/pppd.h | 2 +- usr.sbin/pppd/sys-bsd.c | 2 +- usr.sbin/pppd/upap.c | 2 +- usr.sbin/pppd/upap.h | 2 +- usr.sbin/pppstats/Makefile | 2 +- usr.sbin/pppstats/pppstats.8 | 2 +- usr.sbin/pppstats/pppstats.c | 2 +- usr.sbin/prefix/Makefile | 2 +- usr.sbin/prefix/prefix.8 | 2 +- usr.sbin/prefix/prefix.c | 2 +- usr.sbin/procctl/Makefile | 2 +- usr.sbin/procctl/procctl.8 | 2 +- usr.sbin/procctl/procctl.c | 2 +- usr.sbin/pstat/pstat.8 | 2 +- usr.sbin/pstat/pstat.c | 2 +- usr.sbin/pw/Makefile | 2 +- usr.sbin/pw/README | 2 +- usr.sbin/pw/bitmap.c | 2 +- usr.sbin/pw/bitmap.h | 2 +- usr.sbin/pw/cpdir.c | 2 +- usr.sbin/pw/edgroup.c | 2 +- usr.sbin/pw/fileupd.c | 2 +- usr.sbin/pw/grupd.c | 2 +- usr.sbin/pw/psdate.c | 2 +- usr.sbin/pw/psdate.h | 2 +- usr.sbin/pw/pw.8 | 2 +- usr.sbin/pw/pw.c | 2 +- usr.sbin/pw/pw.conf.5 | 2 +- usr.sbin/pw/pw.h | 2 +- usr.sbin/pw/pw_conf.c | 2 +- usr.sbin/pw/pw_group.c | 2 +- usr.sbin/pw/pw_log.c | 2 +- usr.sbin/pw/pw_nis.c | 2 +- usr.sbin/pw/pw_user.c | 2 +- usr.sbin/pw/pw_vpw.c | 2 +- usr.sbin/pw/pwupd.c | 2 +- usr.sbin/pw/pwupd.h | 2 +- usr.sbin/pw/rm_r.c | 2 +- usr.sbin/pwd_mkdb/pw_scan.c | 2 +- usr.sbin/pwd_mkdb/pw_scan.h | 2 +- usr.sbin/pwd_mkdb/pwd_mkdb.8 | 2 +- usr.sbin/pwd_mkdb/pwd_mkdb.c | 2 +- usr.sbin/quot/Makefile | 2 +- usr.sbin/quot/quot.8 | 2 +- usr.sbin/quot/quot.c | 2 +- usr.sbin/quotaon/quotaon.8 | 2 +- usr.sbin/quotaon/quotaon.c | 2 +- usr.sbin/rarpd/Makefile | 2 +- usr.sbin/rarpd/rarpd.8 | 2 +- usr.sbin/rarpd/rarpd.c | 2 +- usr.sbin/repquota/repquota.8 | 2 +- usr.sbin/repquota/repquota.c | 2 +- usr.sbin/rip6query/Makefile | 2 +- usr.sbin/rip6query/rip6query.8 | 2 +- usr.sbin/rip6query/rip6query.c | 2 +- usr.sbin/rmt/rmt.8 | 2 +- usr.sbin/rmt/rmt.c | 2 +- usr.sbin/rndcontrol/random.4 | 2 +- usr.sbin/rndcontrol/rndcontrol.8 | 2 +- usr.sbin/rndcontrol/rndcontrol.c | 2 +- usr.sbin/route6d/Makefile | 2 +- usr.sbin/route6d/misc/chkrt | 2 +- usr.sbin/route6d/misc/cksum.c | 2 +- usr.sbin/route6d/route6d.8 | 2 +- usr.sbin/route6d/route6d.c | 2 +- usr.sbin/route6d/route6d.h | 2 +- usr.sbin/rpc.lockd/Makefile | 2 +- usr.sbin/rpc.lockd/handles.c | 2 +- usr.sbin/rpc.lockd/lockd.c | 2 +- usr.sbin/rpc.lockd/procs.c | 2 +- usr.sbin/rpc.lockd/rpc.lockd.8 | 2 +- usr.sbin/rpc.lockd/test.c | 2 +- usr.sbin/rpc.statd/Makefile | 2 +- usr.sbin/rpc.statd/procs.c | 2 +- usr.sbin/rpc.statd/rpc.statd.8 | 2 +- usr.sbin/rpc.statd/statd.c | 2 +- usr.sbin/rpc.statd/test.c | 2 +- usr.sbin/rpc.umntall/Makefile | 2 +- usr.sbin/rpc.umntall/mounttab.c | 2 +- usr.sbin/rpc.umntall/mounttab.h | 2 +- usr.sbin/rpc.umntall/rpc.umntall.8 | 2 +- usr.sbin/rpc.umntall/rpc.umntall.c | 2 +- usr.sbin/rpc.yppasswdd/Makefile | 2 +- usr.sbin/rpc.yppasswdd/pw_copy.c | 2 +- usr.sbin/rpc.yppasswdd/pw_util.c | 2 +- usr.sbin/rpc.yppasswdd/rpc.yppasswdd.8 | 2 +- usr.sbin/rpc.yppasswdd/yppasswd_private.x | 2 +- usr.sbin/rpc.yppasswdd/yppasswdd_extern.h | 2 +- usr.sbin/rpc.yppasswdd/yppasswdd_main.c | 2 +- usr.sbin/rpc.yppasswdd/yppasswdd_server.c | 2 +- usr.sbin/rpc.yppasswdd/yppwupdate | 2 +- usr.sbin/rpc.ypupdated/Makefile | 2 +- usr.sbin/rpc.ypupdated/update.c | 2 +- usr.sbin/rpc.ypupdated/yp_dbdelete.c | 2 +- usr.sbin/rpc.ypupdated/yp_dbupdate.c | 2 +- usr.sbin/rpc.ypupdated/ypupdate | 2 +- usr.sbin/rpc.ypupdated/ypupdated_main.c | 2 +- usr.sbin/rpc.ypupdated/ypupdated_server.c | 2 +- usr.sbin/rpc.ypxfrd/Makefile | 2 +- usr.sbin/rpc.ypxfrd/rpc.ypxfrd.8 | 2 +- usr.sbin/rpc.ypxfrd/ypxfrd_extern.h | 2 +- usr.sbin/rpc.ypxfrd/ypxfrd_main.c | 2 +- usr.sbin/rpc.ypxfrd/ypxfrd_server.c | 2 +- usr.sbin/rrenumd/Makefile | 2 +- usr.sbin/rrenumd/lexer.l | 2 +- usr.sbin/rrenumd/parser.y | 2 +- usr.sbin/rrenumd/rrenumd.8 | 2 +- usr.sbin/rrenumd/rrenumd.c | 2 +- usr.sbin/rrenumd/rrenumd.conf.5 | 2 +- usr.sbin/rrenumd/rrenumd.h | 2 +- usr.sbin/rtadvd/Makefile | 2 +- usr.sbin/rtadvd/advcap.c | 2 +- usr.sbin/rtadvd/advcap.h | 2 +- usr.sbin/rtadvd/config.c | 2 +- usr.sbin/rtadvd/config.h | 2 +- usr.sbin/rtadvd/if.c | 2 +- usr.sbin/rtadvd/if.h | 2 +- usr.sbin/rtadvd/pathnames.h | 2 +- usr.sbin/rtadvd/rrenum.c | 2 +- usr.sbin/rtadvd/rrenum.h | 2 +- usr.sbin/rtadvd/rtadvd.8 | 2 +- usr.sbin/rtadvd/rtadvd.c | 2 +- usr.sbin/rtadvd/rtadvd.conf | 2 +- usr.sbin/rtadvd/rtadvd.conf.5 | 2 +- usr.sbin/rtadvd/rtadvd.h | 2 +- usr.sbin/rtadvd/timer.c | 2 +- usr.sbin/rtadvd/timer.h | 2 +- usr.sbin/rtprio/Makefile | 2 +- usr.sbin/rtprio/rtprio.1 | 2 +- usr.sbin/rtprio/rtprio.c | 2 +- usr.sbin/rtsold/Makefile | 2 +- usr.sbin/rtsold/dump.c | 2 +- usr.sbin/rtsold/if.c | 2 +- usr.sbin/rtsold/probe.c | 2 +- usr.sbin/rtsold/rtsol.c | 2 +- usr.sbin/rtsold/rtsold.8 | 2 +- usr.sbin/rtsold/rtsold.c | 2 +- usr.sbin/rtsold/rtsold.h | 2 +- usr.sbin/rwhod/rwhod.8 | 2 +- usr.sbin/rwhod/rwhod.c | 2 +- usr.sbin/sa/Makefile | 2 +- usr.sbin/sa/extern.h | 2 +- usr.sbin/sa/main.c | 2 +- usr.sbin/sa/pathnames.h | 2 +- usr.sbin/sa/pdb.c | 2 +- usr.sbin/sa/sa.8 | 2 +- usr.sbin/sa/usrdb.c | 2 +- usr.sbin/sendmail/Makefile | 2 +- usr.sbin/setkey/Makefile | 2 +- usr.sbin/setkey/parse.y | 2 +- usr.sbin/setkey/sample.cf | 2 +- usr.sbin/setkey/scriptdump.pl | 2 +- usr.sbin/setkey/setkey.8 | 2 +- usr.sbin/setkey/setkey.c | 2 +- usr.sbin/setkey/test-pfkey.c | 2 +- usr.sbin/setkey/test-policy.c | 2 +- usr.sbin/setkey/token.l | 2 +- usr.sbin/setkey/vchar.h | 2 +- usr.sbin/sgsc/Makefile | 2 +- usr.sbin/sgsc/sgsc.1 | 2 +- usr.sbin/sgsc/sgsc.c | 2 +- usr.sbin/sicontrol/Makefile | 2 +- usr.sbin/sicontrol/sicontrol.8 | 2 +- usr.sbin/sicontrol/sicontrol.c | 2 +- usr.sbin/sliplogin/sliplogin.8 | 2 +- usr.sbin/slstat/Makefile | 2 +- usr.sbin/slstat/slstat.8 | 2 +- usr.sbin/slstat/slstat.c | 2 +- usr.sbin/spkrtest/Makefile | 2 +- usr.sbin/spkrtest/spkrtest.8 | 2 +- usr.sbin/spkrtest/spkrtest.pl | 2 +- usr.sbin/spray/Makefile | 2 +- usr.sbin/spray/spray.8 | 2 +- usr.sbin/spray/spray.c | 2 +- usr.sbin/stallion/Makefile | 2 +- usr.sbin/stallion/Makefile.inc | 2 +- usr.sbin/stallion/bootcode/Makefile | 2 +- usr.sbin/stallion/bootcode/stl.4 | 2 +- usr.sbin/stallion/stlload/Makefile | 2 +- usr.sbin/stallion/stlload/stlload.8 | 2 +- usr.sbin/stallion/stlload/stlload.c | 2 +- usr.sbin/stallion/stlstats/Makefile | 2 +- usr.sbin/stallion/stlstats/stlstats.8 | 2 +- usr.sbin/stallion/stlstats/stlstats.c | 2 +- usr.sbin/syslogd/syslog.conf.5 | 2 +- usr.sbin/syslogd/syslogd.8 | 2 +- usr.sbin/syslogd/syslogd.c | 2 +- usr.sbin/tcpdchk/Makefile | 2 +- usr.sbin/tcpdmatch/Makefile | 2 +- usr.sbin/tcpdump/tcpdump/Makefile | 2 +- usr.sbin/tcpdump/tcpdump/config.h | 2 +- usr.sbin/tcpdump/tcpslice/gwtm2secs.c | 2 +- usr.sbin/tcpdump/tcpslice/search.c | 2 +- usr.sbin/tcpdump/tcpslice/tcpslice.1 | 2 +- usr.sbin/tcpdump/tcpslice/tcpslice.c | 2 +- usr.sbin/tcpdump/tcpslice/util.c | 2 +- usr.sbin/timed/timed/acksend.c | 2 +- usr.sbin/timed/timed/byteorder.c | 2 +- usr.sbin/timed/timed/candidate.c | 2 +- usr.sbin/timed/timed/cksum.c | 2 +- usr.sbin/timed/timed/correct.c | 2 +- usr.sbin/timed/timed/globals.h | 2 +- usr.sbin/timed/timed/master.c | 2 +- usr.sbin/timed/timed/measure.c | 2 +- usr.sbin/timed/timed/networkdelta.c | 2 +- usr.sbin/timed/timed/readmsg.c | 2 +- usr.sbin/timed/timed/slave.c | 2 +- usr.sbin/timed/timed/timed.8 | 2 +- usr.sbin/timed/timed/timed.c | 2 +- usr.sbin/timed/timedc/cmds.c | 2 +- usr.sbin/timed/timedc/cmdtab.c | 2 +- usr.sbin/timed/timedc/timedc.8 | 2 +- usr.sbin/timed/timedc/timedc.c | 2 +- usr.sbin/traceroute/Makefile | 2 +- usr.sbin/traceroute6/Makefile | 2 +- usr.sbin/traceroute6/traceroute6.8 | 2 +- usr.sbin/traceroute6/traceroute6.c | 2 +- usr.sbin/trpt/Makefile | 2 +- usr.sbin/trpt/trpt.8 | 2 +- usr.sbin/trpt/trpt.c | 2 +- usr.sbin/tzsetup/Makefile | 2 +- usr.sbin/tzsetup/tzsetup.8 | 2 +- usr.sbin/tzsetup/tzsetup.c | 2 +- usr.sbin/usbd/Makefile | 2 +- usr.sbin/usbd/usbd.8 | 2 +- usr.sbin/usbd/usbd.c | 2 +- usr.sbin/usbd/usbd.conf.5 | 2 +- usr.sbin/usbdevs/Makefile | 2 +- usr.sbin/usbdevs/usbdevs.8 | 4 +- usr.sbin/usbdevs/usbdevs.c | 2 +- usr.sbin/vidcontrol/decode.c | 2 +- usr.sbin/vidcontrol/vidcontrol.1 | 2 +- usr.sbin/vidcontrol/vidcontrol.c | 2 +- usr.sbin/vipw/pw_util.c | 2 +- usr.sbin/vipw/vipw.8 | 2 +- usr.sbin/vipw/vipw.c | 2 +- usr.sbin/vnconfig/Makefile | 2 +- usr.sbin/vnconfig/vnconfig.8 | 2 +- usr.sbin/vnconfig/vnconfig.c | 2 +- usr.sbin/watch/Makefile | 2 +- usr.sbin/watch/watch.8 | 2 +- usr.sbin/watch/watch.c | 2 +- usr.sbin/wicontrol/Makefile | 2 +- usr.sbin/wicontrol/wicontrol.8 | 2 +- usr.sbin/wicontrol/wicontrol.c | 4 +- usr.sbin/wlconfig/Makefile | 2 +- usr.sbin/wlconfig/wlconfig.8 | 2 +- usr.sbin/wlconfig/wlconfig.c | 2 +- usr.sbin/wormcontrol/wormcontrol.8 | 2 +- usr.sbin/wormcontrol/wormcontrol.c | 2 +- usr.sbin/xten/Makefile | 2 +- usr.sbin/xten/xten.1 | 2 +- usr.sbin/xten/xten.c | 2 +- usr.sbin/yp_mkdb/Makefile | 2 +- usr.sbin/yp_mkdb/yp_mkdb.8 | 2 +- usr.sbin/yp_mkdb/yp_mkdb.c | 2 +- usr.sbin/ypbind/Makefile | 2 +- usr.sbin/ypbind/yp_ping.c | 2 +- usr.sbin/ypbind/ypbind.8 | 2 +- usr.sbin/ypbind/ypbind.c | 2 +- usr.sbin/yppoll/Makefile | 2 +- usr.sbin/yppoll/yppoll.8 | 2 +- usr.sbin/yppoll/yppoll.c | 2 +- usr.sbin/yppush/Makefile | 2 +- usr.sbin/yppush/yppush.8 | 2 +- usr.sbin/yppush/yppush_extern.h | 2 +- usr.sbin/yppush/yppush_main.c | 2 +- usr.sbin/ypserv/Makefile | 2 +- usr.sbin/ypserv/Makefile.yp | 2 +- usr.sbin/ypserv/yp_access.c | 2 +- usr.sbin/ypserv/yp_dblookup.c | 2 +- usr.sbin/ypserv/yp_dnslookup.c | 2 +- usr.sbin/ypserv/yp_error.c | 2 +- usr.sbin/ypserv/yp_extern.h | 2 +- usr.sbin/ypserv/yp_main.c | 2 +- usr.sbin/ypserv/yp_server.c | 2 +- usr.sbin/ypserv/yp_svc_udp.c | 2 +- usr.sbin/ypserv/ypinit.8 | 2 +- usr.sbin/ypserv/ypinit.sh | 2 +- usr.sbin/ypserv/ypserv.8 | 2 +- usr.sbin/ypset/ypset.8 | 2 +- usr.sbin/ypset/ypset.c | 2 +- usr.sbin/zic/Makefile | 2 +- usr.sbin/zic/Makefile.inc | 2 +- usr.sbin/zic/ialloc.c | 2 +- usr.sbin/zic/private.h | 2 +- usr.sbin/zic/scheck.c | 2 +- usr.sbin/zic/zdump.8 | 2 +- usr.sbin/zic/zdump.c | 2 +- usr.sbin/zic/zdump/Makefile | 2 +- usr.sbin/zic/zic.8 | 2 +- usr.sbin/zic/zic.c | 2 +- usr.sbin/zic/zic/Makefile | 2 +- 12628 files changed, 117242 insertions(+), 736248 deletions(-) create mode 100644 contrib/binutils/bfd/VERSION create mode 100644 contrib/binutils/bfd/doc/bfd.texi create mode 100644 contrib/binutils/bfd/hosts/mipsbsd.h create mode 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delete mode 100644 sys/ufs/ffs/ffs_softdep.c delete mode 100644 sys/ufs/ffs/softdep.h diff --git a/COPYRIGHT b/COPYRIGHT index 1a96b64934cfa..bfbb9c08e947d 100644 --- a/COPYRIGHT +++ b/COPYRIGHT @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/COPYRIGHT,v 1.4 1999/09/05 21:33:47 obrien Exp $ # @(#)COPYRIGHT 8.2 (Berkeley) 3/21/94 All of the documentation and software included in the 4.4BSD and 4.4BSD-Lite diff --git a/Makefile b/Makefile index bad55f732cc06..8a4f73d928c7f 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ # -# $FreeBSD$ +# $FreeBSD: src/Makefile,v 1.234 2000/02/24 23:03:15 markm Exp $ # # The user-driven targets are: # diff --git a/Makefile.inc1 b/Makefile.inc1 index 95bac4e39ae41..0f7110f442674 100644 --- a/Makefile.inc1 +++ b/Makefile.inc1 @@ -1,5 +1,5 @@ # -# $FreeBSD$ +# $FreeBSD: src/Makefile.inc1,v 1.141 2000/03/09 06:28:19 kris Exp $ # # Make command line options: # -DMAKE_KERBEROS4 to build KerberosIV diff --git a/Makefile.upgrade b/Makefile.upgrade index a0a68bca6e5b3..ba2db4d8c9b1e 100644 --- a/Makefile.upgrade +++ b/Makefile.upgrade @@ -1,5 +1,5 @@ # -# $FreeBSD$ +# $FreeBSD: src/Makefile.upgrade,v 1.17 1999/08/28 01:35:58 peter Exp $ # # This makefile contains rules for preforming upgrades that are outside # the scope of the normal build world process. diff --git a/README b/README index 2801b274b3547..9028313e4cc2e 100644 --- a/README +++ b/README @@ -1,6 +1,6 @@ This is the top level of the FreeBSD source directory. This file was last revised on: -$FreeBSD$ +$FreeBSD: src/README,v 1.15 1999/08/28 01:35:58 peter Exp $ For copyright information, please see the file COPYRIGHT in this directory (additional copyright information also exists for some diff --git a/UPDATING b/UPDATING index 02c755fc38307..cc9906b98f403 100644 --- a/UPDATING +++ b/UPDATING @@ -677,4 +677,4 @@ version of FreeBSD, you are on your own to get to November 18, 1998. Please filter your entries through Warner Losh (imp@village.org) so that the style, formatting, etc of this file can be maintained. -$FreeBSD$ +$FreeBSD: src/UPDATING,v 1.73 2000/03/09 07:34:46 imp Exp $ diff --git a/bin/Makefile b/bin/Makefile index c78bf08d8cf43..aad9cdf7fc73e 100644 --- a/bin/Makefile +++ b/bin/Makefile @@ -1,5 +1,5 @@ # From: @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/Makefile,v 1.15 1999/08/27 23:12:20 peter Exp $ SUBDIR= cat \ chio \ diff --git a/bin/Makefile.inc b/bin/Makefile.inc index d29f43ab50c75..a67fc2940defc 100644 --- a/bin/Makefile.inc +++ b/bin/Makefile.inc @@ -1,5 +1,5 @@ # @(#)Makefile.inc 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/Makefile.inc,v 1.11 1999/08/27 23:12:21 peter Exp $ BINDIR?= /bin CFLAGS+= -Wall -Wformat diff --git a/bin/cat/Makefile b/bin/cat/Makefile index 672a4eeeeff50..441efde3ee398 100644 --- a/bin/cat/Makefile +++ b/bin/cat/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/cat/Makefile,v 1.5 1999/08/27 23:13:32 peter Exp $ PROG= cat diff --git a/bin/cat/cat.1 b/bin/cat/cat.1 index ce684fd94ad8e..20a7f50e63f59 100644 --- a/bin/cat/cat.1 +++ b/bin/cat/cat.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)cat.1 8.3 (Berkeley) 5/2/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/cat/cat.1,v 1.10 1999/08/27 23:13:32 peter Exp $ .\" .Dd May 2, 1995 .Dt CAT 1 diff --git a/bin/cat/cat.c b/bin/cat/cat.c index f88c125ff3169..6dc8536c9069b 100644 --- a/bin/cat/cat.c +++ b/bin/cat/cat.c @@ -45,7 +45,7 @@ static char const copyright[] = static char sccsid[] = "@(#)cat.c 8.2 (Berkeley) 4/27/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/cat/cat.c,v 1.14 1999/08/27 23:13:32 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/chio/Makefile b/bin/chio/Makefile index d4b7f56e3c97b..24d8c6a5e6848 100644 --- a/bin/chio/Makefile +++ b/bin/chio/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/chio/Makefile,v 1.6 1999/08/27 23:13:34 peter Exp $ # @(#)Makefile 8.1 (Berkeley) 6/6/93 CFLAGS+=-I${.CURDIR}/../../sys diff --git a/bin/chio/chio.1 b/bin/chio/chio.1 index 34f913f4287d0..b681da3956cca 100644 --- a/bin/chio/chio.1 +++ b/bin/chio/chio.1 @@ -30,7 +30,7 @@ .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/chio/chio.1,v 1.10 1999/08/27 23:13:34 peter Exp $ .\" .Dd May 14, 1998 .Dt CHIO 1 diff --git a/bin/chio/chio.c b/bin/chio/chio.c index c7ee34429f27f..734674fc9c434 100644 --- a/bin/chio/chio.c +++ b/bin/chio/chio.c @@ -38,7 +38,7 @@ static const char copyright[] = "@(#) Copyright (c) 1996 Jason R. Thorpe. All rights reserved."; static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/chio/chio.c,v 1.15 1999/08/27 23:13:34 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/chio/defs.h b/bin/chio/defs.h index f4580a54b5863..7d21e20095b48 100644 --- a/bin/chio/defs.h +++ b/bin/chio/defs.h @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/bin/chio/defs.h,v 1.2 1999/08/27 23:13:35 peter Exp $ */ /* * Copyright (c) 1996 Jason R. Thorpe diff --git a/bin/chio/pathnames.h b/bin/chio/pathnames.h index 9a9b74a548156..990709906c8cc 100644 --- a/bin/chio/pathnames.h +++ b/bin/chio/pathnames.h @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/bin/chio/pathnames.h,v 1.2 1999/08/27 23:13:35 peter Exp $ */ /* * Copyright (c) 1996 Jason R. Thorpe diff --git a/bin/chmod/Makefile b/bin/chmod/Makefile index 71006d00a5232..22d0d8ab5a0ea 100644 --- a/bin/chmod/Makefile +++ b/bin/chmod/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/chmod/Makefile,v 1.5 1999/08/27 23:13:36 peter Exp $ PROG= chmod diff --git a/bin/chmod/chmod.1 b/bin/chmod/chmod.1 index 847e1900fa08e..6c3dfe4ed01b1 100644 --- a/bin/chmod/chmod.1 +++ b/bin/chmod/chmod.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)chmod.1 8.4 (Berkeley) 3/31/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/chmod/chmod.1,v 1.17 2000/02/17 03:17:03 unfurl Exp $ .\" .Dd March 31, 1994 .Dt CHMOD 1 diff --git a/bin/chmod/chmod.c b/bin/chmod/chmod.c index 90164ebff5a86..6e0d307f6dc28 100644 --- a/bin/chmod/chmod.c +++ b/bin/chmod/chmod.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)chmod.c 8.8 (Berkeley) 4/1/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/chmod/chmod.c,v 1.16 1999/11/28 12:24:16 obrien Exp $"; #endif /* not lint */ #include diff --git a/bin/cp/Makefile b/bin/cp/Makefile index 1b0037f35f2fd..2346f9f5a9e18 100644 --- a/bin/cp/Makefile +++ b/bin/cp/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/cp/Makefile,v 1.7 1999/08/27 23:13:38 peter Exp $ PROG= cp SRCS= cp.c utils.c diff --git a/bin/cp/cp.1 b/bin/cp/cp.1 index 54e050a50cef0..71f57b04ae3fe 100644 --- a/bin/cp/cp.1 +++ b/bin/cp/cp.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)cp.1 8.3 (Berkeley) 4/18/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/cp/cp.1,v 1.16 1999/11/28 09:34:20 mharo Exp $ .\" .Dd April 18, 1994 .Dt CP 1 diff --git a/bin/cp/cp.c b/bin/cp/cp.c index e528aeae93cb6..f18d10da4766a 100644 --- a/bin/cp/cp.c +++ b/bin/cp/cp.c @@ -45,7 +45,7 @@ static char const copyright[] = static char sccsid[] = "@(#)cp.c 8.2 (Berkeley) 4/1/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/cp/cp.c,v 1.24 1999/11/28 09:34:21 mharo Exp $"; #endif /* not lint */ /* diff --git a/bin/cp/extern.h b/bin/cp/extern.h index 272d632d3ed2c..39def0fea9b21 100644 --- a/bin/cp/extern.h +++ b/bin/cp/extern.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.2 (Berkeley) 4/1/94 - * $FreeBSD$ + * $FreeBSD: src/bin/cp/extern.h,v 1.9 1999/08/27 23:13:39 peter Exp $ */ typedef struct { diff --git a/bin/cp/utils.c b/bin/cp/utils.c index 86ab3ab6c87c4..1f8b38b2bf0c6 100644 --- a/bin/cp/utils.c +++ b/bin/cp/utils.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)utils.c 8.3 (Berkeley) 4/1/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/cp/utils.c,v 1.27 2000/01/23 03:04:49 mharo Exp $"; #endif /* not lint */ #include diff --git a/bin/csh/Makefile b/bin/csh/Makefile index 3ebbb1e1f9db3..d37253ed301da 100644 --- a/bin/csh/Makefile +++ b/bin/csh/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/csh/Makefile,v 1.11 1999/09/08 15:40:42 sheldonh Exp $ # @(#)Makefile 8.1 (Berkeley) 5/31/93 # # C Shell with process control; VM/UNIX VAX Makefile diff --git a/bin/csh/USD.doc/Makefile b/bin/csh/USD.doc/Makefile index e067417f94b3c..ec1e49226a909 100644 --- a/bin/csh/USD.doc/Makefile +++ b/bin/csh/USD.doc/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 8/14/93 -# $FreeBSD$ +# $FreeBSD: src/bin/csh/USD.doc/Makefile,v 1.5 1999/08/27 23:13:53 peter Exp $ DIR= usd/04.csh SRCS= tabs csh.1 csh.2 csh.3 csh.4 csh.a csh.g diff --git a/bin/csh/USD.doc/csh.1 b/bin/csh/USD.doc/csh.1 index db6d46866a0a1..1dee19fd23f37 100644 --- a/bin/csh/USD.doc/csh.1 +++ b/bin/csh/USD.doc/csh.1 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)csh.1 8.1 (Berkeley) 6/8/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/USD.doc/csh.1,v 1.9 2000/03/03 15:22:15 sheldonh Exp $ .\" .EH 'USD:4-%''An Introduction to the C shell' .OH 'An Introduction to the C shell''USD:4-%' diff --git a/bin/csh/USD.doc/csh.2 b/bin/csh/USD.doc/csh.2 index 043b73f717487..701c55ec954d7 100644 --- a/bin/csh/USD.doc/csh.2 +++ b/bin/csh/USD.doc/csh.2 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)csh.2 8.1 (Berkeley) 6/8/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/USD.doc/csh.2,v 1.7 2000/03/02 14:53:23 sheldonh Exp $ .\" .nr H1 1 .NH diff --git a/bin/csh/USD.doc/csh.3 b/bin/csh/USD.doc/csh.3 index 083fbcc7d4298..e90fb94299bec 100644 --- a/bin/csh/USD.doc/csh.3 +++ b/bin/csh/USD.doc/csh.3 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)csh.3 8.1 (Berkeley) 6/8/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/USD.doc/csh.3,v 1.6 2000/03/02 14:53:24 sheldonh Exp $ .\" .nr H1 2 .NH diff --git a/bin/csh/USD.doc/csh.4 b/bin/csh/USD.doc/csh.4 index 8a2bcbda5ecd3..330c3ef62c44f 100644 --- a/bin/csh/USD.doc/csh.4 +++ b/bin/csh/USD.doc/csh.4 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)csh.4 8.1 (Berkeley) 6/8/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/USD.doc/csh.4,v 1.5 1999/08/27 23:13:55 peter Exp $ .\" .nr H1 3 .NH diff --git a/bin/csh/USD.doc/csh.a b/bin/csh/USD.doc/csh.a index 176534fac1d3d..50fcafc1ae7fb 100644 --- a/bin/csh/USD.doc/csh.a +++ b/bin/csh/USD.doc/csh.a @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)csh.a 8.1 (Berkeley) 6/8/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/USD.doc/csh.a,v 1.5 1999/08/27 23:13:56 peter Exp $ .\" .SH Appendix \- Special characters diff --git a/bin/csh/USD.doc/csh.g b/bin/csh/USD.doc/csh.g index 41151735df235..fbf1c62ee0b97 100644 --- a/bin/csh/USD.doc/csh.g +++ b/bin/csh/USD.doc/csh.g @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)csh.g 8.1 (Berkeley) 6/8/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/USD.doc/csh.g,v 1.5 1999/08/27 23:13:56 peter Exp $ .\" .SH Glossary diff --git a/bin/csh/USD.doc/tabs b/bin/csh/USD.doc/tabs index 7066e0716d36e..6e73af5c1b153 100644 --- a/bin/csh/USD.doc/tabs +++ b/bin/csh/USD.doc/tabs @@ -30,6 +30,6 @@ .\" SUCH DAMAGE. .\" .\" @(#)tabs 8.1 (Berkeley) 6/8/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/USD.doc/tabs,v 1.5 1999/08/27 23:13:56 peter Exp $ .\" .ta 5n 10n 15n 20n 25n 30n 35n 40n 45n 50n 55n 60n 65n 70n 75n 80n diff --git a/bin/csh/alloc.c b/bin/csh/alloc.c index 16533298f62f6..c45163f10b2c2 100644 --- a/bin/csh/alloc.c +++ b/bin/csh/alloc.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)alloc.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/alloc.c,v 1.10 1999/08/27 23:13:41 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/char.c b/bin/csh/char.c index b2aa378df6828..c8d242c947f99 100644 --- a/bin/csh/char.c +++ b/bin/csh/char.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)char.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/char.c,v 1.6 1999/08/27 23:13:41 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/char.h b/bin/csh/char.h index 396e7ab340674..2208edcd96e97 100644 --- a/bin/csh/char.h +++ b/bin/csh/char.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)char.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/csh/char.h,v 1.5 1999/08/27 23:13:41 peter Exp $ */ #include diff --git a/bin/csh/const.c b/bin/csh/const.c index 41de3c1241570..272fe98526e15 100644 --- a/bin/csh/const.c +++ b/bin/csh/const.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)const.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/const.c,v 1.8 1999/08/27 23:13:42 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/csh.1 b/bin/csh/csh.1 index bca5047f990b0..b27cb149af1fe 100644 --- a/bin/csh/csh.1 +++ b/bin/csh/csh.1 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)csh.1 8.2 (Berkeley) 1/21/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/csh/csh.1,v 1.18 2000/02/17 03:40:21 unfurl Exp $ .\" .Dd January 21, 1994 .Dt CSH 1 diff --git a/bin/csh/csh.c b/bin/csh/csh.c index 0bbc55773c1b1..560c8a498ce02 100644 --- a/bin/csh/csh.c +++ b/bin/csh/csh.c @@ -42,7 +42,7 @@ static const char copyright[] = static char sccsid[] = "@(#)csh.c 8.2 (Berkeley) 10/12/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/csh.c,v 1.15 1999/08/27 23:13:43 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/csh.h b/bin/csh/csh.h index cf6723f92aeb2..25c3f9f70e3be 100644 --- a/bin/csh/csh.h +++ b/bin/csh/csh.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)csh.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/csh/csh.h,v 1.8 1999/08/27 23:13:43 peter Exp $ */ /* diff --git a/bin/csh/dir.c b/bin/csh/dir.c index 62acd391493c4..106654b1c6aaf 100644 --- a/bin/csh/dir.c +++ b/bin/csh/dir.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)dir.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/dir.c,v 1.10 1999/08/27 23:13:44 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/dir.h b/bin/csh/dir.h index 285acb7ccca3c..e1a4acceda789 100644 --- a/bin/csh/dir.h +++ b/bin/csh/dir.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)dir.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/csh/dir.h,v 1.5 1999/08/27 23:13:44 peter Exp $ */ /* diff --git a/bin/csh/dol.c b/bin/csh/dol.c index fdab1077077f6..873bd98550be7 100644 --- a/bin/csh/dol.c +++ b/bin/csh/dol.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)dol.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/dol.c,v 1.10 1999/08/27 23:13:44 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/err.c b/bin/csh/err.c index 9eb689d64665c..eb5e9d6074703 100644 --- a/bin/csh/err.c +++ b/bin/csh/err.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)err.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/err.c,v 1.10 1999/08/27 23:13:45 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/exec.c b/bin/csh/exec.c index 64d45d29fadde..161d72d1d9798 100644 --- a/bin/csh/exec.c +++ b/bin/csh/exec.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)exec.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/exec.c,v 1.11 1999/08/27 23:13:45 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/exp.c b/bin/csh/exp.c index b6ec28095c539..2076c275b3848 100644 --- a/bin/csh/exp.c +++ b/bin/csh/exp.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)exp.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/exp.c,v 1.8 1999/08/27 23:13:45 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/extern.h b/bin/csh/extern.h index a1cbfcb5aa23b..7ced11967f5b2 100644 --- a/bin/csh/extern.h +++ b/bin/csh/extern.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/csh/extern.h,v 1.6 1999/08/27 23:13:46 peter Exp $ */ #include diff --git a/bin/csh/file.c b/bin/csh/file.c index a1f5ab2f19bf0..4b7404430a4e8 100644 --- a/bin/csh/file.c +++ b/bin/csh/file.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)file.c 8.2 (Berkeley) 3/19/94"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/file.c,v 1.10 1999/08/27 23:13:46 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/func.c b/bin/csh/func.c index 2a1b80258c54e..a8e16cc713770 100644 --- a/bin/csh/func.c +++ b/bin/csh/func.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)func.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/func.c,v 1.15 1999/10/09 20:47:59 green Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/glob.c b/bin/csh/glob.c index 09c928a570ec1..d392b2af9ad8e 100644 --- a/bin/csh/glob.c +++ b/bin/csh/glob.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)glob.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/glob.c,v 1.12 1999/08/27 23:13:47 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/hist.c b/bin/csh/hist.c index 2df74e1d17405..820f602a62589 100644 --- a/bin/csh/hist.c +++ b/bin/csh/hist.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)hist.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/hist.c,v 1.9 1999/08/27 23:13:47 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/init.c b/bin/csh/init.c index c290a6b5d85b6..00c7ac11a3bb4 100644 --- a/bin/csh/init.c +++ b/bin/csh/init.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)init.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/init.c,v 1.6 1999/08/27 23:13:47 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/lex.c b/bin/csh/lex.c index 6ea61ace58ae2..984363ad93f93 100644 --- a/bin/csh/lex.c +++ b/bin/csh/lex.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)lex.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/lex.c,v 1.13 1999/08/27 23:13:48 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/misc.c b/bin/csh/misc.c index 56491d12163fc..438b0df7beff2 100644 --- a/bin/csh/misc.c +++ b/bin/csh/misc.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)misc.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/misc.c,v 1.9 1999/08/27 23:13:48 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/parse.c b/bin/csh/parse.c index 4cb2fcf5af1cd..87eca19d7dfaa 100644 --- a/bin/csh/parse.c +++ b/bin/csh/parse.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)parse.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/parse.c,v 1.9 1999/08/27 23:13:49 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/pathnames.h b/bin/csh/pathnames.h index bcdb4caf46f0c..07bcf8eeb4da4 100644 --- a/bin/csh/pathnames.h +++ b/bin/csh/pathnames.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)pathnames.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/csh/pathnames.h,v 1.6 1999/08/27 23:13:49 peter Exp $ */ #define _PATH_BIN "/bin" diff --git a/bin/csh/proc.c b/bin/csh/proc.c index a6631ec3eb306..aaa323aec1e25 100644 --- a/bin/csh/proc.c +++ b/bin/csh/proc.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)proc.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/proc.c,v 1.11 1999/08/27 23:13:49 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/proc.h b/bin/csh/proc.h index 0aa52595ba829..74b6a537b9c15 100644 --- a/bin/csh/proc.h +++ b/bin/csh/proc.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)proc.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/csh/proc.h,v 1.5 1999/08/27 23:13:50 peter Exp $ */ /* diff --git a/bin/csh/sem.c b/bin/csh/sem.c index ee7eb2076a617..74a83c9ad7793 100644 --- a/bin/csh/sem.c +++ b/bin/csh/sem.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)sem.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/sem.c,v 1.11 1999/08/27 23:13:50 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/set.c b/bin/csh/set.c index af6c6cd19241c..932cca943ccf0 100644 --- a/bin/csh/set.c +++ b/bin/csh/set.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)set.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/set.c,v 1.12 1999/08/27 23:13:51 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/str.c b/bin/csh/str.c index e205e22ed6dd5..7761744b731b9 100644 --- a/bin/csh/str.c +++ b/bin/csh/str.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)str.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/str.c,v 1.7 1999/08/27 23:13:51 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/csh/time.c b/bin/csh/time.c index bda3874b5dd13..7183ba5eb469b 100644 --- a/bin/csh/time.c +++ b/bin/csh/time.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)time.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/csh/time.c,v 1.10 1999/08/27 23:13:51 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/date/Makefile b/bin/date/Makefile index 8a1dc85793307..83bf86e000e7b 100644 --- a/bin/date/Makefile +++ b/bin/date/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/date/Makefile,v 1.8 1999/08/27 23:13:58 peter Exp $ PROG= date SRCS= date.c netdate.c vary.c diff --git a/bin/date/date.1 b/bin/date/date.1 index 955505f480b49..19fec255bb710 100644 --- a/bin/date/date.1 +++ b/bin/date/date.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)date.1 8.3 (Berkeley) 4/28/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/date/date.1,v 1.34 2000/03/07 20:54:17 sheldonh Exp $ .\" .Dd November 17, 1993 .Dt DATE 1 diff --git a/bin/date/date.c b/bin/date/date.c index fcd90697b3e52..45480c887fe63 100644 --- a/bin/date/date.c +++ b/bin/date/date.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)date.c 8.2 (Berkeley) 4/28/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/date/date.c,v 1.32 1999/12/29 16:50:08 sheldonh Exp $"; #endif /* not lint */ #include diff --git a/bin/date/extern.h b/bin/date/extern.h index 4726eb6a97c35..2d42723b03a62 100644 --- a/bin/date/extern.h +++ b/bin/date/extern.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/date/extern.h,v 1.5 1999/08/27 23:13:59 peter Exp $ */ int netsettime __P((time_t)); diff --git a/bin/date/netdate.c b/bin/date/netdate.c index 3ec041ad18138..7fa0896a297e3 100644 --- a/bin/date/netdate.c +++ b/bin/date/netdate.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)netdate.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/date/netdate.c,v 1.11 1999/08/27 23:13:59 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/date/vary.c b/bin/date/vary.c index 97556fd52e507..0a64c08b2410c 100644 --- a/bin/date/vary.c +++ b/bin/date/vary.c @@ -26,7 +26,7 @@ #ifndef lint static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/date/vary.c,v 1.8 2000/02/18 23:41:45 alfred Exp $"; #endif /* not lint */ #include diff --git a/bin/date/vary.h b/bin/date/vary.h index b39306a2bb233..27eddf7e74fe0 100644 --- a/bin/date/vary.h +++ b/bin/date/vary.h @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD$ + * $FreeBSD: src/bin/date/vary.h,v 1.4 1999/08/27 23:14:00 peter Exp $ */ struct vary { diff --git a/bin/dd/Makefile b/bin/dd/Makefile index 0cbd23895879f..7bf3e4bd57444 100644 --- a/bin/dd/Makefile +++ b/bin/dd/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/dd/Makefile,v 1.8 1999/12/07 03:32:37 green Exp $ PROG= dd SRCS= args.c conv.c conv_tab.c dd.c misc.c position.c diff --git a/bin/dd/args.c b/bin/dd/args.c index 9843ddbf91760..4e571ddb8730a 100644 --- a/bin/dd/args.c +++ b/bin/dd/args.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)args.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/dd/args.c,v 1.25 2000/02/26 21:29:44 green Exp $"; #endif /* not lint */ #include diff --git a/bin/dd/conv.c b/bin/dd/conv.c index 0987a67f081b6..3b9887b81064b 100644 --- a/bin/dd/conv.c +++ b/bin/dd/conv.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)conv.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/dd/conv.c,v 1.15 1999/09/13 21:47:10 green Exp $"; #endif /* not lint */ #include diff --git a/bin/dd/conv_tab.c b/bin/dd/conv_tab.c index bd951a76b34ce..ebc37363d2b2d 100644 --- a/bin/dd/conv_tab.c +++ b/bin/dd/conv_tab.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)conv_tab.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/dd/conv_tab.c,v 1.10 1999/09/12 16:51:53 green Exp $"; #endif /* not lint */ #include diff --git a/bin/dd/dd.1 b/bin/dd/dd.1 index 24149f4c483eb..018a0a67747b0 100644 --- a/bin/dd/dd.1 +++ b/bin/dd/dd.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)dd.1 8.2 (Berkeley) 1/13/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/dd/dd.1,v 1.15 2000/03/01 05:28:45 green Exp $ .\" .Dd January 13, 1994 .Dt DD 1 diff --git a/bin/dd/dd.c b/bin/dd/dd.c index 97613f557b607..06285e7ab5e93 100644 --- a/bin/dd/dd.c +++ b/bin/dd/dd.c @@ -46,7 +46,7 @@ static char const copyright[] = static char sccsid[] = "@(#)dd.c 8.5 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/dd/dd.c,v 1.27 1999/10/03 18:49:51 green Exp $"; #endif /* not lint */ #include diff --git a/bin/dd/dd.h b/bin/dd/dd.h index ae27a0ef9f285..0d5ac87aa98fb 100644 --- a/bin/dd/dd.h +++ b/bin/dd/dd.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)dd.h 8.3 (Berkeley) 4/2/94 - * $FreeBSD$ + * $FreeBSD: src/bin/dd/dd.h,v 1.15 1999/09/13 21:47:10 green Exp $ */ /* Input/output stream state. */ diff --git a/bin/dd/extern.h b/bin/dd/extern.h index e5c982ca1b571..766012cd398fb 100644 --- a/bin/dd/extern.h +++ b/bin/dd/extern.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.3 (Berkeley) 4/2/94 - * $FreeBSD$ + * $FreeBSD: src/bin/dd/extern.h,v 1.9 1999/09/13 21:47:10 green Exp $ */ #include diff --git a/bin/dd/misc.c b/bin/dd/misc.c index 8d756683e4340..c62df93d225d2 100644 --- a/bin/dd/misc.c +++ b/bin/dd/misc.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)misc.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/dd/misc.c,v 1.18 1999/08/27 23:14:04 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/dd/position.c b/bin/dd/position.c index 9d3d0d896b65a..6c7af102033b5 100644 --- a/bin/dd/position.c +++ b/bin/dd/position.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)position.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/dd/position.c,v 1.17 1999/09/16 19:50:59 green Exp $"; #endif /* not lint */ #include diff --git a/bin/df/Makefile b/bin/df/Makefile index 182ac8c6b47b2..24f6e8ba304da 100644 --- a/bin/df/Makefile +++ b/bin/df/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/df/Makefile,v 1.9 1999/12/15 03:44:08 mharo Exp $ # @(#)Makefile 8.3 (Berkeley) 5/8/95 PROG= df diff --git a/bin/df/df.1 b/bin/df/df.1 index 3e99fb5583213..3ac2d1fa7d61d 100644 --- a/bin/df/df.1 +++ b/bin/df/df.1 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)df.1 8.3 (Berkeley) 5/8/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/df/df.1,v 1.18 1999/12/15 03:44:08 mharo Exp $ .\" .Dd May 8, 1995 .Dt DF 1 diff --git a/bin/df/df.c b/bin/df/df.c index f75b468905e96..27f8a5e8d208e 100644 --- a/bin/df/df.c +++ b/bin/df/df.c @@ -47,7 +47,7 @@ static const char copyright[] = static char sccsid[] = "@(#)df.c 8.9 (Berkeley) 5/8/95"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/df/df.c,v 1.23 1999/12/15 03:44:09 mharo Exp $"; #endif #endif /* not lint */ diff --git a/bin/domainname/Makefile b/bin/domainname/Makefile index 724bd06f6a39f..c36faa9758bf5 100644 --- a/bin/domainname/Makefile +++ b/bin/domainname/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/domainname/Makefile,v 1.4 1999/08/27 23:14:07 peter Exp $ PROG= domainname diff --git a/bin/domainname/domainname.1 b/bin/domainname/domainname.1 index 96e4f076fdf6f..24e0a3212ecc6 100644 --- a/bin/domainname/domainname.1 +++ b/bin/domainname/domainname.1 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" From: @(#)hostname.1 8.1 (Berkeley) 5/31/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/domainname/domainname.1,v 1.8 1999/08/27 23:14:08 peter Exp $ .\" .Dd September 18, 1994 .Dt DOMAINNAME 1 diff --git a/bin/domainname/domainname.c b/bin/domainname/domainname.c index d0c989c39fddd..8523ce8046bdb 100644 --- a/bin/domainname/domainname.c +++ b/bin/domainname/domainname.c @@ -42,7 +42,7 @@ static char const copyright[] = static char const sccsid[] = "From: @(#)hostname.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/domainname/domainname.c,v 1.12 1999/08/27 23:14:08 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/echo/Makefile b/bin/echo/Makefile index d00d4679d7ac8..7a3b9fe879d4f 100644 --- a/bin/echo/Makefile +++ b/bin/echo/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/echo/Makefile,v 1.5 1999/08/27 23:14:09 peter Exp $ PROG= echo diff --git a/bin/echo/echo.1 b/bin/echo/echo.1 index 0f43f99553773..e85550c12d66c 100644 --- a/bin/echo/echo.1 +++ b/bin/echo/echo.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)echo.1 8.1 (Berkeley) 7/22/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/echo/echo.1,v 1.10 1999/09/14 11:46:02 sheldonh Exp $ .\" .Dd July 22, 1993 .Dt ECHO 1 diff --git a/bin/echo/echo.c b/bin/echo/echo.c index edab483ddbbc6..6af5f21d06c1d 100644 --- a/bin/echo/echo.c +++ b/bin/echo/echo.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)echo.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/echo/echo.c,v 1.8 1999/08/27 23:14:10 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/ed/Makefile b/bin/ed/Makefile index 95901a69bd0e3..98f82f2ef6f85 100644 --- a/bin/ed/Makefile +++ b/bin/ed/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/ed/Makefile,v 1.18 2000/02/29 11:39:24 markm Exp $ PROG= ed SRCS= buf.c cbc.c glbl.c io.c main.c re.c sub.c undo.c diff --git a/bin/ed/POSIX b/bin/ed/POSIX index 47b720d867ef8..249cf26fc6a23 100644 --- a/bin/ed/POSIX +++ b/bin/ed/POSIX @@ -1,4 +1,4 @@ -$FreeBSD$ +$FreeBSD: src/bin/ed/POSIX,v 1.7 1999/08/27 23:14:12 peter Exp $ This version of ed(1) is not strictly POSIX compliant, as described in the POSIX 1003.2 document. The following is a summary of the omissions, diff --git a/bin/ed/README b/bin/ed/README index 478e7af07c701..1f50f106fdb55 100644 --- a/bin/ed/README +++ b/bin/ed/README @@ -1,4 +1,4 @@ -$FreeBSD$ +$FreeBSD: src/bin/ed/README,v 1.7 1999/08/27 23:14:12 peter Exp $ ed is an 8-bit-clean, POSIX-compliant line editor. It should work with any regular expression package that conforms to the POSIX interface diff --git a/bin/ed/buf.c b/bin/ed/buf.c index 4e24796425526..5b690d4bb8f98 100644 --- a/bin/ed/buf.c +++ b/bin/ed/buf.c @@ -31,7 +31,7 @@ static char * const rcsid = "@(#)buf.c,v 1.4 1994/02/01 00:34:35 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/buf.c,v 1.17 1999/08/27 23:14:12 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ed/cbc.c b/bin/ed/cbc.c index f77ce0dc5a18f..702d5cff97448 100644 --- a/bin/ed/cbc.c +++ b/bin/ed/cbc.c @@ -42,7 +42,7 @@ static char * const rcsid = "@(#)cbc.c,v 1.2 1994/02/01 00:34:36 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/cbc.c,v 1.12 1999/08/27 23:14:12 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ed/ed.1 b/bin/ed/ed.1 index bbb6a1745073a..5deaa2101da26 100644 --- a/bin/ed/ed.1 +++ b/bin/ed/ed.1 @@ -1,4 +1,4 @@ -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/ed/ed.1,v 1.17 2000/03/01 10:43:03 sheldonh Exp $ .Dd May 21, 1993 .Dt ED 1 .Os diff --git a/bin/ed/ed.h b/bin/ed/ed.h index d313a84f1cdf0..c6d0177379782 100644 --- a/bin/ed/ed.h +++ b/bin/ed/ed.h @@ -25,7 +25,7 @@ * SUCH DAMAGE. * * @(#)ed.h,v 1.5 1994/02/01 00:34:39 alm Exp - * $FreeBSD$ + * $FreeBSD: src/bin/ed/ed.h,v 1.13 1999/08/27 23:14:13 peter Exp $ */ #include /* for MAXPATHLEN */ diff --git a/bin/ed/glbl.c b/bin/ed/glbl.c index 3eae4f250f829..6d987bc11b072 100644 --- a/bin/ed/glbl.c +++ b/bin/ed/glbl.c @@ -31,7 +31,7 @@ static char * const rcsid = "@(#)glob.c,v 1.1 1994/02/01 00:34:40 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/glbl.c,v 1.9 1999/08/27 23:14:14 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ed/io.c b/bin/ed/io.c index 203079898f637..c0158d27a138e 100644 --- a/bin/ed/io.c +++ b/bin/ed/io.c @@ -30,7 +30,7 @@ static char * const rcsid = "@(#)io.c,v 1.1 1994/02/01 00:34:41 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/io.c,v 1.10 1999/08/27 23:14:14 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ed/main.c b/bin/ed/main.c index 7bff1297900a8..9a7fd914c31fb 100644 --- a/bin/ed/main.c +++ b/bin/ed/main.c @@ -37,7 +37,7 @@ static char * const copyright = static char * const rcsid = "@(#)main.c,v 1.1 1994/02/01 00:34:42 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/main.c,v 1.14 1999/08/27 23:14:14 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ed/re.c b/bin/ed/re.c index d81d0d786e95a..6a56d71b64ef3 100644 --- a/bin/ed/re.c +++ b/bin/ed/re.c @@ -31,7 +31,7 @@ static char * const rcsid = "@(#)re.c,v 1.6 1994/02/01 00:34:43 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/re.c,v 1.15 1999/08/27 23:14:15 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ed/sub.c b/bin/ed/sub.c index 32213734b6b7c..dba8676e158eb 100644 --- a/bin/ed/sub.c +++ b/bin/ed/sub.c @@ -31,7 +31,7 @@ static char * const rcsid = "@(#)sub.c,v 1.1 1994/02/01 00:34:44 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/sub.c,v 1.12 1999/08/27 23:14:15 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ed/test/Makefile b/bin/ed/test/Makefile index aedfb698f131d..c6265ea518a56 100644 --- a/bin/ed/test/Makefile +++ b/bin/ed/test/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/ed/test/Makefile,v 1.9 1999/08/27 23:14:17 peter Exp $ SHELL= /bin/sh ED= ${.OBJDIR}/ed diff --git a/bin/ed/test/README b/bin/ed/test/README index 74c4826a269d9..e360c4fe86ddc 100644 --- a/bin/ed/test/README +++ b/bin/ed/test/README @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/ed/test/README,v 1.7 1999/08/27 23:14:17 peter Exp $ The files in this directory with suffixes `.t', `.d', `.r' and `.err' are used for testing ed. To run the tests, set the ED variable in the Makefile diff --git a/bin/ed/test/ckscripts.sh b/bin/ed/test/ckscripts.sh index deab47555f7ad..2c57449fc3a77 100644 --- a/bin/ed/test/ckscripts.sh +++ b/bin/ed/test/ckscripts.sh @@ -3,7 +3,7 @@ # and compares their output against the .r files, which contain # the correct output # -# $FreeBSD$ +# $FreeBSD: src/bin/ed/test/ckscripts.sh,v 1.6 1999/08/27 23:14:18 peter Exp $ PATH="/bin:/usr/bin:/usr/local/bin/:." ED=$1 diff --git a/bin/ed/test/mkscripts.sh b/bin/ed/test/mkscripts.sh index 1b8b3ee531827..2d1a06f14a7aa 100644 --- a/bin/ed/test/mkscripts.sh +++ b/bin/ed/test/mkscripts.sh @@ -1,7 +1,7 @@ #!/bin/sh - # This script generates ed test scripts (.ed) from .t files # -# $FreeBSD$ +# $FreeBSD: src/bin/ed/test/mkscripts.sh,v 1.6 1999/08/27 23:14:20 peter Exp $ PATH="/bin:/usr/bin:/usr/local/bin/:." ED=$1 diff --git a/bin/ed/undo.c b/bin/ed/undo.c index b2063c7c2791f..1866c35fefeaf 100644 --- a/bin/ed/undo.c +++ b/bin/ed/undo.c @@ -30,7 +30,7 @@ static char * const rcsid = "@(#)undo.c,v 1.1 1994/02/01 00:34:44 alm Exp"; #else static char * const rcsid = - "$FreeBSD$"; + "$FreeBSD: src/bin/ed/undo.c,v 1.9 1999/08/27 23:14:15 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/expr/Makefile b/bin/expr/Makefile index 544853e10a257..3066131b8ee0d 100644 --- a/bin/expr/Makefile +++ b/bin/expr/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/expr/Makefile,v 1.14 1999/08/27 23:14:22 peter Exp $ PROG= expr SRCS= expr.y diff --git a/bin/expr/expr.1 b/bin/expr/expr.1 index 85a0c8ebf601e..ca9b1e85a91a5 100644 --- a/bin/expr/expr.1 +++ b/bin/expr/expr.1 @@ -28,7 +28,7 @@ .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. .\" -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/expr/expr.1,v 1.9 1999/08/27 23:14:22 peter Exp $ .\" .Dd July 3, 1993 .Dt EXPR 1 diff --git a/bin/expr/expr.y b/bin/expr/expr.y index 117270a14f77f..67c65abf4e1a9 100644 --- a/bin/expr/expr.y +++ b/bin/expr/expr.y @@ -4,7 +4,7 @@ * * Largely rewritten by J.T. Conklin (jtc@wimsey.com) * - * $FreeBSD$ + * $FreeBSD: src/bin/expr/expr.y,v 1.14 1999/08/27 23:14:22 peter Exp $ */ #include diff --git a/bin/hostname/Makefile b/bin/hostname/Makefile index 3c7997f862fc5..a377f7e282f9b 100644 --- a/bin/hostname/Makefile +++ b/bin/hostname/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/hostname/Makefile,v 1.5 1999/08/27 23:14:23 peter Exp $ PROG= hostname diff --git a/bin/hostname/hostname.1 b/bin/hostname/hostname.1 index ebadd2e341d14..2c498d111f0af 100644 --- a/bin/hostname/hostname.1 +++ b/bin/hostname/hostname.1 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)hostname.1 8.2 (Berkeley) 4/28/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/hostname/hostname.1,v 1.10 1999/12/22 01:28:49 jhb Exp $ .\" .Dd April 28, 1995 .Dt HOSTNAME 1 diff --git a/bin/hostname/hostname.c b/bin/hostname/hostname.c index 94e5d4a724340..e89ebcdfffac6 100644 --- a/bin/hostname/hostname.c +++ b/bin/hostname/hostname.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)hostname.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/hostname/hostname.c,v 1.10 1999/08/27 23:14:25 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/kill/Makefile b/bin/kill/Makefile index 55ef16dfce2c9..67d11d811277b 100644 --- a/bin/kill/Makefile +++ b/bin/kill/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/kill/Makefile,v 1.5 1999/08/27 23:14:25 peter Exp $ PROG= kill diff --git a/bin/kill/kill.1 b/bin/kill/kill.1 index 1a6d0f734f3c1..b9c963195b2d8 100644 --- a/bin/kill/kill.1 +++ b/bin/kill/kill.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)kill.1 8.2 (Berkeley) 4/28/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/kill/kill.1,v 1.11 1999/09/14 11:46:02 sheldonh Exp $ .\" .Dd April 28, 1995 .Dt KILL 1 diff --git a/bin/kill/kill.c b/bin/kill/kill.c index 9de184f0cfa1e..5fb578cdb3621 100644 --- a/bin/kill/kill.c +++ b/bin/kill/kill.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)kill.c 8.4 (Berkeley) 4/28/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/kill/kill.c,v 1.11 1999/08/27 23:14:26 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/ln/Makefile b/bin/ln/Makefile index bfbcef839f842..f21cb89b27639 100644 --- a/bin/ln/Makefile +++ b/bin/ln/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.2 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/ln/Makefile,v 1.7 1999/12/20 16:13:45 sheldonh Exp $ PROG= ln MAN1= ln.1 diff --git a/bin/ln/ln.1 b/bin/ln/ln.1 index 89f4e5fda4ed6..25a24f6d185b1 100644 --- a/bin/ln/ln.1 +++ b/bin/ln/ln.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)ln.1 8.2 (Berkeley) 12/30/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/ln/ln.1,v 1.11 1999/12/21 08:57:58 sheldonh Exp $ .\" .Dd December 30, 1993 .Dt LN 1 diff --git a/bin/ln/ln.c b/bin/ln/ln.c index dc2db0ff2f6f9..7ba8b227dab05 100644 --- a/bin/ln/ln.c +++ b/bin/ln/ln.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)ln.c 8.2 (Berkeley) 3/31/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ln/ln.c,v 1.15 1999/12/20 16:13:45 sheldonh Exp $"; #endif /* not lint */ #include diff --git a/bin/ln/symlink.7 b/bin/ln/symlink.7 index 83f997373c57d..775e3dc8e9acb 100644 --- a/bin/ln/symlink.7 +++ b/bin/ln/symlink.7 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)symlink.7 8.3 (Berkeley) 3/31/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/ln/symlink.7,v 1.13 2000/03/01 11:34:04 sheldonh Exp $ .\" .Dd March 31, 1994 .Dt SYMLINK 7 diff --git a/bin/ls/Makefile b/bin/ls/Makefile index 8496dd9cdf58f..ccdc1809ed72f 100644 --- a/bin/ls/Makefile +++ b/bin/ls/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 6/2/93 -# $FreeBSD$ +# $FreeBSD: src/bin/ls/Makefile,v 1.9 2000/02/05 18:42:27 joe Exp $ PROG= ls diff --git a/bin/ls/cmp.c b/bin/ls/cmp.c index 91852ba76fc28..6655e8fc7b4d6 100644 --- a/bin/ls/cmp.c +++ b/bin/ls/cmp.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)cmp.c 8.1 (Berkeley) 5/31/93"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ls/cmp.c,v 1.9 1999/08/27 23:14:31 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ls/extern.h b/bin/ls/extern.h index fd26b372c5f7d..b05e1f4bda863 100644 --- a/bin/ls/extern.h +++ b/bin/ls/extern.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * from: @(#)extern.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/ls/extern.h,v 1.7 1999/08/27 23:14:31 peter Exp $ */ int acccmp __P((const FTSENT *, const FTSENT *)); diff --git a/bin/ls/ls.1 b/bin/ls/ls.1 index 6b29b1fce9243..b1e0abef75c5d 100644 --- a/bin/ls/ls.1 +++ b/bin/ls/ls.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)ls.1 8.7 (Berkeley) 7/29/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/ls/ls.1,v 1.33 2000/03/02 14:53:20 sheldonh Exp $ .\" .Dd July 29, 1994 .Dt LS 1 diff --git a/bin/ls/ls.c b/bin/ls/ls.c index 754236b9450f2..ac0cb5deb82bc 100644 --- a/bin/ls/ls.c +++ b/bin/ls/ls.c @@ -45,7 +45,7 @@ static const char copyright[] = static char sccsid[] = "@(#)ls.c 8.5 (Berkeley) 4/2/94"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ls/ls.c,v 1.32 2000/02/05 18:42:27 joe Exp $"; #endif #endif /* not lint */ diff --git a/bin/ls/ls.h b/bin/ls/ls.h index 33c98c45aab8d..bdb6f543535db 100644 --- a/bin/ls/ls.h +++ b/bin/ls/ls.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * from: @(#)ls.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/ls/ls.h,v 1.11 1999/08/27 23:14:32 peter Exp $ */ #define NO_PRINT 1 diff --git a/bin/ls/print.c b/bin/ls/print.c index 702b6b1ccc974..c6b57bcaad7ba 100644 --- a/bin/ls/print.c +++ b/bin/ls/print.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)print.c 8.4 (Berkeley) 4/17/94"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ls/print.c,v 1.19 2000/01/06 14:40:10 bde Exp $"; #endif #endif /* not lint */ diff --git a/bin/ls/util.c b/bin/ls/util.c index eea247587a9c8..1b750f9a26d9d 100644 --- a/bin/ls/util.c +++ b/bin/ls/util.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)util.c 8.3 (Berkeley) 4/2/94"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ls/util.c,v 1.20 1999/08/27 23:14:33 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/mkdir/Makefile b/bin/mkdir/Makefile index fadc6b294ef72..8af8b7b72541d 100644 --- a/bin/mkdir/Makefile +++ b/bin/mkdir/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/mkdir/Makefile,v 1.5 1999/08/27 23:14:34 peter Exp $ PROG= mkdir diff --git a/bin/mkdir/mkdir.1 b/bin/mkdir/mkdir.1 index 759382ecfe550..d5fa8d3c28ad9 100644 --- a/bin/mkdir/mkdir.1 +++ b/bin/mkdir/mkdir.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)mkdir.1 8.2 (Berkeley) 1/25/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/mkdir/mkdir.1,v 1.12 1999/09/04 03:19:38 mharo Exp $ .\" .Dd January 25, 1994 .Dt MKDIR 1 diff --git a/bin/mkdir/mkdir.c b/bin/mkdir/mkdir.c index 6c61abff5f14c..38576a3a7faac 100644 --- a/bin/mkdir/mkdir.c +++ b/bin/mkdir/mkdir.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)mkdir.c 8.2 (Berkeley) 1/25/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/mkdir/mkdir.c,v 1.19 1999/09/04 03:19:38 mharo Exp $"; #endif /* not lint */ #include diff --git a/bin/mv/Makefile b/bin/mv/Makefile index 840578276d5a3..72598c4ac8ad8 100644 --- a/bin/mv/Makefile +++ b/bin/mv/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.2 (Berkeley) 4/2/94 -# $FreeBSD$ +# $FreeBSD: src/bin/mv/Makefile,v 1.6 2000/01/01 15:40:40 joe Exp $ PROG= mv diff --git a/bin/mv/mv.1 b/bin/mv/mv.1 index 528eeaa1a8be4..3e20b44285c20 100644 --- a/bin/mv/mv.1 +++ b/bin/mv/mv.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)mv.1 8.1 (Berkeley) 5/31/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/mv/mv.1,v 1.15 1999/09/04 03:33:18 mharo Exp $ .\" .Dd May 31, 1993 .Dt MV 1 diff --git a/bin/mv/mv.c b/bin/mv/mv.c index 5f0f28b1882d6..47a6b9221a012 100644 --- a/bin/mv/mv.c +++ b/bin/mv/mv.c @@ -45,7 +45,7 @@ static char const copyright[] = static char sccsid[] = "@(#)mv.c 8.2 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/mv/mv.c,v 1.24 1999/08/29 08:21:16 mharo Exp $"; #endif /* not lint */ #include diff --git a/bin/mv/pathnames.h b/bin/mv/pathnames.h index b9cd27ff297cc..23a432391581f 100644 --- a/bin/mv/pathnames.h +++ b/bin/mv/pathnames.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)pathnames.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/mv/pathnames.h,v 1.5 1999/08/27 23:14:37 peter Exp $ */ #define _PATH_RM "/bin/rm" diff --git a/bin/pax/Makefile b/bin/pax/Makefile index b1a4dcf88f106..778669a745ab1 100644 --- a/bin/pax/Makefile +++ b/bin/pax/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/pax/Makefile,v 1.5 1999/08/27 23:14:38 peter Exp $ # To install on versions prior to BSD 4.4 the following may have to be # defined with CFLAGS += diff --git a/bin/pax/ar_io.c b/bin/pax/ar_io.c index b286aa6c88c63..b3015fb0b73d6 100644 --- a/bin/pax/ar_io.c +++ b/bin/pax/ar_io.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)ar_io.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/ar_io.c,v 1.12 1999/08/27 23:14:39 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/ar_subs.c b/bin/pax/ar_subs.c index 151fe2aa0206d..e75d4f547ed28 100644 --- a/bin/pax/ar_subs.c +++ b/bin/pax/ar_subs.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)ar_subs.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/ar_subs.c,v 1.13 1999/08/27 23:14:39 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/buf_subs.c b/bin/pax/buf_subs.c index 50c30761a3e5f..d8dba4c51035e 100644 --- a/bin/pax/buf_subs.c +++ b/bin/pax/buf_subs.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)buf_subs.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/buf_subs.c,v 1.12 1999/08/27 23:14:40 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/cache.c b/bin/pax/cache.c index 7f3b37f6ee127..cc1fa7ecbc1fd 100644 --- a/bin/pax/cache.c +++ b/bin/pax/cache.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)cache.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/cache.c,v 1.12 1999/08/27 23:14:40 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/cache.h b/bin/pax/cache.h index 642058851070b..a950a0cc7d4c1 100644 --- a/bin/pax/cache.h +++ b/bin/pax/cache.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)cache.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/cache.h,v 1.6 1999/08/27 23:14:40 peter Exp $ */ /* diff --git a/bin/pax/cpio.c b/bin/pax/cpio.c index 626a77d94c54c..1595c32e0aa53 100644 --- a/bin/pax/cpio.c +++ b/bin/pax/cpio.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)cpio.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/cpio.c,v 1.12 1999/08/27 23:14:41 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/cpio.h b/bin/pax/cpio.h index 2b72f53b6c1ec..e6f4a0ba32dd3 100644 --- a/bin/pax/cpio.h +++ b/bin/pax/cpio.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)cpio.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/cpio.h,v 1.6 1999/08/27 23:14:41 peter Exp $ */ /* diff --git a/bin/pax/extern.h b/bin/pax/extern.h index 2b062cbde3007..dacfa0dc161b6 100644 --- a/bin/pax/extern.h +++ b/bin/pax/extern.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.2 (Berkeley) 4/18/94 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/extern.h,v 1.6 1999/08/27 23:14:41 peter Exp $ */ /* diff --git a/bin/pax/file_subs.c b/bin/pax/file_subs.c index b8f2a4917c7bd..691a05636befc 100644 --- a/bin/pax/file_subs.c +++ b/bin/pax/file_subs.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)file_subs.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/file_subs.c,v 1.12 1999/08/27 23:14:41 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/ftree.c b/bin/pax/ftree.c index ba1e4890e4558..89879aceb0f14 100644 --- a/bin/pax/ftree.c +++ b/bin/pax/ftree.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)ftree.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/ftree.c,v 1.13 1999/08/27 23:14:42 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/ftree.h b/bin/pax/ftree.h index e5c9749341a1f..85ea7de0b9a71 100644 --- a/bin/pax/ftree.h +++ b/bin/pax/ftree.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)ftree.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/ftree.h,v 1.5 1999/08/27 23:14:42 peter Exp $ */ /* diff --git a/bin/pax/gen_subs.c b/bin/pax/gen_subs.c index 22b77f0feef87..8441dd4826738 100644 --- a/bin/pax/gen_subs.c +++ b/bin/pax/gen_subs.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)gen_subs.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/gen_subs.c,v 1.12 1999/08/27 23:14:43 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/options.c b/bin/pax/options.c index 4ea96e4022974..fa03101ee84d9 100644 --- a/bin/pax/options.c +++ b/bin/pax/options.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)options.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/options.c,v 1.13 1999/08/27 23:14:43 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/options.h b/bin/pax/options.h index b1de2b6de7cfe..0711b6bde5b9b 100644 --- a/bin/pax/options.h +++ b/bin/pax/options.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)options.h 8.2 (Berkeley) 4/18/94 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/options.h,v 1.5 1999/08/27 23:14:43 peter Exp $ */ /* diff --git a/bin/pax/pat_rep.c b/bin/pax/pat_rep.c index e68a0ebf6035e..655d926083ec2 100644 --- a/bin/pax/pat_rep.c +++ b/bin/pax/pat_rep.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)pat_rep.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/pat_rep.c,v 1.15 1999/08/27 23:14:43 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/pat_rep.h b/bin/pax/pat_rep.h index e0d812b1de95a..5475527f26d9f 100644 --- a/bin/pax/pat_rep.h +++ b/bin/pax/pat_rep.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)pat_rep.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/pat_rep.h,v 1.5 1999/08/27 23:14:44 peter Exp $ */ /* diff --git a/bin/pax/pax.1 b/bin/pax/pax.1 index 43311b9f77565..241a187ff5b05 100644 --- a/bin/pax/pax.1 +++ b/bin/pax/pax.1 @@ -34,7 +34,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)pax.1 8.4 (Berkeley) 4/18/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/pax/pax.1,v 1.12 2000/03/02 14:53:22 sheldonh Exp $ .\" .Dd April 18, 1994 .Dt PAX 1 diff --git a/bin/pax/pax.c b/bin/pax/pax.c index 7bcc81e7ad0b4..9616a965c27cd 100644 --- a/bin/pax/pax.c +++ b/bin/pax/pax.c @@ -46,7 +46,7 @@ static char const copyright[] = static char sccsid[] = "@(#)pax.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/pax.c,v 1.13 1999/08/27 23:14:45 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/pax.h b/bin/pax/pax.h index a87b359f14b2a..af06923db9444 100644 --- a/bin/pax/pax.h +++ b/bin/pax/pax.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)pax.h 8.2 (Berkeley) 4/18/94 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/pax.h,v 1.8 1999/08/27 23:14:45 peter Exp $ */ /* diff --git a/bin/pax/sel_subs.c b/bin/pax/sel_subs.c index ba7b71e7e0128..cbec7ab160493 100644 --- a/bin/pax/sel_subs.c +++ b/bin/pax/sel_subs.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)sel_subs.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/sel_subs.c,v 1.11 1999/08/27 23:14:46 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/sel_subs.h b/bin/pax/sel_subs.h index ab24ab00d1991..9c31ba03823b9 100644 --- a/bin/pax/sel_subs.h +++ b/bin/pax/sel_subs.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)sel_subs.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/sel_subs.h,v 1.5 1999/08/27 23:14:46 peter Exp $ */ /* diff --git a/bin/pax/tables.c b/bin/pax/tables.c index e6c106b83d581..d84a41b2954a7 100644 --- a/bin/pax/tables.c +++ b/bin/pax/tables.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)tables.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/tables.c,v 1.13 1999/08/27 23:14:46 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/tables.h b/bin/pax/tables.h index 74c91f79d0ad2..2bda321ba7ad6 100644 --- a/bin/pax/tables.h +++ b/bin/pax/tables.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)tables.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/tables.h,v 1.7 1999/08/27 23:14:47 peter Exp $ */ /* diff --git a/bin/pax/tar.c b/bin/pax/tar.c index f5415f4f74aed..82bd021d63b03 100644 --- a/bin/pax/tar.c +++ b/bin/pax/tar.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)tar.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/tar.c,v 1.13 1999/08/27 23:14:47 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/pax/tar.h b/bin/pax/tar.h index 83df0da2784e1..3bdb2f60e4002 100644 --- a/bin/pax/tar.h +++ b/bin/pax/tar.h @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * @(#)tar.h 8.2 (Berkeley) 4/18/94 - * $FreeBSD$ + * $FreeBSD: src/bin/pax/tar.h,v 1.6 1999/08/27 23:14:47 peter Exp $ */ /* diff --git a/bin/pax/tty_subs.c b/bin/pax/tty_subs.c index d70bffac1827f..68902289febab 100644 --- a/bin/pax/tty_subs.c +++ b/bin/pax/tty_subs.c @@ -40,7 +40,7 @@ static char sccsid[] = "@(#)tty_subs.c 8.2 (Berkeley) 4/18/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pax/tty_subs.c,v 1.11 1999/08/27 23:14:48 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/ps/Makefile b/bin/ps/Makefile index d5c791c2226b1..a13e16e819952 100644 --- a/bin/ps/Makefile +++ b/bin/ps/Makefile @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/ps/Makefile,v 1.13 1999/11/17 13:37:30 peter Exp $ # @(#)Makefile 8.1 (Berkeley) 6/2/93 PROG= ps diff --git a/bin/ps/extern.h b/bin/ps/extern.h index a14390dc1d1fb..ef5a25c6e5025 100644 --- a/bin/ps/extern.h +++ b/bin/ps/extern.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.3 (Berkeley) 4/2/94 - * $FreeBSD$ + * $FreeBSD: src/bin/ps/extern.h,v 1.9 1999/08/27 23:14:50 peter Exp $ */ struct kinfo; diff --git a/bin/ps/fmt.c b/bin/ps/fmt.c index 9c0f8d3f17103..1e92996bc36cd 100644 --- a/bin/ps/fmt.c +++ b/bin/ps/fmt.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)fmt.c 8.4 (Berkeley) 4/15/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ps/fmt.c,v 1.14 1999/08/27 23:14:51 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/ps/keyword.c b/bin/ps/keyword.c index cbabd978c7840..5d9d835e8ce84 100644 --- a/bin/ps/keyword.c +++ b/bin/ps/keyword.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)keyword.c 8.5 (Berkeley) 4/2/94"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ps/keyword.c,v 1.24 1999/08/27 23:14:51 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/ps/print.c b/bin/ps/print.c index a49c8fa656b2a..b682e10dc0cff 100644 --- a/bin/ps/print.c +++ b/bin/ps/print.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)print.c 8.6 (Berkeley) 4/16/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ps/print.c,v 1.36 1999/08/27 23:14:51 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/ps/ps.1 b/bin/ps/ps.1 index f89f8da0ed6dc..fbeeca05521a9 100644 --- a/bin/ps/ps.1 +++ b/bin/ps/ps.1 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)ps.1 8.3 (Berkeley) 4/18/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/ps/ps.1,v 1.24 1999/08/27 23:14:51 peter Exp $ .\" .Dd April 18, 1994 .Dt PS 1 diff --git a/bin/ps/ps.c b/bin/ps/ps.c index 004b0a7bd2e89..346750a694cd4 100644 --- a/bin/ps/ps.c +++ b/bin/ps/ps.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)ps.c 8.4 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/ps/ps.c,v 1.30 1999/11/17 12:52:42 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/ps/ps.h b/bin/ps/ps.h index f8d244c83e539..6cb262d88751d 100644 --- a/bin/ps/ps.h +++ b/bin/ps/ps.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)ps.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/ps/ps.h,v 1.7 1999/08/27 23:14:52 peter Exp $ */ #define UNLIMITED 0 /* unlimited terminal width */ diff --git a/bin/pwd/Makefile b/bin/pwd/Makefile index 4a8e66ac8320d..b411790a1f8f8 100644 --- a/bin/pwd/Makefile +++ b/bin/pwd/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/pwd/Makefile,v 1.5 1999/08/27 23:14:53 peter Exp $ PROG= pwd diff --git a/bin/pwd/pwd.1 b/bin/pwd/pwd.1 index 455f791be0a73..7c3d6f1baa335 100644 --- a/bin/pwd/pwd.1 +++ b/bin/pwd/pwd.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)pwd.1 8.2 (Berkeley) 4/28/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/pwd/pwd.1,v 1.10 1999/09/14 11:46:04 sheldonh Exp $ .\" .Dd April 28, 1995 .Dt PWD 1 diff --git a/bin/pwd/pwd.c b/bin/pwd/pwd.c index 1adb3c86f508e..b3f0be267954d 100644 --- a/bin/pwd/pwd.c +++ b/bin/pwd/pwd.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)pwd.c 8.3 (Berkeley) 4/1/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/pwd/pwd.c,v 1.9 1999/08/27 23:14:54 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/rcp/Makefile b/bin/rcp/Makefile index c3d24835eb169..7c0385cb89ca7 100644 --- a/bin/rcp/Makefile +++ b/bin/rcp/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 7/19/93 -# $FreeBSD$ +# $FreeBSD: src/bin/rcp/Makefile,v 1.16 2000/02/24 21:21:15 markm Exp $ PROG= rcp SRCS= rcp.c util.c diff --git a/bin/rcp/extern.h b/bin/rcp/extern.h index 5081c9dcbb57f..c4d770d3fad0e 100644 --- a/bin/rcp/extern.h +++ b/bin/rcp/extern.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/rcp/extern.h,v 1.5 1999/08/27 23:14:57 peter Exp $ */ typedef struct { diff --git a/bin/rcp/pathnames.h b/bin/rcp/pathnames.h index b1f0ec0831799..2f220ab8338d2 100644 --- a/bin/rcp/pathnames.h +++ b/bin/rcp/pathnames.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)pathnames.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/rcp/pathnames.h,v 1.6 1999/08/27 23:14:57 peter Exp $ */ #include diff --git a/bin/rcp/rcp.1 b/bin/rcp/rcp.1 index 3034e20b486a8..9a64e8e54986a 100644 --- a/bin/rcp/rcp.1 +++ b/bin/rcp/rcp.1 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)rcp.1 8.1 (Berkeley) 5/31/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/rcp/rcp.1,v 1.9 2000/01/07 13:13:58 phantom Exp $ .\" .Dd May 31, 1993 .Dt RCP 1 diff --git a/bin/rcp/rcp.c b/bin/rcp/rcp.c index a1534ea6d823d..ea942a9f6b159 100644 --- a/bin/rcp/rcp.c +++ b/bin/rcp/rcp.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)rcp.c 8.2 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/rcp/rcp.c,v 1.26 2000/02/24 21:21:15 markm Exp $"; #endif /* not lint */ #include diff --git a/bin/rcp/util.c b/bin/rcp/util.c index a8ba4c09f9076..5675f406bbaca 100644 --- a/bin/rcp/util.c +++ b/bin/rcp/util.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)util.c 8.2 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/rcp/util.c,v 1.9 1999/08/27 23:14:58 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/rm/Makefile b/bin/rm/Makefile index 2bbcdf89effc7..88658517a81c3 100644 --- a/bin/rm/Makefile +++ b/bin/rm/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/rm/Makefile,v 1.12 2000/02/05 18:42:29 joe Exp $ PROG= rm SRCS= rm.c setflags.c diff --git a/bin/rm/rm.1 b/bin/rm/rm.1 index a038392f6f140..87c1b24965c63 100644 --- a/bin/rm/rm.1 +++ b/bin/rm/rm.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)rm.1 8.5 (Berkeley) 12/5/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/rm/rm.1,v 1.19 1999/12/21 08:57:57 sheldonh Exp $ .\" .Dd January 28, 1999 .Dt RM 1 diff --git a/bin/rm/rm.c b/bin/rm/rm.c index 3c9071f45fb14..24d922bd7d76e 100644 --- a/bin/rm/rm.c +++ b/bin/rm/rm.c @@ -42,7 +42,7 @@ static const char copyright[] = static char sccsid[] = "@(#)rm.c 8.5 (Berkeley) 4/18/94"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/rm/rm.c,v 1.29 2000/02/05 18:42:30 joe Exp $"; #endif #endif /* not lint */ diff --git a/bin/rmail/Makefile b/bin/rmail/Makefile index 8484be8ec691f..2a730d06978ca 100644 --- a/bin/rmail/Makefile +++ b/bin/rmail/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/rmail/Makefile,v 1.8 1999/08/27 23:15:02 peter Exp $ .PATH: ${.CURDIR}/../../contrib/sendmail/rmail diff --git a/bin/rmdir/Makefile b/bin/rmdir/Makefile index c2c7f301ce492..95d04453b659c 100644 --- a/bin/rmdir/Makefile +++ b/bin/rmdir/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/rmdir/Makefile,v 1.5 1999/08/27 23:15:03 peter Exp $ PROG= rmdir diff --git a/bin/rmdir/rmdir.1 b/bin/rmdir/rmdir.1 index a6a247873b5b9..fbf819b68d0fb 100644 --- a/bin/rmdir/rmdir.1 +++ b/bin/rmdir/rmdir.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)rmdir.1 8.1 (Berkeley) 5/31/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/rmdir/rmdir.1,v 1.8 1999/08/27 23:15:04 peter Exp $ .\" .Dd May 31, 1993 .Dt RMDIR 1 diff --git a/bin/rmdir/rmdir.c b/bin/rmdir/rmdir.c index 4be8427b2eab7..c105542858f8c 100644 --- a/bin/rmdir/rmdir.c +++ b/bin/rmdir/rmdir.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)rmdir.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/rmdir/rmdir.c,v 1.9 1999/08/27 23:15:04 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/Makefile b/bin/sh/Makefile index 01c46f5499c17..9217278caec4c 100644 --- a/bin/sh/Makefile +++ b/bin/sh/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.4 (Berkeley) 5/5/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/Makefile,v 1.30 1999/09/08 15:40:43 sheldonh Exp $ PROG= sh SHSRCS= alias.c arith.y arith_lex.l cd.c echo.c error.c eval.c exec.c expand.c \ diff --git a/bin/sh/TOUR b/bin/sh/TOUR index 5a0b76b7ea909..66605d2902931 100644 --- a/bin/sh/TOUR +++ b/bin/sh/TOUR @@ -1,5 +1,5 @@ # @(#)TOUR 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/TOUR,v 1.6 1999/08/27 23:15:07 peter Exp $ NOTE -- This is the original TOUR paper distributed with ash and does not represent the current state of the shell. It is provided anyway diff --git a/bin/sh/alias.c b/bin/sh/alias.c index 2d605ec59196f..97ab764d3a251 100644 --- a/bin/sh/alias.c +++ b/bin/sh/alias.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)alias.c 8.3 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/alias.c,v 1.12 1999/08/27 23:15:07 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/alias.h b/bin/sh/alias.h index a282a69767038..023d1b987fbe6 100644 --- a/bin/sh/alias.h +++ b/bin/sh/alias.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)alias.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/alias.h,v 1.6 1999/08/27 23:15:07 peter Exp $ */ #define ALIASINUSE 1 diff --git a/bin/sh/arith.h b/bin/sh/arith.h index c58cd3c7cb5cb..33af0b82a7b25 100644 --- a/bin/sh/arith.h +++ b/bin/sh/arith.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)arith.h 1.1 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/arith.h,v 1.5 1999/08/27 23:15:07 peter Exp $ */ int arith __P((char *)); diff --git a/bin/sh/arith.y b/bin/sh/arith.y index 6d5bf95ce1bc1..b2fc3c706ba96 100644 --- a/bin/sh/arith.y +++ b/bin/sh/arith.y @@ -88,7 +88,7 @@ expr: ARITH_LPAREN expr ARITH_RPAREN = { $$ = $2; } * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD$ + * $FreeBSD: src/bin/sh/arith.y,v 1.10 1999/08/27 23:15:08 peter Exp $ */ #ifndef lint @@ -96,7 +96,7 @@ expr: ARITH_LPAREN expr ARITH_RPAREN = { $$ = $2; } static char sccsid[] = "@(#)arith.y 8.3 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/arith.y,v 1.10 1999/08/27 23:15:08 peter Exp $"; #endif /* not lint */ #include "shell.h" diff --git a/bin/sh/arith_lex.l b/bin/sh/arith_lex.l index 8b855bd78121f..e552b1e57b366 100644 --- a/bin/sh/arith_lex.l +++ b/bin/sh/arith_lex.l @@ -34,7 +34,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD$ + * $FreeBSD: src/bin/sh/arith_lex.l,v 1.14 1999/08/27 23:15:08 peter Exp $ */ #ifndef lint @@ -42,7 +42,7 @@ static char sccsid[] = "@(#)arith_lex.l 8.3 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/arith_lex.l,v 1.14 1999/08/27 23:15:08 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/bltin/bltin.h b/bin/sh/bltin/bltin.h index a96c4761006d6..1e4cc7006e7b7 100644 --- a/bin/sh/bltin/bltin.h +++ b/bin/sh/bltin/bltin.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)bltin.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/bltin/bltin.h,v 1.10 1999/08/27 23:15:30 peter Exp $ */ /* diff --git a/bin/sh/bltin/echo.1 b/bin/sh/bltin/echo.1 index a2f57f3d80485..60c21d4b2c59c 100644 --- a/bin/sh/bltin/echo.1 +++ b/bin/sh/bltin/echo.1 @@ -34,7 +34,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)echo.1 8.2 (Berkeley) 5/4/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/sh/bltin/echo.1,v 1.7 1999/08/27 23:15:30 peter Exp $ .\" .Dd May 4, 1995 .Dt ECHO 1 diff --git a/bin/sh/bltin/echo.c b/bin/sh/bltin/echo.c index 8ce088ad060e8..a0827ca71d6b7 100644 --- a/bin/sh/bltin/echo.c +++ b/bin/sh/bltin/echo.c @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)echo.c 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/bltin/echo.c,v 1.9 1999/08/27 23:15:31 peter Exp $ */ /* diff --git a/bin/sh/builtins.def b/bin/sh/builtins.def index 7cdcc38683aa6..4138dae16d0a9 100644 --- a/bin/sh/builtins.def +++ b/bin/sh/builtins.def @@ -35,7 +35,7 @@ # SUCH DAMAGE. # # @(#)builtins.def 8.4 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/builtins.def,v 1.7 1999/08/27 23:15:08 peter Exp $ # # This file lists all the builtin commands. The first column is the name diff --git a/bin/sh/cd.c b/bin/sh/cd.c index 3ec8deee804f8..3a591bb26b4cf 100644 --- a/bin/sh/cd.c +++ b/bin/sh/cd.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)cd.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/cd.c,v 1.20 1999/11/29 19:10:58 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/cd.h b/bin/sh/cd.h index 078b40efe61d7..4a647b018b898 100644 --- a/bin/sh/cd.h +++ b/bin/sh/cd.h @@ -30,7 +30,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD$ + * $FreeBSD: src/bin/sh/cd.h,v 1.5 1999/08/27 23:15:09 peter Exp $ */ char *getpwd __P((void)); diff --git a/bin/sh/error.c b/bin/sh/error.c index e079699d81413..5f0fb5c20a239 100644 --- a/bin/sh/error.c +++ b/bin/sh/error.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)error.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/error.c,v 1.15 1999/11/29 19:10:58 cracauer Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/error.h b/bin/sh/error.h index 6c58c123373dd..efc8332b66152 100644 --- a/bin/sh/error.h +++ b/bin/sh/error.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)error.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/error.h,v 1.11 1999/08/27 23:15:10 peter Exp $ */ /* diff --git a/bin/sh/eval.c b/bin/sh/eval.c index 33dec0ea7be42..32239a6c59405 100644 --- a/bin/sh/eval.c +++ b/bin/sh/eval.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)eval.c 8.9 (Berkeley) 6/8/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/eval.c,v 1.27 1999/12/20 13:42:59 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/eval.h b/bin/sh/eval.h index 4f0b8988cae37..c433be87afbfd 100644 --- a/bin/sh/eval.h +++ b/bin/sh/eval.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)eval.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/eval.h,v 1.7 1999/08/27 23:15:11 peter Exp $ */ extern char *commandname; /* currently executing command */ diff --git a/bin/sh/exec.c b/bin/sh/exec.c index 67a858b184dad..8dfa2a880e659 100644 --- a/bin/sh/exec.c +++ b/bin/sh/exec.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)exec.c 8.4 (Berkeley) 6/8/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/exec.c,v 1.14 1999/12/20 13:42:59 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/exec.h b/bin/sh/exec.h index bb593f0101152..9331b6e74c10d 100644 --- a/bin/sh/exec.h +++ b/bin/sh/exec.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)exec.h 8.3 (Berkeley) 6/8/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/exec.h,v 1.9 1999/12/20 13:42:59 cracauer Exp $ */ /* values of cmdtype */ diff --git a/bin/sh/expand.c b/bin/sh/expand.c index 00c5f09424644..74b5399fbb293 100644 --- a/bin/sh/expand.c +++ b/bin/sh/expand.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)expand.c 8.5 (Berkeley) 5/15/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/expand.c,v 1.31 1999/12/15 11:46:32 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/expand.h b/bin/sh/expand.h index 955b8bf424e7e..581b3c5a2bd2e 100644 --- a/bin/sh/expand.h +++ b/bin/sh/expand.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)expand.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/expand.h,v 1.9 1999/08/27 23:15:12 peter Exp $ */ struct strlist { diff --git a/bin/sh/funcs/cmv b/bin/sh/funcs/cmv index 6e9dcff9c088a..b43e6919c89c5 100644 --- a/bin/sh/funcs/cmv +++ b/bin/sh/funcs/cmv @@ -33,7 +33,7 @@ # SUCH DAMAGE. # # @(#)cmv 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/cmv,v 1.6 1999/08/27 23:15:33 peter Exp $ # Conditional move--don't replace an existing file. diff --git a/bin/sh/funcs/dirs b/bin/sh/funcs/dirs index a5d3c8e7eeffc..83916f553faaf 100644 --- a/bin/sh/funcs/dirs +++ b/bin/sh/funcs/dirs @@ -33,7 +33,7 @@ # SUCH DAMAGE. # # @(#)dirs 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/dirs,v 1.6 1999/08/27 23:15:34 peter Exp $ # pushd, popd, and dirs --- written by Chris Bertin # Pixel Computer Inc. ...!wjh12!pixel!pixutl!chris diff --git a/bin/sh/funcs/kill b/bin/sh/funcs/kill index 7455571f8b982..d5ea3536884fb 100644 --- a/bin/sh/funcs/kill +++ b/bin/sh/funcs/kill @@ -33,7 +33,7 @@ # SUCH DAMAGE. # # @(#)kill 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/kill,v 1.6 1999/08/27 23:15:34 peter Exp $ # Convert job names to process ids and then run /bin/kill. diff --git a/bin/sh/funcs/login b/bin/sh/funcs/login index 7a6fc855bfc2e..d8f5ae29dad53 100644 --- a/bin/sh/funcs/login +++ b/bin/sh/funcs/login @@ -33,7 +33,7 @@ # SUCH DAMAGE. # # @(#)login 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/login,v 1.6 1999/08/27 23:15:34 peter Exp $ # replaces the login builtin in the BSD shell login () exec login "$@" diff --git a/bin/sh/funcs/newgrp b/bin/sh/funcs/newgrp index fd8e5d6ee5a73..cbb0b3acdcabf 100644 --- a/bin/sh/funcs/newgrp +++ b/bin/sh/funcs/newgrp @@ -33,6 +33,6 @@ # SUCH DAMAGE. # # @(#)newgrp 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/newgrp,v 1.6 1999/08/27 23:15:34 peter Exp $ newgrp() exec newgrp "$@" diff --git a/bin/sh/funcs/popd b/bin/sh/funcs/popd index e0be35a13a79c..fb0d4fab159e6 100644 --- a/bin/sh/funcs/popd +++ b/bin/sh/funcs/popd @@ -33,7 +33,7 @@ # SUCH DAMAGE. # # @(#)popd 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/popd,v 1.6 1999/08/27 23:15:35 peter Exp $ # pushd, popd, and dirs --- written by Chris Bertin # Pixel Computer Inc. ...!wjh12!pixel!pixutl!chris diff --git a/bin/sh/funcs/pushd b/bin/sh/funcs/pushd index d60ede2cbbccb..94325e9fae8c2 100644 --- a/bin/sh/funcs/pushd +++ b/bin/sh/funcs/pushd @@ -33,7 +33,7 @@ # SUCH DAMAGE. # # @(#)pushd 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/pushd,v 1.6 1999/08/27 23:15:35 peter Exp $ # pushd, popd, and dirs --- written by Chris Bertin # Pixel Computer Inc. ...!wjh12!pixel!pixutl!chris diff --git a/bin/sh/funcs/suspend b/bin/sh/funcs/suspend index f06e12ff0575b..69817cceec459 100644 --- a/bin/sh/funcs/suspend +++ b/bin/sh/funcs/suspend @@ -33,7 +33,7 @@ # SUCH DAMAGE. # # @(#)suspend 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/funcs/suspend,v 1.6 1999/08/27 23:15:35 peter Exp $ suspend() { local - diff --git a/bin/sh/histedit.c b/bin/sh/histedit.c index 798118b90a61b..4ab6efdca8bd4 100644 --- a/bin/sh/histedit.c +++ b/bin/sh/histedit.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)histedit.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/histedit.c,v 1.13 1999/08/27 23:15:13 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/init.h b/bin/sh/init.h index 366b8a3f376d3..96788b581fd95 100644 --- a/bin/sh/init.h +++ b/bin/sh/init.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)init.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/init.h,v 1.6 1999/08/27 23:15:13 peter Exp $ */ void init __P((void)); diff --git a/bin/sh/input.c b/bin/sh/input.c index d75dfa4d7cc37..f49f148fd9d28 100644 --- a/bin/sh/input.c +++ b/bin/sh/input.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)input.c 8.3 (Berkeley) 6/9/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/input.c,v 1.14 1999/11/29 19:10:59 cracauer Exp $"; #endif /* not lint */ #include /* defines BUFSIZ */ diff --git a/bin/sh/input.h b/bin/sh/input.h index 16d7244cd4e75..97eaa600e70b4 100644 --- a/bin/sh/input.h +++ b/bin/sh/input.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)input.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/input.h,v 1.7 1999/08/27 23:15:14 peter Exp $ */ /* PEOF (the end of file marker) is defined in syntax.h */ diff --git a/bin/sh/jobs.c b/bin/sh/jobs.c index 72a7bd2bf5740..42ef790b1ad4a 100644 --- a/bin/sh/jobs.c +++ b/bin/sh/jobs.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)jobs.c 8.5 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/jobs.c,v 1.27 1999/11/29 19:11:00 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/jobs.h b/bin/sh/jobs.h index e8274b08f0ffe..e42b101327eaf 100644 --- a/bin/sh/jobs.h +++ b/bin/sh/jobs.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)jobs.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/jobs.h,v 1.12 1999/08/27 23:15:14 peter Exp $ */ /* Mode argument to forkshell. Don't change FORK_FG or FORK_BG. */ diff --git a/bin/sh/machdep.h b/bin/sh/machdep.h index 20aadd04180a2..ef431bca61b05 100644 --- a/bin/sh/machdep.h +++ b/bin/sh/machdep.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)machdep.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/machdep.h,v 1.6 1999/08/27 23:15:15 peter Exp $ */ /* diff --git a/bin/sh/mail.c b/bin/sh/mail.c index 826e89a31e8f4..5be370f710bae 100644 --- a/bin/sh/mail.c +++ b/bin/sh/mail.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)mail.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/mail.c,v 1.9 1999/08/27 23:15:15 peter Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/mail.h b/bin/sh/mail.h index 319796b13eef9..87757ea3cc0dd 100644 --- a/bin/sh/mail.h +++ b/bin/sh/mail.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)mail.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/mail.h,v 1.6 1999/08/27 23:15:15 peter Exp $ */ void chkmail __P((int)); diff --git a/bin/sh/main.c b/bin/sh/main.c index 0587161614c9e..55d2bcf1b70c6 100644 --- a/bin/sh/main.c +++ b/bin/sh/main.c @@ -45,7 +45,7 @@ static char const copyright[] = static char sccsid[] = "@(#)main.c 8.6 (Berkeley) 5/28/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/main.c,v 1.18 1999/11/29 19:11:00 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/main.h b/bin/sh/main.h index 3dc3dd77c4d70..a6573a6f895c7 100644 --- a/bin/sh/main.h +++ b/bin/sh/main.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)main.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/main.h,v 1.6 1999/08/27 23:15:16 peter Exp $ */ extern int rootpid; /* pid of main shell */ diff --git a/bin/sh/memalloc.c b/bin/sh/memalloc.c index b2155ffaa1d92..870ba4a8dd831 100644 --- a/bin/sh/memalloc.c +++ b/bin/sh/memalloc.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)memalloc.c 8.3 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/memalloc.c,v 1.15 1999/08/27 23:15:16 peter Exp $"; #endif /* not lint */ #include "shell.h" diff --git a/bin/sh/memalloc.h b/bin/sh/memalloc.h index ab53a833e41ad..2a3611a72298f 100644 --- a/bin/sh/memalloc.h +++ b/bin/sh/memalloc.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)memalloc.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/memalloc.h,v 1.6 1999/08/27 23:15:17 peter Exp $ */ struct stackmark { diff --git a/bin/sh/miscbltin.c b/bin/sh/miscbltin.c index bb602f6a68af8..ffc84d39850b8 100644 --- a/bin/sh/miscbltin.c +++ b/bin/sh/miscbltin.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)miscbltin.c 8.4 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/miscbltin.c,v 1.22 1999/10/09 20:56:06 green Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/mkbuiltins b/bin/sh/mkbuiltins index 89f50d279b92a..e397f0ad203a0 100755 --- a/bin/sh/mkbuiltins +++ b/bin/sh/mkbuiltins @@ -35,7 +35,7 @@ # SUCH DAMAGE. # # @(#)mkbuiltins 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/mkbuiltins,v 1.8 1999/08/27 23:15:18 peter Exp $ temp=/tmp/ka$$ havejobs=0 diff --git a/bin/sh/mkinit.c b/bin/sh/mkinit.c index b8f8ffbe9cc8c..81735afaba5cb 100644 --- a/bin/sh/mkinit.c +++ b/bin/sh/mkinit.c @@ -45,7 +45,7 @@ static char const copyright[] = static char sccsid[] = "@(#)mkinit.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/mkinit.c,v 1.14 1999/11/29 19:11:00 cracauer Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/mknodes.c b/bin/sh/mknodes.c index 007cb3247b2f0..3396ea9ffac16 100644 --- a/bin/sh/mknodes.c +++ b/bin/sh/mknodes.c @@ -45,7 +45,7 @@ static char const copyright[] = static char sccsid[] = "@(#)mknodes.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/mknodes.c,v 1.11 1999/11/29 19:11:01 cracauer Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/mksyntax.c b/bin/sh/mksyntax.c index 3f7f8cbfd63dc..39f7ddc72860e 100644 --- a/bin/sh/mksyntax.c +++ b/bin/sh/mksyntax.c @@ -45,7 +45,7 @@ static char const copyright[] = static char sccsid[] = "@(#)mksyntax.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/mksyntax.c,v 1.14 1999/12/15 11:46:32 cracauer Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/mktokens b/bin/sh/mktokens index 172bb23d49680..f14dadc8b8664 100644 --- a/bin/sh/mktokens +++ b/bin/sh/mktokens @@ -35,7 +35,7 @@ # SUCH DAMAGE. # # @(#)mktokens 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/mktokens,v 1.6 1999/08/27 23:15:19 peter Exp $ # The following is a list of tokens. The second column is nonzero if the # token marks the end of a list. The third column is the name to print in diff --git a/bin/sh/myhistedit.h b/bin/sh/myhistedit.h index e60bf5a43d0ce..719f2625782b9 100644 --- a/bin/sh/myhistedit.h +++ b/bin/sh/myhistedit.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)myhistedit.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/myhistedit.h,v 1.7 1999/08/27 23:15:19 peter Exp $ */ #include diff --git a/bin/sh/mystring.c b/bin/sh/mystring.c index 8013f7da6a7a9..f40dab6cc77e1 100644 --- a/bin/sh/mystring.c +++ b/bin/sh/mystring.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)mystring.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/mystring.c,v 1.10 1999/08/27 23:15:20 peter Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/mystring.h b/bin/sh/mystring.h index 4a78bd9de5ee6..09ebb4abded4b 100644 --- a/bin/sh/mystring.h +++ b/bin/sh/mystring.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)mystring.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/mystring.h,v 1.6 1999/08/27 23:15:20 peter Exp $ */ #include diff --git a/bin/sh/nodes.c.pat b/bin/sh/nodes.c.pat index 526cd88610d00..ca2f3d6c1ac84 100644 --- a/bin/sh/nodes.c.pat +++ b/bin/sh/nodes.c.pat @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)nodes.c.pat 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/nodes.c.pat,v 1.7 1999/08/27 23:15:20 peter Exp $ */ #include diff --git a/bin/sh/nodetypes b/bin/sh/nodetypes index ce82a35d266fa..ecb4fbe079bb9 100644 --- a/bin/sh/nodetypes +++ b/bin/sh/nodetypes @@ -34,7 +34,7 @@ # SUCH DAMAGE. # # @(#)nodetypes 8.2 (Berkeley) 5/4/95 -# $FreeBSD$ +# $FreeBSD: src/bin/sh/nodetypes,v 1.6 1999/08/27 23:15:20 peter Exp $ # This file describes the nodes used in parse trees. Unindented lines # contain a node type followed by a structure tag. Subsequent indented diff --git a/bin/sh/options.c b/bin/sh/options.c index 2bd55f5030e72..9a193f3717dc7 100644 --- a/bin/sh/options.c +++ b/bin/sh/options.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)options.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/options.c,v 1.15 1999/08/27 23:15:21 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/options.h b/bin/sh/options.h index e28370364df73..abaf677609cf0 100644 --- a/bin/sh/options.h +++ b/bin/sh/options.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)options.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/options.h,v 1.9 1999/08/27 23:15:21 peter Exp $ */ struct shparam { diff --git a/bin/sh/output.c b/bin/sh/output.c index 82ae3803774fe..98d9473a6bcf8 100644 --- a/bin/sh/output.c +++ b/bin/sh/output.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)output.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/output.c,v 1.10 1999/08/27 23:15:22 peter Exp $"; #endif /* not lint */ /* diff --git a/bin/sh/output.h b/bin/sh/output.h index f99db6b81b8bd..1657630240d36 100644 --- a/bin/sh/output.h +++ b/bin/sh/output.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)output.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/output.h,v 1.8 1999/08/27 23:15:22 peter Exp $ */ #ifndef OUTPUT_INCL diff --git a/bin/sh/parser.c b/bin/sh/parser.c index 2aa2665e01599..fcbff49720a57 100644 --- a/bin/sh/parser.c +++ b/bin/sh/parser.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)parser.c 8.7 (Berkeley) 5/16/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/parser.c,v 1.29 2000/02/15 08:00:11 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/parser.h b/bin/sh/parser.h index fdb2c342bbda3..60cc68556d363 100644 --- a/bin/sh/parser.h +++ b/bin/sh/parser.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)parser.h 8.3 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/parser.h,v 1.8 1999/08/27 23:15:23 peter Exp $ */ /* control characters in argument strings */ diff --git a/bin/sh/redir.c b/bin/sh/redir.c index 3ef30d0e01512..c390370642d7e 100644 --- a/bin/sh/redir.c +++ b/bin/sh/redir.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)redir.c 8.2 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/redir.c,v 1.12 1999/11/29 19:11:01 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/redir.h b/bin/sh/redir.h index 709ed12326f5e..849e09d8f64b1 100644 --- a/bin/sh/redir.h +++ b/bin/sh/redir.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)redir.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/redir.h,v 1.7 1999/08/27 23:15:23 peter Exp $ */ /* flags passed to redirect */ diff --git a/bin/sh/sh.1 b/bin/sh/sh.1 index e0f3af9874cf7..57b074549a0f8 100644 --- a/bin/sh/sh.1 +++ b/bin/sh/sh.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" from: @(#)sh.1 8.6 (Berkeley) 5/4/95 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/sh/sh.1,v 1.39 1999/12/15 16:12:32 cracauer Exp $ .\" .Dd May 5, 1995 .Dt SH 1 diff --git a/bin/sh/shell.h b/bin/sh/shell.h index 5939df776c2ab..fd48c3e4d3f28 100644 --- a/bin/sh/shell.h +++ b/bin/sh/shell.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)shell.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/shell.h,v 1.11 1999/08/27 23:15:24 peter Exp $ */ /* diff --git a/bin/sh/show.c b/bin/sh/show.c index b8c6f20b95fe0..b9163716a36ba 100644 --- a/bin/sh/show.c +++ b/bin/sh/show.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)show.c 8.3 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/show.c,v 1.11 1999/11/29 19:11:01 cracauer Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/show.h b/bin/sh/show.h index 1b6cbbc21296b..5d0b55f3f7e46 100644 --- a/bin/sh/show.h +++ b/bin/sh/show.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)show.h 1.1 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/show.h,v 1.7 1999/08/27 23:15:25 peter Exp $ */ void showtree __P((union node *)); diff --git a/bin/sh/trap.c b/bin/sh/trap.c index 233746e6b5fa0..fb50c57e004b4 100644 --- a/bin/sh/trap.c +++ b/bin/sh/trap.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)trap.c 8.5 (Berkeley) 6/5/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/trap.c,v 1.20 1999/08/27 23:15:25 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/trap.h b/bin/sh/trap.h index 2140c14604996..68a39a92dbd31 100644 --- a/bin/sh/trap.h +++ b/bin/sh/trap.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)trap.h 8.3 (Berkeley) 6/5/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/trap.h,v 1.9 1999/08/27 23:15:26 peter Exp $ */ extern int pendingsigs; diff --git a/bin/sh/var.c b/bin/sh/var.c index 056ae6fcfe592..a455cfb9f7b18 100644 --- a/bin/sh/var.c +++ b/bin/sh/var.c @@ -39,7 +39,7 @@ static char sccsid[] = "@(#)var.c 8.3 (Berkeley) 5/4/95"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sh/var.c,v 1.15 1999/08/27 23:15:26 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sh/var.h b/bin/sh/var.h index 1a215fc806db9..ccd0d803b41c9 100644 --- a/bin/sh/var.h +++ b/bin/sh/var.h @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * @(#)var.h 8.2 (Berkeley) 5/4/95 - * $FreeBSD$ + * $FreeBSD: src/bin/sh/var.h,v 1.8 1999/08/27 23:15:26 peter Exp $ */ /* diff --git a/bin/sleep/Makefile b/bin/sleep/Makefile index 4ff73308c45b6..d9b913dbd4227 100644 --- a/bin/sleep/Makefile +++ b/bin/sleep/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/sleep/Makefile,v 1.5 1999/08/27 23:15:37 peter Exp $ PROG= sleep diff --git a/bin/sleep/sleep.1 b/bin/sleep/sleep.1 index 41d6664dde878..0017ca0138466 100644 --- a/bin/sleep/sleep.1 +++ b/bin/sleep/sleep.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)sleep.1 8.3 (Berkeley) 4/18/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/sleep/sleep.1,v 1.15 2000/03/02 14:53:22 sheldonh Exp $ .\" .Dd April 18, 1994 .Dt SLEEP 1 diff --git a/bin/sleep/sleep.c b/bin/sleep/sleep.c index 008398759b1f8..514a2b7e3988d 100644 --- a/bin/sleep/sleep.c +++ b/bin/sleep/sleep.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)sleep.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sleep/sleep.c,v 1.9 1999/10/01 07:53:40 ru Exp $"; #endif /* not lint */ #include diff --git a/bin/stty/Makefile b/bin/stty/Makefile index 82b15eb7fcae5..ef3bf266b5858 100644 --- a/bin/stty/Makefile +++ b/bin/stty/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/stty/Makefile,v 1.5 1999/08/27 23:15:39 peter Exp $ PROG= stty SRCS= cchar.c gfmt.c key.c modes.c print.c stty.c util.c diff --git a/bin/stty/cchar.c b/bin/stty/cchar.c index 847cf749e0ac6..6f00653ce072e 100644 --- a/bin/stty/cchar.c +++ b/bin/stty/cchar.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)cchar.c 8.5 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/stty/cchar.c,v 1.9 1999/08/27 23:15:40 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/stty/extern.h b/bin/stty/extern.h index 27869f852dfe9..b02a03c648b54 100644 --- a/bin/stty/extern.h +++ b/bin/stty/extern.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)extern.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/stty/extern.h,v 1.5 1999/08/27 23:15:40 peter Exp $ */ int c_cchars __P((const void *, const void *)); diff --git a/bin/stty/gfmt.c b/bin/stty/gfmt.c index b34a1179f4756..12adcb22bac8e 100644 --- a/bin/stty/gfmt.c +++ b/bin/stty/gfmt.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)gfmt.c 8.6 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/stty/gfmt.c,v 1.10 1999/08/27 23:15:41 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/stty/key.c b/bin/stty/key.c index ba33a81c405fd..dd939fbf90f6a 100644 --- a/bin/stty/key.c +++ b/bin/stty/key.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)key.c 8.3 (Berkeley) 4/2/94"; #else static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/stty/key.c,v 1.11 1999/08/27 23:15:41 peter Exp $"; #endif #endif /* not lint */ diff --git a/bin/stty/modes.c b/bin/stty/modes.c index b1f333e1013f0..5995ff58aacb5 100644 --- a/bin/stty/modes.c +++ b/bin/stty/modes.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)modes.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/stty/modes.c,v 1.8 1999/08/27 23:15:41 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/stty/print.c b/bin/stty/print.c index a0149c24414fb..0fcd12e24ff6f 100644 --- a/bin/stty/print.c +++ b/bin/stty/print.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)print.c 8.6 (Berkeley) 4/16/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/stty/print.c,v 1.12 2000/01/29 16:44:08 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/stty/stty.1 b/bin/stty/stty.1 index 26732d2d6a691..5dadce2ced340 100644 --- a/bin/stty/stty.1 +++ b/bin/stty/stty.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)stty.1 8.4 (Berkeley) 4/18/94 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/stty/stty.1,v 1.13 2000/03/01 10:43:07 sheldonh Exp $ .\" .Dd April 18, 1994 .Dt STTY 1 diff --git a/bin/stty/stty.c b/bin/stty/stty.c index 3b5913134656c..d9c16fd71a2f0 100644 --- a/bin/stty/stty.c +++ b/bin/stty/stty.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)stty.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/stty/stty.c,v 1.13 1999/08/27 23:15:42 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/stty/stty.h b/bin/stty/stty.h index e122979d799dc..5151d02885ab2 100644 --- a/bin/stty/stty.h +++ b/bin/stty/stty.h @@ -31,7 +31,7 @@ * SUCH DAMAGE. * * @(#)stty.h 8.1 (Berkeley) 5/31/93 - * $FreeBSD$ + * $FreeBSD: src/bin/stty/stty.h,v 1.5 1999/08/27 23:15:43 peter Exp $ */ #include diff --git a/bin/stty/util.c b/bin/stty/util.c index b99e83f67d96e..7a696f01f420b 100644 --- a/bin/stty/util.c +++ b/bin/stty/util.c @@ -36,7 +36,7 @@ static char sccsid[] = "@(#)util.c 8.3 (Berkeley) 4/2/94"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/stty/util.c,v 1.8 1999/08/27 23:15:43 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/sync/Makefile b/bin/sync/Makefile index 9698a64dcd0d7..8566d2cc8f64c 100644 --- a/bin/sync/Makefile +++ b/bin/sync/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/sync/Makefile,v 1.6 1999/08/27 23:15:44 peter Exp $ PROG= sync MAN8= sync.8 diff --git a/bin/sync/sync.8 b/bin/sync/sync.8 index 36b017f9edc49..18325dce29f86 100644 --- a/bin/sync/sync.8 +++ b/bin/sync/sync.8 @@ -30,7 +30,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)sync.8 8.1 (Berkeley) 5/31/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/sync/sync.8,v 1.8 1999/08/27 23:15:45 peter Exp $ .\" .Dd May 31, 1993 .Dt SYNC 8 diff --git a/bin/sync/sync.c b/bin/sync/sync.c index 6fe3160227021..fe7d221c1b4e5 100644 --- a/bin/sync/sync.c +++ b/bin/sync/sync.c @@ -42,7 +42,7 @@ static char const copyright[] = static char sccsid[] = "@(#)sync.c 8.1 (Berkeley) 5/31/93"; #endif static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/sync/sync.c,v 1.9 1999/08/27 23:15:45 peter Exp $"; #endif /* not lint */ #include diff --git a/bin/test/Makefile b/bin/test/Makefile index c1bc62c5fc6eb..c26708ffadaaa 100644 --- a/bin/test/Makefile +++ b/bin/test/Makefile @@ -1,5 +1,5 @@ # @(#)Makefile 8.1 (Berkeley) 5/31/93 -# $FreeBSD$ +# $FreeBSD: src/bin/test/Makefile,v 1.6 1999/08/27 23:15:46 peter Exp $ PROG= test LINKS= ${BINDIR}/test ${BINDIR}/[ diff --git a/bin/test/TEST.README b/bin/test/TEST.README index f291953749680..d4c5a65b4cfaa 100644 --- a/bin/test/TEST.README +++ b/bin/test/TEST.README @@ -1,4 +1,4 @@ -# $FreeBSD$ +# $FreeBSD: src/bin/test/TEST.README,v 1.4 1999/08/27 23:15:47 peter Exp $ OS/shell syntax error failed -------------------------------------------------------------------- diff --git a/bin/test/TEST.csh b/bin/test/TEST.csh index afa1c91f158a2..f3e0237926d10 100644 --- a/bin/test/TEST.csh +++ b/bin/test/TEST.csh @@ -1,5 +1,5 @@ # @(#)TEST.csh 5.2 (Berkeley) 4/30/93 -# $FreeBSD$ +# $FreeBSD: src/bin/test/TEST.csh,v 1.6 1999/08/27 23:15:47 peter Exp $ #alias t '/usr/src/bin/test/obj/test \!*; echo $status' alias t '/bin/test \!*; echo $status' diff --git a/bin/test/TEST.sh b/bin/test/TEST.sh index 148cba25624ab..7273d13c37192 100644 --- a/bin/test/TEST.sh +++ b/bin/test/TEST.sh @@ -26,7 +26,7 @@ # # TEST.sh - check if test(1) or builtin test works # -# $FreeBSD$ +# $FreeBSD: src/bin/test/TEST.sh,v 1.6 1999/08/27 23:15:48 peter Exp $ # force a specified test program, e.g. `env test=/bin/test sh TEST.sh' : ${test=test} diff --git a/bin/test/test.1 b/bin/test/test.1 index da9686bc58f17..fb9a1a5bb2cba 100644 --- a/bin/test/test.1 +++ b/bin/test/test.1 @@ -33,7 +33,7 @@ .\" SUCH DAMAGE. .\" .\" @(#)test.1 8.1 (Berkeley) 5/31/93 -.\" $FreeBSD$ +.\" $FreeBSD: src/bin/test/test.1,v 1.11 2000/03/01 10:43:09 sheldonh Exp $ .\" .Dd May 31, 1993 .Dt TEST 1 diff --git a/bin/test/test.c b/bin/test/test.c index c9df4e3cb758c..9d53256a78460 100644 --- a/bin/test/test.c +++ b/bin/test/test.c @@ -12,7 +12,7 @@ #ifndef lint static const char rcsid[] = - "$FreeBSD$"; + "$FreeBSD: src/bin/test/test.c,v 1.29 1999/12/28 09:34:57 sheldonh Exp $"; #endif /* not lint */ #include diff --git a/contrib/amd/FREEBSD-Xlist b/contrib/amd/FREEBSD-Xlist index 2cfa5cabcc8fb..b178dea8277be 100644 --- a/contrib/amd/FREEBSD-Xlist +++ b/contrib/amd/FREEBSD-Xlist @@ -1,4 +1,4 @@ -$FreeBSD$ +$FreeBSD: src/contrib/amd/FREEBSD-Xlist,v 1.1 1999/09/18 09:25:20 obrien Exp $ *Makefile.* *README.autofs *aux diff --git a/contrib/amd/FREEBSD-upgrade b/contrib/amd/FREEBSD-upgrade index 618e962ca0679..ecf348fda05e6 100644 --- a/contrib/amd/FREEBSD-upgrade +++ b/contrib/amd/FREEBSD-upgrade @@ -1,5 +1,5 @@ # ex:ts=8 -$FreeBSD$ +$FreeBSD: src/contrib/amd/FREEBSD-upgrade,v 1.11 1999/11/05 11:59:47 obrien Exp $ AMD (am-utils) 6.0.3s1 originals can be found at: ftp://shekel.mcl.cs.columbia.edu/pub/am-utils/ diff --git a/contrib/amd/amd/amd.8 b/contrib/amd/amd/amd.8 index 93a9226421f30..60eb2fa782db4 100644 --- a/contrib/amd/amd/amd.8 +++ b/contrib/amd/amd/amd.8 @@ -39,7 +39,7 @@ .\" %W% (Berkeley) %G% .\" .\" $Id: amd.8,v 1.3 1999/09/30 21:01:29 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/amd/amd.8,v 1.6 2000/03/01 10:48:31 nik Exp $ .\" .Dd April 19, 1994 .Dt AMD 8 diff --git a/contrib/amd/amd/amd.c b/contrib/amd/amd/amd.c index 07022e7de4e69..028f6c645575a 100644 --- a/contrib/amd/amd/amd.c +++ b/contrib/amd/amd/amd.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: amd.c,v 1.6 1999/09/30 21:01:29 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/amd/amd.c,v 1.6 1999/11/05 11:58:05 obrien Exp $ * */ diff --git a/contrib/amd/amd/amq_subr.c b/contrib/amd/amd/amq_subr.c index 4fb0541772e0f..50fd578ca4093 100644 --- a/contrib/amd/amd/amq_subr.c +++ b/contrib/amd/amd/amq_subr.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: amq_subr.c,v 1.5 1999/08/24 21:31:06 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/amd/amq_subr.c,v 1.5 1999/09/15 05:45:13 obrien Exp $ * */ /* diff --git a/contrib/amd/amd/get_args.c b/contrib/amd/amd/get_args.c index a5f5a4bfca90b..5d29e8d89bbf0 100644 --- a/contrib/amd/amd/get_args.c +++ b/contrib/amd/amd/get_args.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: get_args.c,v 1.4 1999/09/30 21:01:31 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/amd/get_args.c,v 1.5 1999/11/05 11:58:05 obrien Exp $ * */ diff --git a/contrib/amd/amd/srvr_nfs.c b/contrib/amd/amd/srvr_nfs.c index b5425bf7a724d..2129222852f9e 100644 --- a/contrib/amd/amd/srvr_nfs.c +++ b/contrib/amd/amd/srvr_nfs.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: srvr_nfs.c,v 1.5 1999/09/08 23:36:39 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/amd/srvr_nfs.c,v 1.4 1999/09/15 05:45:13 obrien Exp $ * */ diff --git a/contrib/amd/amq/amq.8 b/contrib/amd/amq/amq.8 index c44f036262054..99c4e9e658983 100644 --- a/contrib/amd/amq/amq.8 +++ b/contrib/amd/amq/amq.8 @@ -39,7 +39,7 @@ .\" %W% (Berkeley) %G% .\" .\" $Id: amq.8,v 1.2 1999/01/10 21:53:58 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/amq/amq.8,v 1.5 1999/09/15 05:45:14 obrien Exp $ .\" .Dd March 16, 1991 .Dt AMQ 8 diff --git a/contrib/amd/amq/amq.c b/contrib/amd/amq/amq.c index 98711ebe73929..22ec8547d282e 100644 --- a/contrib/amd/amq/amq.c +++ b/contrib/amd/amq/amq.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: amq.c,v 1.6 1999/09/08 23:36:40 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/amq/amq.c,v 1.5 1999/09/15 05:45:14 obrien Exp $ * */ diff --git a/contrib/amd/amq/pawd.1 b/contrib/amd/amq/pawd.1 index 6713907ac1089..96315ddb29faa 100644 --- a/contrib/amd/amq/pawd.1 +++ b/contrib/amd/amq/pawd.1 @@ -39,7 +39,7 @@ .\" %W% (Berkeley) %G% .\" .\" $Id: pawd.1,v 1.2 1998/09/05 06:56:36 obrien Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/amq/pawd.1,v 1.4 1999/09/15 05:45:14 obrien Exp $ .\" .Dd January 6, 1998 .Dt PAWD 1 diff --git a/contrib/amd/conf/nfs_prot/nfs_prot_freebsd2.h b/contrib/amd/conf/nfs_prot/nfs_prot_freebsd2.h index e719e9985cd4b..447143d1ff388 100644 --- a/contrib/amd/conf/nfs_prot/nfs_prot_freebsd2.h +++ b/contrib/amd/conf/nfs_prot/nfs_prot_freebsd2.h @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: nfs_prot_freebsd2.h,v 1.2 1999/01/10 21:54:14 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/conf/nfs_prot/nfs_prot_freebsd2.h,v 1.4 1999/09/15 05:45:14 obrien Exp $ * */ diff --git a/contrib/amd/conf/nfs_prot/nfs_prot_freebsd3.h b/contrib/amd/conf/nfs_prot/nfs_prot_freebsd3.h index 29ce9496093e2..9f7c1ca3e6220 100644 --- a/contrib/amd/conf/nfs_prot/nfs_prot_freebsd3.h +++ b/contrib/amd/conf/nfs_prot/nfs_prot_freebsd3.h @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: nfs_prot_freebsd3.h,v 1.4 1999/03/30 17:22:54 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/conf/nfs_prot/nfs_prot_freebsd3.h,v 1.7 1999/09/15 05:45:14 obrien Exp $ * */ diff --git a/contrib/amd/fixmount/fixmount.8 b/contrib/amd/fixmount/fixmount.8 index 14915affd7dfe..bba73cc9094ef 100644 --- a/contrib/amd/fixmount/fixmount.8 +++ b/contrib/amd/fixmount/fixmount.8 @@ -39,7 +39,7 @@ .\" %W% (Berkeley) %G% .\" .\" $Id: fixmount.8,v 1.2 1999/01/10 21:54:26 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/fixmount/fixmount.8,v 1.5 1999/09/15 05:45:14 obrien Exp $ .\" .Dd February 26, 1993 .Dt FIXMOUNT 8 diff --git a/contrib/amd/fixmount/fixmount.c b/contrib/amd/fixmount/fixmount.c index 628e645fc0d06..8a8481111d6c4 100644 --- a/contrib/amd/fixmount/fixmount.c +++ b/contrib/amd/fixmount/fixmount.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: fixmount.c,v 1.4 1999/02/04 07:24:42 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/fixmount/fixmount.c,v 1.5 1999/09/15 05:45:14 obrien Exp $ * */ diff --git a/contrib/amd/fsinfo/fsinfo.8 b/contrib/amd/fsinfo/fsinfo.8 index 2bc2d51044c45..1f603638537eb 100644 --- a/contrib/amd/fsinfo/fsinfo.8 +++ b/contrib/amd/fsinfo/fsinfo.8 @@ -34,7 +34,7 @@ .\" .\" from: @(#)fsinfo.8 8.1 (Berkeley) 6/28/93 .\" $Id: fsinfo.8,v 1.2 1999/01/10 21:54:28 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/fsinfo/fsinfo.8,v 1.4 1999/09/15 05:45:15 obrien Exp $ .\" .Dd June 26, 1999 .Dt FSINFO 8 diff --git a/contrib/amd/fsinfo/fsinfo.c b/contrib/amd/fsinfo/fsinfo.c index 111d205f63f35..35fe24cd7ffd4 100644 --- a/contrib/amd/fsinfo/fsinfo.c +++ b/contrib/amd/fsinfo/fsinfo.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: fsinfo.c,v 1.4 1999/02/04 07:24:44 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/fsinfo/fsinfo.c,v 1.4 1999/09/15 05:45:15 obrien Exp $ * */ diff --git a/contrib/amd/hlfsd/hlfsd.8 b/contrib/amd/hlfsd/hlfsd.8 index 77a2b8077c008..8d1bb4810c03a 100644 --- a/contrib/amd/hlfsd/hlfsd.8 +++ b/contrib/amd/hlfsd/hlfsd.8 @@ -37,7 +37,7 @@ .\" SUCH DAMAGE. .\" .\" $Id: hlfsd.8,v 1.2 1999/01/10 21:54:32 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/hlfsd/hlfsd.8,v 1.5 1999/09/15 05:45:15 obrien Exp $ .\" .\" HLFSD was written at Columbia University Computer Science Department, by .\" Erez Zadok and Alexander Dupuy diff --git a/contrib/amd/hlfsd/hlfsd.c b/contrib/amd/hlfsd/hlfsd.c index dc5b2ace0713d..61f9dd0ccc85f 100644 --- a/contrib/amd/hlfsd/hlfsd.c +++ b/contrib/amd/hlfsd/hlfsd.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: hlfsd.c,v 1.5 1999/09/08 23:36:51 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/hlfsd/hlfsd.c,v 1.5 1999/09/15 05:45:15 obrien Exp $ * * HLFSD was written at Columbia University Computer Science Department, by * Erez Zadok and Alexander Dupuy diff --git a/contrib/amd/hlfsd/homedir.c b/contrib/amd/hlfsd/homedir.c index 582acc831a9df..8abe9d606cd5a 100644 --- a/contrib/amd/hlfsd/homedir.c +++ b/contrib/amd/hlfsd/homedir.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: homedir.c,v 1.4 1999/01/13 23:31:19 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/hlfsd/homedir.c,v 1.4 1999/09/15 05:45:15 obrien Exp $ * * HLFSD was written at Columbia University Computer Science Department, by * Erez Zadok and Alexander Dupuy diff --git a/contrib/amd/include/am_defs.h b/contrib/amd/include/am_defs.h index 36c695eada4c3..854f8f291dd3b 100644 --- a/contrib/amd/include/am_defs.h +++ b/contrib/amd/include/am_defs.h @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: am_defs.h,v 1.11 1999/09/18 08:38:05 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/include/am_defs.h,v 1.8 1999/11/05 11:58:03 obrien Exp $ * */ diff --git a/contrib/amd/libamu/mount_fs.c b/contrib/amd/libamu/mount_fs.c index 1a4deeee07d57..21ba86cf26d98 100644 --- a/contrib/amd/libamu/mount_fs.c +++ b/contrib/amd/libamu/mount_fs.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: mount_fs.c,v 1.8 1999/09/18 08:38:06 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/libamu/mount_fs.c,v 1.4 1999/09/23 05:36:01 obrien Exp $ * */ diff --git a/contrib/amd/mk-amd-map/mk-amd-map.8 b/contrib/amd/mk-amd-map/mk-amd-map.8 index 99f93e122be50..6e69aef6c7a2d 100644 --- a/contrib/amd/mk-amd-map/mk-amd-map.8 +++ b/contrib/amd/mk-amd-map/mk-amd-map.8 @@ -34,7 +34,7 @@ .\" .\" from: @(#)mk-amd-map.8 8.1 (Berkeley) 6/28/93 .\" $Id: mk-amd-map.8,v 1.2 1999/01/10 21:54:41 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/mk-amd-map/mk-amd-map.8,v 1.3 1999/09/15 05:45:16 obrien Exp $ .\" .Dd June 28, 1993 .Dt MK-AMD-MAP 8 diff --git a/contrib/amd/mk-amd-map/mk-amd-map.c b/contrib/amd/mk-amd-map/mk-amd-map.c index 755d5bf22b4ce..38760575d6113 100644 --- a/contrib/amd/mk-amd-map/mk-amd-map.c +++ b/contrib/amd/mk-amd-map/mk-amd-map.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: mk-amd-map.c,v 1.4 1999/02/04 07:24:50 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/mk-amd-map/mk-amd-map.c,v 1.7 1999/09/15 05:45:16 obrien Exp $ */ /* diff --git a/contrib/amd/scripts/amd.conf.5 b/contrib/amd/scripts/amd.conf.5 index 2142622a4585a..585463975d070 100644 --- a/contrib/amd/scripts/amd.conf.5 +++ b/contrib/amd/scripts/amd.conf.5 @@ -39,7 +39,7 @@ .\" %W% (Berkeley) %G% .\" .\" $Id: amd.conf.5,v 1.3 1999/03/30 17:23:08 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/scripts/amd.conf.5,v 1.9 1999/09/15 05:45:17 obrien Exp $ .\" .Dd April 7, 1997 .Dt AMD.CONF 5 diff --git a/contrib/amd/wire-test/wire-test.8 b/contrib/amd/wire-test/wire-test.8 index dfb8a862a2bb9..14a7b3fd7ff80 100644 --- a/contrib/amd/wire-test/wire-test.8 +++ b/contrib/amd/wire-test/wire-test.8 @@ -39,7 +39,7 @@ .\" %W% (Berkeley) %G% .\" .\" $Id: wire-test.8,v 1.2 1999/01/10 21:54:44 ezk Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/amd/wire-test/wire-test.8,v 1.3 1999/09/15 05:45:17 obrien Exp $ .\" .Dd February 26, 1993 .Dt WIRE-TEST 8 diff --git a/contrib/amd/wire-test/wire-test.c b/contrib/amd/wire-test/wire-test.c index c55764707e159..d4ff1214631f2 100644 --- a/contrib/amd/wire-test/wire-test.c +++ b/contrib/amd/wire-test/wire-test.c @@ -39,7 +39,7 @@ * %W% (Berkeley) %G% * * $Id: wire-test.c,v 1.4 1999/02/04 07:24:54 ezk Exp $ - * $FreeBSD$ + * $FreeBSD: src/contrib/amd/wire-test/wire-test.c,v 1.5 1999/09/15 05:45:17 obrien Exp $ * */ diff --git a/contrib/awk/FREEBSD-upgrade b/contrib/awk/FREEBSD-upgrade index 97e4270e182c5..0340b3510c71d 100644 --- a/contrib/awk/FREEBSD-upgrade +++ b/contrib/awk/FREEBSD-upgrade @@ -1,4 +1,4 @@ -$FreeBSD$ +$FreeBSD: src/contrib/awk/FREEBSD-upgrade,v 1.6 1999/09/27 09:09:08 sheldonh Exp $ Import of GNU awk 3.0.4 diff --git a/contrib/awk/awk.h b/contrib/awk/awk.h index 621a981095743..1a9486245511f 100644 --- a/contrib/awk/awk.h +++ b/contrib/awk/awk.h @@ -22,7 +22,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * - * $FreeBSD$ + * $FreeBSD: src/contrib/awk/awk.h,v 1.5 1999/09/27 08:56:57 sheldonh Exp $ */ /* ------------------------------ Includes ------------------------------ */ diff --git a/contrib/awk/builtin.c b/contrib/awk/builtin.c index 3de6f2ecddd04..20d6d64aa170d 100644 --- a/contrib/awk/builtin.c +++ b/contrib/awk/builtin.c @@ -22,7 +22,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * - * $FreeBSD$ + * $FreeBSD: src/contrib/awk/builtin.c,v 1.7 1999/12/23 18:24:31 sheldonh Exp $ */ diff --git a/contrib/awk/doc/awk.1 b/contrib/awk/doc/awk.1 index 807f79f156b98..3f52141b2c96d 100644 --- a/contrib/awk/doc/awk.1 +++ b/contrib/awk/doc/awk.1 @@ -1,4 +1,4 @@ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/awk/doc/awk.1,v 1.5 1999/09/27 08:57:04 sheldonh Exp $ .ds PX \s-1POSIX\s+1 .ds UX \s-1UNIX\s+1 .ds AN \s-1ANSI\s+1 diff --git a/contrib/awk/eval.c b/contrib/awk/eval.c index 37c5fef867894..37d738a2ea288 100644 --- a/contrib/awk/eval.c +++ b/contrib/awk/eval.c @@ -22,7 +22,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * - * $FreeBSD$ + * $FreeBSD: src/contrib/awk/eval.c,v 1.4 1999/09/27 08:56:57 sheldonh Exp $ */ #include "awk.h" diff --git a/contrib/awk/field.c b/contrib/awk/field.c index 72cbd78e8c204..bba847aa64abb 100644 --- a/contrib/awk/field.c +++ b/contrib/awk/field.c @@ -22,7 +22,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * - * $FreeBSD$ + * $FreeBSD: src/contrib/awk/field.c,v 1.4 1999/09/27 08:56:57 sheldonh Exp $ */ #include "awk.h" diff --git a/contrib/awk/io.c b/contrib/awk/io.c index 0a24f8af30ce7..460928630b010 100644 --- a/contrib/awk/io.c +++ b/contrib/awk/io.c @@ -22,7 +22,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * - * $FreeBSD$ + * $FreeBSD: src/contrib/awk/io.c,v 1.4 1999/09/27 08:56:57 sheldonh Exp $ */ #include "awk.h" diff --git a/contrib/awk/main.c b/contrib/awk/main.c index 27452f00aed36..bb36f71996a09 100644 --- a/contrib/awk/main.c +++ b/contrib/awk/main.c @@ -22,7 +22,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * - * $FreeBSD$ + * $FreeBSD: src/contrib/awk/main.c,v 1.4 1999/09/27 08:56:57 sheldonh Exp $ */ #include "awk.h" diff --git a/contrib/awk/node.c b/contrib/awk/node.c index a8892a35678b3..1762a4339f478 100644 --- a/contrib/awk/node.c +++ b/contrib/awk/node.c @@ -22,7 +22,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * - * $FreeBSD$ + * $FreeBSD: src/contrib/awk/node.c,v 1.4 1999/09/27 08:56:57 sheldonh Exp $ */ #include "awk.h" diff --git a/contrib/bc/FREEBSD-upgrade b/contrib/bc/FREEBSD-upgrade index 6552a9c2b2036..b6bfc7b519746 100644 --- a/contrib/bc/FREEBSD-upgrade +++ b/contrib/bc/FREEBSD-upgrade @@ -1,4 +1,4 @@ -$FreeBSD$ +$FreeBSD: src/contrib/bc/FREEBSD-upgrade,v 1.5 2000/01/16 10:22:31 obrien Exp $ bc 1.0.5a originals can be found at: ftp://prep.ai.mit.edu/pub/gnu/ diff --git a/contrib/bc/bc/main.c b/contrib/bc/bc/main.c index bd4efcb959139..14e81e51514d9 100644 --- a/contrib/bc/bc/main.c +++ b/contrib/bc/bc/main.c @@ -24,7 +24,7 @@ Western Washington University Bellingham, WA 98226-9062 -$FreeBSD$ +$FreeBSD: src/contrib/bc/bc/main.c,v 1.4 2000/01/16 10:10:15 obrien Exp $ *************************************************************************/ diff --git a/contrib/bc/doc/dc.1 b/contrib/bc/doc/dc.1 index 856b6bb53c801..480a0d7c1c8a4 100644 --- a/contrib/bc/doc/dc.1 +++ b/contrib/bc/doc/dc.1 @@ -18,7 +18,7 @@ .\" along with this program; see the file COPYING. If not, write to .\" the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. .\" -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/bc/doc/dc.1,v 1.3 2000/01/16 10:14:50 obrien Exp $ .\" .TH DC 1 "1997-03-25" "GNU Project" .ds dc \fIdc\fP diff --git a/contrib/bind/bin/named-xfer/named-xfer.c b/contrib/bind/bin/named-xfer/named-xfer.c index d7db8869d47b8..de6bac1371673 100644 --- a/contrib/bind/bin/named-xfer/named-xfer.c +++ b/contrib/bind/bin/named-xfer/named-xfer.c @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/bind/bin/named-xfer/named-xfer.c,v 1.3 1999/11/30 02:52:51 peter Exp $ */ /* * The original version of named-xfer by Kevin Dunlap. * Completed and integrated with named by David Waitzman diff --git a/contrib/bind/bin/named/Makefile b/contrib/bind/bin/named/Makefile index 96a392725fb4e..9489cd808ff06 100644 --- a/contrib/bind/bin/named/Makefile +++ b/contrib/bind/bin/named/Makefile @@ -14,7 +14,7 @@ ## SOFTWARE. # $Id: Makefile,v 8.47 1999/08/26 18:42:31 vixie Exp $ -# $FreeBSD$ +# $FreeBSD: src/contrib/bind/bin/named/Makefile,v 1.3 1999/11/30 02:52:44 peter Exp $ DESTDIR= CC= cc diff --git a/contrib/bind/bin/nslookup/commands.l b/contrib/bind/bin/nslookup/commands.l index c480d46e52acd..b90192f68d38f 100644 --- a/contrib/bind/bin/nslookup/commands.l +++ b/contrib/bind/bin/nslookup/commands.l @@ -1,5 +1,5 @@ %{ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/bind/bin/nslookup/commands.l,v 1.4 1999/11/30 02:52:52 peter Exp $ */ /* * Copyright (c) 1985 * The Regents of the University of California. All rights reserved. diff --git a/contrib/bind/bin/nslookup/debug.c b/contrib/bind/bin/nslookup/debug.c index 7dac192e5cb02..07cd7b6998ac6 100644 --- a/contrib/bind/bin/nslookup/debug.c +++ b/contrib/bind/bin/nslookup/debug.c @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/bind/bin/nslookup/debug.c,v 1.3 1999/11/30 02:52:53 peter Exp $ */ /* * Copyright (c) 1985, 1989 * The Regents of the University of California. All rights reserved. diff --git a/contrib/bind/bin/nslookup/getinfo.c b/contrib/bind/bin/nslookup/getinfo.c index 673bad0a443bb..45dd2af7409e0 100644 --- a/contrib/bind/bin/nslookup/getinfo.c +++ b/contrib/bind/bin/nslookup/getinfo.c @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/bind/bin/nslookup/getinfo.c,v 1.3 1999/11/30 02:52:53 peter Exp $ */ /* * Copyright (c) 1985, 1989 * The Regents of the University of California. All rights reserved. diff --git a/contrib/bind/bin/nslookup/main.c b/contrib/bind/bin/nslookup/main.c index 454fe12b1c2af..132e1ceefda56 100644 --- a/contrib/bind/bin/nslookup/main.c +++ b/contrib/bind/bin/nslookup/main.c @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/bind/bin/nslookup/main.c,v 1.3 1999/11/30 02:52:53 peter Exp $ */ /* * Copyright (c) 1985, 1989 * The Regents of the University of California. All rights reserved. diff --git a/contrib/bind/doc/man/dig.1 b/contrib/bind/doc/man/dig.1 index 3e59b056c58c7..7f9f1ff3488d2 100644 --- a/contrib/bind/doc/man/dig.1 +++ b/contrib/bind/doc/man/dig.1 @@ -1,4 +1,4 @@ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/bind/doc/man/dig.1,v 1.3 1999/11/30 02:52:54 peter Exp $ .\" $Id: dig.1,v 8.4 1999/10/15 21:29:58 vixie Exp $ .\" .\" ++Copyright++ 1993 diff --git a/contrib/bind/doc/man/host.1 b/contrib/bind/doc/man/host.1 index 89611e4823fc0..01cf203f1c7a5 100644 --- a/contrib/bind/doc/man/host.1 +++ b/contrib/bind/doc/man/host.1 @@ -51,7 +51,7 @@ .\" - .\" --Copyright-- .\" $Id: host.1,v 8.2 1997/03/14 02:29:44 vixie Exp $ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/bind/doc/man/host.1,v 1.3 2000/01/02 11:13:23 obrien Exp $ .\" .Dd December 15, 1994 .Dt HOST @CMD_EXT_U@ diff --git a/contrib/bind/port/freebsd/include/port_after.h b/contrib/bind/port/freebsd/include/port_after.h index f6490babf1bcf..dc3083b7f3ca1 100644 --- a/contrib/bind/port/freebsd/include/port_after.h +++ b/contrib/bind/port/freebsd/include/port_after.h @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/bind/port/freebsd/include/port_after.h,v 1.6 1999/12/13 15:43:32 peter Exp $ */ #ifndef PORT_AFTER_H #define PORT_AFTER_H #define CAN_RECONNECT diff --git a/contrib/binutils/bfd/VERSION b/contrib/binutils/bfd/VERSION new file mode 100644 index 0000000000000..dbe590065479b --- /dev/null +++ b/contrib/binutils/bfd/VERSION @@ -0,0 +1 @@ +2.8.1 diff --git a/contrib/binutils/bfd/doc/bfd.texi b/contrib/binutils/bfd/doc/bfd.texi new file mode 100644 index 0000000000000..ea0ca9e56dc96 --- /dev/null +++ b/contrib/binutils/bfd/doc/bfd.texi @@ -0,0 +1,585 @@ +@section @code{typedef bfd} +A BFD has type @code{bfd}; objects of this type are the +cornerstone of any application using BFD. Using BFD +consists of making references though the BFD and to data in the BFD. + +Here is the structure that defines the type @code{bfd}. It +contains the major data about the file and pointers +to the rest of the data. +@* +. +@example +struct _bfd +@{ + /* The filename the application opened the BFD with. */ + CONST char *filename; + + /* A pointer to the target jump table. */ + const struct bfd_target *xvec; + + /* To avoid dragging too many header files into every file that + includes `@code{bfd.h}', IOSTREAM has been declared as a "char + *", and MTIME as a "long". Their correct types, to which they + are cast when used, are "FILE *" and "time_t". The iostream + is the result of an fopen on the filename. However, if the + BFD_IN_MEMORY flag is set, then iostream is actually a pointer + to a bfd_in_memory struct. */ + PTR iostream; + + /* Is the file descriptor being cached? That is, can it be closed as + needed, and re-opened when accessed later? */ + + boolean cacheable; + + /* Marks whether there was a default target specified when the + BFD was opened. This is used to select which matching algorithm + to use to choose the back end. */ + + boolean target_defaulted; + + /* The caching routines use these to maintain a + least-recently-used list of BFDs */ + + struct _bfd *lru_prev, *lru_next; + + /* When a file is closed by the caching routines, BFD retains + state information on the file here: */ + + file_ptr where; + + /* and here: (``once'' means at least once) */ + + boolean opened_once; + + /* Set if we have a locally maintained mtime value, rather than + getting it from the file each time: */ + + boolean mtime_set; + + /* File modified time, if mtime_set is true: */ + + long mtime; + + /* Reserved for an unimplemented file locking extension.*/ + + int ifd; + + /* The format which belongs to the BFD. (object, core, etc.) */ + + bfd_format format; + + /* The direction the BFD was opened with*/ + + enum bfd_direction @{no_direction = 0, + read_direction = 1, + write_direction = 2, + both_direction = 3@} direction; + + /* Format_specific flags*/ + + flagword flags; + + /* Currently my_archive is tested before adding origin to + anything. I believe that this can become always an add of + origin, with origin set to 0 for non archive files. */ + + file_ptr origin; + + /* Remember when output has begun, to stop strange things + from happening. */ + boolean output_has_begun; + + /* Pointer to linked list of sections*/ + struct sec *sections; + + /* The number of sections */ + unsigned int section_count; + + /* Stuff only useful for object files: + The start address. */ + bfd_vma start_address; + + /* Used for input and output*/ + unsigned int symcount; + + /* Symbol table for output BFD (with symcount entries) */ + struct symbol_cache_entry **outsymbols; + + /* Pointer to structure which contains architecture information*/ + const struct bfd_arch_info *arch_info; + + /* Stuff only useful for archives:*/ + PTR arelt_data; + struct _bfd *my_archive; /* The containing archive BFD. */ + struct _bfd *next; /* The next BFD in the archive. */ + struct _bfd *archive_head; /* The first BFD in the archive. */ + boolean has_armap; + + /* A chain of BFD structures involved in a link. */ + struct _bfd *link_next; + + /* A field used by _bfd_generic_link_add_archive_symbols. This will + be used only for archive elements. */ + int archive_pass; + + /* Used by the back end to hold private data. */ + + union + @{ + struct aout_data_struct *aout_data; + struct artdata *aout_ar_data; + struct _oasys_data *oasys_obj_data; + struct _oasys_ar_data *oasys_ar_data; + struct coff_tdata *coff_obj_data; + struct pe_tdata *pe_obj_data; + struct xcoff_tdata *xcoff_obj_data; + struct ecoff_tdata *ecoff_obj_data; + struct ieee_data_struct *ieee_data; + struct ieee_ar_data_struct *ieee_ar_data; + struct srec_data_struct *srec_data; + struct ihex_data_struct *ihex_data; + struct tekhex_data_struct *tekhex_data; + struct elf_obj_tdata *elf_obj_data; + struct nlm_obj_tdata *nlm_obj_data; + struct bout_data_struct *bout_data; + struct sun_core_struct *sun_core_data; + struct trad_core_struct *trad_core_data; + struct som_data_struct *som_data; + struct hpux_core_struct *hpux_core_data; + struct hppabsd_core_struct *hppabsd_core_data; + struct sgi_core_struct *sgi_core_data; + struct lynx_core_struct *lynx_core_data; + struct osf_core_struct *osf_core_data; + struct cisco_core_struct *cisco_core_data; + struct versados_data_struct *versados_data; + struct netbsd_core_struct *netbsd_core_data; + PTR any; + @} tdata; + + /* Used by the application to hold private data*/ + PTR usrdata; + + /* Where all the allocated stuff under this BFD goes. This is a + struct objalloc *, but we use PTR to avoid requiring the inclusion of + objalloc.h. */ + PTR memory; +@}; + +@end example +@section Error reporting +Most BFD functions return nonzero on success (check their +individual documentation for precise semantics). On an error, +they call @code{bfd_set_error} to set an error condition that callers +can check by calling @code{bfd_get_error}. +If that returns @code{bfd_error_system_call}, then check +@code{errno}. + +The easiest way to report a BFD error to the user is to +use @code{bfd_perror}. +@* +@subsection Type @code{bfd_error_type} +The values returned by @code{bfd_get_error} are defined by the +enumerated type @code{bfd_error_type}. +@* +. +@example +typedef enum bfd_error +@{ + bfd_error_no_error = 0, + bfd_error_system_call, + bfd_error_invalid_target, + bfd_error_wrong_format, + bfd_error_invalid_operation, + bfd_error_no_memory, + bfd_error_no_symbols, + bfd_error_no_armap, + bfd_error_no_more_archived_files, + bfd_error_malformed_archive, + bfd_error_file_not_recognized, + bfd_error_file_ambiguously_recognized, + bfd_error_no_contents, + bfd_error_nonrepresentable_section, + bfd_error_no_debug_section, + bfd_error_bad_value, + bfd_error_file_truncated, + bfd_error_file_too_big, + bfd_error_invalid_error_code +@} bfd_error_type; + +@end example +@findex bfd_get_error +@subsubsection @code{bfd_get_error} +@strong{Synopsis} +@example +bfd_error_type bfd_get_error (void); +@end example +@strong{Description}@* +Return the current BFD error condition. +@* +@findex bfd_set_error +@subsubsection @code{bfd_set_error} +@strong{Synopsis} +@example +void bfd_set_error (bfd_error_type error_tag); +@end example +@strong{Description}@* +Set the BFD error condition to be @var{error_tag}. +@* +@findex bfd_errmsg +@subsubsection @code{bfd_errmsg} +@strong{Synopsis} +@example +CONST char *bfd_errmsg (bfd_error_type error_tag); +@end example +@strong{Description}@* +Return a string describing the error @var{error_tag}, or +the system error if @var{error_tag} is @code{bfd_error_system_call}. +@* +@findex bfd_perror +@subsubsection @code{bfd_perror} +@strong{Synopsis} +@example +void bfd_perror (CONST char *message); +@end example +@strong{Description}@* +Print to the standard error stream a string describing the +last BFD error that occurred, or the last system error if +the last BFD error was a system call failure. If @var{message} +is non-NULL and non-empty, the error string printed is preceded +by @var{message}, a colon, and a space. It is followed by a newline. +@* +@subsection BFD error handler +Some BFD functions want to print messages describing the +problem. They call a BFD error handler function. This +function may be overriden by the program. + +The BFD error handler acts like printf. +@* +. +@example +typedef void (*bfd_error_handler_type) PARAMS ((const char *, ...)); + +@end example +@findex bfd_set_error_handler +@subsubsection @code{bfd_set_error_handler} +@strong{Synopsis} +@example +bfd_error_handler_type bfd_set_error_handler (bfd_error_handler_type); +@end example +@strong{Description}@* +Set the BFD error handler function. Returns the previous +function. +@* +@findex bfd_set_error_program_name +@subsubsection @code{bfd_set_error_program_name} +@strong{Synopsis} +@example +void bfd_set_error_program_name (const char *); +@end example +@strong{Description}@* +Set the program name to use when printing a BFD error. This +is printed before the error message followed by a colon and +space. The string must not be changed after it is passed to +this function. +@* +@section Symbols + +@* +@findex bfd_get_reloc_upper_bound +@subsubsection @code{bfd_get_reloc_upper_bound} +@strong{Synopsis} +@example +long bfd_get_reloc_upper_bound(bfd *abfd, asection *sect); +@end example +@strong{Description}@* +Return the number of bytes required to store the +relocation information associated with section @var{sect} +attached to bfd @var{abfd}. If an error occurs, return -1. +@* +@findex bfd_canonicalize_reloc +@subsubsection @code{bfd_canonicalize_reloc} +@strong{Synopsis} +@example +long bfd_canonicalize_reloc + (bfd *abfd, + asection *sec, + arelent **loc, + asymbol **syms); +@end example +@strong{Description}@* +Call the back end associated with the open BFD +@var{abfd} and translate the external form of the relocation +information attached to @var{sec} into the internal canonical +form. Place the table into memory at @var{loc}, which has +been preallocated, usually by a call to +@code{bfd_get_reloc_upper_bound}. Returns the number of relocs, or +-1 on error. + +The @var{syms} table is also needed for horrible internal magic +reasons. +@* +@findex bfd_set_reloc +@subsubsection @code{bfd_set_reloc} +@strong{Synopsis} +@example +void bfd_set_reloc + (bfd *abfd, asection *sec, arelent **rel, unsigned int count) +@end example +@strong{Description}@* +Set the relocation pointer and count within +section @var{sec} to the values @var{rel} and @var{count}. +The argument @var{abfd} is ignored. +@* +@findex bfd_set_file_flags +@subsubsection @code{bfd_set_file_flags} +@strong{Synopsis} +@example +boolean bfd_set_file_flags(bfd *abfd, flagword flags); +@end example +@strong{Description}@* +Set the flag word in the BFD @var{abfd} to the value @var{flags}. + +Possible errors are: +@itemize @bullet + +@item +@code{bfd_error_wrong_format} - The target bfd was not of object format. +@item +@code{bfd_error_invalid_operation} - The target bfd was open for reading. +@item +@code{bfd_error_invalid_operation} - +The flag word contained a bit which was not applicable to the +type of file. E.g., an attempt was made to set the @code{D_PAGED} bit +on a BFD format which does not support demand paging. +@end itemize +@* +@findex bfd_set_start_address +@subsubsection @code{bfd_set_start_address} +@strong{Synopsis} +@example +boolean bfd_set_start_address(bfd *abfd, bfd_vma vma); +@end example +@strong{Description}@* +Make @var{vma} the entry point of output BFD @var{abfd}. +@* +@strong{Returns}@* +Returns @code{true} on success, @code{false} otherwise. +@* +@findex bfd_get_mtime +@subsubsection @code{bfd_get_mtime} +@strong{Synopsis} +@example +long bfd_get_mtime(bfd *abfd); +@end example +@strong{Description}@* +Return the file modification time (as read from the file system, or +from the archive header for archive members). +@* +@findex bfd_get_size +@subsubsection @code{bfd_get_size} +@strong{Synopsis} +@example +long bfd_get_size(bfd *abfd); +@end example +@strong{Description}@* +Return the file size (as read from file system) for the file +associated with BFD @var{abfd}. + +The initial motivation for, and use of, this routine is not +so we can get the exact size of the object the BFD applies to, since +that might not be generally possible (archive members for example). +It would be ideal if someone could eventually modify +it so that such results were guaranteed. + +Instead, we want to ask questions like "is this NNN byte sized +object I'm about to try read from file offset YYY reasonable?" +As as example of where we might do this, some object formats +use string tables for which the first @code{sizeof(long)} bytes of the +table contain the size of the table itself, including the size bytes. +If an application tries to read what it thinks is one of these +string tables, without some way to validate the size, and for +some reason the size is wrong (byte swapping error, wrong location +for the string table, etc.), the only clue is likely to be a read +error when it tries to read the table, or a "virtual memory +exhausted" error when it tries to allocate 15 bazillon bytes +of space for the 15 bazillon byte table it is about to read. +This function at least allows us to answer the quesion, "is the +size reasonable?". +@* +@findex bfd_get_gp_size +@subsubsection @code{bfd_get_gp_size} +@strong{Synopsis} +@example +int bfd_get_gp_size(bfd *abfd); +@end example +@strong{Description}@* +Return the maximum size of objects to be optimized using the GP +register under MIPS ECOFF. This is typically set by the @code{-G} +argument to the compiler, assembler or linker. +@* +@findex bfd_set_gp_size +@subsubsection @code{bfd_set_gp_size} +@strong{Synopsis} +@example +void bfd_set_gp_size(bfd *abfd, int i); +@end example +@strong{Description}@* +Set the maximum size of objects to be optimized using the GP +register under ECOFF or MIPS ELF. This is typically set by +the @code{-G} argument to the compiler, assembler or linker. +@* +@findex bfd_scan_vma +@subsubsection @code{bfd_scan_vma} +@strong{Synopsis} +@example +bfd_vma bfd_scan_vma(CONST char *string, CONST char **end, int base); +@end example +@strong{Description}@* +Convert, like @code{strtoul}, a numerical expression +@var{string} into a @code{bfd_vma} integer, and return that integer. +(Though without as many bells and whistles as @code{strtoul}.) +The expression is assumed to be unsigned (i.e., positive). +If given a @var{base}, it is used as the base for conversion. +A base of 0 causes the function to interpret the string +in hex if a leading "0x" or "0X" is found, otherwise +in octal if a leading zero is found, otherwise in decimal. + +Overflow is not detected. +@* +@findex bfd_copy_private_bfd_data +@subsubsection @code{bfd_copy_private_bfd_data} +@strong{Synopsis} +@example +boolean bfd_copy_private_bfd_data(bfd *ibfd, bfd *obfd); +@end example +@strong{Description}@* +Copy private BFD information from the BFD @var{ibfd} to the +the BFD @var{obfd}. Return @code{true} on success, @code{false} on error. +Possible error returns are: + +@itemize @bullet + +@item +@code{bfd_error_no_memory} - +Not enough memory exists to create private data for @var{obfd}. +@end itemize +@example +#define bfd_copy_private_bfd_data(ibfd, obfd) \ + BFD_SEND (obfd, _bfd_copy_private_bfd_data, \ + (ibfd, obfd)) +@end example +@* +@findex bfd_merge_private_bfd_data +@subsubsection @code{bfd_merge_private_bfd_data} +@strong{Synopsis} +@example +boolean bfd_merge_private_bfd_data(bfd *ibfd, bfd *obfd); +@end example +@strong{Description}@* +Merge private BFD information from the BFD @var{ibfd} to the +the output file BFD @var{obfd} when linking. Return @code{true} +on success, @code{false} on error. Possible error returns are: + +@itemize @bullet + +@item +@code{bfd_error_no_memory} - +Not enough memory exists to create private data for @var{obfd}. +@end itemize +@example +#define bfd_merge_private_bfd_data(ibfd, obfd) \ + BFD_SEND (obfd, _bfd_merge_private_bfd_data, \ + (ibfd, obfd)) +@end example +@* +@findex bfd_set_private_flags +@subsubsection @code{bfd_set_private_flags} +@strong{Synopsis} +@example +boolean bfd_set_private_flags(bfd *abfd, flagword flags); +@end example +@strong{Description}@* +Set private BFD flag information in the BFD @var{abfd}. +Return @code{true} on success, @code{false} on error. Possible error +returns are: + +@itemize @bullet + +@item +@code{bfd_error_no_memory} - +Not enough memory exists to create private data for @var{obfd}. +@end itemize +@example +#define bfd_set_private_flags(abfd, flags) \ + BFD_SEND (abfd, _bfd_set_private_flags, \ + (abfd, flags)) +@end example +@* +@findex stuff +@subsubsection @code{stuff} +@strong{Description}@* +Stuff which should be documented: +@example +#define bfd_sizeof_headers(abfd, reloc) \ + BFD_SEND (abfd, _bfd_sizeof_headers, (abfd, reloc)) + +#define bfd_find_nearest_line(abfd, sec, syms, off, file, func, line) \ + BFD_SEND (abfd, _bfd_find_nearest_line, (abfd, sec, syms, off, file, func, line)) + + /* Do these three do anything useful at all, for any back end? */ +#define bfd_debug_info_start(abfd) \ + BFD_SEND (abfd, _bfd_debug_info_start, (abfd)) + +#define bfd_debug_info_end(abfd) \ + BFD_SEND (abfd, _bfd_debug_info_end, (abfd)) + +#define bfd_debug_info_accumulate(abfd, section) \ + BFD_SEND (abfd, _bfd_debug_info_accumulate, (abfd, section)) + + +#define bfd_stat_arch_elt(abfd, stat) \ + BFD_SEND (abfd, _bfd_stat_arch_elt,(abfd, stat)) + +#define bfd_update_armap_timestamp(abfd) \ + BFD_SEND (abfd, _bfd_update_armap_timestamp, (abfd)) + +#define bfd_set_arch_mach(abfd, arch, mach)\ + BFD_SEND ( abfd, _bfd_set_arch_mach, (abfd, arch, mach)) + +#define bfd_relax_section(abfd, section, link_info, again) \ + BFD_SEND (abfd, _bfd_relax_section, (abfd, section, link_info, again)) + +#define bfd_link_hash_table_create(abfd) \ + BFD_SEND (abfd, _bfd_link_hash_table_create, (abfd)) + +#define bfd_link_add_symbols(abfd, info) \ + BFD_SEND (abfd, _bfd_link_add_symbols, (abfd, info)) + +#define bfd_final_link(abfd, info) \ + BFD_SEND (abfd, _bfd_final_link, (abfd, info)) + +#define bfd_free_cached_info(abfd) \ + BFD_SEND (abfd, _bfd_free_cached_info, (abfd)) + +#define bfd_get_dynamic_symtab_upper_bound(abfd) \ + BFD_SEND (abfd, _bfd_get_dynamic_symtab_upper_bound, (abfd)) + +#define bfd_print_private_bfd_data(abfd, file)\ + BFD_SEND (abfd, _bfd_print_private_bfd_data, (abfd, file)) + +#define bfd_canonicalize_dynamic_symtab(abfd, asymbols) \ + BFD_SEND (abfd, _bfd_canonicalize_dynamic_symtab, (abfd, asymbols)) + +#define bfd_get_dynamic_reloc_upper_bound(abfd) \ + BFD_SEND (abfd, _bfd_get_dynamic_reloc_upper_bound, (abfd)) + +#define bfd_canonicalize_dynamic_reloc(abfd, arels, asyms) \ + BFD_SEND (abfd, _bfd_canonicalize_dynamic_reloc, (abfd, arels, asyms)) + +extern bfd_byte *bfd_get_relocated_section_contents + PARAMS ((bfd *, struct bfd_link_info *, + struct bfd_link_order *, bfd_byte *, + boolean, asymbol **)); + +@end example +@* diff --git a/contrib/binutils/bfd/elf32-i386.c b/contrib/binutils/bfd/elf32-i386.c index ee18864be0703..92168cf752cf1 100644 --- a/contrib/binutils/bfd/elf32-i386.c +++ b/contrib/binutils/bfd/elf32-i386.c @@ -17,7 +17,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/binutils/bfd/elf32-i386.c,v 1.4 2000/02/24 05:46:27 jdp Exp $ */ #include "bfd.h" #include "sysdep.h" diff --git a/contrib/binutils/bfd/elf64-alpha.c b/contrib/binutils/bfd/elf64-alpha.c index 2d4f221585d9c..c90aa29696ab2 100644 --- a/contrib/binutils/bfd/elf64-alpha.c +++ b/contrib/binutils/bfd/elf64-alpha.c @@ -18,7 +18,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/binutils/bfd/elf64-alpha.c,v 1.3 2000/02/24 05:46:27 jdp Exp $ */ /* We need a published ABI spec for this. Until one comes out, don't assume this'll remain unchanged forever. */ diff --git a/contrib/binutils/bfd/hosts/mipsbsd.h b/contrib/binutils/bfd/hosts/mipsbsd.h new file mode 100644 index 0000000000000..a2fad21fcf7a1 --- /dev/null +++ b/contrib/binutils/bfd/hosts/mipsbsd.h @@ -0,0 +1,12 @@ +#include +#include +#undef ALIGN + +#define HOST_PAGE_SIZE NBPG +/* #define HOST_SEGMENT_SIZE NBPG -- we use HOST_DATA_START_ADDR */ +#define HOST_MACHINE_ARCH bfd_arch_mips +/* #define HOST_MACHINE_MACHINE */ + +#define HOST_TEXT_START_ADDR USRTEXT +#define HOST_STACK_END_ADDR USRSTACK +#define NO_CORE_COMMAND diff --git a/contrib/binutils/gas/conf.in b/contrib/binutils/gas/conf.in new file mode 100644 index 0000000000000..d56807cd88d59 --- /dev/null +++ b/contrib/binutils/gas/conf.in @@ -0,0 +1,127 @@ +/* conf.in. Generated automatically from configure.in by autoheader. */ + +/* Define if using alloca.c. */ +#undef C_ALLOCA + +/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. + This function is required for alloca.c support on those systems. */ +#undef CRAY_STACKSEG_END + +/* Define if you have alloca, as a function or macro. */ +#undef HAVE_ALLOCA + +/* Define if you have and it should be used (not on Ultrix). */ +#undef HAVE_ALLOCA_H + +/* Define as __inline if that's what the C compiler calls it. */ +#undef inline + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown + */ +#undef STACK_DIRECTION + +/* Should gas use high-level BFD interfaces? */ +#undef BFD_ASSEMBLER + +/* Some assert/preprocessor combinations are incapable of handling + certain kinds of constructs in the argument of assert. For example, + quoted strings (if requoting isn't done right) or newlines. */ +#undef BROKEN_ASSERT + +/* If we aren't doing cross-assembling, some operations can be optimized, + since byte orders and value sizes don't need to be adjusted. */ +#undef CROSS_COMPILE + +/* Some gas code wants to know these parameters. */ +#undef TARGET_ALIAS +#undef TARGET_CPU +#undef TARGET_CANONICAL +#undef TARGET_OS +#undef TARGET_VENDOR + +/* Sometimes the system header files don't declare strstr. */ +#undef NEED_DECLARATION_STRSTR + +/* Sometimes the system header files don't declare malloc and realloc. */ +#undef NEED_DECLARATION_MALLOC + +/* Sometimes the system header files don't declare free. */ +#undef NEED_DECLARATION_FREE + +/* Sometimes the system header files don't declare sbrk. */ +#undef NEED_DECLARATION_SBRK + +/* Sometimes errno.h doesn't declare errno itself. */ +#undef NEED_DECLARATION_ERRNO + +#undef MANY_SEGMENTS + +/* Needed only for sparc configuration. */ +#undef SPARC_V9 +#undef SPARC_ARCH64 + +/* Defined if using CGEN. */ +#undef USING_CGEN + +/* Needed only for some configurations that can produce multiple output + formats. */ +#undef DEFAULT_EMULATION +#undef EMULATIONS +#undef USE_EMULATIONS +#undef OBJ_MAYBE_AOUT +#undef OBJ_MAYBE_BOUT +#undef OBJ_MAYBE_COFF +#undef OBJ_MAYBE_ECOFF +#undef OBJ_MAYBE_ELF +#undef OBJ_MAYBE_GENERIC +#undef OBJ_MAYBE_HP300 +#undef OBJ_MAYBE_IEEE +#undef OBJ_MAYBE_SOM +#undef OBJ_MAYBE_VMS + +/* Used for some of the COFF configurations, when the COFF code needs + to select something based on the CPU type before it knows it... */ +#undef I386COFF +#undef M68KCOFF +#undef M88KCOFF + +/* Define if you have the remove function. */ +#undef HAVE_REMOVE + +/* Define if you have the sbrk function. */ +#undef HAVE_SBRK + +/* Define if you have the unlink function. */ +#undef HAVE_UNLINK + +/* Define if you have the header file. */ +#undef HAVE_ERRNO_H + +/* Define if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define if you have the header file. */ +#undef HAVE_STDARG_H + +/* Define if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define if you have the header file. */ +#undef HAVE_STRING_H + +/* Define if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define if you have the header file. */ +#undef HAVE_VARARGS_H diff --git a/contrib/binutils/gas/config/e-mipsecoff.c b/contrib/binutils/gas/config/e-mipsecoff.c new file mode 100644 index 0000000000000..be2f71b7d46a6 --- /dev/null +++ b/contrib/binutils/gas/config/e-mipsecoff.c @@ -0,0 +1,37 @@ +#include "as.h" +#include "emul.h" + +static const char *mipsecoff_bfd_name PARAMS ((void)); + +static const char * +mipsecoff_bfd_name () +{ + abort (); + return NULL; +} + +#define emul_bfd_name mipsecoff_bfd_name +#define emul_format &ecoff_format_ops + +#define emul_name "mipsbecoff" +#define emul_struct_name mipsbecoff +#define emul_default_endian 1 +#include "emul-target.h" + +#undef emul_name +#undef emul_struct_name +#undef emul_default_endian + +#define emul_name "mipslecoff" +#define emul_struct_name mipslecoff +#define emul_default_endian 0 +#include "emul-target.h" + +#undef emul_name +#undef emul_struct_name +#undef emul_default_endian + +#define emul_name "mipsecoff" +#define emul_struct_name mipsecoff +#define emul_default_endian 2 +#include "emul-target.h" diff --git a/contrib/binutils/gas/config/e-mipself.c b/contrib/binutils/gas/config/e-mipself.c new file mode 100644 index 0000000000000..eea72f5165c77 --- /dev/null +++ b/contrib/binutils/gas/config/e-mipself.c @@ -0,0 +1,37 @@ +#include "as.h" +#include "emul.h" + +static const char *mipself_bfd_name PARAMS ((void)); + +static const char * +mipself_bfd_name () +{ + abort (); + return NULL; +} + +#define emul_bfd_name mipself_bfd_name +#define emul_format &elf_format_ops + +#define emul_name "mipsbelf" +#define emul_struct_name mipsbelf +#define emul_default_endian 1 +#include "emul-target.h" + +#undef emul_name +#undef emul_struct_name +#undef emul_default_endian + +#define emul_name "mipslelf" +#define emul_struct_name mipslelf +#define emul_default_endian 0 +#include "emul-target.h" + +#undef emul_name +#undef emul_struct_name +#undef emul_default_endian + +#define emul_name "mipself" +#define emul_struct_name mipself +#define emul_default_endian 2 +#include "emul-target.h" diff --git a/contrib/binutils/gas/config/i386coff.mt b/contrib/binutils/gas/config/i386coff.mt new file mode 100644 index 0000000000000..efda833651817 --- /dev/null +++ b/contrib/binutils/gas/config/i386coff.mt @@ -0,0 +1 @@ +TDEFINES=-DI386COFF diff --git a/contrib/binutils/gas/config/itbl-mips.h b/contrib/binutils/gas/config/itbl-mips.h new file mode 100644 index 0000000000000..f6482bd1f75e9 --- /dev/null +++ b/contrib/binutils/gas/config/itbl-mips.h @@ -0,0 +1,47 @@ + +/* itbl-mips.h + + Copyright (C) 1997 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* Defines for Mips itbl cop support */ + +#include "opcode/mips.h" + +/* Values for processors will be from 0 to NUMBER_OF_PROCESSORS-1 */ +#define NUMBER_OF_PROCESSORS 4 +#define MAX_BITPOS 31 + +/* Mips specifics */ +#define MIPS_OPCODE_COP0 (0x21) /* COPz+CO, bits 31-25: 0100zz1 */ +#define MIPS_ENCODE_COP_NUM(z) ((MIPS_OPCODE_COP0|z<<1)<<25) +#define MIPS_IS_COP_INSN(insn) ((MIPS_OPCODE_COP0&(insn>>25)) \ + == MIPS_OPCODE_COP0) +#define MIPS_DECODE_COP_NUM(insn) ((~MIPS_OPCODE_COP0&(insn>>25))>>1) +#define MIPS_DECODE_COP_COFUN(insn) ((~MIPS_ENCODE_COP_NUM(3))&(insn)) + +/* definitions required by generic code */ +#define ITBL_IS_INSN(insn) MIPS_IS_COP_INSN(insn) +#define ITBL_DECODE_PNUM(insn) MIPS_DECODE_COP_NUM(insn) +#define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum) + +#define ITBL_OPCODE_STRUCT mips_opcode +#define ITBL_OPCODES mips_opcodes +#define ITBL_NUM_OPCODES NUMOPCODES +#define ITBL_NUM_MACROS M_NUM_MACROS diff --git a/contrib/binutils/gas/config/sco5.mt b/contrib/binutils/gas/config/sco5.mt new file mode 100644 index 0000000000000..8879320c4e1e5 --- /dev/null +++ b/contrib/binutils/gas/config/sco5.mt @@ -0,0 +1 @@ +TDEFINES=-DSCO_ELF diff --git a/contrib/binutils/gas/config/tc-i386.c b/contrib/binutils/gas/config/tc-i386.c index d93456dd9a3d1..bf880e91eace4 100644 --- a/contrib/binutils/gas/config/tc-i386.c +++ b/contrib/binutils/gas/config/tc-i386.c @@ -19,7 +19,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/binutils/gas/config/tc-i386.c,v 1.4 2000/03/08 12:58:03 cracauer Exp $ */ /* Intel 80386 machine specific gas. diff --git a/contrib/binutils/gas/config/tc-mips.c b/contrib/binutils/gas/config/tc-mips.c new file mode 100644 index 0000000000000..48763bb726238 --- /dev/null +++ b/contrib/binutils/gas/config/tc-mips.c @@ -0,0 +1,11455 @@ +/* tc-mips.c -- assemble code for a MIPS chip. + Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. + Contributed by the OSF and Ralph Campbell. + Written by Keith Knowles and Ralph Campbell, working independently. + Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus + Support. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "as.h" +#include "config.h" +#include "subsegs.h" + +#include + +#ifdef USE_STDARG +#include +#endif +#ifdef USE_VARARGS +#include +#endif + +#include "opcode/mips.h" +#include "itbl-ops.h" + +#ifdef DEBUG +#define DBG(x) printf x +#else +#define DBG(x) +#endif + +#ifdef OBJ_MAYBE_ELF +/* Clean up namespace so we can include obj-elf.h too. */ +static int mips_output_flavor PARAMS ((void)); +static int mips_output_flavor () { return OUTPUT_FLAVOR; } +#undef OBJ_PROCESS_STAB +#undef OUTPUT_FLAVOR +#undef S_GET_ALIGN +#undef S_GET_SIZE +#undef S_SET_ALIGN +#undef S_SET_SIZE +#undef TARGET_SYMBOL_FIELDS +#undef obj_frob_file +#undef obj_frob_file_after_relocs +#undef obj_frob_symbol +#undef obj_pop_insert +#undef obj_sec_sym_ok_for_reloc +#undef OBJ_COPY_SYMBOL_ATTRIBUTES + +#include "obj-elf.h" +/* Fix any of them that we actually care about. */ +#undef OUTPUT_FLAVOR +#define OUTPUT_FLAVOR mips_output_flavor() +#endif + +#if defined (OBJ_ELF) +#include "elf/mips.h" +#endif + +#ifndef ECOFF_DEBUGGING +#define NO_ECOFF_DEBUGGING +#define ECOFF_DEBUGGING 0 +#endif + +#include "ecoff.h" + +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) +static char *mips_regmask_frag; +#endif + +#define AT 1 +#define TREG 24 +#define PIC_CALL_REG 25 +#define KT0 26 +#define KT1 27 +#define GP 28 +#define SP 29 +#define FP 30 +#define RA 31 + +#define ILLEGAL_REG (32) + +/* Allow override of standard little-endian ECOFF format. */ + +#ifndef ECOFF_LITTLE_FORMAT +#define ECOFF_LITTLE_FORMAT "ecoff-littlemips" +#endif + +extern int target_big_endian; + +/* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the + 32 bit ABI. This has no meaning for ECOFF. + Note that the default is always 32 bit, even if "configured" for + 64 bit [e.g. --target=mips64-elf]. */ +static int mips_64; + +/* The default target format to use. */ +const char * +mips_target_format () +{ + switch (OUTPUT_FLAVOR) + { + case bfd_target_aout_flavour: + return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; + case bfd_target_ecoff_flavour: + return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; + case bfd_target_elf_flavour: + return (target_big_endian + ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") + : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); + default: + abort (); + return NULL; + } +} + +/* The name of the readonly data section. */ +#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ + ? ".data" \ + : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ + ? ".rdata" \ + : OUTPUT_FLAVOR == bfd_target_elf_flavour \ + ? ".rodata" \ + : (abort (), "")) + +/* This is the set of options which may be modified by the .set + pseudo-op. We use a struct so that .set push and .set pop are more + reliable. */ + +struct mips_set_options +{ + /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 + if it has not been initialized. Changed by `.set mipsN', and the + -mipsN command line option, and the default CPU. */ + int isa; + /* Whether we are assembling for the mips16 processor. 0 if we are + not, 1 if we are, and -1 if the value has not been initialized. + Changed by `.set mips16' and `.set nomips16', and the -mips16 and + -nomips16 command line options, and the default CPU. */ + int mips16; + /* Non-zero if we should not reorder instructions. Changed by `.set + reorder' and `.set noreorder'. */ + int noreorder; + /* Non-zero if we should not permit the $at ($1) register to be used + in instructions. Changed by `.set at' and `.set noat'. */ + int noat; + /* Non-zero if we should warn when a macro instruction expands into + more than one machine instruction. Changed by `.set nomacro' and + `.set macro'. */ + int warn_about_macros; + /* Non-zero if we should not move instructions. Changed by `.set + move', `.set volatile', `.set nomove', and `.set novolatile'. */ + int nomove; + /* Non-zero if we should not optimize branches by moving the target + of the branch into the delay slot. Actually, we don't perform + this optimization anyhow. Changed by `.set bopt' and `.set + nobopt'. */ + int nobopt; + /* Non-zero if we should not autoextend mips16 instructions. + Changed by `.set autoextend' and `.set noautoextend'. */ + int noautoextend; +}; + +/* This is the struct we use to hold the current set of options. Note + that we must set the isa and mips16 fields to -1 to indicate that + they have not been initialized. */ + +static struct mips_set_options mips_opts = { -1, -1 }; + +/* These variables are filled in with the masks of registers used. + The object format code reads them and puts them in the appropriate + place. */ +unsigned long mips_gprmask; +unsigned long mips_cprmask[4]; + +/* MIPS ISA we are using for this output file. */ +static int file_mips_isa; + +/* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ +static int mips_cpu = -1; + +/* Whether the 4650 instructions (mad/madu) are permitted. */ +static int mips_4650 = -1; + +/* Whether the 4010 instructions are permitted. */ +static int mips_4010 = -1; + +/* Whether the 4100 MADD16 and DMADD16 are permitted. */ +static int mips_4100 = -1; + +/* Whether Toshiba r3900 instructions are permitted. */ +static int mips_3900 = -1; + + +/* Whether the processor uses hardware interlocks to protect + reads from the HI and LO registers, and thus does not + require nops to be inserted. */ +#define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \ + ) + +/* Whether the processor uses hardware interlocks to protect reads + from the GPRs, and thus does not require nops to be inserted. */ +#define gpr_interlocks (mips_opts.isa >= 2 || mips_3900) + + +/* As with other "interlocks" this is used by hardware that has FP + (co-processor) interlocks. */ +/* Itbl support may require additional care here. */ +#define cop_interlocks (mips_cpu == 4300 \ + ) + +/* MIPS PIC level. */ + +enum mips_pic_level +{ + /* Do not generate PIC code. */ + NO_PIC, + + /* Generate PIC code as in Irix 4. This is not implemented, and I'm + not sure what it is supposed to do. */ + IRIX4_PIC, + + /* Generate PIC code as in the SVR4 MIPS ABI. */ + SVR4_PIC, + + /* Generate PIC code without using a global offset table: the data + segment has a maximum size of 64K, all data references are off + the $gp register, and all text references are PC relative. This + is used on some embedded systems. */ + EMBEDDED_PIC +}; + +static enum mips_pic_level mips_pic; + +/* 1 if we should generate 32 bit offsets from the GP register in + SVR4_PIC mode. Currently has no meaning in other modes. */ +static int mips_big_got; + +/* 1 if trap instructions should used for overflow rather than break + instructions. */ +static int mips_trap; + +/* Non-zero if any .set noreorder directives were used. */ + +static int mips_any_noreorder; + +/* The size of the small data section. */ +static int g_switch_value = 8; +/* Whether the -G option was used. */ +static int g_switch_seen = 0; + +#define N_RMASK 0xc4 +#define N_VFP 0xd4 + +/* If we can determine in advance that GP optimization won't be + possible, we can skip the relaxation stuff that tries to produce + GP-relative references. This makes delay slot optimization work + better. + + This function can only provide a guess, but it seems to work for + gcc output. If it guesses wrong, the only loss should be in + efficiency; it shouldn't introduce any bugs. + + I don't know if a fix is needed for the SVR4_PIC mode. I've only + fixed it for the non-PIC mode. KR 95/04/07 */ +static int nopic_need_relax PARAMS ((symbolS *, int)); + +/* handle of the OPCODE hash table */ +static struct hash_control *op_hash = NULL; + +/* The opcode hash table we use for the mips16. */ +static struct hash_control *mips16_op_hash = NULL; + +/* This array holds the chars that always start a comment. If the + pre-processor is disabled, these aren't very useful */ +const char comment_chars[] = "#"; + +/* This array holds the chars that only start a comment at the beginning of + a line. If the line seems to have the form '# 123 filename' + .line and .file directives will appear in the pre-processed output */ +/* Note that input_file.c hand checks for '#' at the beginning of the + first line of the input file. This is because the compiler outputs + #NO_APP at the beginning of its output. */ +/* Also note that C style comments are always supported. */ +const char line_comment_chars[] = "#"; + +/* This array holds machine specific line separator characters. */ +const char line_separator_chars[] = ""; + +/* Chars that can be used to separate mant from exp in floating point nums */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant */ +/* As in 0f12.456 */ +/* or 0d1.2345e12 */ +const char FLT_CHARS[] = "rRsSfFdDxXpP"; + +/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be + changed in read.c . Ideally it shouldn't have to know about it at all, + but nothing is ideal around here. + */ + +static char *insn_error; + +static int auto_align = 1; + +/* When outputting SVR4 PIC code, the assembler needs to know the + offset in the stack frame from which to restore the $gp register. + This is set by the .cprestore pseudo-op, and saved in this + variable. */ +static offsetT mips_cprestore_offset = -1; + +/* This is the register which holds the stack frame, as set by the + .frame pseudo-op. This is needed to implement .cprestore. */ +static int mips_frame_reg = SP; + +/* To output NOP instructions correctly, we need to keep information + about the previous two instructions. */ + +/* Whether we are optimizing. The default value of 2 means to remove + unneeded NOPs and swap branch instructions when possible. A value + of 1 means to not swap branches. A value of 0 means to always + insert NOPs. */ +static int mips_optimize = 2; + +/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is + equivalent to seeing no -g option at all. */ +static int mips_debug = 0; + +/* The previous instruction. */ +static struct mips_cl_insn prev_insn; + +/* The instruction before prev_insn. */ +static struct mips_cl_insn prev_prev_insn; + +/* If we don't want information for prev_insn or prev_prev_insn, we + point the insn_mo field at this dummy integer. */ +static const struct mips_opcode dummy_opcode = { 0 }; + +/* Non-zero if prev_insn is valid. */ +static int prev_insn_valid; + +/* The frag for the previous instruction. */ +static struct frag *prev_insn_frag; + +/* The offset into prev_insn_frag for the previous instruction. */ +static long prev_insn_where; + +/* The reloc type for the previous instruction, if any. */ +static bfd_reloc_code_real_type prev_insn_reloc_type; + +/* The reloc for the previous instruction, if any. */ +static fixS *prev_insn_fixp; + +/* Non-zero if the previous instruction was in a delay slot. */ +static int prev_insn_is_delay_slot; + +/* Non-zero if the previous instruction was in a .set noreorder. */ +static int prev_insn_unreordered; + +/* Non-zero if the previous instruction uses an extend opcode (if + mips16). */ +static int prev_insn_extended; + +/* Non-zero if the previous previous instruction was in a .set + noreorder. */ +static int prev_prev_insn_unreordered; + +/* If this is set, it points to a frag holding nop instructions which + were inserted before the start of a noreorder section. If those + nops turn out to be unnecessary, the size of the frag can be + decreased. */ +static fragS *prev_nop_frag; + +/* The number of nop instructions we created in prev_nop_frag. */ +static int prev_nop_frag_holds; + +/* The number of nop instructions that we know we need in + prev_nop_frag. */ +static int prev_nop_frag_required; + +/* The number of instructions we've seen since prev_nop_frag. */ +static int prev_nop_frag_since; + +/* For ECOFF and ELF, relocations against symbols are done in two + parts, with a HI relocation and a LO relocation. Each relocation + has only 16 bits of space to store an addend. This means that in + order for the linker to handle carries correctly, it must be able + to locate both the HI and the LO relocation. This means that the + relocations must appear in order in the relocation table. + + In order to implement this, we keep track of each unmatched HI + relocation. We then sort them so that they immediately precede the + corresponding LO relocation. */ + +struct mips_hi_fixup +{ + /* Next HI fixup. */ + struct mips_hi_fixup *next; + /* This fixup. */ + fixS *fixp; + /* The section this fixup is in. */ + segT seg; +}; + +/* The list of unmatched HI relocs. */ + +static struct mips_hi_fixup *mips_hi_fixup_list; + +/* Map normal MIPS register numbers to mips16 register numbers. */ + +#define X ILLEGAL_REG +static const int mips32_to_16_reg_map[] = +{ + X, X, 2, 3, 4, 5, 6, 7, + X, X, X, X, X, X, X, X, + 0, 1, X, X, X, X, X, X, + X, X, X, X, X, X, X, X +}; +#undef X + +/* Map mips16 register numbers to normal MIPS register numbers. */ + +static const int mips16_to_32_reg_map[] = +{ + 16, 17, 2, 3, 4, 5, 6, 7 +}; + +/* Since the MIPS does not have multiple forms of PC relative + instructions, we do not have to do relaxing as is done on other + platforms. However, we do have to handle GP relative addressing + correctly, which turns out to be a similar problem. + + Every macro that refers to a symbol can occur in (at least) two + forms, one with GP relative addressing and one without. For + example, loading a global variable into a register generally uses + a macro instruction like this: + lw $4,i + If i can be addressed off the GP register (this is true if it is in + the .sbss or .sdata section, or if it is known to be smaller than + the -G argument) this will generate the following instruction: + lw $4,i($gp) + This instruction will use a GPREL reloc. If i can not be addressed + off the GP register, the following instruction sequence will be used: + lui $at,i + lw $4,i($at) + In this case the first instruction will have a HI16 reloc, and the + second reloc will have a LO16 reloc. Both relocs will be against + the symbol i. + + The issue here is that we may not know whether i is GP addressable + until after we see the instruction that uses it. Therefore, we + want to be able to choose the final instruction sequence only at + the end of the assembly. This is similar to the way other + platforms choose the size of a PC relative instruction only at the + end of assembly. + + When generating position independent code we do not use GP + addressing in quite the same way, but the issue still arises as + external symbols and local symbols must be handled differently. + + We handle these issues by actually generating both possible + instruction sequences. The longer one is put in a frag_var with + type rs_machine_dependent. We encode what to do with the frag in + the subtype field. We encode (1) the number of existing bytes to + replace, (2) the number of new bytes to use, (3) the offset from + the start of the existing bytes to the first reloc we must generate + (that is, the offset is applied from the start of the existing + bytes after they are replaced by the new bytes, if any), (4) the + offset from the start of the existing bytes to the second reloc, + (5) whether a third reloc is needed (the third reloc is always four + bytes after the second reloc), and (6) whether to warn if this + variant is used (this is sometimes needed if .set nomacro or .set + noat is in effect). All these numbers are reasonably small. + + Generating two instruction sequences must be handled carefully to + ensure that delay slots are handled correctly. Fortunately, there + are a limited number of cases. When the second instruction + sequence is generated, append_insn is directed to maintain the + existing delay slot information, so it continues to apply to any + code after the second instruction sequence. This means that the + second instruction sequence must not impose any requirements not + required by the first instruction sequence. + + These variant frags are then handled in functions called by the + machine independent code. md_estimate_size_before_relax returns + the final size of the frag. md_convert_frag sets up the final form + of the frag. tc_gen_reloc adjust the first reloc and adds a second + one if needed. */ +#define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ + ((relax_substateT) \ + (((old) << 23) \ + | ((new) << 16) \ + | (((reloc1) + 64) << 9) \ + | (((reloc2) + 64) << 2) \ + | ((reloc3) ? (1 << 1) : 0) \ + | ((warn) ? 1 : 0))) +#define RELAX_OLD(i) (((i) >> 23) & 0x7f) +#define RELAX_NEW(i) (((i) >> 16) & 0x7f) +#define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) +#define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) +#define RELAX_RELOC3(i) (((i) >> 1) & 1) +#define RELAX_WARN(i) ((i) & 1) + +/* For mips16 code, we use an entirely different form of relaxation. + mips16 supports two versions of most instructions which take + immediate values: a small one which takes some small value, and a + larger one which takes a 16 bit value. Since branches also follow + this pattern, relaxing these values is required. + + We can assemble both mips16 and normal MIPS code in a single + object. Therefore, we need to support this type of relaxation at + the same time that we support the relaxation described above. We + use the high bit of the subtype field to distinguish these cases. + + The information we store for this type of relaxation is the + argument code found in the opcode file for this relocation, whether + the user explicitly requested a small or extended form, and whether + the relocation is in a jump or jal delay slot. That tells us the + size of the value, and how it should be stored. We also store + whether the fragment is considered to be extended or not. We also + store whether this is known to be a branch to a different section, + whether we have tried to relax this frag yet, and whether we have + ever extended a PC relative fragment because of a shift count. */ +#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ + (0x80000000 \ + | ((type) & 0xff) \ + | ((small) ? 0x100 : 0) \ + | ((ext) ? 0x200 : 0) \ + | ((dslot) ? 0x400 : 0) \ + | ((jal_dslot) ? 0x800 : 0)) +#define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) +#define RELAX_MIPS16_TYPE(i) ((i) & 0xff) +#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) +#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) +#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) +#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) +#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) +#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) +#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) +#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) +#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) +#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) + +/* Prototypes for static functions. */ + +#ifdef __STDC__ +#define internalError() \ + as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) +#else +#define internalError() as_fatal ("MIPS internal Error"); +#endif + +enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; + +static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, + unsigned int reg, enum mips_regclass class)); +static int reg_needs_delay PARAMS ((int)); +static void mips16_mark_labels PARAMS ((void)); +static void append_insn PARAMS ((char *place, + struct mips_cl_insn * ip, + expressionS * p, + bfd_reloc_code_real_type r, + boolean)); +static void mips_no_prev_insn PARAMS ((int)); +static void mips_emit_delays PARAMS ((boolean)); +#ifdef USE_STDARG +static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, + const char *name, const char *fmt, + ...)); +#else +static void macro_build (); +#endif +static void mips16_macro_build PARAMS ((char *, int *, expressionS *, + const char *, const char *, + va_list)); +static void macro_build_lui PARAMS ((char *place, int *counter, + expressionS * ep, int regnum)); +static void set_at PARAMS ((int *counter, int reg, int unsignedp)); +static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, + expressionS *)); +static void load_register PARAMS ((int *, int, expressionS *, int)); +static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); +static void macro PARAMS ((struct mips_cl_insn * ip)); +static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); +#ifdef LOSING_COMPILER +static void macro2 PARAMS ((struct mips_cl_insn * ip)); +#endif +static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); +static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); +static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, + boolean, boolean, unsigned long *, + boolean *, unsigned short *)); +static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); +static void my_getExpression PARAMS ((expressionS * ep, char *str)); +static symbolS *get_symbol PARAMS ((void)); +static void mips_align PARAMS ((int to, int fill, symbolS *label)); +static void s_align PARAMS ((int)); +static void s_change_sec PARAMS ((int)); +static void s_cons PARAMS ((int)); +static void s_float_cons PARAMS ((int)); +static void s_mips_globl PARAMS ((int)); +static void s_option PARAMS ((int)); +static void s_mipsset PARAMS ((int)); +static void s_abicalls PARAMS ((int)); +static void s_cpload PARAMS ((int)); +static void s_cprestore PARAMS ((int)); +static void s_gpword PARAMS ((int)); +static void s_cpadd PARAMS ((int)); +static void s_insn PARAMS ((int)); +static void md_obj_begin PARAMS ((void)); +static void md_obj_end PARAMS ((void)); +static long get_number PARAMS ((void)); +static void s_ent PARAMS ((int)); +static void s_mipsend PARAMS ((int)); +static void s_file PARAMS ((int)); +static void s_mips_stab PARAMS ((int)); +static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); + +static int validate_mips_insn PARAMS ((const struct mips_opcode *)); + +/* Pseudo-op table. + + The following pseudo-ops from the Kane and Heinrich MIPS book + should be defined here, but are currently unsupported: .alias, + .galive, .gjaldef, .gjrlive, .livereg, .noalias. + + The following pseudo-ops from the Kane and Heinrich MIPS book are + specific to the type of debugging information being generated, and + should be defined by the object format: .aent, .begin, .bend, + .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, + .vreg. + + The following pseudo-ops from the Kane and Heinrich MIPS book are + not MIPS CPU specific, but are also not specific to the object file + format. This file is probably the best place to define them, but + they are not currently supported: .asm0, .endr, .lab, .repeat, + .struct, .weakext. */ + +static const pseudo_typeS mips_pseudo_table[] = +{ + /* MIPS specific pseudo-ops. */ + {"option", s_option, 0}, + {"set", s_mipsset, 0}, + {"rdata", s_change_sec, 'r'}, + {"sdata", s_change_sec, 's'}, + {"livereg", s_ignore, 0}, + {"abicalls", s_abicalls, 0}, + {"cpload", s_cpload, 0}, + {"cprestore", s_cprestore, 0}, + {"gpword", s_gpword, 0}, + {"cpadd", s_cpadd, 0}, + {"insn", s_insn, 0}, + + /* Relatively generic pseudo-ops that happen to be used on MIPS + chips. */ + {"asciiz", stringer, 1}, + {"bss", s_change_sec, 'b'}, + {"err", s_err, 0}, + {"half", s_cons, 1}, + {"dword", s_cons, 3}, + + /* These pseudo-ops are defined in read.c, but must be overridden + here for one reason or another. */ + {"align", s_align, 0}, + {"byte", s_cons, 0}, + {"data", s_change_sec, 'd'}, + {"double", s_float_cons, 'd'}, + {"float", s_float_cons, 'f'}, + {"globl", s_mips_globl, 0}, + {"global", s_mips_globl, 0}, + {"hword", s_cons, 1}, + {"int", s_cons, 2}, + {"long", s_cons, 2}, + {"octa", s_cons, 4}, + {"quad", s_cons, 3}, + {"short", s_cons, 1}, + {"single", s_float_cons, 'f'}, + {"stabn", s_mips_stab, 'n'}, + {"text", s_change_sec, 't'}, + {"word", s_cons, 2}, + { 0 }, +}; + +static const pseudo_typeS mips_nonecoff_pseudo_table[] = { + /* These pseudo-ops should be defined by the object file format. + However, a.out doesn't support them, so we have versions here. */ + {"aent", s_ent, 1}, + {"bgnb", s_ignore, 0}, + {"end", s_mipsend, 0}, + {"endb", s_ignore, 0}, + {"ent", s_ent, 0}, + {"file", s_file, 0}, + {"fmask", s_ignore, 'F'}, + {"frame", s_ignore, 0}, + {"loc", s_ignore, 0}, + {"mask", s_ignore, 'R'}, + {"verstamp", s_ignore, 0}, + { 0 }, +}; + +extern void pop_insert PARAMS ((const pseudo_typeS *)); + +void +mips_pop_insert () +{ + pop_insert (mips_pseudo_table); + if (! ECOFF_DEBUGGING) + pop_insert (mips_nonecoff_pseudo_table); +} + +/* Symbols labelling the current insn. */ + +struct insn_label_list +{ + struct insn_label_list *next; + symbolS *label; +}; + +static struct insn_label_list *insn_labels; +static struct insn_label_list *free_insn_labels; + +static void mips_clear_insn_labels PARAMS ((void)); + +static inline void +mips_clear_insn_labels () +{ + register struct insn_label_list **pl; + + for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) + ; + *pl = insn_labels; + insn_labels = NULL; +} + +static char *expr_end; + +/* Expressions which appear in instructions. These are set by + mips_ip. */ + +static expressionS imm_expr; +static expressionS offset_expr; + +/* Relocs associated with imm_expr and offset_expr. */ + +static bfd_reloc_code_real_type imm_reloc; +static bfd_reloc_code_real_type offset_reloc; + +/* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ + +static boolean imm_unmatched_hi; + +/* These are set by mips16_ip if an explicit extension is used. */ + +static boolean mips16_small, mips16_ext; + +/* + * This function is called once, at assembler startup time. It should + * set up all the tables, etc. that the MD part of the assembler will need. + */ +void +md_begin () +{ + boolean ok = false; + register const char *retval = NULL; + register unsigned int i = 0; + const char *cpu; + char *a = NULL; + int broken = 0; + + cpu = TARGET_CPU; + if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) + { + a = xmalloc (sizeof TARGET_CPU); + strcpy (a, TARGET_CPU); + a[(sizeof TARGET_CPU) - 3] = '\0'; + cpu = a; + } + + if (mips_cpu < 0) + { + /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is + just the generic 'mips', in which case set mips_cpu based + on the given ISA, if any. */ + + if (strcmp (cpu, "mips") == 0) + { + if (mips_opts.isa < 0) + mips_cpu = 3000; + + else if (mips_opts.isa == 2) + mips_cpu = 6000; + + else if (mips_opts.isa == 3) + mips_cpu = 4000; + + else if (mips_opts.isa == 4) + mips_cpu = 8000; + + else + mips_cpu = 3000; + } + + else if (strcmp (cpu, "r3900") == 0 + || strcmp (cpu, "mipstx39") == 0 + ) + mips_cpu = 3900; + + else if (strcmp (cpu, "r6000") == 0 + || strcmp (cpu, "mips2") == 0) + mips_cpu = 6000; + + else if (strcmp (cpu, "mips64") == 0 + || strcmp (cpu, "r4000") == 0 + || strcmp (cpu, "mips3") == 0) + mips_cpu = 4000; + + else if (strcmp (cpu, "r4400") == 0) + mips_cpu = 4400; + + else if (strcmp (cpu, "mips64orion") == 0 + || strcmp (cpu, "r4600") == 0) + mips_cpu = 4600; + + else if (strcmp (cpu, "r4650") == 0) + mips_cpu = 4650; + + else if (strcmp (cpu, "mips64vr4300") == 0) + mips_cpu = 4300; + + else if (strcmp (cpu, "mips64vr4100") == 0) + mips_cpu = 4100; + + else if (strcmp (cpu, "r4010") == 0) + mips_cpu = 4010; + + + else if (strcmp (cpu, "r5000") == 0 + || strcmp (cpu, "mips64vr5000") == 0) + mips_cpu = 5000; + + + + else if (strcmp (cpu, "r8000") == 0 + || strcmp (cpu, "mips4") == 0) + mips_cpu = 8000; + + else if (strcmp (cpu, "r10000") == 0) + mips_cpu = 10000; + + else if (strcmp (cpu, "mips16") == 0) + mips_cpu = 0; /* FIXME */ + + else + mips_cpu = 3000; + } + + if (mips_opts.isa == -1) + { + if (mips_cpu == 3000 + || mips_cpu == 3900) + mips_opts.isa = 1; + + else if (mips_cpu == 6000 + || mips_cpu == 4010) + mips_opts.isa = 2; + + else if (mips_cpu == 4000 + || mips_cpu == 4100 + || mips_cpu == 4400 + || mips_cpu == 4300 + || mips_cpu == 4600 + || mips_cpu == 4650) + mips_opts.isa = 3; + + else if (mips_cpu == 5000 + || mips_cpu == 8000 + || mips_cpu == 10000) + mips_opts.isa = 4; + + else + mips_opts.isa = 1; + } + + if (mips_opts.mips16 < 0) + { + if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) + mips_opts.mips16 = 1; + else + mips_opts.mips16 = 0; + } + + if (mips_4650 < 0) + mips_4650 = (mips_cpu == 4650); + + if (mips_4010 < 0) + mips_4010 = (mips_cpu == 4010); + + if (mips_4100 < 0) + mips_4100 = (mips_cpu == 4100); + + + + if (mips_3900 < 0) + mips_3900 = (mips_cpu == 3900); + + + /* End of TARGET_CPU processing, get rid of malloced memory + if necessary. */ + cpu = NULL; + if (a != NULL) + { + free (a); + a = NULL; + } + + if (mips_opts.isa < 2 && mips_trap) + as_bad ("trap exception not supported at ISA 1"); + + if (mips_cpu != 0 && mips_cpu != -1) + { + ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); + } + else + { + switch (mips_opts.isa) + { + case 1: + ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); + break; + case 2: + ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); + break; + case 3: + ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); + break; + case 4: + ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); + break; + } + } + + if (! ok) + as_warn ("Could not set architecture and machine"); + + file_mips_isa = mips_opts.isa; + + op_hash = hash_new (); + + for (i = 0; i < NUMOPCODES;) + { + const char *name = mips_opcodes[i].name; + + retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); + if (retval != NULL) + { + fprintf (stderr, "internal error: can't hash `%s': %s\n", + mips_opcodes[i].name, retval); + /* Probably a memory allocation problem? Give up now. */ + as_fatal ("Broken assembler. No assembly attempted."); + } + do + { + if (mips_opcodes[i].pinfo != INSN_MACRO) + { + if (!validate_mips_insn (&mips_opcodes[i])) + broken = 1; + } + ++i; + } + while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); + } + + mips16_op_hash = hash_new (); + + i = 0; + while (i < bfd_mips16_num_opcodes) + { + const char *name = mips16_opcodes[i].name; + + retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); + if (retval != NULL) + as_fatal ("internal: can't hash `%s': %s", + mips16_opcodes[i].name, retval); + do + { + if (mips16_opcodes[i].pinfo != INSN_MACRO + && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) + != mips16_opcodes[i].match)) + { + fprintf (stderr, "internal error: bad mips16 opcode: %s %s\n", + mips16_opcodes[i].name, mips16_opcodes[i].args); + broken = 1; + } + ++i; + } + while (i < bfd_mips16_num_opcodes + && strcmp (mips16_opcodes[i].name, name) == 0); + } + + if (broken) + as_fatal ("Broken assembler. No assembly attempted."); + + /* We add all the general register names to the symbol table. This + helps us detect invalid uses of them. */ + for (i = 0; i < 32; i++) + { + char buf[5]; + + sprintf (buf, "$%d", i); + symbol_table_insert (symbol_new (buf, reg_section, i, + &zero_address_frag)); + } + symbol_table_insert (symbol_new ("$fp", reg_section, FP, + &zero_address_frag)); + symbol_table_insert (symbol_new ("$sp", reg_section, SP, + &zero_address_frag)); + symbol_table_insert (symbol_new ("$gp", reg_section, GP, + &zero_address_frag)); + symbol_table_insert (symbol_new ("$at", reg_section, AT, + &zero_address_frag)); + symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, + &zero_address_frag)); + symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, + &zero_address_frag)); + symbol_table_insert (symbol_new ("$pc", reg_section, -1, + &zero_address_frag)); + + mips_no_prev_insn (false); + + mips_gprmask = 0; + mips_cprmask[0] = 0; + mips_cprmask[1] = 0; + mips_cprmask[2] = 0; + mips_cprmask[3] = 0; + + /* set the default alignment for the text section (2**2) */ + record_alignment (text_section, 2); + + if (USE_GLOBAL_POINTER_OPT) + bfd_set_gp_size (stdoutput, g_switch_value); + + if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + { + /* On a native system, sections must be aligned to 16 byte + boundaries. When configured for an embedded ELF target, we + don't bother. */ + if (strcmp (TARGET_OS, "elf") != 0) + { + (void) bfd_set_section_alignment (stdoutput, text_section, 4); + (void) bfd_set_section_alignment (stdoutput, data_section, 4); + (void) bfd_set_section_alignment (stdoutput, bss_section, 4); + } + + /* Create a .reginfo section for register masks and a .mdebug + section for debugging information. */ + { + segT seg; + subsegT subseg; + flagword flags; + segT sec; + + seg = now_seg; + subseg = now_subseg; + + /* The ABI says this section should be loaded so that the + running program can access it. However, we don't load it + if we are configured for an embedded target */ + flags = SEC_READONLY | SEC_DATA; + if (strcmp (TARGET_OS, "elf") != 0) + flags |= SEC_ALLOC | SEC_LOAD; + + if (! mips_64) + { + sec = subseg_new (".reginfo", (subsegT) 0); + + + (void) bfd_set_section_flags (stdoutput, sec, flags); + (void) bfd_set_section_alignment (stdoutput, sec, 2); + +#ifdef OBJ_ELF + mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); +#endif + } + else + { + /* The 64-bit ABI uses a .MIPS.options section rather than + .reginfo section. */ + sec = subseg_new (".MIPS.options", (subsegT) 0); + (void) bfd_set_section_flags (stdoutput, sec, flags); + (void) bfd_set_section_alignment (stdoutput, sec, 3); + +#ifdef OBJ_ELF + /* Set up the option header. */ + { + Elf_Internal_Options opthdr; + char *f; + + opthdr.kind = ODK_REGINFO; + opthdr.size = (sizeof (Elf_External_Options) + + sizeof (Elf64_External_RegInfo)); + opthdr.section = 0; + opthdr.info = 0; + f = frag_more (sizeof (Elf_External_Options)); + bfd_mips_elf_swap_options_out (stdoutput, &opthdr, + (Elf_External_Options *) f); + + mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); + } +#endif + } + + if (ECOFF_DEBUGGING) + { + sec = subseg_new (".mdebug", (subsegT) 0); + (void) bfd_set_section_flags (stdoutput, sec, + SEC_HAS_CONTENTS | SEC_READONLY); + (void) bfd_set_section_alignment (stdoutput, sec, 2); + } + + subseg_set (seg, subseg); + } + } + + if (! ECOFF_DEBUGGING) + md_obj_begin (); +} + +void +md_mips_end () +{ + if (! ECOFF_DEBUGGING) + md_obj_end (); +} + +void +md_assemble (str) + char *str; +{ + struct mips_cl_insn insn; + + imm_expr.X_op = O_absent; + imm_reloc = BFD_RELOC_UNUSED; + imm_unmatched_hi = false; + offset_expr.X_op = O_absent; + offset_reloc = BFD_RELOC_UNUSED; + + if (mips_opts.mips16) + mips16_ip (str, &insn); + else + { + mips_ip (str, &insn); + DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", + str, insn.insn_opcode)); + } + + if (insn_error) + { + as_bad ("%s `%s'", insn_error, str); + return; + } + + if (insn.insn_mo->pinfo == INSN_MACRO) + { + if (mips_opts.mips16) + mips16_macro (&insn); + else + macro (&insn); + } + else + { + if (imm_expr.X_op != O_absent) + append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, + imm_unmatched_hi); + else if (offset_expr.X_op != O_absent) + append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); + else + append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); + } +} + +/* See whether instruction IP reads register REG. CLASS is the type + of register. */ + +static int +insn_uses_reg (ip, reg, class) + struct mips_cl_insn *ip; + unsigned int reg; + enum mips_regclass class; +{ + if (class == MIPS16_REG) + { + assert (mips_opts.mips16); + reg = mips16_to_32_reg_map[reg]; + class = MIPS_GR_REG; + } + + /* Don't report on general register 0, since it never changes. */ + if (class == MIPS_GR_REG && reg == 0) + return 0; + + if (class == MIPS_FP_REG) + { + assert (! mips_opts.mips16); + /* If we are called with either $f0 or $f1, we must check $f0. + This is not optimal, because it will introduce an unnecessary + NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would + need to distinguish reading both $f0 and $f1 or just one of + them. Note that we don't have to check the other way, + because there is no instruction that sets both $f0 and $f1 + and requires a delay. */ + if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) + && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) + == (reg &~ (unsigned) 1))) + return 1; + if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) + && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) + == (reg &~ (unsigned) 1))) + return 1; + } + else if (! mips_opts.mips16) + { + if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) + && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) + return 1; + if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) + && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) + return 1; + } + else + { + if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) + && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX)] + == reg)) + return 1; + if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) + && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY)] + == reg)) + return 1; + if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) + && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z)] + == reg)) + return 1; + if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) + return 1; + if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) + return 1; + if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) + return 1; + if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) + && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) + & MIPS16OP_MASK_REGR32) == reg) + return 1; + } + + return 0; +} + +/* This function returns true if modifying a register requires a + delay. */ + +static int +reg_needs_delay (reg) + int reg; +{ + unsigned long prev_pinfo; + + prev_pinfo = prev_insn.insn_mo->pinfo; + if (! mips_opts.noreorder + && mips_opts.isa < 4 + && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) + || (! gpr_interlocks + && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) + { + /* A load from a coprocessor or from memory. All load + delays delay the use of general register rt for one + instruction on the r3000. The r6000 and r4000 use + interlocks. */ + /* Itbl support may require additional care here. */ + know (prev_pinfo & INSN_WRITE_GPR_T); + if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) + return 1; + } + + return 0; +} + +/* Mark instruction labels in mips16 mode. This permits the linker to + handle them specially, such as generating jalx instructions when + needed. We also make them odd for the duration of the assembly, in + order to generate the right sort of code. We will make them even + in the adjust_symtab routine, while leaving them marked. This is + convenient for the debugger and the disassembler. The linker knows + to make them odd again. */ + +static void +mips16_mark_labels () +{ + if (mips_opts.mips16) + { + struct insn_label_list *l; + + for (l = insn_labels; l != NULL; l = l->next) + { +#ifdef OBJ_ELF + if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + S_SET_OTHER (l->label, STO_MIPS16); +#endif + if ((l->label->sy_value.X_add_number & 1) == 0) + ++l->label->sy_value.X_add_number; + } + } +} + +/* Output an instruction. PLACE is where to put the instruction; if + it is NULL, this uses frag_more to get room. IP is the instruction + information. ADDRESS_EXPR is an operand of the instruction to be + used with RELOC_TYPE. */ + +static void +append_insn (place, ip, address_expr, reloc_type, unmatched_hi) + char *place; + struct mips_cl_insn *ip; + expressionS *address_expr; + bfd_reloc_code_real_type reloc_type; + boolean unmatched_hi; +{ + register unsigned long prev_pinfo, pinfo; + char *f; + fixS *fixp; + int nops = 0; + + /* Mark instruction labels in mips16 mode. */ + if (mips_opts.mips16) + mips16_mark_labels (); + + prev_pinfo = prev_insn.insn_mo->pinfo; + pinfo = ip->insn_mo->pinfo; + + if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) + { + int prev_prev_nop; + + /* If the previous insn required any delay slots, see if we need + to insert a NOP or two. There are eight kinds of possible + hazards, of which an instruction can have at most one type. + (1) a load from memory delay + (2) a load from a coprocessor delay + (3) an unconditional branch delay + (4) a conditional branch delay + (5) a move to coprocessor register delay + (6) a load coprocessor register from memory delay + (7) a coprocessor condition code delay + (8) a HI/LO special register delay + + There are a lot of optimizations we could do that we don't. + In particular, we do not, in general, reorder instructions. + If you use gcc with optimization, it will reorder + instructions and generally do much more optimization then we + do here; repeating all that work in the assembler would only + benefit hand written assembly code, and does not seem worth + it. */ + + /* This is how a NOP is emitted. */ +#define emit_nop() \ + (mips_opts.mips16 \ + ? md_number_to_chars (frag_more (2), 0x6500, 2) \ + : md_number_to_chars (frag_more (4), 0, 4)) + + /* The previous insn might require a delay slot, depending upon + the contents of the current insn. */ + if (! mips_opts.mips16 + && mips_opts.isa < 4 + && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) + && ! cop_interlocks) + || (! gpr_interlocks + && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) + { + /* A load from a coprocessor or from memory. All load + delays delay the use of general register rt for one + instruction on the r3000. The r6000 and r4000 use + interlocks. */ + /* Itbl support may require additional care here. */ + know (prev_pinfo & INSN_WRITE_GPR_T); + if (mips_optimize == 0 + || insn_uses_reg (ip, + ((prev_insn.insn_opcode >> OP_SH_RT) + & OP_MASK_RT), + MIPS_GR_REG)) + ++nops; + } + else if (! mips_opts.mips16 + && mips_opts.isa < 4 + && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) + && ! cop_interlocks) + || (mips_opts.isa < 2 + && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) + { + /* A generic coprocessor delay. The previous instruction + modified a coprocessor general or control register. If + it modified a control register, we need to avoid any + coprocessor instruction (this is probably not always + required, but it sometimes is). If it modified a general + register, we avoid using that register. + + On the r6000 and r4000 loading a coprocessor register + from memory is interlocked, and does not require a delay. + + This case is not handled very well. There is no special + knowledge of CP0 handling, and the coprocessors other + than the floating point unit are not distinguished at + all. */ + /* Itbl support may require additional care here. FIXME! + Need to modify this to include knowledge about + user specified delays! */ + if (prev_pinfo & INSN_WRITE_FPR_T) + { + if (mips_optimize == 0 + || insn_uses_reg (ip, + ((prev_insn.insn_opcode >> OP_SH_FT) + & OP_MASK_FT), + MIPS_FP_REG)) + ++nops; + } + else if (prev_pinfo & INSN_WRITE_FPR_S) + { + if (mips_optimize == 0 + || insn_uses_reg (ip, + ((prev_insn.insn_opcode >> OP_SH_FS) + & OP_MASK_FS), + MIPS_FP_REG)) + ++nops; + } + else + { + /* We don't know exactly what the previous instruction + does. If the current instruction uses a coprocessor + register, we must insert a NOP. If previous + instruction may set the condition codes, and the + current instruction uses them, we must insert two + NOPS. */ + /* Itbl support may require additional care here. */ + if (mips_optimize == 0 + || ((prev_pinfo & INSN_WRITE_COND_CODE) + && (pinfo & INSN_READ_COND_CODE))) + nops += 2; + else if (pinfo & INSN_COP) + ++nops; + } + } + else if (! mips_opts.mips16 + && mips_opts.isa < 4 + && (prev_pinfo & INSN_WRITE_COND_CODE) + && ! cop_interlocks) + { + /* The previous instruction sets the coprocessor condition + codes, but does not require a general coprocessor delay + (this means it is a floating point comparison + instruction). If this instruction uses the condition + codes, we need to insert a single NOP. */ + /* Itbl support may require additional care here. */ + if (mips_optimize == 0 + || (pinfo & INSN_READ_COND_CODE)) + ++nops; + } + else if (prev_pinfo & INSN_READ_LO) + { + /* The previous instruction reads the LO register; if the + current instruction writes to the LO register, we must + insert two NOPS. Some newer processors have interlocks. */ + if (! hilo_interlocks + && (mips_optimize == 0 + || (pinfo & INSN_WRITE_LO))) + nops += 2; + } + else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) + { + /* The previous instruction reads the HI register; if the + current instruction writes to the HI register, we must + insert a NOP. Some newer processors have interlocks. */ + if (! hilo_interlocks + && (mips_optimize == 0 + || (pinfo & INSN_WRITE_HI))) + nops += 2; + } + + /* If the previous instruction was in a noreorder section, then + we don't want to insert the nop after all. */ + /* Itbl support may require additional care here. */ + if (prev_insn_unreordered) + nops = 0; + + /* There are two cases which require two intervening + instructions: 1) setting the condition codes using a move to + coprocessor instruction which requires a general coprocessor + delay and then reading the condition codes 2) reading the HI + or LO register and then writing to it (except on processors + which have interlocks). If we are not already emitting a NOP + instruction, we must check for these cases compared to the + instruction previous to the previous instruction. */ + if ((! mips_opts.mips16 + && mips_opts.isa < 4 + && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) + && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) + && (pinfo & INSN_READ_COND_CODE) + && ! cop_interlocks) + || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) + && (pinfo & INSN_WRITE_LO) + && ! hilo_interlocks) + || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) + && (pinfo & INSN_WRITE_HI) + && ! hilo_interlocks)) + prev_prev_nop = 1; + else + prev_prev_nop = 0; + + if (prev_prev_insn_unreordered) + prev_prev_nop = 0; + + if (prev_prev_nop && nops == 0) + ++nops; + + /* If we are being given a nop instruction, don't bother with + one of the nops we would otherwise output. This will only + happen when a nop instruction is used with mips_optimize set + to 0. */ + if (nops > 0 + && ! mips_opts.noreorder + && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) + --nops; + + /* Now emit the right number of NOP instructions. */ + if (nops > 0 && ! mips_opts.noreorder) + { + fragS *old_frag; + unsigned long old_frag_offset; + int i; + struct insn_label_list *l; + + old_frag = frag_now; + old_frag_offset = frag_now_fix (); + + for (i = 0; i < nops; i++) + emit_nop (); + + if (listing) + { + listing_prev_line (); + /* We may be at the start of a variant frag. In case we + are, make sure there is enough space for the frag + after the frags created by listing_prev_line. The + argument to frag_grow here must be at least as large + as the argument to all other calls to frag_grow in + this file. We don't have to worry about being in the + middle of a variant frag, because the variants insert + all needed nop instructions themselves. */ + frag_grow (40); + } + + for (l = insn_labels; l != NULL; l = l->next) + { + assert (S_GET_SEGMENT (l->label) == now_seg); + l->label->sy_frag = frag_now; + S_SET_VALUE (l->label, (valueT) frag_now_fix ()); + /* mips16 text labels are stored as odd. */ + if (mips_opts.mips16) + ++l->label->sy_value.X_add_number; + } + +#ifndef NO_ECOFF_DEBUGGING + if (ECOFF_DEBUGGING) + ecoff_fix_loc (old_frag, old_frag_offset); +#endif + } + else if (prev_nop_frag != NULL) + { + /* We have a frag holding nops we may be able to remove. If + we don't need any nops, we can decrease the size of + prev_nop_frag by the size of one instruction. If we do + need some nops, we count them in prev_nops_required. */ + if (prev_nop_frag_since == 0) + { + if (nops == 0) + { + prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; + --prev_nop_frag_holds; + } + else + prev_nop_frag_required += nops; + } + else + { + if (prev_prev_nop == 0) + { + prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; + --prev_nop_frag_holds; + } + else + ++prev_nop_frag_required; + } + + if (prev_nop_frag_holds <= prev_nop_frag_required) + prev_nop_frag = NULL; + + ++prev_nop_frag_since; + + /* Sanity check: by the time we reach the second instruction + after prev_nop_frag, we should have used up all the nops + one way or another. */ + assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); + } + } + + if (reloc_type > BFD_RELOC_UNUSED) + { + /* We need to set up a variant frag. */ + assert (mips_opts.mips16 && address_expr != NULL); + f = frag_var (rs_machine_dependent, 4, 0, + RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, + mips16_small, mips16_ext, + (prev_pinfo + & INSN_UNCOND_BRANCH_DELAY), + (prev_insn_reloc_type + == BFD_RELOC_MIPS16_JMP)), + make_expr_symbol (address_expr), (offsetT) 0, + (char *) NULL); + } + else if (place != NULL) + f = place; + else if (mips_opts.mips16 + && ! ip->use_extend + && reloc_type != BFD_RELOC_MIPS16_JMP) + { + /* Make sure there is enough room to swap this instruction with + a following jump instruction. */ + frag_grow (6); + f = frag_more (2); + } + else + { + if (mips_opts.mips16 + && mips_opts.noreorder + && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + as_warn ("extended instruction in delay slot"); + + f = frag_more (4); + } + + fixp = NULL; + if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) + { + if (address_expr->X_op == O_constant) + { + switch (reloc_type) + { + case BFD_RELOC_32: + ip->insn_opcode |= address_expr->X_add_number; + break; + + case BFD_RELOC_LO16: + ip->insn_opcode |= address_expr->X_add_number & 0xffff; + break; + + case BFD_RELOC_MIPS_JMP: + if ((address_expr->X_add_number & 3) != 0) + as_bad ("jump to misaligned address (0x%lx)", + (unsigned long) address_expr->X_add_number); + ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; + break; + + case BFD_RELOC_MIPS16_JMP: + if ((address_expr->X_add_number & 3) != 0) + as_bad ("jump to misaligned address (0x%lx)", + (unsigned long) address_expr->X_add_number); + ip->insn_opcode |= + (((address_expr->X_add_number & 0x7c0000) << 3) + | ((address_expr->X_add_number & 0xf800000) >> 7) + | ((address_expr->X_add_number & 0x3fffc) >> 2)); + break; + + + case BFD_RELOC_16_PCREL_S2: + goto need_reloc; + + default: + internalError (); + } + } + else + { + need_reloc: + /* Don't generate a reloc if we are writing into a variant + frag. */ + if (place == NULL) + { + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, + address_expr, + reloc_type == BFD_RELOC_16_PCREL_S2, + reloc_type); + if (unmatched_hi) + { + struct mips_hi_fixup *hi_fixup; + + assert (reloc_type == BFD_RELOC_HI16_S); + hi_fixup = ((struct mips_hi_fixup *) + xmalloc (sizeof (struct mips_hi_fixup))); + hi_fixup->fixp = fixp; + hi_fixup->seg = now_seg; + hi_fixup->next = mips_hi_fixup_list; + mips_hi_fixup_list = hi_fixup; + } + } + } + } + + if (! mips_opts.mips16) + md_number_to_chars (f, ip->insn_opcode, 4); + else if (reloc_type == BFD_RELOC_MIPS16_JMP) + { + md_number_to_chars (f, ip->insn_opcode >> 16, 2); + md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); + } + else + { + if (ip->use_extend) + { + md_number_to_chars (f, 0xf000 | ip->extend, 2); + f += 2; + } + md_number_to_chars (f, ip->insn_opcode, 2); + } + + /* Update the register mask information. */ + if (! mips_opts.mips16) + { + if (pinfo & INSN_WRITE_GPR_D) + mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); + if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) + mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); + if (pinfo & INSN_READ_GPR_S) + mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); + if (pinfo & INSN_WRITE_GPR_31) + mips_gprmask |= 1 << 31; + if (pinfo & INSN_WRITE_FPR_D) + mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); + if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) + mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); + if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) + mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); + if ((pinfo & INSN_READ_FPR_R) != 0) + mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); + if (pinfo & INSN_COP) + { + /* We don't keep enough information to sort these cases out. + The itbl support does keep this information however, although + we currently don't support itbl fprmats as part of the cop + instruction. May want to add this support in the future. */ + } + /* Never set the bit for $0, which is always zero. */ + mips_gprmask &=~ 1 << 0; + } + else + { + if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) + mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX); + if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) + mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY); + if (pinfo & MIPS16_INSN_WRITE_Z) + mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ); + if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) + mips_gprmask |= 1 << TREG; + if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) + mips_gprmask |= 1 << SP; + if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) + mips_gprmask |= 1 << RA; + if (pinfo & MIPS16_INSN_WRITE_GPR_Y) + mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); + if (pinfo & MIPS16_INSN_READ_Z) + mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z); + if (pinfo & MIPS16_INSN_READ_GPR_X) + mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) + & MIPS16OP_MASK_REGR32); + } + + if (place == NULL && ! mips_opts.noreorder) + { + /* Filling the branch delay slot is more complex. We try to + switch the branch with the previous instruction, which we can + do if the previous instruction does not set up a condition + that the branch tests and if the branch is not itself the + target of any branch. */ + if ((pinfo & INSN_UNCOND_BRANCH_DELAY) + || (pinfo & INSN_COND_BRANCH_DELAY)) + { + if (mips_optimize < 2 + /* If we have seen .set volatile or .set nomove, don't + optimize. */ + || mips_opts.nomove != 0 + /* If we had to emit any NOP instructions, then we + already know we can not swap. */ + || nops != 0 + /* If we don't even know the previous insn, we can not + swap. */ + || ! prev_insn_valid + /* If the previous insn is already in a branch delay + slot, then we can not swap. */ + || prev_insn_is_delay_slot + /* If the previous previous insn was in a .set + noreorder, we can't swap. Actually, the MIPS + assembler will swap in this situation. However, gcc + configured -with-gnu-as will generate code like + .set noreorder + lw $4,XXX + .set reorder + INSN + bne $4,$0,foo + in which we can not swap the bne and INSN. If gcc is + not configured -with-gnu-as, it does not output the + .set pseudo-ops. We don't have to check + prev_insn_unreordered, because prev_insn_valid will + be 0 in that case. We don't want to use + prev_prev_insn_valid, because we do want to be able + to swap at the start of a function. */ + || prev_prev_insn_unreordered + /* If the branch is itself the target of a branch, we + can not swap. We cheat on this; all we check for is + whether there is a label on this instruction. If + there are any branches to anything other than a + label, users must use .set noreorder. */ + || insn_labels != NULL + /* If the previous instruction is in a variant frag, we + can not do the swap. This does not apply to the + mips16, which uses variant frags for different + purposes. */ + || (! mips_opts.mips16 + && prev_insn_frag->fr_type == rs_machine_dependent) + /* If the branch reads the condition codes, we don't + even try to swap, because in the sequence + ctc1 $X,$31 + INSN + INSN + bc1t LABEL + we can not swap, and I don't feel like handling that + case. */ + || (! mips_opts.mips16 + && mips_opts.isa < 4 + && (pinfo & INSN_READ_COND_CODE)) + /* We can not swap with an instruction that requires a + delay slot, becase the target of the branch might + interfere with that instruction. */ + || (! mips_opts.mips16 + && mips_opts.isa < 4 + && (prev_pinfo + /* Itbl support may require additional care here. */ + & (INSN_LOAD_COPROC_DELAY + | INSN_COPROC_MOVE_DELAY + | INSN_WRITE_COND_CODE))) + || (! hilo_interlocks + && (prev_pinfo + & (INSN_READ_LO + | INSN_READ_HI))) + || (! mips_opts.mips16 + && ! gpr_interlocks + && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) + || (! mips_opts.mips16 + && mips_opts.isa < 2 + /* Itbl support may require additional care here. */ + && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) + /* We can not swap with a branch instruction. */ + || (prev_pinfo + & (INSN_UNCOND_BRANCH_DELAY + | INSN_COND_BRANCH_DELAY + | INSN_COND_BRANCH_LIKELY)) + /* We do not swap with a trap instruction, since it + complicates trap handlers to have the trap + instruction be in a delay slot. */ + || (prev_pinfo & INSN_TRAP) + /* If the branch reads a register that the previous + instruction sets, we can not swap. */ + || (! mips_opts.mips16 + && (prev_pinfo & INSN_WRITE_GPR_T) + && insn_uses_reg (ip, + ((prev_insn.insn_opcode >> OP_SH_RT) + & OP_MASK_RT), + MIPS_GR_REG)) + || (! mips_opts.mips16 + && (prev_pinfo & INSN_WRITE_GPR_D) + && insn_uses_reg (ip, + ((prev_insn.insn_opcode >> OP_SH_RD) + & OP_MASK_RD), + MIPS_GR_REG)) + || (mips_opts.mips16 + && (((prev_pinfo & MIPS16_INSN_WRITE_X) + && insn_uses_reg (ip, + ((prev_insn.insn_opcode + >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX), + MIPS16_REG)) + || ((prev_pinfo & MIPS16_INSN_WRITE_Y) + && insn_uses_reg (ip, + ((prev_insn.insn_opcode + >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY), + MIPS16_REG)) + || ((prev_pinfo & MIPS16_INSN_WRITE_Z) + && insn_uses_reg (ip, + ((prev_insn.insn_opcode + >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ), + MIPS16_REG)) + || ((prev_pinfo & MIPS16_INSN_WRITE_T) + && insn_uses_reg (ip, TREG, MIPS_GR_REG)) + || ((prev_pinfo & MIPS16_INSN_WRITE_31) + && insn_uses_reg (ip, RA, MIPS_GR_REG)) + || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) + && insn_uses_reg (ip, + MIPS16OP_EXTRACT_REG32R (prev_insn. + insn_opcode), + MIPS_GR_REG)))) + /* If the branch writes a register that the previous + instruction sets, we can not swap (we know that + branches write only to RD or to $31). */ + || (! mips_opts.mips16 + && (prev_pinfo & INSN_WRITE_GPR_T) + && (((pinfo & INSN_WRITE_GPR_D) + && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) + == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) + || ((pinfo & INSN_WRITE_GPR_31) + && (((prev_insn.insn_opcode >> OP_SH_RT) + & OP_MASK_RT) + == 31)))) + || (! mips_opts.mips16 + && (prev_pinfo & INSN_WRITE_GPR_D) + && (((pinfo & INSN_WRITE_GPR_D) + && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) + == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) + || ((pinfo & INSN_WRITE_GPR_31) + && (((prev_insn.insn_opcode >> OP_SH_RD) + & OP_MASK_RD) + == 31)))) + || (mips_opts.mips16 + && (pinfo & MIPS16_INSN_WRITE_31) + && ((prev_pinfo & MIPS16_INSN_WRITE_31) + || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) + && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) + == RA)))) + /* If the branch writes a register that the previous + instruction reads, we can not swap (we know that + branches only write to RD or to $31). */ + || (! mips_opts.mips16 + && (pinfo & INSN_WRITE_GPR_D) + && insn_uses_reg (&prev_insn, + ((ip->insn_opcode >> OP_SH_RD) + & OP_MASK_RD), + MIPS_GR_REG)) + || (! mips_opts.mips16 + && (pinfo & INSN_WRITE_GPR_31) + && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) + || (mips_opts.mips16 + && (pinfo & MIPS16_INSN_WRITE_31) + && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) + /* If we are generating embedded PIC code, the branch + might be expanded into a sequence which uses $at, so + we can't swap with an instruction which reads it. */ + || (mips_pic == EMBEDDED_PIC + && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) + /* If the previous previous instruction has a load + delay, and sets a register that the branch reads, we + can not swap. */ + || (! mips_opts.mips16 + && mips_opts.isa < 4 + /* Itbl support may require additional care here. */ + && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) + || (! gpr_interlocks + && (prev_prev_insn.insn_mo->pinfo + & INSN_LOAD_MEMORY_DELAY))) + && insn_uses_reg (ip, + ((prev_prev_insn.insn_opcode >> OP_SH_RT) + & OP_MASK_RT), + MIPS_GR_REG)) + /* If one instruction sets a condition code and the + other one uses a condition code, we can not swap. */ + || ((pinfo & INSN_READ_COND_CODE) + && (prev_pinfo & INSN_WRITE_COND_CODE)) + || ((pinfo & INSN_WRITE_COND_CODE) + && (prev_pinfo & INSN_READ_COND_CODE)) + /* If the previous instruction uses the PC, we can not + swap. */ + || (mips_opts.mips16 + && (prev_pinfo & MIPS16_INSN_READ_PC)) + /* If the previous instruction was extended, we can not + swap. */ + || (mips_opts.mips16 && prev_insn_extended) + /* If the previous instruction had a fixup in mips16 + mode, we can not swap. This normally means that the + previous instruction was a 4 byte branch anyhow. */ + || (mips_opts.mips16 && prev_insn_fixp)) + { + /* We could do even better for unconditional branches to + portions of this object file; we could pick up the + instruction at the destination, put it in the delay + slot, and bump the destination address. */ + emit_nop (); + /* Update the previous insn information. */ + prev_prev_insn = *ip; + prev_insn.insn_mo = &dummy_opcode; + } + else + { + /* It looks like we can actually do the swap. */ + if (! mips_opts.mips16) + { + char *prev_f; + char temp[4]; + + prev_f = prev_insn_frag->fr_literal + prev_insn_where; + memcpy (temp, prev_f, 4); + memcpy (prev_f, f, 4); + memcpy (f, temp, 4); + if (prev_insn_fixp) + { + prev_insn_fixp->fx_frag = frag_now; + prev_insn_fixp->fx_where = f - frag_now->fr_literal; + } + if (fixp) + { + fixp->fx_frag = prev_insn_frag; + fixp->fx_where = prev_insn_where; + } + } + else + { + char *prev_f; + char temp[2]; + + assert (prev_insn_fixp == NULL); + prev_f = prev_insn_frag->fr_literal + prev_insn_where; + memcpy (temp, prev_f, 2); + memcpy (prev_f, f, 2); + if (reloc_type != BFD_RELOC_MIPS16_JMP) + { + assert (reloc_type == BFD_RELOC_UNUSED); + memcpy (f, temp, 2); + } + else + { + memcpy (f, f + 2, 2); + memcpy (f + 2, temp, 2); + } + if (fixp) + { + fixp->fx_frag = prev_insn_frag; + fixp->fx_where = prev_insn_where; + } + } + + /* Update the previous insn information; leave prev_insn + unchanged. */ + prev_prev_insn = *ip; + } + prev_insn_is_delay_slot = 1; + + /* If that was an unconditional branch, forget the previous + insn information. */ + if (pinfo & INSN_UNCOND_BRANCH_DELAY) + { + prev_prev_insn.insn_mo = &dummy_opcode; + prev_insn.insn_mo = &dummy_opcode; + } + + prev_insn_fixp = NULL; + prev_insn_reloc_type = BFD_RELOC_UNUSED; + prev_insn_extended = 0; + } + else if (pinfo & INSN_COND_BRANCH_LIKELY) + { + /* We don't yet optimize a branch likely. What we should do + is look at the target, copy the instruction found there + into the delay slot, and increment the branch to jump to + the next instruction. */ + emit_nop (); + /* Update the previous insn information. */ + prev_prev_insn = *ip; + prev_insn.insn_mo = &dummy_opcode; + prev_insn_fixp = NULL; + prev_insn_reloc_type = BFD_RELOC_UNUSED; + prev_insn_extended = 0; + } + else + { + /* Update the previous insn information. */ + if (nops > 0) + prev_prev_insn.insn_mo = &dummy_opcode; + else + prev_prev_insn = prev_insn; + prev_insn = *ip; + + /* Any time we see a branch, we always fill the delay slot + immediately; since this insn is not a branch, we know it + is not in a delay slot. */ + prev_insn_is_delay_slot = 0; + + prev_insn_fixp = fixp; + prev_insn_reloc_type = reloc_type; + if (mips_opts.mips16) + prev_insn_extended = (ip->use_extend + || reloc_type > BFD_RELOC_UNUSED); + } + + prev_prev_insn_unreordered = prev_insn_unreordered; + prev_insn_unreordered = 0; + prev_insn_frag = frag_now; + prev_insn_where = f - frag_now->fr_literal; + prev_insn_valid = 1; + } + else if (place == NULL) + { + /* We need to record a bit of information even when we are not + reordering, in order to determine the base address for mips16 + PC relative relocs. */ + prev_prev_insn = prev_insn; + prev_insn = *ip; + prev_insn_reloc_type = reloc_type; + prev_prev_insn_unreordered = prev_insn_unreordered; + prev_insn_unreordered = 1; + } + + /* We just output an insn, so the next one doesn't have a label. */ + mips_clear_insn_labels (); + + /* We must ensure that a fixup associated with an unmatched %hi + reloc does not become a variant frag. Otherwise, the + rearrangement of %hi relocs in frob_file may confuse + tc_gen_reloc. */ + if (unmatched_hi) + { + frag_wane (frag_now); + frag_new (0); + } +} + +/* This function forgets that there was any previous instruction or + label. If PRESERVE is non-zero, it remembers enough information to + know whether nops are needed before a noreorder section. */ + +static void +mips_no_prev_insn (preserve) + int preserve; +{ + if (! preserve) + { + prev_insn.insn_mo = &dummy_opcode; + prev_prev_insn.insn_mo = &dummy_opcode; + prev_nop_frag = NULL; + prev_nop_frag_holds = 0; + prev_nop_frag_required = 0; + prev_nop_frag_since = 0; + } + prev_insn_valid = 0; + prev_insn_is_delay_slot = 0; + prev_insn_unreordered = 0; + prev_insn_extended = 0; + prev_insn_reloc_type = BFD_RELOC_UNUSED; + prev_prev_insn_unreordered = 0; + mips_clear_insn_labels (); +} + +/* This function must be called whenever we turn on noreorder or emit + something other than instructions. It inserts any NOPS which might + be needed by the previous instruction, and clears the information + kept for the previous instructions. The INSNS parameter is true if + instructions are to follow. */ + +static void +mips_emit_delays (insns) + boolean insns; +{ + if (! mips_opts.noreorder) + { + int nops; + + nops = 0; + if ((! mips_opts.mips16 + && mips_opts.isa < 4 + && (! cop_interlocks + && (prev_insn.insn_mo->pinfo + & (INSN_LOAD_COPROC_DELAY + | INSN_COPROC_MOVE_DELAY + | INSN_WRITE_COND_CODE)))) + || (! hilo_interlocks + && (prev_insn.insn_mo->pinfo + & (INSN_READ_LO + | INSN_READ_HI))) + || (! mips_opts.mips16 + && ! gpr_interlocks + && (prev_insn.insn_mo->pinfo + & INSN_LOAD_MEMORY_DELAY)) + || (! mips_opts.mips16 + && mips_opts.isa < 2 + && (prev_insn.insn_mo->pinfo + & INSN_COPROC_MEMORY_DELAY))) + { + /* Itbl support may require additional care here. */ + ++nops; + if ((! mips_opts.mips16 + && mips_opts.isa < 4 + && (! cop_interlocks + && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) + || (! hilo_interlocks + && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) + || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) + ++nops; + + if (prev_insn_unreordered) + nops = 0; + } + else if ((! mips_opts.mips16 + && mips_opts.isa < 4 + && (! cop_interlocks + && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) + || (! hilo_interlocks + && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) + || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) + { + /* Itbl support may require additional care here. */ + if (! prev_prev_insn_unreordered) + ++nops; + } + + if (nops > 0) + { + struct insn_label_list *l; + + if (insns) + { + /* Record the frag which holds the nop instructions, so + that we can remove them if we don't need them. */ + frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); + prev_nop_frag = frag_now; + prev_nop_frag_holds = nops; + prev_nop_frag_required = 0; + prev_nop_frag_since = 0; + } + + for (; nops > 0; --nops) + emit_nop (); + + if (insns) + { + /* Move on to a new frag, so that it is safe to simply + decrease the size of prev_nop_frag. */ + frag_wane (frag_now); + frag_new (0); + } + + for (l = insn_labels; l != NULL; l = l->next) + { + assert (S_GET_SEGMENT (l->label) == now_seg); + l->label->sy_frag = frag_now; + S_SET_VALUE (l->label, (valueT) frag_now_fix ()); + /* mips16 text labels are stored as odd. */ + if (mips_opts.mips16) + ++l->label->sy_value.X_add_number; + } + } + } + + /* Mark instruction labels in mips16 mode. */ + if (mips_opts.mips16 && insns) + mips16_mark_labels (); + + mips_no_prev_insn (insns); +} + +/* Build an instruction created by a macro expansion. This is passed + a pointer to the count of instructions created so far, an + expression, the name of the instruction to build, an operand format + string, and corresponding arguments. */ + +#ifdef USE_STDARG +static void +macro_build (char *place, + int *counter, + expressionS * ep, + const char *name, + const char *fmt, + ...) +#else +static void +macro_build (place, counter, ep, name, fmt, va_alist) + char *place; + int *counter; + expressionS *ep; + const char *name; + const char *fmt; + va_dcl +#endif +{ + struct mips_cl_insn insn; + bfd_reloc_code_real_type r; + va_list args; + int insn_isa; + +#ifdef USE_STDARG + va_start (args, fmt); +#else + va_start (args); +#endif + + /* + * If the macro is about to expand into a second instruction, + * print a warning if needed. We need to pass ip as a parameter + * to generate a better warning message here... + */ + if (mips_opts.warn_about_macros && place == NULL && *counter == 1) + as_warn ("Macro instruction expanded into multiple instructions"); + + if (place == NULL) + *counter += 1; /* bump instruction counter */ + + if (mips_opts.mips16) + { + mips16_macro_build (place, counter, ep, name, fmt, args); + va_end (args); + return; + } + + r = BFD_RELOC_UNUSED; + insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); + assert (insn.insn_mo); + assert (strcmp (name, insn.insn_mo->name) == 0); + + /* Search until we get a match for NAME. */ + while (1) + { + if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) + insn_isa = 1; + else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) + insn_isa = 2; + else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) + insn_isa = 3; + else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) + insn_isa = 4; + else + insn_isa = 15; + + if (strcmp (fmt, insn.insn_mo->args) == 0 + && insn.insn_mo->pinfo != INSN_MACRO + && (insn_isa <= mips_opts.isa + || (mips_4650 + && (insn.insn_mo->membership & INSN_4650) != 0) + || (mips_4010 + && (insn.insn_mo->membership & INSN_4010) != 0) + || (mips_4100 + && (insn.insn_mo->membership & INSN_4100) != 0) + || (mips_3900 + && (insn.insn_mo->membership & INSN_3900) != 0)) + && (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0)) + break; + + ++insn.insn_mo; + assert (insn.insn_mo->name); + assert (strcmp (name, insn.insn_mo->name) == 0); + } + + insn.insn_opcode = insn.insn_mo->match; + for (;;) + { + switch (*fmt++) + { + case '\0': + break; + + case ',': + case '(': + case ')': + continue; + + case 't': + case 'w': + case 'E': + insn.insn_opcode |= va_arg (args, int) << 16; + continue; + + case 'c': + case 'T': + case 'W': + insn.insn_opcode |= va_arg (args, int) << 16; + continue; + + case 'd': + case 'G': + insn.insn_opcode |= va_arg (args, int) << 11; + continue; + + case 'V': + case 'S': + insn.insn_opcode |= va_arg (args, int) << 11; + continue; + + case 'z': + continue; + + case '<': + insn.insn_opcode |= va_arg (args, int) << 6; + continue; + + case 'D': + insn.insn_opcode |= va_arg (args, int) << 6; + continue; + + case 'B': + insn.insn_opcode |= va_arg (args, int) << 6; + continue; + + case 'b': + case 's': + case 'r': + case 'v': + insn.insn_opcode |= va_arg (args, int) << 21; + continue; + + case 'i': + case 'j': + case 'o': + r = (bfd_reloc_code_real_type) va_arg (args, int); + assert (r == BFD_RELOC_MIPS_GPREL + || r == BFD_RELOC_MIPS_LITERAL + || r == BFD_RELOC_LO16 + || r == BFD_RELOC_MIPS_GOT16 + || r == BFD_RELOC_MIPS_CALL16 + || r == BFD_RELOC_MIPS_GOT_LO16 + || r == BFD_RELOC_MIPS_CALL_LO16 + || (ep->X_op == O_subtract + && now_seg == text_section + && r == BFD_RELOC_PCREL_LO16)); + continue; + + case 'u': + r = (bfd_reloc_code_real_type) va_arg (args, int); + assert (ep != NULL + && (ep->X_op == O_constant + || (ep->X_op == O_symbol + && (r == BFD_RELOC_HI16_S + || r == BFD_RELOC_HI16 + || r == BFD_RELOC_MIPS_GOT_HI16 + || r == BFD_RELOC_MIPS_CALL_HI16)) + || (ep->X_op == O_subtract + && now_seg == text_section + && r == BFD_RELOC_PCREL_HI16_S))); + if (ep->X_op == O_constant) + { + insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; + ep = NULL; + r = BFD_RELOC_UNUSED; + } + continue; + + case 'p': + assert (ep != NULL); + /* + * This allows macro() to pass an immediate expression for + * creating short branches without creating a symbol. + * Note that the expression still might come from the assembly + * input, in which case the value is not checked for range nor + * is a relocation entry generated (yuck). + */ + if (ep->X_op == O_constant) + { + insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; + ep = NULL; + } + else + r = BFD_RELOC_16_PCREL_S2; + continue; + + case 'a': + assert (ep != NULL); + r = BFD_RELOC_MIPS_JMP; + continue; + + case 'C': + insn.insn_opcode |= va_arg (args, unsigned long); + continue; + + default: + internalError (); + } + break; + } + va_end (args); + assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); + + append_insn (place, &insn, ep, r, false); +} + +static void +mips16_macro_build (place, counter, ep, name, fmt, args) + char *place; + int *counter; + expressionS *ep; + const char *name; + const char *fmt; + va_list args; +{ + struct mips_cl_insn insn; + bfd_reloc_code_real_type r; + + r = BFD_RELOC_UNUSED; + insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); + assert (insn.insn_mo); + assert (strcmp (name, insn.insn_mo->name) == 0); + + while (strcmp (fmt, insn.insn_mo->args) != 0 + || insn.insn_mo->pinfo == INSN_MACRO) + { + ++insn.insn_mo; + assert (insn.insn_mo->name); + assert (strcmp (name, insn.insn_mo->name) == 0); + } + + insn.insn_opcode = insn.insn_mo->match; + insn.use_extend = false; + + for (;;) + { + int c; + + c = *fmt++; + switch (c) + { + case '\0': + break; + + case ',': + case '(': + case ')': + continue; + + case 'y': + case 'w': + insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; + continue; + + case 'x': + case 'v': + insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; + continue; + + case 'z': + insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; + continue; + + case 'Z': + insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; + continue; + + case '0': + case 'S': + case 'P': + case 'R': + continue; + + case 'X': + insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; + continue; + + case 'Y': + { + int regno; + + regno = va_arg (args, int); + regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); + insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; + } + continue; + + case '<': + case '>': + case '4': + case '5': + case 'H': + case 'W': + case 'D': + case 'j': + case '8': + case 'V': + case 'C': + case 'U': + case 'k': + case 'K': + case 'p': + case 'q': + { + assert (ep != NULL); + + if (ep->X_op != O_constant) + r = BFD_RELOC_UNUSED + c; + else + { + mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, + false, false, &insn.insn_opcode, + &insn.use_extend, &insn.extend); + ep = NULL; + r = BFD_RELOC_UNUSED; + } + } + continue; + + case '6': + insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; + continue; + } + + break; + } + + assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); + + append_insn (place, &insn, ep, r, false); +} + +/* + * Generate a "lui" instruction. + */ +static void +macro_build_lui (place, counter, ep, regnum) + char *place; + int *counter; + expressionS *ep; + int regnum; +{ + expressionS high_expr; + struct mips_cl_insn insn; + bfd_reloc_code_real_type r; + CONST char *name = "lui"; + CONST char *fmt = "t,u"; + + assert (! mips_opts.mips16); + + if (place == NULL) + high_expr = *ep; + else + { + high_expr.X_op = O_constant; + high_expr.X_add_number = ep->X_add_number; + } + + if (high_expr.X_op == O_constant) + { + /* we can compute the instruction now without a relocation entry */ + if (high_expr.X_add_number & 0x8000) + high_expr.X_add_number += 0x10000; + high_expr.X_add_number = + ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; + r = BFD_RELOC_UNUSED; + } + else + { + assert (ep->X_op == O_symbol); + /* _gp_disp is a special case, used from s_cpload. */ + assert (mips_pic == NO_PIC + || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); + r = BFD_RELOC_HI16_S; + } + + /* + * If the macro is about to expand into a second instruction, + * print a warning if needed. We need to pass ip as a parameter + * to generate a better warning message here... + */ + if (mips_opts.warn_about_macros && place == NULL && *counter == 1) + as_warn ("Macro instruction expanded into multiple instructions"); + + if (place == NULL) + *counter += 1; /* bump instruction counter */ + + insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); + assert (insn.insn_mo); + assert (strcmp (name, insn.insn_mo->name) == 0); + assert (strcmp (fmt, insn.insn_mo->args) == 0); + + insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); + if (r == BFD_RELOC_UNUSED) + { + insn.insn_opcode |= high_expr.X_add_number; + append_insn (place, &insn, NULL, r, false); + } + else + append_insn (place, &insn, &high_expr, r, false); +} + +/* set_at() + * Generates code to set the $at register to true (one) + * if reg is less than the immediate expression. + */ +static void +set_at (counter, reg, unsignedp) + int *counter; + int reg; + int unsignedp; +{ + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= -0x8000 + && imm_expr.X_add_number < 0x8000) + macro_build ((char *) NULL, counter, &imm_expr, + unsignedp ? "sltiu" : "slti", + "t,r,j", AT, reg, (int) BFD_RELOC_LO16); + else + { + load_register (counter, AT, &imm_expr, 0); + macro_build ((char *) NULL, counter, NULL, + unsignedp ? "sltu" : "slt", + "d,v,t", AT, reg, AT); + } +} + +/* Warn if an expression is not a constant. */ + +static void +check_absolute_expr (ip, ex) + struct mips_cl_insn *ip; + expressionS *ex; +{ + if (ex->X_op == O_big) + as_bad ("unsupported large constant"); + else if (ex->X_op != O_constant) + as_bad ("Instruction %s requires absolute expression", ip->insn_mo->name); +} + +/* Count the leading zeroes by performing a binary chop. This is a + bulky bit of source, but performance is a LOT better for the + majority of values than a simple loop to count the bits: + for (lcnt = 0; (lcnt < 32); lcnt++) + if ((v) & (1 << (31 - lcnt))) + break; + However it is not code size friendly, and the gain will drop a bit + on certain cached systems. +*/ +#define COUNT_TOP_ZEROES(v) \ + (((v) & ~0xffff) == 0 \ + ? ((v) & ~0xff) == 0 \ + ? ((v) & ~0xf) == 0 \ + ? ((v) & ~0x3) == 0 \ + ? ((v) & ~0x1) == 0 \ + ? !(v) \ + ? 32 \ + : 31 \ + : 30 \ + : ((v) & ~0x7) == 0 \ + ? 29 \ + : 28 \ + : ((v) & ~0x3f) == 0 \ + ? ((v) & ~0x1f) == 0 \ + ? 27 \ + : 26 \ + : ((v) & ~0x7f) == 0 \ + ? 25 \ + : 24 \ + : ((v) & ~0xfff) == 0 \ + ? ((v) & ~0x3ff) == 0 \ + ? ((v) & ~0x1ff) == 0 \ + ? 23 \ + : 22 \ + : ((v) & ~0x7ff) == 0 \ + ? 21 \ + : 20 \ + : ((v) & ~0x3fff) == 0 \ + ? ((v) & ~0x1fff) == 0 \ + ? 19 \ + : 18 \ + : ((v) & ~0x7fff) == 0 \ + ? 17 \ + : 16 \ + : ((v) & ~0xffffff) == 0 \ + ? ((v) & ~0xfffff) == 0 \ + ? ((v) & ~0x3ffff) == 0 \ + ? ((v) & ~0x1ffff) == 0 \ + ? 15 \ + : 14 \ + : ((v) & ~0x7ffff) == 0 \ + ? 13 \ + : 12 \ + : ((v) & ~0x3fffff) == 0 \ + ? ((v) & ~0x1fffff) == 0 \ + ? 11 \ + : 10 \ + : ((v) & ~0x7fffff) == 0 \ + ? 9 \ + : 8 \ + : ((v) & ~0xfffffff) == 0 \ + ? ((v) & ~0x3ffffff) == 0 \ + ? ((v) & ~0x1ffffff) == 0 \ + ? 7 \ + : 6 \ + : ((v) & ~0x7ffffff) == 0 \ + ? 5 \ + : 4 \ + : ((v) & ~0x3fffffff) == 0 \ + ? ((v) & ~0x1fffffff) == 0 \ + ? 3 \ + : 2 \ + : ((v) & ~0x7fffffff) == 0 \ + ? 1 \ + : 0) + +/* load_register() + * This routine generates the least number of instructions neccessary to load + * an absolute expression value into a register. + */ +static void +load_register (counter, reg, ep, dbl) + int *counter; + int reg; + expressionS *ep; + int dbl; +{ + int freg; + expressionS hi32, lo32; + + if (ep->X_op != O_big) + { + assert (ep->X_op == O_constant); + if (ep->X_add_number < 0x8000 + && (ep->X_add_number >= 0 + || (ep->X_add_number >= -0x8000 + && (! dbl + || ! ep->X_unsigned + || sizeof (ep->X_add_number) > 4)))) + { + /* We can handle 16 bit signed values with an addiu to + $zero. No need to ever use daddiu here, since $zero and + the result are always correct in 32 bit mode. */ + macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, + (int) BFD_RELOC_LO16); + return; + } + else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) + { + /* We can handle 16 bit unsigned values with an ori to + $zero. */ + macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, + (int) BFD_RELOC_LO16); + return; + } + else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 + || ((ep->X_add_number &~ (offsetT) 0x7fffffff) + == ~ (offsetT) 0x7fffffff)) + && (! dbl + || ! ep->X_unsigned + || sizeof (ep->X_add_number) > 4 + || (ep->X_add_number & 0x80000000) == 0)) + || ((mips_opts.isa < 3 || ! dbl) + && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) + || (mips_opts.isa < 3 + && ! dbl + && ((ep->X_add_number &~ (offsetT) 0xffffffff) + == ~ (offsetT) 0xffffffff))) + { + /* 32 bit values require an lui. */ + macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, + (int) BFD_RELOC_HI16); + if ((ep->X_add_number & 0xffff) != 0) + macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, + (int) BFD_RELOC_LO16); + return; + } + } + + /* The value is larger than 32 bits. */ + + if (mips_opts.isa < 3) + { + as_bad ("Number larger than 32 bits"); + macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, + (int) BFD_RELOC_LO16); + return; + } + + if (ep->X_op != O_big) + { + hi32 = *ep; + hi32.X_add_number = (valueT) hi32.X_add_number >> 16; + hi32.X_add_number = (valueT) hi32.X_add_number >> 16; + hi32.X_add_number &= 0xffffffff; + lo32 = *ep; + lo32.X_add_number &= 0xffffffff; + } + else + { + assert (ep->X_add_number > 2); + if (ep->X_add_number == 3) + generic_bignum[3] = 0; + else if (ep->X_add_number > 4) + as_bad ("Number larger than 64 bits"); + lo32.X_op = O_constant; + lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); + hi32.X_op = O_constant; + hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); + } + + if (hi32.X_add_number == 0) + freg = 0; + else + { + int shift, bit; + unsigned long hi, lo; + + if (hi32.X_add_number == 0xffffffff) + { + if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) + { + macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", + reg, 0, (int) BFD_RELOC_LO16); + return; + } + if (lo32.X_add_number & 0x80000000) + { + macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, + (int) BFD_RELOC_HI16); + if (lo32.X_add_number & 0xffff) + macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", + reg, reg, (int) BFD_RELOC_LO16); + return; + } + } + + /* Check for 16bit shifted constant. We know that hi32 is + non-zero, so start the mask on the first bit of the hi32 + value. */ + shift = 17; + do + { + unsigned long himask, lomask; + + if (shift < 32) + { + himask = 0xffff >> (32 - shift); + lomask = (0xffff << shift) & 0xffffffff; + } + else + { + himask = 0xffff << (shift - 32); + lomask = 0; + } + if ((hi32.X_add_number & ~ (offsetT) himask) == 0 + && (lo32.X_add_number & ~ (offsetT) lomask) == 0) + { + expressionS tmp; + + tmp.X_op = O_constant; + if (shift < 32) + tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) + | (lo32.X_add_number >> shift)); + else + tmp.X_add_number = hi32.X_add_number >> (shift - 32); + macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, + (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, counter, NULL, + (shift >= 32) ? "dsll32" : "dsll", + "d,w,<", reg, reg, + (shift >= 32) ? shift - 32 : shift); + return; + } + shift++; + } while (shift <= (64 - 16)); + + /* Find the bit number of the lowest one bit, and store the + shifted value in hi/lo. */ + hi = (unsigned long) (hi32.X_add_number & 0xffffffff); + lo = (unsigned long) (lo32.X_add_number & 0xffffffff); + if (lo != 0) + { + bit = 0; + while ((lo & 1) == 0) + { + lo >>= 1; + ++bit; + } + lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); + hi >>= bit; + } + else + { + bit = 32; + while ((hi & 1) == 0) + { + hi >>= 1; + ++bit; + } + lo = hi; + hi = 0; + } + + /* Optimize if the shifted value is a (power of 2) - 1. */ + if ((hi == 0 && ((lo + 1) & lo) == 0) + || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) + { + shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); + if (shift != 0) + { + expressionS tmp; + + /* This instruction will set the register to be all + ones. */ + tmp.X_op = O_constant; + tmp.X_add_number = (offsetT) -1; + macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", + reg, 0, (int) BFD_RELOC_LO16); + if (bit != 0) + { + bit += shift; + macro_build ((char *) NULL, counter, NULL, + (bit >= 32) ? "dsll32" : "dsll", + "d,w,<", reg, reg, + (bit >= 32) ? bit - 32 : bit); + } + macro_build ((char *) NULL, counter, NULL, + (shift >= 32) ? "dsrl32" : "dsrl", + "d,w,<", reg, reg, + (shift >= 32) ? shift - 32 : shift); + return; + } + } + + /* Sign extend hi32 before calling load_register, because we can + generally get better code when we load a sign extended value. */ + if ((hi32.X_add_number & 0x80000000) != 0) + hi32.X_add_number |= ~ (offsetT) 0xffffffff; + load_register (counter, reg, &hi32, 0); + freg = reg; + } + if ((lo32.X_add_number & 0xffff0000) == 0) + { + if (freg != 0) + { + macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, + freg, 0); + freg = reg; + } + } + else + { + expressionS mid16; + + if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) + { + macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, + (int) BFD_RELOC_HI16); + macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, + reg, 0); + return; + } + + if (freg != 0) + { + macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, + freg, 16); + freg = reg; + } + mid16 = lo32; + mid16.X_add_number >>= 16; + macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, + freg, (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, + reg, 16); + freg = reg; + } + if ((lo32.X_add_number & 0xffff) != 0) + macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, + (int) BFD_RELOC_LO16); +} + +/* Load an address into a register. */ + +static void +load_address (counter, reg, ep) + int *counter; + int reg; + expressionS *ep; +{ + char *p; + + if (ep->X_op != O_constant + && ep->X_op != O_symbol) + { + as_bad ("expression too complex"); + ep->X_op = O_constant; + } + + if (ep->X_op == O_constant) + { + load_register (counter, reg, ep, 0); + return; + } + + if (mips_pic == NO_PIC) + { + /* If this is a reference to a GP relative symbol, we want + addiu $reg,$gp, (BFD_RELOC_MIPS_GPREL) + Otherwise we want + lui $reg, (BFD_RELOC_HI16_S) + addiu $reg,$reg, (BFD_RELOC_LO16) + If we have an addend, we always use the latter form. */ + if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET + || nopic_need_relax (ep->X_add_symbol, 1)) + p = NULL; + else + { + frag_grow (20); + macro_build ((char *) NULL, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); + p = frag_var (rs_machine_dependent, 8, 0, + RELAX_ENCODE (4, 8, 0, 4, 0, + mips_opts.warn_about_macros), + ep->X_add_symbol, (offsetT) 0, (char *) NULL); + } + macro_build_lui (p, counter, ep, reg); + if (p != NULL) + p += 4; + macro_build (p, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", reg, reg, (int) BFD_RELOC_LO16); + } + else if (mips_pic == SVR4_PIC && ! mips_big_got) + { + expressionS ex; + + /* If this is a reference to an external symbol, we want + lw $reg,($gp) (BFD_RELOC_MIPS_GOT16) + Otherwise we want + lw $reg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $reg,$reg, (BFD_RELOC_LO16) + If there is a constant, it must be added in after. */ + ex.X_add_number = ep->X_add_number; + ep->X_add_number = 0; + frag_grow (20); + macro_build ((char *) NULL, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); + macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); + p = frag_var (rs_machine_dependent, 4, 0, + RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), + ep->X_add_symbol, (offsetT) 0, (char *) NULL); + macro_build (p, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", reg, reg, (int) BFD_RELOC_LO16); + if (ex.X_add_number != 0) + { + if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) + as_bad ("PIC code offset overflow (max 16 signed bits)"); + ex.X_op = O_constant; + macro_build ((char *) NULL, counter, &ex, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", reg, reg, (int) BFD_RELOC_LO16); + } + } + else if (mips_pic == SVR4_PIC) + { + expressionS ex; + int off; + + /* This is the large GOT case. If this is a reference to an + external symbol, we want + lui $reg, (BFD_RELOC_MIPS_GOT_HI16) + addu $reg,$reg,$gp + lw $reg,($reg) (BFD_RELOC_MIPS_GOT_LO16) + Otherwise, for a reference to a local symbol, we want + lw $reg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $reg,$reg, (BFD_RELOC_LO16) + If there is a constant, it must be added in after. */ + ex.X_add_number = ep->X_add_number; + ep->X_add_number = 0; + if (reg_needs_delay (GP)) + off = 4; + else + off = 0; + frag_grow (32); + macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, + (int) BFD_RELOC_MIPS_GOT_HI16); + macro_build ((char *) NULL, counter, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", reg, reg, GP); + macro_build ((char *) NULL, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); + p = frag_var (rs_machine_dependent, 12 + off, 0, + RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, + mips_opts.warn_about_macros), + ep->X_add_symbol, (offsetT) 0, (char *) NULL); + if (off > 0) + { + /* We need a nop before loading from $gp. This special + check is required because the lui which starts the main + instruction stream does not refer to $gp, and so will not + insert the nop which may be required. */ + macro_build (p, counter, (expressionS *) NULL, "nop", ""); + p += 4; + } + macro_build (p, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); + p += 4; + macro_build (p, counter, (expressionS *) NULL, "nop", ""); + p += 4; + macro_build (p, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", reg, reg, (int) BFD_RELOC_LO16); + if (ex.X_add_number != 0) + { + if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) + as_bad ("PIC code offset overflow (max 16 signed bits)"); + ex.X_op = O_constant; + macro_build ((char *) NULL, counter, &ex, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", reg, reg, (int) BFD_RELOC_LO16); + } + } + else if (mips_pic == EMBEDDED_PIC) + { + /* We always do + addiu $reg,$gp, (BFD_RELOC_MIPS_GPREL) + */ + macro_build ((char *) NULL, counter, ep, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); + } + else + abort (); +} + +/* + * Build macros + * This routine implements the seemingly endless macro or synthesized + * instructions and addressing modes in the mips assembly language. Many + * of these macros are simple and are similar to each other. These could + * probably be handled by some kind of table or grammer aproach instead of + * this verbose method. Others are not simple macros but are more like + * optimizing code generation. + * One interesting optimization is when several store macros appear + * consecutivly that would load AT with the upper half of the same address. + * The ensuing load upper instructions are ommited. This implies some kind + * of global optimization. We currently only optimize within a single macro. + * For many of the load and store macros if the address is specified as a + * constant expression in the first 64k of memory (ie ld $2,0x4000c) we + * first load register 'at' with zero and use it as the base register. The + * mips assembler simply uses register $zero. Just one tiny optimization + * we're missing. + */ +static void +macro (ip) + struct mips_cl_insn *ip; +{ + register int treg, sreg, dreg, breg; + int tempreg; + int mask; + int icnt = 0; + int used_at; + expressionS expr1; + const char *s; + const char *s2; + const char *fmt; + int likely = 0; + int dbl = 0; + int coproc = 0; + int lr = 0; + offsetT maxnum; + int off; + bfd_reloc_code_real_type r; + char *p; + int hold_mips_optimize; + + assert (! mips_opts.mips16); + + treg = (ip->insn_opcode >> 16) & 0x1f; + dreg = (ip->insn_opcode >> 11) & 0x1f; + sreg = breg = (ip->insn_opcode >> 21) & 0x1f; + mask = ip->insn_mo->mask; + + expr1.X_op = O_constant; + expr1.X_op_symbol = NULL; + expr1.X_add_symbol = NULL; + expr1.X_add_number = 1; + + switch (mask) + { + case M_DABS: + dbl = 1; + case M_ABS: + /* bgez $a0,.+12 + move v0,$a0 + sub v0,$zero,$a0 + */ + + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + + expr1.X_add_number = 8; + macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); + if (dreg == sreg) + macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); + else + macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dsub" : "sub", + "d,v,t", dreg, 0, sreg); + + --mips_opts.noreorder; + return; + + case M_ADD_I: + s = "addi"; + s2 = "add"; + goto do_addi; + case M_ADDU_I: + s = "addiu"; + s2 = "addu"; + goto do_addi; + case M_DADD_I: + dbl = 1; + s = "daddi"; + s2 = "dadd"; + goto do_addi; + case M_DADDU_I: + dbl = 1; + s = "daddiu"; + s2 = "daddu"; + do_addi: + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= -0x8000 + && imm_expr.X_add_number < 0x8000) + { + macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, + (int) BFD_RELOC_LO16); + return; + } + load_register (&icnt, AT, &imm_expr, dbl); + macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); + break; + + case M_AND_I: + s = "andi"; + s2 = "and"; + goto do_bit; + case M_OR_I: + s = "ori"; + s2 = "or"; + goto do_bit; + case M_NOR_I: + s = ""; + s2 = "nor"; + goto do_bit; + case M_XOR_I: + s = "xori"; + s2 = "xor"; + do_bit: + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= 0 + && imm_expr.X_add_number < 0x10000) + { + if (mask != M_NOR_I) + macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, + sreg, (int) BFD_RELOC_LO16); + else + { + macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", + treg, sreg, (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", + treg, treg, 0); + } + return; + } + + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); + break; + + case M_BEQ_I: + s = "beq"; + goto beq_i; + case M_BEQL_I: + s = "beql"; + likely = 1; + goto beq_i; + case M_BNE_I: + s = "bne"; + goto beq_i; + case M_BNEL_I: + s = "bnel"; + likely = 1; + beq_i: + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, + 0); + return; + } + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); + break; + + case M_BGEL: + likely = 1; + case M_BGE: + if (treg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bgezl" : "bgez", + "s,p", sreg); + return; + } + if (sreg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "blezl" : "blez", + "s,p", treg); + return; + } + macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", AT, 0); + break; + + case M_BGTL_I: + likely = 1; + case M_BGT_I: + /* check for > max integer */ + maxnum = 0x7fffffff; + if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) + { + maxnum <<= 16; + maxnum |= 0xffff; + maxnum <<= 16; + maxnum |= 0xffff; + } + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= maxnum + && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) + { + do_false: + /* result is always false */ + if (! likely) + { + as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); + macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); + } + else + { + as_warn ("Branch likely %s is always false", ip->insn_mo->name); + macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", + "s,t,p", 0, 0); + } + return; + } + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + imm_expr.X_add_number++; + /* FALLTHROUGH */ + case M_BGE_I: + case M_BGEL_I: + if (mask == M_BGEL_I) + likely = 1; + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bgezl" : "bgez", + "s,p", sreg); + return; + } + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bgtzl" : "bgtz", + "s,p", sreg); + return; + } + maxnum = 0x7fffffff; + if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) + { + maxnum <<= 16; + maxnum |= 0xffff; + maxnum <<= 16; + maxnum |= 0xffff; + } + maxnum = - maxnum - 1; + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number <= maxnum + && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) + { + do_true: + /* result is always true */ + as_warn ("Branch %s is always true", ip->insn_mo->name); + macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); + return; + } + set_at (&icnt, sreg, 0); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", AT, 0); + break; + + case M_BGEUL: + likely = 1; + case M_BGEU: + if (treg == 0) + goto do_true; + if (sreg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", 0, treg); + return; + } + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, + treg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", AT, 0); + break; + + case M_BGTUL_I: + likely = 1; + case M_BGTU_I: + if (sreg == 0 + || (mips_opts.isa < 3 + && imm_expr.X_op == O_constant + && imm_expr.X_add_number == 0xffffffff)) + goto do_false; + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + imm_expr.X_add_number++; + /* FALLTHROUGH */ + case M_BGEU_I: + case M_BGEUL_I: + if (mask == M_BGEUL_I) + likely = 1; + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + goto do_true; + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", sreg, 0); + return; + } + set_at (&icnt, sreg, 1); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", AT, 0); + break; + + case M_BGTL: + likely = 1; + case M_BGT: + if (treg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bgtzl" : "bgtz", + "s,p", sreg); + return; + } + if (sreg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bltzl" : "bltz", + "s,p", treg); + return; + } + macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", AT, 0); + break; + + case M_BGTUL: + likely = 1; + case M_BGTU: + if (treg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", sreg, 0); + return; + } + if (sreg == 0) + goto do_false; + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, + sreg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", AT, 0); + break; + + case M_BLEL: + likely = 1; + case M_BLE: + if (treg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "blezl" : "blez", + "s,p", sreg); + return; + } + if (sreg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bgezl" : "bgez", + "s,p", treg); + return; + } + macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", AT, 0); + break; + + case M_BLEL_I: + likely = 1; + case M_BLE_I: + maxnum = 0x7fffffff; + if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) + { + maxnum <<= 16; + maxnum |= 0xffff; + maxnum <<= 16; + maxnum |= 0xffff; + } + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= maxnum + && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) + goto do_true; + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + imm_expr.X_add_number++; + /* FALLTHROUGH */ + case M_BLT_I: + case M_BLTL_I: + if (mask == M_BLTL_I) + likely = 1; + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bltzl" : "bltz", + "s,p", sreg); + return; + } + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "blezl" : "blez", + "s,p", sreg); + return; + } + set_at (&icnt, sreg, 0); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", AT, 0); + break; + + case M_BLEUL: + likely = 1; + case M_BLEU: + if (treg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", sreg, 0); + return; + } + if (sreg == 0) + goto do_true; + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, + sreg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", AT, 0); + break; + + case M_BLEUL_I: + likely = 1; + case M_BLEU_I: + if (sreg == 0 + || (mips_opts.isa < 3 + && imm_expr.X_op == O_constant + && imm_expr.X_add_number == 0xffffffff)) + goto do_true; + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + imm_expr.X_add_number++; + /* FALLTHROUGH */ + case M_BLTU_I: + case M_BLTUL_I: + if (mask == M_BLTUL_I) + likely = 1; + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + goto do_false; + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "beql" : "beq", + "s,t,p", sreg, 0); + return; + } + set_at (&icnt, sreg, 1); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", AT, 0); + break; + + case M_BLTL: + likely = 1; + case M_BLT: + if (treg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bltzl" : "bltz", + "s,p", sreg); + return; + } + if (sreg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bgtzl" : "bgtz", + "s,p", treg); + return; + } + macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", AT, 0); + break; + + case M_BLTUL: + likely = 1; + case M_BLTU: + if (treg == 0) + goto do_false; + if (sreg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", 0, treg); + return; + } + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, + treg); + macro_build ((char *) NULL, &icnt, &offset_expr, + likely ? "bnel" : "bne", + "s,t,p", AT, 0); + break; + + case M_DDIV_3: + dbl = 1; + case M_DIV_3: + s = "mflo"; + goto do_div3; + case M_DREM_3: + dbl = 1; + case M_REM_3: + s = "mfhi"; + do_div3: + if (treg == 0) + { + as_warn ("Divide by zero."); + if (mips_trap) + macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); + else + macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); + return; + } + + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + if (mips_trap) + { + macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "ddiv" : "div", + "z,s,t", sreg, treg); + } + else + { + expr1.X_add_number = 8; + macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "ddiv" : "div", + "z,s,t", sreg, treg); + macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); + } + expr1.X_add_number = -1; + macro_build ((char *) NULL, &icnt, &expr1, + dbl ? "daddiu" : "addiu", + "t,r,j", AT, 0, (int) BFD_RELOC_LO16); + expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); + macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); + if (dbl) + { + expr1.X_add_number = 1; + macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, + (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, + 31); + } + else + { + expr1.X_add_number = 0x80000000; + macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, + (int) BFD_RELOC_HI16); + } + if (mips_trap) + macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); + else + { + expr1.X_add_number = 8; + macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); + macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); + macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); + } + --mips_opts.noreorder; + macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); + break; + + case M_DIV_3I: + s = "div"; + s2 = "mflo"; + goto do_divi; + case M_DIVU_3I: + s = "divu"; + s2 = "mflo"; + goto do_divi; + case M_REM_3I: + s = "div"; + s2 = "mfhi"; + goto do_divi; + case M_REMU_3I: + s = "divu"; + s2 = "mfhi"; + goto do_divi; + case M_DDIV_3I: + dbl = 1; + s = "ddiv"; + s2 = "mflo"; + goto do_divi; + case M_DDIVU_3I: + dbl = 1; + s = "ddivu"; + s2 = "mflo"; + goto do_divi; + case M_DREM_3I: + dbl = 1; + s = "ddiv"; + s2 = "mfhi"; + goto do_divi; + case M_DREMU_3I: + dbl = 1; + s = "ddivu"; + s2 = "mfhi"; + do_divi: + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + { + as_warn ("Divide by zero."); + if (mips_trap) + macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); + else + macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); + return; + } + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) + { + if (strcmp (s2, "mflo") == 0) + macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, + sreg); + else + macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); + return; + } + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number == -1 + && s[strlen (s) - 1] != 'u') + { + if (strcmp (s2, "mflo") == 0) + { + if (dbl) + macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, + sreg); + else + macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, + sreg); + } + else + macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); + return; + } + + load_register (&icnt, AT, &imm_expr, dbl); + macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); + macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); + break; + + case M_DIVU_3: + s = "divu"; + s2 = "mflo"; + goto do_divu3; + case M_REMU_3: + s = "divu"; + s2 = "mfhi"; + goto do_divu3; + case M_DDIVU_3: + s = "ddivu"; + s2 = "mflo"; + goto do_divu3; + case M_DREMU_3: + s = "ddivu"; + s2 = "mfhi"; + do_divu3: + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + if (mips_trap) + { + macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); + macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); + } + else + { + expr1.X_add_number = 8; + macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); + macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); + macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); + } + --mips_opts.noreorder; + macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); + return; + + case M_DLA_AB: + dbl = 1; + case M_LA_AB: + /* Load the address of a symbol into a register. If breg is not + zero, we then add a base register to it. */ + + /* When generating embedded PIC code, we permit expressions of + the form + la $4,foo-bar + where bar is an address in the .text section. These are used + when getting the addresses of functions. We don't permit + X_add_number to be non-zero, because if the symbol is + external the relaxing code needs to know that any addend is + purely the offset to X_op_symbol. */ + if (mips_pic == EMBEDDED_PIC + && offset_expr.X_op == O_subtract + && now_seg == text_section + && (offset_expr.X_op_symbol->sy_value.X_op == O_constant + ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section + : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol + && (S_GET_SEGMENT (offset_expr.X_op_symbol + ->sy_value.X_add_symbol) + == text_section))) + && breg == 0 + && offset_expr.X_add_number == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", + treg, (int) BFD_RELOC_PCREL_HI16_S); + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); + return; + } + + if (offset_expr.X_op != O_symbol + && offset_expr.X_op != O_constant) + { + as_bad ("expression too complex"); + offset_expr.X_op = O_constant; + } + + if (treg == breg) + { + tempreg = AT; + used_at = 1; + } + else + { + tempreg = treg; + used_at = 0; + } + + if (offset_expr.X_op == O_constant) + load_register (&icnt, tempreg, &offset_expr, dbl); + else if (mips_pic == NO_PIC) + { + /* If this is a reference to an GP relative symbol, we want + addiu $tempreg,$gp, (BFD_RELOC_MIPS_GPREL) + Otherwise we want + lui $tempreg, (BFD_RELOC_HI16_S) + addiu $tempreg,$tempreg, (BFD_RELOC_LO16) + If we have a constant, we need two instructions anyhow, + so we may as well always use the latter form. */ + if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET + || nopic_need_relax (offset_expr.X_add_symbol, 1)) + p = NULL; + else + { + frag_grow (20); + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); + p = frag_var (rs_machine_dependent, 8, 0, + RELAX_ENCODE (4, 8, 0, 4, 0, + mips_opts.warn_about_macros), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + } + macro_build_lui (p, &icnt, &offset_expr, tempreg); + if (p != NULL) + p += 4; + macro_build (p, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); + } + else if (mips_pic == SVR4_PIC && ! mips_big_got) + { + /* If this is a reference to an external symbol, and there + is no constant, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + For a local symbol, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $tempreg,$tempreg, (BFD_RELOC_LO16) + + If we have a small constant, and this is a reference to + an external symbol, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $tempreg,$tempreg, + For a local symbol, we want the same instruction + sequence, but we output a BFD_RELOC_LO16 reloc on the + addiu instruction. + + If we have a large constant, and this is a reference to + an external symbol, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + lui $at, + addiu $at,$at, + addu $tempreg,$tempreg,$at + For a local symbol, we want the same instruction + sequence, but we output a BFD_RELOC_LO16 reloc on the + addiu instruction. */ + expr1.X_add_number = offset_expr.X_add_number; + offset_expr.X_add_number = 0; + frag_grow (32); + macro_build ((char *) NULL, &icnt, &offset_expr, + dbl ? "ld" : "lw", + "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); + if (expr1.X_add_number == 0) + { + int off; + + if (breg == 0) + off = 0; + else + { + /* We're going to put in an addu instruction using + tempreg, so we may as well insert the nop right + now. */ + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + off = 4; + } + p = frag_var (rs_machine_dependent, 8 - off, 0, + RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, + (breg == 0 + ? mips_opts.warn_about_macros + : 0)), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + if (breg == 0) + { + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + } + macro_build (p, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); + /* FIXME: If breg == 0, and the next instruction uses + $tempreg, then if this variant case is used an extra + nop will be generated. */ + } + else if (expr1.X_add_number >= -0x8000 + && expr1.X_add_number < 0x8000) + { + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + macro_build ((char *) NULL, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); + (void) frag_var (rs_machine_dependent, 0, 0, + RELAX_ENCODE (0, 0, -12, -4, 0, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + } + else + { + int off1; + + /* If we are going to add in a base register, and the + target register and the base register are the same, + then we are using AT as a temporary register. Since + we want to load the constant into AT, we add our + current AT (from the global offset table) and the + register into the register now, and pretend we were + not using a base register. */ + if (breg != treg) + off1 = 0; + else + { + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", treg, AT, breg); + breg = 0; + tempreg = treg; + off1 = -8; + } + + /* Set mips_optimize around the lui instruction to avoid + inserting an unnecessary nop after the lw. */ + hold_mips_optimize = mips_optimize; + mips_optimize = 2; + macro_build_lui ((char *) NULL, &icnt, &expr1, AT); + mips_optimize = hold_mips_optimize; + + macro_build ((char *) NULL, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", AT, AT, (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, tempreg, AT); + (void) frag_var (rs_machine_dependent, 0, 0, + RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + used_at = 1; + } + } + else if (mips_pic == SVR4_PIC) + { + int gpdel; + + /* This is the large GOT case. If this is a reference to an + external symbol, and there is no constant, we want + lui $tempreg, (BFD_RELOC_MIPS_GOT_HI16) + addu $tempreg,$tempreg,$gp + lw $tempreg,($tempreg) (BFD_RELOC_MIPS_GOT_LO16) + For a local symbol, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $tempreg,$tempreg, (BFD_RELOC_LO16) + + If we have a small constant, and this is a reference to + an external symbol, we want + lui $tempreg, (BFD_RELOC_MIPS_GOT_HI16) + addu $tempreg,$tempreg,$gp + lw $tempreg,($tempreg) (BFD_RELOC_MIPS_GOT_LO16) + nop + addiu $tempreg,$tempreg, + For a local symbol, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $tempreg,$tempreg, (BFD_RELOC_LO16) + + If we have a large constant, and this is a reference to + an external symbol, we want + lui $tempreg, (BFD_RELOC_MIPS_GOT_HI16) + addu $tempreg,$tempreg,$gp + lw $tempreg,($tempreg) (BFD_RELOC_MIPS_GOT_LO16) + lui $at, + addiu $at,$at, + addu $tempreg,$tempreg,$at + For a local symbol, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + lui $at, + addiu $at,$at, (BFD_RELOC_LO16) + addu $tempreg,$tempreg,$at + */ + expr1.X_add_number = offset_expr.X_add_number; + offset_expr.X_add_number = 0; + frag_grow (52); + if (reg_needs_delay (GP)) + gpdel = 4; + else + gpdel = 0; + macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", + tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, tempreg, GP); + macro_build ((char *) NULL, &icnt, &offset_expr, + dbl ? "ld" : "lw", + "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, + tempreg); + if (expr1.X_add_number == 0) + { + int off; + + if (breg == 0) + off = 0; + else + { + /* We're going to put in an addu instruction using + tempreg, so we may as well insert the nop right + now. */ + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + off = 4; + } + + p = frag_var (rs_machine_dependent, 12 + gpdel, 0, + RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, + 8 + gpdel, 0, + (breg == 0 + ? mips_opts.warn_about_macros + : 0)), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + } + else if (expr1.X_add_number >= -0x8000 + && expr1.X_add_number < 0x8000) + { + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + macro_build ((char *) NULL, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); + + p = frag_var (rs_machine_dependent, 12 + gpdel, 0, + RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, + (breg == 0 + ? mips_opts.warn_about_macros + : 0)), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + } + else + { + int adj, dreg; + + /* If we are going to add in a base register, and the + target register and the base register are the same, + then we are using AT as a temporary register. Since + we want to load the constant into AT, we add our + current AT (from the global offset table) and the + register into the register now, and pretend we were + not using a base register. */ + if (breg != treg) + { + adj = 0; + dreg = tempreg; + } + else + { + assert (tempreg == AT); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", treg, AT, breg); + dreg = treg; + adj = 8; + } + + /* Set mips_optimize around the lui instruction to avoid + inserting an unnecessary nop after the lw. */ + hold_mips_optimize = mips_optimize; + mips_optimize = 2; + macro_build_lui ((char *) NULL, &icnt, &expr1, AT); + mips_optimize = hold_mips_optimize; + + macro_build ((char *) NULL, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", AT, AT, (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", dreg, dreg, AT); + + p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, + RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, + 8 + gpdel, 0, + (breg == 0 + ? mips_opts.warn_about_macros + : 0)), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + + used_at = 1; + } + + if (gpdel > 0) + { + /* This is needed because this instruction uses $gp, but + the first instruction on the main stream does not. */ + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + } + macro_build (p, &icnt, &offset_expr, + dbl ? "ld" : "lw", + "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); + p += 4; + if (expr1.X_add_number >= -0x8000 + && expr1.X_add_number < 0x8000) + { + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + macro_build (p, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); + /* FIXME: If add_number is 0, and there was no base + register, the external symbol case ended with a load, + so if the symbol turns out to not be external, and + the next instruction uses tempreg, an unnecessary nop + will be inserted. */ + } + else + { + if (breg == treg) + { + /* We must add in the base register now, as in the + external symbol case. */ + assert (tempreg == AT); + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + macro_build (p, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", treg, AT, breg); + p += 4; + tempreg = treg; + /* We set breg to 0 because we have arranged to add + it in in both cases. */ + breg = 0; + } + + macro_build_lui (p, &icnt, &expr1, AT); + p += 4; + macro_build (p, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", AT, AT, (int) BFD_RELOC_LO16); + p += 4; + macro_build (p, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, tempreg, AT); + p += 4; + } + } + else if (mips_pic == EMBEDDED_PIC) + { + /* We use + addiu $tempreg,$gp, (BFD_RELOC_MIPS_GPREL) + */ + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); + } + else + abort (); + + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", treg, tempreg, breg); + + if (! used_at) + return; + + break; + + case M_J_A: + /* The j instruction may not be used in PIC code, since it + requires an absolute address. We convert it to a b + instruction. */ + if (mips_pic == NO_PIC) + macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); + else + macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); + return; + + /* The jal instructions must be handled as macros because when + generating PIC code they expand to multi-instruction + sequences. Normally they are simple instructions. */ + case M_JAL_1: + dreg = RA; + /* Fall through. */ + case M_JAL_2: + if (mips_pic == NO_PIC + || mips_pic == EMBEDDED_PIC) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", + "d,s", dreg, sreg); + else if (mips_pic == SVR4_PIC) + { + if (sreg != PIC_CALL_REG) + as_warn ("MIPS PIC call to register other than $25"); + + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", + "d,s", dreg, sreg); + if (mips_cprestore_offset < 0) + as_warn ("No .cprestore pseudo-op used in PIC code"); + else + { + expr1.X_add_number = mips_cprestore_offset; + macro_build ((char *) NULL, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); + } + } + else + abort (); + + return; + + case M_JAL_A: + if (mips_pic == NO_PIC) + macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); + else if (mips_pic == SVR4_PIC) + { + /* If this is a reference to an external symbol, and we are + using a small GOT, we want + lw $25,($gp) (BFD_RELOC_MIPS_CALL16) + nop + jalr $25 + nop + lw $gp,cprestore($sp) + The cprestore value is set using the .cprestore + pseudo-op. If we are using a big GOT, we want + lui $25, (BFD_RELOC_MIPS_CALL_HI16) + addu $25,$25,$gp + lw $25,($25) (BFD_RELOC_MIPS_CALL_LO16) + nop + jalr $25 + nop + lw $gp,cprestore($sp) + If the symbol is not external, we want + lw $25,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $25,$25, (BFD_RELOC_LO16) + jalr $25 + nop + lw $gp,cprestore($sp) */ + frag_grow (40); + if (! mips_big_got) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", PIC_CALL_REG, + (int) BFD_RELOC_MIPS_CALL16, GP); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + p = frag_var (rs_machine_dependent, 4, 0, + RELAX_ENCODE (0, 4, -8, 0, 0, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + } + else + { + int gpdel; + + if (reg_needs_delay (GP)) + gpdel = 4; + else + gpdel = 0; + macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", + PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", PIC_CALL_REG, + (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + p = frag_var (rs_machine_dependent, 12 + gpdel, 0, + RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, + 0, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + if (gpdel > 0) + { + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + } + macro_build (p, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", PIC_CALL_REG, + (int) BFD_RELOC_MIPS_GOT16, GP); + p += 4; + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + } + macro_build (p, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", PIC_CALL_REG, PIC_CALL_REG, + (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "jalr", "s", PIC_CALL_REG); + if (mips_cprestore_offset < 0) + as_warn ("No .cprestore pseudo-op used in PIC code"); + else + { + if (mips_opts.noreorder) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "nop", ""); + expr1.X_add_number = mips_cprestore_offset; + macro_build ((char *) NULL, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", GP, (int) BFD_RELOC_LO16, + mips_frame_reg); + } + } + else if (mips_pic == EMBEDDED_PIC) + { + macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); + /* The linker may expand the call to a longer sequence which + uses $at, so we must break rather than return. */ + break; + } + else + abort (); + + return; + + case M_LB_AB: + s = "lb"; + goto ld; + case M_LBU_AB: + s = "lbu"; + goto ld; + case M_LH_AB: + s = "lh"; + goto ld; + case M_LHU_AB: + s = "lhu"; + goto ld; + case M_LW_AB: + s = "lw"; + goto ld; + case M_LWC0_AB: + s = "lwc0"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ld; + case M_LWC1_AB: + s = "lwc1"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ld; + case M_LWC2_AB: + s = "lwc2"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ld; + case M_LWC3_AB: + s = "lwc3"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ld; + case M_LWL_AB: + s = "lwl"; + lr = 1; + goto ld; + case M_LWR_AB: + s = "lwr"; + lr = 1; + goto ld; + case M_LDC1_AB: + if (mips_4650) + { + as_bad ("opcode not supported on this processor"); + return; + } + s = "ldc1"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ld; + case M_LDC2_AB: + s = "ldc2"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ld; + case M_LDC3_AB: + s = "ldc3"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ld; + case M_LDL_AB: + s = "ldl"; + lr = 1; + goto ld; + case M_LDR_AB: + s = "ldr"; + lr = 1; + goto ld; + case M_LL_AB: + s = "ll"; + goto ld; + case M_LLD_AB: + s = "lld"; + goto ld; + case M_LWU_AB: + s = "lwu"; + ld: + if (breg == treg || coproc || lr) + { + tempreg = AT; + used_at = 1; + } + else + { + tempreg = treg; + used_at = 0; + } + goto ld_st; + case M_SB_AB: + s = "sb"; + goto st; + case M_SH_AB: + s = "sh"; + goto st; + case M_SW_AB: + s = "sw"; + goto st; + case M_SWC0_AB: + s = "swc0"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto st; + case M_SWC1_AB: + s = "swc1"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto st; + case M_SWC2_AB: + s = "swc2"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto st; + case M_SWC3_AB: + s = "swc3"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto st; + case M_SWL_AB: + s = "swl"; + goto st; + case M_SWR_AB: + s = "swr"; + goto st; + case M_SC_AB: + s = "sc"; + goto st; + case M_SCD_AB: + s = "scd"; + goto st; + case M_SDC1_AB: + if (mips_4650) + { + as_bad ("opcode not supported on this processor"); + return; + } + s = "sdc1"; + coproc = 1; + /* Itbl support may require additional care here. */ + goto st; + case M_SDC2_AB: + s = "sdc2"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto st; + case M_SDC3_AB: + s = "sdc3"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto st; + case M_SDL_AB: + s = "sdl"; + goto st; + case M_SDR_AB: + s = "sdr"; + st: + tempreg = AT; + used_at = 1; + ld_st: + /* Itbl support may require additional care here. */ + if (mask == M_LWC1_AB + || mask == M_SWC1_AB + || mask == M_LDC1_AB + || mask == M_SDC1_AB + || mask == M_L_DAB + || mask == M_S_DAB) + fmt = "T,o(b)"; + else if (coproc) + fmt = "E,o(b)"; + else + fmt = "t,o(b)"; + + if (offset_expr.X_op != O_constant + && offset_expr.X_op != O_symbol) + { + as_bad ("expression too complex"); + offset_expr.X_op = O_constant; + } + + /* A constant expression in PIC code can be handled just as it + is in non PIC code. */ + if (mips_pic == NO_PIC + || offset_expr.X_op == O_constant) + { + /* If this is a reference to a GP relative symbol, and there + is no base register, we want + $treg,($gp) (BFD_RELOC_MIPS_GPREL) + Otherwise, if there is no base register, we want + lui $tempreg, (BFD_RELOC_HI16_S) + $treg,($tempreg) (BFD_RELOC_LO16) + If we have a constant, we need two instructions anyhow, + so we always use the latter form. + + If we have a base register, and this is a reference to a + GP relative symbol, we want + addu $tempreg,$breg,$gp + $treg,($tempreg) (BFD_RELOC_MIPS_GPREL) + Otherwise we want + lui $tempreg, (BFD_RELOC_HI16_S) + addu $tempreg,$tempreg,$breg + $treg,($tempreg) (BFD_RELOC_LO16) + With a constant we always use the latter case. */ + if (breg == 0) + { + if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET + || nopic_need_relax (offset_expr.X_add_symbol, 1)) + p = NULL; + else + { + frag_grow (20); + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + treg, (int) BFD_RELOC_MIPS_GPREL, GP); + p = frag_var (rs_machine_dependent, 8, 0, + RELAX_ENCODE (4, 8, 0, 4, 0, + (mips_opts.warn_about_macros + || (used_at + && mips_opts.noat))), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + used_at = 0; + } + macro_build_lui (p, &icnt, &offset_expr, tempreg); + if (p != NULL) + p += 4; + macro_build (p, &icnt, &offset_expr, s, fmt, treg, + (int) BFD_RELOC_LO16, tempreg); + } + else + { + if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET + || nopic_need_relax (offset_expr.X_add_symbol, 1)) + p = NULL; + else + { + frag_grow (28); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, breg, GP); + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); + p = frag_var (rs_machine_dependent, 12, 0, + RELAX_ENCODE (8, 12, 0, 8, 0, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + } + macro_build_lui (p, &icnt, &offset_expr, tempreg); + if (p != NULL) + p += 4; + macro_build (p, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, tempreg, breg); + if (p != NULL) + p += 4; + macro_build (p, &icnt, &offset_expr, s, fmt, treg, + (int) BFD_RELOC_LO16, tempreg); + } + } + else if (mips_pic == SVR4_PIC && ! mips_big_got) + { + /* If this is a reference to an external symbol, we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + $treg,0($tempreg) + Otherwise we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $tempreg,$tempreg, (BFD_RELOC_LO16) + $treg,0($tempreg) + If there is a base register, we add it to $tempreg before + the . If there is a constant, we stick it in the + instruction. We don't handle constants larger than + 16 bits, because we have no way to load the upper 16 bits + (actually, we could handle them for the subset of cases + in which we are not using $at). */ + assert (offset_expr.X_op == O_symbol); + expr1.X_add_number = offset_expr.X_add_number; + offset_expr.X_add_number = 0; + if (expr1.X_add_number < -0x8000 + || expr1.X_add_number >= 0x8000) + as_bad ("PIC code offset overflow (max 16 signed bits)"); + frag_grow (20); + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); + p = frag_var (rs_machine_dependent, 4, 0, + RELAX_ENCODE (0, 4, -8, 0, 0, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + macro_build (p, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, tempreg, breg); + macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, + (int) BFD_RELOC_LO16, tempreg); + } + else if (mips_pic == SVR4_PIC) + { + int gpdel; + + /* If this is a reference to an external symbol, we want + lui $tempreg, (BFD_RELOC_MIPS_GOT_HI16) + addu $tempreg,$tempreg,$gp + lw $tempreg,($tempreg) (BFD_RELOC_MIPS_GOT_LO16) + $treg,0($tempreg) + Otherwise we want + lw $tempreg,($gp) (BFD_RELOC_MIPS_GOT16) + nop + addiu $tempreg,$tempreg, (BFD_RELOC_LO16) + $treg,0($tempreg) + If there is a base register, we add it to $tempreg before + the . If there is a constant, we stick it in the + instruction. We don't handle constants larger than + 16 bits, because we have no way to load the upper 16 bits + (actually, we could handle them for the subset of cases + in which we are not using $at). */ + assert (offset_expr.X_op == O_symbol); + expr1.X_add_number = offset_expr.X_add_number; + offset_expr.X_add_number = 0; + if (expr1.X_add_number < -0x8000 + || expr1.X_add_number >= 0x8000) + as_bad ("PIC code offset overflow (max 16 signed bits)"); + if (reg_needs_delay (GP)) + gpdel = 4; + else + gpdel = 0; + frag_grow (36); + macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", + tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, tempreg, GP); + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, + tempreg); + p = frag_var (rs_machine_dependent, 12 + gpdel, 0, + RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), + offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); + if (gpdel > 0) + { + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + } + macro_build (p, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); + p += 4; + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + macro_build (p, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, tempreg, breg); + macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, + (int) BFD_RELOC_LO16, tempreg); + } + else if (mips_pic == EMBEDDED_PIC) + { + /* If there is no base register, we want + $treg,($gp) (BFD_RELOC_MIPS_GPREL) + If there is a base register, we want + addu $tempreg,$breg,$gp + $treg,($tempreg) (BFD_RELOC_MIPS_GPREL) + */ + assert (offset_expr.X_op == O_symbol); + if (breg == 0) + { + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + treg, (int) BFD_RELOC_MIPS_GPREL, GP); + used_at = 0; + } + else + { + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", tempreg, breg, GP); + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); + } + } + else + abort (); + + if (! used_at) + return; + + break; + + case M_LI: + case M_LI_S: + load_register (&icnt, treg, &imm_expr, 0); + return; + + case M_DLI: + load_register (&icnt, treg, &imm_expr, 1); + return; + + case M_LI_SS: + if (imm_expr.X_op == O_constant) + { + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "mtc1", "t,G", AT, treg); + break; + } + else + { + assert (offset_expr.X_op == O_symbol + && strcmp (segment_name (S_GET_SEGMENT + (offset_expr.X_add_symbol)), + ".lit4") == 0 + && offset_expr.X_add_number == 0); + macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", + treg, (int) BFD_RELOC_MIPS_LITERAL, GP); + return; + } + + case M_LI_D: + /* If we have a constant in IMM_EXPR, then in mips3 mode it is + the entire value, and in mips1 mode it is the high order 32 + bits of the value and the low order 32 bits are either zero + or in offset_expr. */ + if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) + { + if (mips_opts.isa >= 3) + load_register (&icnt, treg, &imm_expr, 1); + else + { + int hreg, lreg; + + if (target_big_endian) + { + hreg = treg; + lreg = treg + 1; + } + else + { + hreg = treg + 1; + lreg = treg; + } + + if (hreg <= 31) + load_register (&icnt, hreg, &imm_expr, 0); + if (lreg <= 31) + { + if (offset_expr.X_op == O_absent) + macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", + lreg, 0); + else + { + assert (offset_expr.X_op == O_constant); + load_register (&icnt, lreg, &offset_expr, 0); + } + } + } + return; + } + + /* We know that sym is in the .rdata section. First we get the + upper 16 bits of the address. */ + if (mips_pic == NO_PIC) + { + /* FIXME: This won't work for a 64 bit address. */ + macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); + } + else if (mips_pic == SVR4_PIC) + { + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); + } + else if (mips_pic == EMBEDDED_PIC) + { + /* For embedded PIC we pick up the entire address off $gp in + a single instruction. */ + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); + offset_expr.X_op = O_constant; + offset_expr.X_add_number = 0; + } + else + abort (); + + /* Now we load the register(s). */ + if (mips_opts.isa >= 3) + macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", + treg, (int) BFD_RELOC_LO16, AT); + else + { + macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", + treg, (int) BFD_RELOC_LO16, AT); + if (treg != 31) + { + /* FIXME: How in the world do we deal with the possible + overflow here? */ + offset_expr.X_add_number += 4; + macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", + treg + 1, (int) BFD_RELOC_LO16, AT); + } + } + + /* To avoid confusion in tc_gen_reloc, we must ensure that this + does not become a variant frag. */ + frag_wane (frag_now); + frag_new (0); + + break; + + case M_LI_DD: + /* If we have a constant in IMM_EXPR, then in mips3 mode it is + the entire value, and in mips1 mode it is the high order 32 + bits of the value and the low order 32 bits are either zero + or in offset_expr. */ + if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) + { + load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); + if (mips_opts.isa >= 3) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "dmtc1", "t,S", AT, treg); + else + { + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "mtc1", "t,G", AT, treg + 1); + if (offset_expr.X_op == O_absent) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "mtc1", "t,G", 0, treg); + else + { + assert (offset_expr.X_op == O_constant); + load_register (&icnt, AT, &offset_expr, 0); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "mtc1", "t,G", AT, treg); + } + } + break; + } + + assert (offset_expr.X_op == O_symbol + && offset_expr.X_add_number == 0); + s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); + if (strcmp (s, ".lit8") == 0) + { + if (mips_opts.isa >= 2) + { + macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", + "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); + return; + } + breg = GP; + r = BFD_RELOC_MIPS_LITERAL; + goto dob; + } + else + { + assert (strcmp (s, RDATA_SECTION_NAME) == 0); + if (mips_pic == SVR4_PIC) + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); + else + { + /* FIXME: This won't work for a 64 bit address. */ + macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); + } + + if (mips_opts.isa >= 2) + { + macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", + "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); + + /* To avoid confusion in tc_gen_reloc, we must ensure + that this does not become a variant frag. */ + frag_wane (frag_now); + frag_new (0); + + break; + } + breg = AT; + r = BFD_RELOC_LO16; + goto dob; + } + + case M_L_DOB: + if (mips_4650) + { + as_bad ("opcode not supported on this processor"); + return; + } + /* Even on a big endian machine $fn comes before $fn+1. We have + to adjust when loading from memory. */ + r = BFD_RELOC_LO16; + dob: + assert (mips_opts.isa < 2); + macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", + target_big_endian ? treg + 1 : treg, + (int) r, breg); + /* FIXME: A possible overflow which I don't know how to deal + with. */ + offset_expr.X_add_number += 4; + macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", + target_big_endian ? treg : treg + 1, + (int) r, breg); + + /* To avoid confusion in tc_gen_reloc, we must ensure that this + does not become a variant frag. */ + frag_wane (frag_now); + frag_new (0); + + if (breg != AT) + return; + break; + + case M_L_DAB: + /* + * The MIPS assembler seems to check for X_add_number not + * being double aligned and generating: + * lui at,%hi(foo+1) + * addu at,at,v1 + * addiu at,at,%lo(foo+1) + * lwc1 f2,0(at) + * lwc1 f3,4(at) + * But, the resulting address is the same after relocation so why + * generate the extra instruction? + */ + if (mips_4650) + { + as_bad ("opcode not supported on this processor"); + return; + } + /* Itbl support may require additional care here. */ + coproc = 1; + if (mips_opts.isa >= 2) + { + s = "ldc1"; + goto ld; + } + + s = "lwc1"; + fmt = "T,o(b)"; + goto ldd_std; + + case M_S_DAB: + if (mips_4650) + { + as_bad ("opcode not supported on this processor"); + return; + } + + if (mips_opts.isa >= 2) + { + s = "sdc1"; + goto st; + } + + s = "swc1"; + fmt = "T,o(b)"; + /* Itbl support may require additional care here. */ + coproc = 1; + goto ldd_std; + + case M_LD_AB: + if (mips_opts.isa >= 3) + { + s = "ld"; + goto ld; + } + + s = "lw"; + fmt = "t,o(b)"; + goto ldd_std; + + case M_SD_AB: + if (mips_opts.isa >= 3) + { + s = "sd"; + goto st; + } + + s = "sw"; + fmt = "t,o(b)"; + + ldd_std: + if (offset_expr.X_op != O_symbol + && offset_expr.X_op != O_constant) + { + as_bad ("expression too complex"); + offset_expr.X_op = O_constant; + } + + /* Even on a big endian machine $fn comes before $fn+1. We have + to adjust when loading from memory. We set coproc if we must + load $fn+1 first. */ + /* Itbl support may require additional care here. */ + if (! target_big_endian) + coproc = 0; + + if (mips_pic == NO_PIC + || offset_expr.X_op == O_constant) + { + /* If this is a reference to a GP relative symbol, we want + $treg,($gp) (BFD_RELOC_MIPS_GPREL) + $treg+1,+4($gp) (BFD_RELOC_MIPS_GPREL) + If we have a base register, we use this + addu $at,$breg,$gp + $treg,($at) (BFD_RELOC_MIPS_GPREL) + $treg+1,+4($at) (BFD_RELOC_MIPS_GPREL) + If this is not a GP relative symbol, we want + lui $at, (BFD_RELOC_HI16_S) + $treg,($at) (BFD_RELOC_LO16) + $treg+1,+4($at) (BFD_RELOC_LO16) + If there is a base register, we add it to $at after the + lui instruction. If there is a constant, we always use + the last case. */ + if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET + || nopic_need_relax (offset_expr.X_add_symbol, 1)) + { + p = NULL; + used_at = 1; + } + else + { + int off; + + if (breg == 0) + { + frag_grow (28); + tempreg = GP; + off = 0; + used_at = 0; + } + else + { + frag_grow (36); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, breg, GP); + tempreg = AT; + off = 4; + used_at = 1; + } + + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + coproc ? treg + 1 : treg, + (int) BFD_RELOC_MIPS_GPREL, tempreg); + offset_expr.X_add_number += 4; + + /* Set mips_optimize to 2 to avoid inserting an + undesired nop. */ + hold_mips_optimize = mips_optimize; + mips_optimize = 2; + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + coproc ? treg : treg + 1, + (int) BFD_RELOC_MIPS_GPREL, tempreg); + mips_optimize = hold_mips_optimize; + + p = frag_var (rs_machine_dependent, 12 + off, 0, + RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, + used_at && mips_opts.noat), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + + /* We just generated two relocs. When tc_gen_reloc + handles this case, it will skip the first reloc and + handle the second. The second reloc already has an + extra addend of 4, which we added above. We must + subtract it out, and then subtract another 4 to make + the first reloc come out right. The second reloc + will come out right because we are going to add 4 to + offset_expr when we build its instruction below. + + If we have a symbol, then we don't want to include + the offset, because it will wind up being included + when we generate the reloc. */ + + if (offset_expr.X_op == O_constant) + offset_expr.X_add_number -= 8; + else + { + offset_expr.X_add_number = -4; + offset_expr.X_op = O_constant; + } + } + macro_build_lui (p, &icnt, &offset_expr, AT); + if (p != NULL) + p += 4; + if (breg != 0) + { + macro_build (p, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, breg, AT); + if (p != NULL) + p += 4; + } + /* Itbl support may require additional care here. */ + macro_build (p, &icnt, &offset_expr, s, fmt, + coproc ? treg + 1 : treg, + (int) BFD_RELOC_LO16, AT); + if (p != NULL) + p += 4; + /* FIXME: How do we handle overflow here? */ + offset_expr.X_add_number += 4; + /* Itbl support may require additional care here. */ + macro_build (p, &icnt, &offset_expr, s, fmt, + coproc ? treg : treg + 1, + (int) BFD_RELOC_LO16, AT); + } + else if (mips_pic == SVR4_PIC && ! mips_big_got) + { + int off; + + /* If this is a reference to an external symbol, we want + lw $at,($gp) (BFD_RELOC_MIPS_GOT16) + nop + $treg,0($at) + $treg+1,4($at) + Otherwise we want + lw $at,($gp) (BFD_RELOC_MIPS_GOT16) + nop + $treg,($at) (BFD_RELOC_LO16) + $treg+1,+4($at) (BFD_RELOC_LO16) + If there is a base register we add it to $at before the + lwc1 instructions. If there is a constant we include it + in the lwc1 instructions. */ + used_at = 1; + expr1.X_add_number = offset_expr.X_add_number; + offset_expr.X_add_number = 0; + if (expr1.X_add_number < -0x8000 + || expr1.X_add_number >= 0x8000 - 4) + as_bad ("PIC code offset overflow (max 16 signed bits)"); + if (breg == 0) + off = 0; + else + off = 4; + frag_grow (24 + off); + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, breg, AT); + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &expr1, s, fmt, + coproc ? treg + 1 : treg, + (int) BFD_RELOC_LO16, AT); + expr1.X_add_number += 4; + + /* Set mips_optimize to 2 to avoid inserting an undesired + nop. */ + hold_mips_optimize = mips_optimize; + mips_optimize = 2; + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &expr1, s, fmt, + coproc ? treg : treg + 1, + (int) BFD_RELOC_LO16, AT); + mips_optimize = hold_mips_optimize; + + (void) frag_var (rs_machine_dependent, 0, 0, + RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + } + else if (mips_pic == SVR4_PIC) + { + int gpdel, off; + + /* If this is a reference to an external symbol, we want + lui $at, (BFD_RELOC_MIPS_GOT_HI16) + addu $at,$at,$gp + lw $at,($at) (BFD_RELOC_MIPS_GOT_LO16) + nop + $treg,0($at) + $treg+1,4($at) + Otherwise we want + lw $at,($gp) (BFD_RELOC_MIPS_GOT16) + nop + $treg,($at) (BFD_RELOC_LO16) + $treg+1,+4($at) (BFD_RELOC_LO16) + If there is a base register we add it to $at before the + lwc1 instructions. If there is a constant we include it + in the lwc1 instructions. */ + used_at = 1; + expr1.X_add_number = offset_expr.X_add_number; + offset_expr.X_add_number = 0; + if (expr1.X_add_number < -0x8000 + || expr1.X_add_number >= 0x8000 - 4) + as_bad ("PIC code offset overflow (max 16 signed bits)"); + if (reg_needs_delay (GP)) + gpdel = 4; + else + gpdel = 0; + if (breg == 0) + off = 0; + else + off = 4; + frag_grow (56); + macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", + AT, (int) BFD_RELOC_MIPS_GOT_HI16); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, AT, GP); + macro_build ((char *) NULL, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, breg, AT); + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &expr1, s, fmt, + coproc ? treg + 1 : treg, + (int) BFD_RELOC_LO16, AT); + expr1.X_add_number += 4; + + /* Set mips_optimize to 2 to avoid inserting an undesired + nop. */ + hold_mips_optimize = mips_optimize; + mips_optimize = 2; + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &expr1, s, fmt, + coproc ? treg : treg + 1, + (int) BFD_RELOC_LO16, AT); + mips_optimize = hold_mips_optimize; + expr1.X_add_number -= 4; + + p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, + RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, + 8 + gpdel + off, 1, 0), + offset_expr.X_add_symbol, (offsetT) 0, + (char *) NULL); + if (gpdel > 0) + { + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + } + macro_build (p, &icnt, &offset_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "lw" : "ld"), + "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); + p += 4; + macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); + p += 4; + if (breg != 0) + { + macro_build (p, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, breg, AT); + p += 4; + } + /* Itbl support may require additional care here. */ + macro_build (p, &icnt, &expr1, s, fmt, + coproc ? treg + 1 : treg, + (int) BFD_RELOC_LO16, AT); + p += 4; + expr1.X_add_number += 4; + + /* Set mips_optimize to 2 to avoid inserting an undesired + nop. */ + hold_mips_optimize = mips_optimize; + mips_optimize = 2; + /* Itbl support may require additional care here. */ + macro_build (p, &icnt, &expr1, s, fmt, + coproc ? treg : treg + 1, + (int) BFD_RELOC_LO16, AT); + mips_optimize = hold_mips_optimize; + } + else if (mips_pic == EMBEDDED_PIC) + { + /* If there is no base register, we use + $treg,($gp) (BFD_RELOC_MIPS_GPREL) + $treg+1,+4($gp) (BFD_RELOC_MIPS_GPREL) + If we have a base register, we use + addu $at,$breg,$gp + $treg,($at) (BFD_RELOC_MIPS_GPREL) + $treg+1,+4($at) (BFD_RELOC_MIPS_GPREL) + */ + if (breg == 0) + { + tempreg = GP; + used_at = 0; + } + else + { + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, breg, GP); + tempreg = AT; + used_at = 1; + } + + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + coproc ? treg + 1 : treg, + (int) BFD_RELOC_MIPS_GPREL, tempreg); + offset_expr.X_add_number += 4; + /* Itbl support may require additional care here. */ + macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, + coproc ? treg : treg + 1, + (int) BFD_RELOC_MIPS_GPREL, tempreg); + } + else + abort (); + + if (! used_at) + return; + + break; + + case M_LD_OB: + s = "lw"; + goto sd_ob; + case M_SD_OB: + s = "sw"; + sd_ob: + assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3); + macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, + (int) BFD_RELOC_LO16, breg); + offset_expr.X_add_number += 4; + macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, + (int) BFD_RELOC_LO16, breg); + return; + + /* New code added to support COPZ instructions. + This code builds table entries out of the macros in mip_opcodes. + R4000 uses interlocks to handle coproc delays. + Other chips (like the R3000) require nops to be inserted for delays. + + FIXME: Currently, we require that the user handle delays. + In order to fill delay slots for non-interlocked chips, + we must have a way to specify delays based on the coprocessor. + Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. + What are the side-effects of the cop instruction? + What cache support might we have and what are its effects? + Both coprocessor & memory require delays. how long??? + What registers are read/set/modified? + + If an itbl is provided to interpret cop instructions, + this knowledge can be encoded in the itbl spec. */ + + case M_COP0: + s = "c0"; + goto copz; + case M_COP1: + s = "c1"; + goto copz; + case M_COP2: + s = "c2"; + goto copz; + case M_COP3: + s = "c3"; + copz: + /* For now we just do C (same as Cz). The parameter will be + stored in insn_opcode by mips_ip. */ + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", + ip->insn_opcode); + return; + +#ifdef LOSING_COMPILER + default: + /* Try and see if this is a new itbl instruction. + This code builds table entries out of the macros in mip_opcodes. + FIXME: For now we just assemble the expression and pass it's + value along as a 32-bit immediate. + We may want to have the assembler assemble this value, + so that we gain the assembler's knowledge of delay slots, + symbols, etc. + Would it be more efficient to use mask (id) here? */ + if (itbl_have_entries + && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) + { + s = ip->insn_mo->name; + s2 = "cop3"; + coproc = ITBL_DECODE_PNUM (immed_expr);; + macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); + return; + } + macro2 (ip); + return; + } + if (mips_opts.noat) + as_warn ("Macro used $at after \".set noat\""); +} + +static void +macro2 (ip) + struct mips_cl_insn *ip; +{ + register int treg, sreg, dreg, breg; + int tempreg; + int mask; + int icnt = 0; + int used_at; + expressionS expr1; + const char *s; + const char *s2; + const char *fmt; + int likely = 0; + int dbl = 0; + int coproc = 0; + int lr = 0; + int off; + offsetT maxnum; + bfd_reloc_code_real_type r; + char *p; + + treg = (ip->insn_opcode >> 16) & 0x1f; + dreg = (ip->insn_opcode >> 11) & 0x1f; + sreg = breg = (ip->insn_opcode >> 21) & 0x1f; + mask = ip->insn_mo->mask; + + expr1.X_op = O_constant; + expr1.X_op_symbol = NULL; + expr1.X_add_symbol = NULL; + expr1.X_add_number = 1; + + switch (mask) + { +#endif /* LOSING_COMPILER */ + + case M_DMUL: + dbl = 1; + case M_MUL: + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dmultu" : "multu", + "s,t", sreg, treg); + macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); + return; + + case M_DMUL_I: + dbl = 1; + case M_MUL_I: + /* The MIPS assembler some times generates shifts and adds. I'm + not trying to be that fancy. GCC should do this for us + anyway. */ + load_register (&icnt, AT, &imm_expr, dbl); + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dmult" : "mult", + "s,t", sreg, AT); + macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); + break; + + case M_DMULO: + dbl = 1; + case M_MULO: + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dmult" : "mult", + "s,t", sreg, treg); + macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dsra32" : "sra", + "d,w,<", dreg, dreg, 31); + macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); + if (mips_trap) + macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); + else + { + expr1.X_add_number = 8; + macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); + macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); + macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); + } + --mips_opts.noreorder; + macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); + break; + + case M_DMULOU: + dbl = 1; + case M_MULOU: + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dmultu" : "multu", + "s,t", sreg, treg); + macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); + macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); + if (mips_trap) + macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); + else + { + expr1.X_add_number = 8; + macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); + macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); + macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); + } + --mips_opts.noreorder; + break; + + case M_ROL: + macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); + macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); + macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, + treg); + macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); + break; + + case M_ROL_I: + if (imm_expr.X_op != O_constant) + as_bad ("rotate count too large"); + macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, + (int) (imm_expr.X_add_number & 0x1f)); + macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, + (int) ((0 - imm_expr.X_add_number) & 0x1f)); + macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); + break; + + case M_ROR: + macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); + macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); + macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, + treg); + macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); + break; + + case M_ROR_I: + if (imm_expr.X_op != O_constant) + as_bad ("rotate count too large"); + macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, + (int) (imm_expr.X_add_number & 0x1f)); + macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, + (int) ((0 - imm_expr.X_add_number) & 0x1f)); + macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); + break; + + case M_S_DOB: + if (mips_4650) + { + as_bad ("opcode not supported on this processor"); + return; + } + assert (mips_opts.isa < 2); + /* Even on a big endian machine $fn comes before $fn+1. We have + to adjust when storing to memory. */ + macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", + target_big_endian ? treg + 1 : treg, + (int) BFD_RELOC_LO16, breg); + offset_expr.X_add_number += 4; + macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", + target_big_endian ? treg : treg + 1, + (int) BFD_RELOC_LO16, breg); + return; + + case M_SEQ: + if (sreg == 0) + macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, + treg, (int) BFD_RELOC_LO16); + else if (treg == 0) + macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, + sreg, (int) BFD_RELOC_LO16); + else + { + macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, + sreg, treg); + macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, + dreg, (int) BFD_RELOC_LO16); + } + return; + + case M_SEQ_I: + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + { + macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, + sreg, (int) BFD_RELOC_LO16); + return; + } + if (sreg == 0) + { + as_warn ("Instruction %s: result is always false", + ip->insn_mo->name); + macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); + return; + } + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= 0 + && imm_expr.X_add_number < 0x10000) + { + macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, + sreg, (int) BFD_RELOC_LO16); + used_at = 0; + } + else if (imm_expr.X_op == O_constant + && imm_expr.X_add_number > -0x8000 + && imm_expr.X_add_number < 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build ((char *) NULL, &icnt, &imm_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", dreg, sreg, + (int) BFD_RELOC_LO16); + used_at = 0; + } + else + { + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, + sreg, AT); + used_at = 1; + } + macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, + (int) BFD_RELOC_LO16); + if (used_at) + break; + return; + + case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ + s = "slt"; + goto sge; + case M_SGEU: + s = "sltu"; + sge: + macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); + macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, + (int) BFD_RELOC_LO16); + return; + + case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ + case M_SGEU_I: + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= -0x8000 + && imm_expr.X_add_number < 0x8000) + { + macro_build ((char *) NULL, &icnt, &expr1, + mask == M_SGE_I ? "slti" : "sltiu", + "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); + used_at = 0; + } + else + { + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, + mask == M_SGE_I ? "slt" : "sltu", + "d,v,t", dreg, sreg, AT); + used_at = 1; + } + macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, + (int) BFD_RELOC_LO16); + if (used_at) + break; + return; + + case M_SGT: /* sreg > treg <==> treg < sreg */ + s = "slt"; + goto sgt; + case M_SGTU: + s = "sltu"; + sgt: + macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); + return; + + case M_SGT_I: /* sreg > I <==> I < sreg */ + s = "slt"; + goto sgti; + case M_SGTU_I: + s = "sltu"; + sgti: + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); + break; + + case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ + s = "slt"; + goto sle; + case M_SLEU: + s = "sltu"; + sle: + macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); + macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, + (int) BFD_RELOC_LO16); + return; + + case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ + s = "slt"; + goto slei; + case M_SLEU_I: + s = "sltu"; + slei: + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); + macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, + (int) BFD_RELOC_LO16); + break; + + case M_SLT_I: + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= -0x8000 + && imm_expr.X_add_number < 0x8000) + { + macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", + dreg, sreg, (int) BFD_RELOC_LO16); + return; + } + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); + break; + + case M_SLTU_I: + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= -0x8000 + && imm_expr.X_add_number < 0x8000) + { + macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", + dreg, sreg, (int) BFD_RELOC_LO16); + return; + } + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, + AT); + break; + + case M_SNE: + if (sreg == 0) + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, + treg); + else if (treg == 0) + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, + sreg); + else + { + macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, + sreg, treg); + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, + dreg); + } + return; + + case M_SNE_I: + if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) + { + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, + sreg); + return; + } + if (sreg == 0) + { + as_warn ("Instruction %s: result is always true", + ip->insn_mo->name); + macro_build ((char *) NULL, &icnt, &expr1, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); + return; + } + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number >= 0 + && imm_expr.X_add_number < 0x10000) + { + macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", + dreg, sreg, (int) BFD_RELOC_LO16); + used_at = 0; + } + else if (imm_expr.X_op == O_constant + && imm_expr.X_add_number > -0x8000 + && imm_expr.X_add_number < 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build ((char *) NULL, &icnt, &imm_expr, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addiu" : "daddiu"), + "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); + used_at = 0; + } + else + { + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, + sreg, AT); + used_at = 1; + } + macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); + if (used_at) + break; + return; + + case M_DSUB_I: + dbl = 1; + case M_SUB_I: + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number > -0x8000 + && imm_expr.X_add_number <= 0x8000) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build ((char *) NULL, &icnt, &imm_expr, + dbl ? "daddi" : "addi", + "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); + return; + } + load_register (&icnt, AT, &imm_expr, dbl); + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dsub" : "sub", + "d,v,t", dreg, sreg, AT); + break; + + case M_DSUBU_I: + dbl = 1; + case M_SUBU_I: + if (imm_expr.X_op == O_constant + && imm_expr.X_add_number > -0x8000 + && imm_expr.X_add_number <= 0x8000) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build ((char *) NULL, &icnt, &imm_expr, + dbl ? "daddiu" : "addiu", + "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); + return; + } + load_register (&icnt, AT, &imm_expr, dbl); + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dsubu" : "subu", + "d,v,t", dreg, sreg, AT); + break; + + case M_TEQ_I: + s = "teq"; + goto trap; + case M_TGE_I: + s = "tge"; + goto trap; + case M_TGEU_I: + s = "tgeu"; + goto trap; + case M_TLT_I: + s = "tlt"; + goto trap; + case M_TLTU_I: + s = "tltu"; + goto trap; + case M_TNE_I: + s = "tne"; + trap: + load_register (&icnt, AT, &imm_expr, 0); + macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); + break; + + case M_TRUNCWD: + case M_TRUNCWS: + assert (mips_opts.isa < 2); + sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ + dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ + + /* + * Is the double cfc1 instruction a bug in the mips assembler; + * or is there a reason for it? + */ + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); + macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); + macro_build ((char *) NULL, &icnt, NULL, "nop", ""); + expr1.X_add_number = 3; + macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, + (int) BFD_RELOC_LO16); + expr1.X_add_number = 2; + macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, + (int) BFD_RELOC_LO16); + macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); + macro_build ((char *) NULL, &icnt, NULL, "nop", ""); + macro_build ((char *) NULL, &icnt, NULL, + mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); + macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); + macro_build ((char *) NULL, &icnt, NULL, "nop", ""); + --mips_opts.noreorder; + break; + + case M_ULH: + s = "lb"; + goto ulh; + case M_ULHU: + s = "lbu"; + ulh: + if (offset_expr.X_add_number >= 0x7fff) + as_bad ("operand overflow"); + /* avoid load delay */ + if (! target_big_endian) + offset_expr.X_add_number += 1; + macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, + (int) BFD_RELOC_LO16, breg); + if (! target_big_endian) + offset_expr.X_add_number -= 1; + else + offset_expr.X_add_number += 1; + macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, + (int) BFD_RELOC_LO16, breg); + macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); + macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); + break; + + case M_ULD: + s = "ldl"; + s2 = "ldr"; + off = 7; + goto ulw; + case M_ULW: + s = "lwl"; + s2 = "lwr"; + off = 3; + ulw: + if (offset_expr.X_add_number >= 0x8000 - off) + as_bad ("operand overflow"); + if (! target_big_endian) + offset_expr.X_add_number += off; + macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, + (int) BFD_RELOC_LO16, breg); + if (! target_big_endian) + offset_expr.X_add_number -= off; + else + offset_expr.X_add_number += off; + macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, + (int) BFD_RELOC_LO16, breg); + return; + + case M_ULD_A: + s = "ldl"; + s2 = "ldr"; + off = 7; + goto ulwa; + case M_ULW_A: + s = "lwl"; + s2 = "lwr"; + off = 3; + ulwa: + load_address (&icnt, AT, &offset_expr); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, AT, breg); + if (! target_big_endian) + expr1.X_add_number = off; + else + expr1.X_add_number = 0; + macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, + (int) BFD_RELOC_LO16, AT); + if (! target_big_endian) + expr1.X_add_number = 0; + else + expr1.X_add_number = off; + macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, + (int) BFD_RELOC_LO16, AT); + break; + + case M_ULH_A: + case M_ULHU_A: + load_address (&icnt, AT, &offset_expr); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, AT, breg); + if (target_big_endian) + expr1.X_add_number = 0; + macro_build ((char *) NULL, &icnt, &expr1, + mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, + (int) BFD_RELOC_LO16, AT); + if (target_big_endian) + expr1.X_add_number = 1; + else + expr1.X_add_number = 0; + macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, + (int) BFD_RELOC_LO16, AT); + macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, + treg, 8); + macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, + treg, AT); + break; + + case M_USH: + if (offset_expr.X_add_number >= 0x7fff) + as_bad ("operand overflow"); + if (target_big_endian) + offset_expr.X_add_number += 1; + macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, + (int) BFD_RELOC_LO16, breg); + macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); + if (target_big_endian) + offset_expr.X_add_number -= 1; + else + offset_expr.X_add_number += 1; + macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, + (int) BFD_RELOC_LO16, breg); + break; + + case M_USD: + s = "sdl"; + s2 = "sdr"; + off = 7; + goto usw; + case M_USW: + s = "swl"; + s2 = "swr"; + off = 3; + usw: + if (offset_expr.X_add_number >= 0x8000 - off) + as_bad ("operand overflow"); + if (! target_big_endian) + offset_expr.X_add_number += off; + macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, + (int) BFD_RELOC_LO16, breg); + if (! target_big_endian) + offset_expr.X_add_number -= off; + else + offset_expr.X_add_number += off; + macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, + (int) BFD_RELOC_LO16, breg); + return; + + case M_USD_A: + s = "sdl"; + s2 = "sdr"; + off = 7; + goto uswa; + case M_USW_A: + s = "swl"; + s2 = "swr"; + off = 3; + uswa: + load_address (&icnt, AT, &offset_expr); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, AT, breg); + if (! target_big_endian) + expr1.X_add_number = off; + else + expr1.X_add_number = 0; + macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, + (int) BFD_RELOC_LO16, AT); + if (! target_big_endian) + expr1.X_add_number = 0; + else + expr1.X_add_number = off; + macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, + (int) BFD_RELOC_LO16, AT); + break; + + case M_USH_A: + load_address (&icnt, AT, &offset_expr); + if (breg != 0) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", AT, AT, breg); + if (! target_big_endian) + expr1.X_add_number = 0; + macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, + (int) BFD_RELOC_LO16, AT); + macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, + treg, 8); + if (! target_big_endian) + expr1.X_add_number = 1; + else + expr1.X_add_number = 0; + macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, + (int) BFD_RELOC_LO16, AT); + if (! target_big_endian) + expr1.X_add_number = 0; + else + expr1.X_add_number = 1; + macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, + (int) BFD_RELOC_LO16, AT); + macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, + treg, 8); + macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, + treg, AT); + break; + + default: + /* FIXME: Check if this is one of the itbl macros, since they + are added dynamically. */ + as_bad ("Macro %s not implemented yet", ip->insn_mo->name); + break; + } + if (mips_opts.noat) + as_warn ("Macro used $at after \".set noat\""); +} + +/* Implement macros in mips16 mode. */ + +static void +mips16_macro (ip) + struct mips_cl_insn *ip; +{ + int mask; + int xreg, yreg, zreg, tmp; + int icnt; + expressionS expr1; + int dbl; + const char *s, *s2, *s3; + + mask = ip->insn_mo->mask; + + xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; + zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + + icnt = 0; + + expr1.X_op = O_constant; + expr1.X_op_symbol = NULL; + expr1.X_add_symbol = NULL; + expr1.X_add_number = 1; + + dbl = 0; + + switch (mask) + { + default: + internalError (); + + case M_DDIV_3: + dbl = 1; + case M_DIV_3: + s = "mflo"; + goto do_div3; + case M_DREM_3: + dbl = 1; + case M_REM_3: + s = "mfhi"; + do_div3: + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "ddiv" : "div", + "0,x,y", xreg, yreg); + expr1.X_add_number = 2; + macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); + macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); + /* FIXME: The normal code checks for of -1 / -0x80000000 here, + since that causes an overflow. We should do that as well, + but I don't see how to do the comparisons without a temporary + register. */ + --mips_opts.noreorder; + macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); + break; + + case M_DIVU_3: + s = "divu"; + s2 = "mflo"; + goto do_divu3; + case M_REMU_3: + s = "divu"; + s2 = "mfhi"; + goto do_divu3; + case M_DDIVU_3: + s = "ddivu"; + s2 = "mflo"; + goto do_divu3; + case M_DREMU_3: + s = "ddivu"; + s2 = "mfhi"; + do_divu3: + mips_emit_delays (true); + ++mips_opts.noreorder; + mips_any_noreorder = 1; + macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); + expr1.X_add_number = 2; + macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); + macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); + --mips_opts.noreorder; + macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); + break; + + case M_DMUL: + dbl = 1; + case M_MUL: + macro_build ((char *) NULL, &icnt, NULL, + dbl ? "dmultu" : "multu", + "x,y", xreg, yreg); + macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); + return; + + case M_DSUBU_I: + dbl = 1; + goto do_subu; + case M_SUBU_I: + do_subu: + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build ((char *) NULL, &icnt, &imm_expr, + dbl ? "daddiu" : "addiu", + "y,x,4", yreg, xreg); + break; + + case M_SUBU_I_2: + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", + "x,k", xreg); + break; + + case M_DSUBU_I_2: + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", + "y,j", yreg); + break; + + case M_BEQ: + s = "cmp"; + s2 = "bteqz"; + goto do_branch; + case M_BNE: + s = "cmp"; + s2 = "btnez"; + goto do_branch; + case M_BLT: + s = "slt"; + s2 = "btnez"; + goto do_branch; + case M_BLTU: + s = "sltu"; + s2 = "btnez"; + goto do_branch; + case M_BLE: + s = "slt"; + s2 = "bteqz"; + goto do_reverse_branch; + case M_BLEU: + s = "sltu"; + s2 = "bteqz"; + goto do_reverse_branch; + case M_BGE: + s = "slt"; + s2 = "bteqz"; + goto do_branch; + case M_BGEU: + s = "sltu"; + s2 = "bteqz"; + goto do_branch; + case M_BGT: + s = "slt"; + s2 = "btnez"; + goto do_reverse_branch; + case M_BGTU: + s = "sltu"; + s2 = "btnez"; + + do_reverse_branch: + tmp = xreg; + xreg = yreg; + yreg = tmp; + + do_branch: + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", + xreg, yreg); + macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); + break; + + case M_BEQ_I: + s = "cmpi"; + s2 = "bteqz"; + s3 = "x,U"; + goto do_branch_i; + case M_BNE_I: + s = "cmpi"; + s2 = "btnez"; + s3 = "x,U"; + goto do_branch_i; + case M_BLT_I: + s = "slti"; + s2 = "btnez"; + s3 = "x,8"; + goto do_branch_i; + case M_BLTU_I: + s = "sltiu"; + s2 = "btnez"; + s3 = "x,8"; + goto do_branch_i; + case M_BLE_I: + s = "slti"; + s2 = "btnez"; + s3 = "x,8"; + goto do_addone_branch_i; + case M_BLEU_I: + s = "sltiu"; + s2 = "btnez"; + s3 = "x,8"; + goto do_addone_branch_i; + case M_BGE_I: + s = "slti"; + s2 = "bteqz"; + s3 = "x,8"; + goto do_branch_i; + case M_BGEU_I: + s = "sltiu"; + s2 = "bteqz"; + s3 = "x,8"; + goto do_branch_i; + case M_BGT_I: + s = "slti"; + s2 = "bteqz"; + s3 = "x,8"; + goto do_addone_branch_i; + case M_BGTU_I: + s = "sltiu"; + s2 = "bteqz"; + s3 = "x,8"; + + do_addone_branch_i: + if (imm_expr.X_op != O_constant) + as_bad ("Unsupported large constant"); + ++imm_expr.X_add_number; + + do_branch_i: + macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); + macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); + break; + + case M_ABS: + expr1.X_add_number = 0; + macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); + if (xreg != yreg) + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "move", "y,X", xreg, yreg); + expr1.X_add_number = 2; + macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + "neg", "x,w", xreg, xreg); + } +} + +/* For consistency checking, verify that all bits are specified either + by the match/mask part of the instruction definition, or by the + operand list. */ +static int +validate_mips_insn (opc) + const struct mips_opcode *opc; +{ + const char *p = opc->args; + char c; + unsigned long used_bits = opc->mask; + + if ((used_bits & opc->match) != opc->match) + { + as_bad ("internal: bad mips opcode (mask error): %s %s", + opc->name, opc->args); + return 0; + } +#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) + while (*p) + switch (c = *p++) + { + case ',': break; + case '(': break; + case ')': break; + case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; + case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; + case 'A': break; + case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; + case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; + case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; + case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; + case 'F': break; + case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; + case 'I': break; + case 'L': break; + case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; + case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; + case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; + case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; + case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; + case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; + case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; + case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; + case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; + case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; + case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; + case 'f': break; + case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; + case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; + case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; + case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; + case 'l': break; + case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; + case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; + case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; + case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; + case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; + case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; + case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; + case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; + case 'x': break; + case 'z': break; + case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; + default: + as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s", + c, opc->name, opc->args); + return 0; + } +#undef USE_BITS + /* Some of the trapping instructions (break, t*, sdbbp) have "code" + fields that cannot currently be set by assembly code. Ignore them + for now. */ + if (opc->pinfo & INSN_TRAP) + { + static const char *const trap_insns[] = { + "break", "sdbbp", + "teq", "tge", "tgeu", "tlt", "tltu", "tne", + }; + int i; + for (i = sizeof(trap_insns)/sizeof(trap_insns[0]) - 1; i >= 0; i--) + if (!strcmp (trap_insns[i], opc->name)) + { + used_bits |= 0xffc0; + break; + } + } + if (used_bits != 0xffffffff) + { + as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s", + ~used_bits & 0xffffffff, opc->name, opc->args); + return 0; + } + return 1; +} + +/* This routine assembles an instruction into its binary format. As a + side effect, it sets one of the global variables imm_reloc or + offset_reloc to the type of relocation to do if one of the operands + is an address expression. */ + +static void +mips_ip (str, ip) + char *str; + struct mips_cl_insn *ip; +{ + char *s; + const char *args; + char c; + struct mips_opcode *insn; + char *argsStart; + unsigned int regno; + unsigned int lastregno = 0; + char *s_reset; + char save_c = 0; + + insn_error = NULL; + + /* If the instruction contains a '.', we first try to match an instruction + including the '.'. Then we try again without the '.'. */ + insn = NULL; + for (s = str; *s != '\0' && !isspace(*s); ++s) + continue; + + /* If we stopped on whitespace, then replace the whitespace with null for + the call to hash_find. Save the character we replaced just in case we + have to re-parse the instruction. */ + if (isspace (*s)) + { + save_c = *s; + *s++ = '\0'; + } + + insn = (struct mips_opcode *) hash_find (op_hash, str); + + /* If we didn't find the instruction in the opcode table, try again, but + this time with just the instruction up to, but not including the + first '.'. */ + if (insn == NULL) + { + /* Restore the character we overwrite above (if any). */ + if (save_c) + *(--s) = save_c; + + /* Scan up to the first '.' or whitespace. */ + for (s = str; *s != '\0' && *s != '.' && !isspace (*s); ++s) + continue; + + /* If we did not find a '.', then we can quit now. */ + if (*s != '.') + { + insn_error = "unrecognized opcode"; + return; + } + + /* Lookup the instruction in the hash table. */ + *s++ = '\0'; + if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) + { + insn_error = "unrecognized opcode"; + return; + } + } + + argsStart = s; + for (;;) + { + int insn_isa; + boolean ok; + + assert (strcmp (insn->name, str) == 0); + + if ((insn->membership & INSN_ISA) == INSN_ISA1) + insn_isa = 1; + else if ((insn->membership & INSN_ISA) == INSN_ISA2) + insn_isa = 2; + else if ((insn->membership & INSN_ISA) == INSN_ISA3) + insn_isa = 3; + else if ((insn->membership & INSN_ISA) == INSN_ISA4) + insn_isa = 4; + else + insn_isa = 15; + + if (insn_isa <= mips_opts.isa) + ok = true; + else if (insn->pinfo == INSN_MACRO) + ok = false; + else if ((mips_4650 && (insn->membership & INSN_4650) != 0) + || (mips_4010 && (insn->membership & INSN_4010) != 0) + || (mips_4100 && (insn->membership & INSN_4100) != 0) + || (mips_3900 && (insn->membership & INSN_3900) != 0)) + ok = true; + else + ok = false; + + if (insn->pinfo != INSN_MACRO) + { + if (mips_4650 && (insn->pinfo & FP_D) != 0) + ok = false; + } + + if (! ok) + { + if (insn + 1 < &mips_opcodes[NUMOPCODES] + && strcmp (insn->name, insn[1].name) == 0) + { + ++insn; + continue; + } + if (insn_isa == 15 + || insn_isa <= mips_opts.isa) + insn_error = "opcode not supported on this processor"; + else + { + static char buf[100]; + + sprintf (buf, "opcode requires -mips%d or greater", insn_isa); + insn_error = buf; + } + return; + } + + ip->insn_mo = insn; + ip->insn_opcode = insn->match; + for (args = insn->args;; ++args) + { + if (*s == ' ') + ++s; + switch (*args) + { + case '\0': /* end of args */ + if (*s == '\0') + return; + break; + + case ',': + if (*s++ == *args) + continue; + s--; + switch (*++args) + { + case 'r': + case 'v': + ip->insn_opcode |= lastregno << 21; + continue; + + case 'w': + case 'W': + ip->insn_opcode |= lastregno << 16; + continue; + + case 'V': + ip->insn_opcode |= lastregno << 11; + continue; + } + break; + + case '(': + /* Handle optional base register. + Either the base register is omitted or + we must have a left paren. */ + /* This is dependent on the next operand specifier + is a base register specification. */ + assert (args[1] == 'b' || args[1] == '5' + || args[1] == '-' || args[1] == '4'); + if (*s == '\0') + return; + + case ')': /* these must match exactly */ + if (*s++ == *args) + continue; + break; + + case '<': /* must be at least one digit */ + /* + * According to the manual, if the shift amount is greater + * than 31 or less than 0 the the shift amount should be + * mod 32. In reality the mips assembler issues an error. + * We issue a warning and mask out all but the low 5 bits. + */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > 31) + { + as_warn ("Improper shift amount (%ld)", + (long) imm_expr.X_add_number); + imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; + } + ip->insn_opcode |= imm_expr.X_add_number << 6; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case '>': /* shift amount minus 32 */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number < 32 + || (unsigned long) imm_expr.X_add_number > 63) + break; + ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + + case 'k': /* cache code */ + case 'h': /* prefx code */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > 31) + { + as_warn ("Invalid value for `%s' (%lu)", + ip->insn_mo->name, + (unsigned long) imm_expr.X_add_number); + imm_expr.X_add_number &= 0x1f; + } + if (*args == 'k') + ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; + else + ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case 'c': /* break code */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned) imm_expr.X_add_number > 1023) + as_warn ("Illegal break code (%ld)", + (long) imm_expr.X_add_number); + ip->insn_opcode |= imm_expr.X_add_number << 16; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case 'B': /* syscall code */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned) imm_expr.X_add_number > 0xfffff) + as_warn ("Illegal syscall code (%ld)", + (long) imm_expr.X_add_number); + ip->insn_opcode |= imm_expr.X_add_number << 6; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case 'C': /* Coprocessor code */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number >= (1<<25)) + { + as_warn ("Coproccesor code > 25 bits (%ld)", + (long) imm_expr.X_add_number); + imm_expr.X_add_number &= ((1<<25) - 1); + } + ip->insn_opcode |= imm_expr.X_add_number; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case 'P': /* Performance register */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) + { + as_warn ("Invalidate performance regster (%ld)", + (long) imm_expr.X_add_number); + imm_expr.X_add_number &= 1; + } + ip->insn_opcode |= (imm_expr.X_add_number << 1); + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case 'b': /* base register */ + case 'd': /* destination register */ + case 's': /* source register */ + case 't': /* target register */ + case 'r': /* both target and source */ + case 'v': /* both dest and source */ + case 'w': /* both dest and target */ + case 'E': /* coprocessor target register */ + case 'G': /* coprocessor destination register */ + case 'x': /* ignore register name */ + case 'z': /* must be zero register */ + s_reset = s; + if (s[0] == '$') + { + if (isdigit (s[1])) + { + ++s; + regno = 0; + do + { + regno *= 10; + regno += *s - '0'; + ++s; + } + while (isdigit (*s)); + if (regno > 31) + as_bad ("Invalid register number (%d)", regno); + } + else if (*args == 'E' || *args == 'G') + goto notreg; + else + { + if (s[1] == 'f' && s[2] == 'p') + { + s += 3; + regno = FP; + } + else if (s[1] == 's' && s[2] == 'p') + { + s += 3; + regno = SP; + } + else if (s[1] == 'g' && s[2] == 'p') + { + s += 3; + regno = GP; + } + else if (s[1] == 'a' && s[2] == 't') + { + s += 3; + regno = AT; + } + else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') + { + s += 4; + regno = KT0; + } + else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') + { + s += 4; + regno = KT1; + } + else if (itbl_have_entries) + { + char *p, *n; + int r; + + p = s+1; /* advance past '$' */ + n = itbl_get_field (&p); /* n is name */ + + /* See if this is a register defined in an + itbl entry */ + r = itbl_get_reg_val (n); + if (r) + { + /* Get_field advances to the start of + the next field, so we need to back + rack to the end of the last field. */ + if (p) + s = p - 1; + else + s = strchr (s,'\0'); + regno = r; + } + else + goto notreg; + } + else + goto notreg; + } + if (regno == AT + && ! mips_opts.noat + && *args != 'E' + && *args != 'G') + as_warn ("Used $at without \".set noat\""); + c = *args; + if (*s == ' ') + s++; + if (args[1] != *s) + { + if (c == 'r' || c == 'v' || c == 'w') + { + regno = lastregno; + s = s_reset; + args++; + } + } + /* 'z' only matches $0. */ + if (c == 'z' && regno != 0) + break; + + /* Now that we have assembled one operand, we use the args string + * to figure out where it goes in the instruction. */ + switch (c) + { + case 'r': + case 's': + case 'v': + case 'b': + ip->insn_opcode |= regno << 21; + break; + case 'd': + case 'G': + ip->insn_opcode |= regno << 11; + break; + case 'w': + case 't': + case 'E': + ip->insn_opcode |= regno << 16; + break; + case 'x': + /* This case exists because on the r3000 trunc + expands into a macro which requires a gp + register. On the r6000 or r4000 it is + assembled into a single instruction which + ignores the register. Thus the insn version + is MIPS_ISA2 and uses 'x', and the macro + version is MIPS_ISA1 and uses 't'. */ + break; + case 'z': + /* This case is for the div instruction, which + acts differently if the destination argument + is $0. This only matches $0, and is checked + outside the switch. */ + break; + case 'D': + /* Itbl operand; not yet implemented. FIXME ?? */ + break; + /* What about all other operands like 'i', which + can be specified in the opcode table? */ + } + lastregno = regno; + continue; + } + notreg: + switch (*args++) + { + case 'r': + case 'v': + ip->insn_opcode |= lastregno << 21; + continue; + case 'w': + ip->insn_opcode |= lastregno << 16; + continue; + } + break; + + case 'D': /* floating point destination register */ + case 'S': /* floating point source register */ + case 'T': /* floating point target register */ + case 'R': /* floating point source register */ + case 'V': + case 'W': + s_reset = s; + if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) + { + s += 2; + regno = 0; + do + { + regno *= 10; + regno += *s - '0'; + ++s; + } + while (isdigit (*s)); + + if (regno > 31) + as_bad ("Invalid float register number (%d)", regno); + + if ((regno & 1) != 0 + && mips_opts.isa < 3 + && ! (strcmp (str, "mtc1") == 0 + || strcmp (str, "mfc1") == 0 + || strcmp (str, "lwc1") == 0 + || strcmp (str, "swc1") == 0 + || strcmp (str, "l.s") == 0 + || strcmp (str, "s.s") == 0)) + as_warn ("Float register should be even, was %d", + regno); + + c = *args; + if (*s == ' ') + s++; + if (args[1] != *s) + { + if (c == 'V' || c == 'W') + { + regno = lastregno; + s = s_reset; + args++; + } + } + switch (c) + { + case 'D': + ip->insn_opcode |= regno << 6; + break; + case 'V': + case 'S': + ip->insn_opcode |= regno << 11; + break; + case 'W': + case 'T': + ip->insn_opcode |= regno << 16; + break; + case 'R': + ip->insn_opcode |= regno << 21; + break; + } + lastregno = regno; + continue; + } + + + switch (*args++) + { + case 'V': + ip->insn_opcode |= lastregno << 11; + continue; + case 'W': + ip->insn_opcode |= lastregno << 16; + continue; + } + break; + + case 'I': + my_getExpression (&imm_expr, s); + if (imm_expr.X_op != O_big + && imm_expr.X_op != O_constant) + insn_error = "absolute expression required"; + s = expr_end; + continue; + + case 'A': + my_getExpression (&offset_expr, s); + imm_reloc = BFD_RELOC_32; + s = expr_end; + continue; + + case 'F': + case 'L': + case 'f': + case 'l': + { + int f64; + char *save_in; + char *err; + unsigned char temp[8]; + int len; + unsigned int length; + segT seg; + subsegT subseg; + char *p; + + /* These only appear as the last operand in an + instruction, and every instruction that accepts + them in any variant accepts them in all variants. + This means we don't have to worry about backing out + any changes if the instruction does not match. + + The difference between them is the size of the + floating point constant and where it goes. For 'F' + and 'L' the constant is 64 bits; for 'f' and 'l' it + is 32 bits. Where the constant is placed is based + on how the MIPS assembler does things: + F -- .rdata + L -- .lit8 + f -- immediate value + l -- .lit4 + + The .lit4 and .lit8 sections are only used if + permitted by the -G argument. + + When generating embedded PIC code, we use the + .lit8 section but not the .lit4 section (we can do + .lit4 inline easily; we need to put .lit8 + somewhere in the data segment, and using .lit8 + permits the linker to eventually combine identical + .lit8 entries). */ + + f64 = *args == 'F' || *args == 'L'; + + save_in = input_line_pointer; + input_line_pointer = s; + err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); + length = len; + s = input_line_pointer; + input_line_pointer = save_in; + if (err != NULL && *err != '\0') + { + as_bad ("Bad floating point constant: %s", err); + memset (temp, '\0', sizeof temp); + length = f64 ? 8 : 4; + } + + assert (length == (f64 ? 8 : 4)); + + if (*args == 'f' + || (*args == 'l' + && (! USE_GLOBAL_POINTER_OPT + || mips_pic == EMBEDDED_PIC + || g_switch_value < 4 + || (temp[0] == 0 && temp[1] == 0) + || (temp[2] == 0 && temp[3] == 0)))) + { + imm_expr.X_op = O_constant; + if (! target_big_endian) + imm_expr.X_add_number = bfd_getl32 (temp); + else + imm_expr.X_add_number = bfd_getb32 (temp); + } + else if (length > 4 + && ((temp[0] == 0 && temp[1] == 0) + || (temp[2] == 0 && temp[3] == 0)) + && ((temp[4] == 0 && temp[5] == 0) + || (temp[6] == 0 && temp[7] == 0))) + { + /* The value is simple enough to load with a + couple of instructions. In mips1 mode, set + imm_expr to the high order 32 bits and + offset_expr to the low order 32 bits. + Otherwise, set imm_expr to the entire 64 bit + constant. */ + if (mips_opts.isa < 3) + { + imm_expr.X_op = O_constant; + offset_expr.X_op = O_constant; + if (! target_big_endian) + { + imm_expr.X_add_number = bfd_getl32 (temp + 4); + offset_expr.X_add_number = bfd_getl32 (temp); + } + else + { + imm_expr.X_add_number = bfd_getb32 (temp); + offset_expr.X_add_number = bfd_getb32 (temp + 4); + } + if (offset_expr.X_add_number == 0) + offset_expr.X_op = O_absent; + } + else if (sizeof (imm_expr.X_add_number) > 4) + { + imm_expr.X_op = O_constant; + if (! target_big_endian) + imm_expr.X_add_number = bfd_getl64 (temp); + else + imm_expr.X_add_number = bfd_getb64 (temp); + } + else + { + imm_expr.X_op = O_big; + imm_expr.X_add_number = 4; + if (! target_big_endian) + { + generic_bignum[0] = bfd_getl16 (temp); + generic_bignum[1] = bfd_getl16 (temp + 2); + generic_bignum[2] = bfd_getl16 (temp + 4); + generic_bignum[3] = bfd_getl16 (temp + 6); + } + else + { + generic_bignum[0] = bfd_getb16 (temp + 6); + generic_bignum[1] = bfd_getb16 (temp + 4); + generic_bignum[2] = bfd_getb16 (temp + 2); + generic_bignum[3] = bfd_getb16 (temp); + } + } + } + else + { + const char *newname; + segT new_seg; + + /* Switch to the right section. */ + seg = now_seg; + subseg = now_subseg; + switch (*args) + { + default: /* unused default case avoids warnings. */ + case 'L': + newname = RDATA_SECTION_NAME; + if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) + newname = ".lit8"; + break; + case 'F': + newname = RDATA_SECTION_NAME; + break; + case 'l': + assert (!USE_GLOBAL_POINTER_OPT + || g_switch_value >= 4); + newname = ".lit4"; + break; + } + new_seg = subseg_new (newname, (subsegT) 0); + if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + bfd_set_section_flags (stdoutput, new_seg, + (SEC_ALLOC + | SEC_LOAD + | SEC_READONLY + | SEC_DATA)); + frag_align (*args == 'l' ? 2 : 3, 0, 0); + if (OUTPUT_FLAVOR == bfd_target_elf_flavour + && strcmp (TARGET_OS, "elf") != 0) + record_alignment (new_seg, 4); + else + record_alignment (new_seg, *args == 'l' ? 2 : 3); + if (seg == now_seg) + as_bad ("Can't use floating point insn in this section"); + + /* Set the argument to the current address in the + section. */ + offset_expr.X_op = O_symbol; + offset_expr.X_add_symbol = + symbol_new ("L0\001", now_seg, + (valueT) frag_now_fix (), frag_now); + offset_expr.X_add_number = 0; + + /* Put the floating point number into the section. */ + p = frag_more ((int) length); + memcpy (p, temp, length); + + /* Switch back to the original section. */ + subseg_set (seg, subseg); + } + } + continue; + + case 'i': /* 16 bit unsigned immediate */ + case 'j': /* 16 bit signed immediate */ + imm_reloc = BFD_RELOC_LO16; + c = my_getSmallExpression (&imm_expr, s); + if (c != '\0') + { + if (c != 'l') + { + if (imm_expr.X_op == O_constant) + imm_expr.X_add_number = + (imm_expr.X_add_number >> 16) & 0xffff; + else if (c == 'h') + { + imm_reloc = BFD_RELOC_HI16_S; + imm_unmatched_hi = true; + } + else + imm_reloc = BFD_RELOC_HI16; + } + } + if (*args == 'i') + { + if ((c == '\0' && imm_expr.X_op != O_constant) + || ((imm_expr.X_add_number < 0 + || imm_expr.X_add_number >= 0x10000) + && imm_expr.X_op == O_constant)) + { + if (insn + 1 < &mips_opcodes[NUMOPCODES] && + !strcmp (insn->name, insn[1].name)) + break; + if (imm_expr.X_op != O_constant + && imm_expr.X_op != O_big) + insn_error = "absolute expression required"; + else + as_bad ("16 bit expression not in range 0..65535"); + } + } + else + { + int more; + offsetT max; + + /* The upper bound should be 0x8000, but + unfortunately the MIPS assembler accepts numbers + from 0x8000 to 0xffff and sign extends them, and + we want to be compatible. We only permit this + extended range for an instruction which does not + provide any further alternates, since those + alternates may handle other cases. People should + use the numbers they mean, rather than relying on + a mysterious sign extension. */ + more = (insn + 1 < &mips_opcodes[NUMOPCODES] && + strcmp (insn->name, insn[1].name) == 0); + if (more) + max = 0x8000; + else + max = 0x10000; + if ((c == '\0' && imm_expr.X_op != O_constant) + || ((imm_expr.X_add_number < -0x8000 + || imm_expr.X_add_number >= max) + && imm_expr.X_op == O_constant) + || (more + && imm_expr.X_add_number < 0 + && mips_opts.isa >= 3 + && imm_expr.X_unsigned + && sizeof (imm_expr.X_add_number) <= 4)) + { + if (more) + break; + if (imm_expr.X_op != O_constant + && imm_expr.X_op != O_big) + insn_error = "absolute expression required"; + else + as_bad ("16 bit expression not in range -32768..32767"); + } + } + s = expr_end; + continue; + + case 'o': /* 16 bit offset */ + c = my_getSmallExpression (&offset_expr, s); + + /* If this value won't fit into a 16 bit offset, then go + find a macro that will generate the 32 bit offset + code pattern. As a special hack, we accept the + difference of two local symbols as a constant. This + is required to suppose embedded PIC switches, which + use an instruction which looks like + lw $4,$L12-$LS12($4) + The problem with handling this in a more general + fashion is that the macro function doesn't expect to + see anything which can be handled in a single + constant instruction. */ + if (c == 0 + && (offset_expr.X_op != O_constant + || offset_expr.X_add_number >= 0x8000 + || offset_expr.X_add_number < -0x8000) + && (mips_pic != EMBEDDED_PIC + || offset_expr.X_op != O_subtract + || now_seg != text_section + || (S_GET_SEGMENT (offset_expr.X_op_symbol) + != text_section))) + break; + + offset_reloc = BFD_RELOC_LO16; + if (c == 'h' || c == 'H') + { + assert (offset_expr.X_op == O_constant); + offset_expr.X_add_number = + (offset_expr.X_add_number >> 16) & 0xffff; + } + s = expr_end; + continue; + + case 'p': /* pc relative offset */ + offset_reloc = BFD_RELOC_16_PCREL_S2; + my_getExpression (&offset_expr, s); + s = expr_end; + continue; + + case 'u': /* upper 16 bits */ + c = my_getSmallExpression (&imm_expr, s); + if (imm_expr.X_op == O_constant + && (imm_expr.X_add_number < 0 + || imm_expr.X_add_number >= 0x10000)) + as_bad ("lui expression not in range 0..65535"); + imm_reloc = BFD_RELOC_LO16; + if (c) + { + if (c != 'l') + { + if (imm_expr.X_op == O_constant) + imm_expr.X_add_number = + (imm_expr.X_add_number >> 16) & 0xffff; + else if (c == 'h') + { + imm_reloc = BFD_RELOC_HI16_S; + imm_unmatched_hi = true; + } + else + imm_reloc = BFD_RELOC_HI16; + } + } + s = expr_end; + continue; + + case 'a': /* 26 bit address */ + my_getExpression (&offset_expr, s); + s = expr_end; + offset_reloc = BFD_RELOC_MIPS_JMP; + continue; + + case 'N': /* 3 bit branch condition code */ + case 'M': /* 3 bit compare condition code */ + if (strncmp (s, "$fcc", 4) != 0) + break; + s += 4; + regno = 0; + do + { + regno *= 10; + regno += *s - '0'; + ++s; + } + while (isdigit (*s)); + if (regno > 7) + as_bad ("invalid condition code register $fcc%d", regno); + if (*args == 'N') + ip->insn_opcode |= regno << OP_SH_BCC; + else + ip->insn_opcode |= regno << OP_SH_CCC; + continue; + + default: + as_bad ("bad char = '%c'\n", *args); + internalError (); + } + break; + } + /* Args don't match. */ + if (insn + 1 < &mips_opcodes[NUMOPCODES] && + !strcmp (insn->name, insn[1].name)) + { + ++insn; + s = argsStart; + continue; + } + insn_error = "illegal operands"; + return; + } +} + +/* This routine assembles an instruction into its binary format when + assembling for the mips16. As a side effect, it sets one of the + global variables imm_reloc or offset_reloc to the type of + relocation to do if one of the operands is an address expression. + It also sets mips16_small and mips16_ext if the user explicitly + requested a small or extended instruction. */ + +static void +mips16_ip (str, ip) + char *str; + struct mips_cl_insn *ip; +{ + char *s; + const char *args; + struct mips_opcode *insn; + char *argsstart; + unsigned int regno; + unsigned int lastregno = 0; + char *s_reset; + + insn_error = NULL; + + mips16_small = false; + mips16_ext = false; + + for (s = str; islower (*s); ++s) + ; + switch (*s) + { + case '\0': + break; + + case ' ': + *s++ = '\0'; + break; + + case '.': + if (s[1] == 't' && s[2] == ' ') + { + *s = '\0'; + mips16_small = true; + s += 3; + break; + } + else if (s[1] == 'e' && s[2] == ' ') + { + *s = '\0'; + mips16_ext = true; + s += 3; + break; + } + /* Fall through. */ + default: + insn_error = "unknown opcode"; + return; + } + + if (mips_opts.noautoextend && ! mips16_ext) + mips16_small = true; + + if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) + { + insn_error = "unrecognized opcode"; + return; + } + + argsstart = s; + for (;;) + { + assert (strcmp (insn->name, str) == 0); + + ip->insn_mo = insn; + ip->insn_opcode = insn->match; + ip->use_extend = false; + imm_expr.X_op = O_absent; + imm_reloc = BFD_RELOC_UNUSED; + offset_expr.X_op = O_absent; + offset_reloc = BFD_RELOC_UNUSED; + for (args = insn->args; 1; ++args) + { + int c; + + if (*s == ' ') + ++s; + + /* In this switch statement we call break if we did not find + a match, continue if we did find a match, or return if we + are done. */ + + c = *args; + switch (c) + { + case '\0': + if (*s == '\0') + { + /* Stuff the immediate value in now, if we can. */ + if (imm_expr.X_op == O_constant + && imm_reloc > BFD_RELOC_UNUSED + && insn->pinfo != INSN_MACRO) + { + mips16_immed ((char *) NULL, 0, + imm_reloc - BFD_RELOC_UNUSED, + imm_expr.X_add_number, true, mips16_small, + mips16_ext, &ip->insn_opcode, + &ip->use_extend, &ip->extend); + imm_expr.X_op = O_absent; + imm_reloc = BFD_RELOC_UNUSED; + } + + return; + } + break; + + case ',': + if (*s++ == c) + continue; + s--; + switch (*++args) + { + case 'v': + ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; + continue; + case 'w': + ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; + continue; + } + break; + + case '(': + case ')': + if (*s++ == c) + continue; + break; + + case 'v': + case 'w': + if (s[0] != '$') + { + if (c == 'v') + ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; + else + ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; + ++args; + continue; + } + /* Fall through. */ + case 'x': + case 'y': + case 'z': + case 'Z': + case '0': + case 'S': + case 'R': + case 'X': + case 'Y': + if (s[0] != '$') + break; + s_reset = s; + if (isdigit (s[1])) + { + ++s; + regno = 0; + do + { + regno *= 10; + regno += *s - '0'; + ++s; + } + while (isdigit (*s)); + if (regno > 31) + { + as_bad ("invalid register number (%d)", regno); + regno = 2; + } + } + else + { + if (s[1] == 'f' && s[2] == 'p') + { + s += 3; + regno = FP; + } + else if (s[1] == 's' && s[2] == 'p') + { + s += 3; + regno = SP; + } + else if (s[1] == 'g' && s[2] == 'p') + { + s += 3; + regno = GP; + } + else if (s[1] == 'a' && s[2] == 't') + { + s += 3; + regno = AT; + } + else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') + { + s += 4; + regno = KT0; + } + else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') + { + s += 4; + regno = KT1; + } + else + break; + } + + if (*s == ' ') + ++s; + if (args[1] != *s) + { + if (c == 'v' || c == 'w') + { + regno = mips16_to_32_reg_map[lastregno]; + s = s_reset; + args++; + } + } + + switch (c) + { + case 'x': + case 'y': + case 'z': + case 'v': + case 'w': + case 'Z': + regno = mips32_to_16_reg_map[regno]; + break; + + case '0': + if (regno != 0) + regno = ILLEGAL_REG; + break; + + case 'S': + if (regno != SP) + regno = ILLEGAL_REG; + break; + + case 'R': + if (regno != RA) + regno = ILLEGAL_REG; + break; + + case 'X': + case 'Y': + if (regno == AT && ! mips_opts.noat) + as_warn ("used $at without \".set noat\""); + break; + + default: + internalError (); + } + + if (regno == ILLEGAL_REG) + break; + + switch (c) + { + case 'x': + case 'v': + ip->insn_opcode |= regno << MIPS16OP_SH_RX; + break; + case 'y': + case 'w': + ip->insn_opcode |= regno << MIPS16OP_SH_RY; + break; + case 'z': + ip->insn_opcode |= regno << MIPS16OP_SH_RZ; + break; + case 'Z': + ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; + case '0': + case 'S': + case 'R': + break; + case 'X': + ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; + break; + case 'Y': + regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); + ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; + break; + default: + internalError (); + } + + lastregno = regno; + continue; + + case 'P': + if (strncmp (s, "$pc", 3) == 0) + { + s += 3; + continue; + } + break; + + case '<': + case '>': + case '[': + case ']': + case '4': + case '5': + case 'H': + case 'W': + case 'D': + case 'j': + case '8': + case 'V': + case 'C': + case 'U': + case 'k': + case 'K': + if (s[0] == '%' + && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) + { + /* This is %gprel(SYMBOL). We need to read SYMBOL, + and generate the appropriate reloc. If the text + inside %gprel is not a symbol name with an + optional offset, then we generate a normal reloc + and will probably fail later. */ + my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); + if (imm_expr.X_op == O_symbol) + { + mips16_ext = true; + imm_reloc = BFD_RELOC_MIPS16_GPREL; + s = expr_end; + ip->use_extend = true; + ip->extend = 0; + continue; + } + } + else + { + /* Just pick up a normal expression. */ + my_getExpression (&imm_expr, s); + } + + if (imm_expr.X_op == O_register) + { + /* What we thought was an expression turned out to + be a register. */ + + if (s[0] == '(' && args[1] == '(') + { + /* It looks like the expression was omitted + before a register indirection, which means + that the expression is implicitly zero. We + still set up imm_expr, so that we handle + explicit extensions correctly. */ + imm_expr.X_op = O_constant; + imm_expr.X_add_number = 0; + imm_reloc = (int) BFD_RELOC_UNUSED + c; + continue; + } + + break; + } + + /* We need to relax this instruction. */ + imm_reloc = (int) BFD_RELOC_UNUSED + c; + s = expr_end; + continue; + + case 'p': + case 'q': + case 'A': + case 'B': + case 'E': + /* We use offset_reloc rather than imm_reloc for the PC + relative operands. This lets macros with both + immediate and address operands work correctly. */ + my_getExpression (&offset_expr, s); + + if (offset_expr.X_op == O_register) + break; + + /* We need to relax this instruction. */ + offset_reloc = (int) BFD_RELOC_UNUSED + c; + s = expr_end; + continue; + + case '6': /* break code */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > 63) + { + as_warn ("Invalid value for `%s' (%lu)", + ip->insn_mo->name, + (unsigned long) imm_expr.X_add_number); + imm_expr.X_add_number &= 0x3f; + } + ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + case 'a': /* 26 bit address */ + my_getExpression (&offset_expr, s); + s = expr_end; + offset_reloc = BFD_RELOC_MIPS16_JMP; + ip->insn_opcode <<= 16; + continue; + + case 'l': /* register list for entry macro */ + case 'L': /* register list for exit macro */ + { + int mask; + + if (c == 'l') + mask = 0; + else + mask = 7 << 3; + while (*s != '\0') + { + int freg, reg1, reg2; + + while (*s == ' ' || *s == ',') + ++s; + if (*s != '$') + { + as_bad ("can't parse register list"); + break; + } + ++s; + if (*s != 'f') + freg = 0; + else + { + freg = 1; + ++s; + } + reg1 = 0; + while (isdigit (*s)) + { + reg1 *= 10; + reg1 += *s - '0'; + ++s; + } + if (*s == ' ') + ++s; + if (*s != '-') + reg2 = reg1; + else + { + ++s; + if (*s != '$') + break; + ++s; + if (freg) + { + if (*s == 'f') + ++s; + else + { + as_bad ("invalid register list"); + break; + } + } + reg2 = 0; + while (isdigit (*s)) + { + reg2 *= 10; + reg2 += *s - '0'; + ++s; + } + } + if (freg && reg1 == 0 && reg2 == 0 && c == 'L') + { + mask &= ~ (7 << 3); + mask |= 5 << 3; + } + else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') + { + mask &= ~ (7 << 3); + mask |= 6 << 3; + } + else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') + mask |= (reg2 - 3) << 3; + else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) + mask |= (reg2 - 15) << 1; + else if (reg1 == 31 && reg2 == 31) + mask |= 1; + else + { + as_bad ("invalid register list"); + break; + } + } + /* The mask is filled in in the opcode table for the + benefit of the disassembler. We remove it before + applying the actual mask. */ + ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); + ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; + } + continue; + + case 'e': /* extend code */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned long) imm_expr.X_add_number > 0x7ff) + { + as_warn ("Invalid value for `%s' (%lu)", + ip->insn_mo->name, + (unsigned long) imm_expr.X_add_number); + imm_expr.X_add_number &= 0x7ff; + } + ip->insn_opcode |= imm_expr.X_add_number; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + + default: + internalError (); + } + break; + } + + /* Args don't match. */ + if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && + strcmp (insn->name, insn[1].name) == 0) + { + ++insn; + s = argsstart; + continue; + } + + insn_error = "illegal operands"; + + return; + } +} + +/* This structure holds information we know about a mips16 immediate + argument type. */ + +struct mips16_immed_operand +{ + /* The type code used in the argument string in the opcode table. */ + int type; + /* The number of bits in the short form of the opcode. */ + int nbits; + /* The number of bits in the extended form of the opcode. */ + int extbits; + /* The amount by which the short form is shifted when it is used; + for example, the sw instruction has a shift count of 2. */ + int shift; + /* The amount by which the short form is shifted when it is stored + into the instruction code. */ + int op_shift; + /* Non-zero if the short form is unsigned. */ + int unsp; + /* Non-zero if the extended form is unsigned. */ + int extu; + /* Non-zero if the value is PC relative. */ + int pcrel; +}; + +/* The mips16 immediate operand types. */ + +static const struct mips16_immed_operand mips16_immed_operands[] = +{ + { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, + { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, + { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, + { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, + { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, + { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, + { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, + { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, + { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, + { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, + { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, + { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, + { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, + { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, + { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, + { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, + { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, + { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, + { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, + { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, + { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } +}; + +#define MIPS16_NUM_IMMED \ + (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) + +/* Handle a mips16 instruction with an immediate value. This or's the + small immediate value into *INSN. It sets *USE_EXTEND to indicate + whether an extended value is needed; if one is needed, it sets + *EXTEND to the value. The argument type is TYPE. The value is VAL. + If SMALL is true, an unextended opcode was explicitly requested. + If EXT is true, an extended opcode was explicitly requested. If + WARN is true, warn if EXT does not match reality. */ + +static void +mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, + extend) + char *file; + unsigned int line; + int type; + offsetT val; + boolean warn; + boolean small; + boolean ext; + unsigned long *insn; + boolean *use_extend; + unsigned short *extend; +{ + register const struct mips16_immed_operand *op; + int mintiny, maxtiny; + boolean needext; + + op = mips16_immed_operands; + while (op->type != type) + { + ++op; + assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); + } + + if (op->unsp) + { + if (type == '<' || type == '>' || type == '[' || type == ']') + { + mintiny = 1; + maxtiny = 1 << op->nbits; + } + else + { + mintiny = 0; + maxtiny = (1 << op->nbits) - 1; + } + } + else + { + mintiny = - (1 << (op->nbits - 1)); + maxtiny = (1 << (op->nbits - 1)) - 1; + } + + /* Branch offsets have an implicit 0 in the lowest bit. */ + if (type == 'p' || type == 'q') + val /= 2; + + if ((val & ((1 << op->shift) - 1)) != 0 + || val < (mintiny << op->shift) + || val > (maxtiny << op->shift)) + needext = true; + else + needext = false; + + if (warn && ext && ! needext) + as_warn_where (file, line, "extended operand requested but not required"); + if (small && needext) + as_bad_where (file, line, "invalid unextended operand value"); + + if (small || (! ext && ! needext)) + { + int insnval; + + *use_extend = false; + insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); + insnval <<= op->op_shift; + *insn |= insnval; + } + else + { + long minext, maxext; + int extval; + + if (op->extu) + { + minext = 0; + maxext = (1 << op->extbits) - 1; + } + else + { + minext = - (1 << (op->extbits - 1)); + maxext = (1 << (op->extbits - 1)) - 1; + } + if (val < minext || val > maxext) + as_bad_where (file, line, + "operand value out of range for instruction"); + + *use_extend = true; + if (op->extbits == 16) + { + extval = ((val >> 11) & 0x1f) | (val & 0x7e0); + val &= 0x1f; + } + else if (op->extbits == 15) + { + extval = ((val >> 11) & 0xf) | (val & 0x7f0); + val &= 0xf; + } + else + { + extval = ((val & 0x1f) << 6) | (val & 0x20); + val = 0; + } + + *extend = (unsigned short) extval; + *insn |= val; + } +} + +#define LP '(' +#define RP ')' + +static int +my_getSmallExpression (ep, str) + expressionS *ep; + char *str; +{ + char *sp; + int c = 0; + + if (*str == ' ') + str++; + if (*str == LP + || (*str == '%' && + ((str[1] == 'h' && str[2] == 'i') + || (str[1] == 'H' && str[2] == 'I') + || (str[1] == 'l' && str[2] == 'o')) + && str[3] == LP)) + { + if (*str == LP) + c = 0; + else + { + c = str[1]; + str += 3; + } + + /* + * A small expression may be followed by a base register. + * Scan to the end of this operand, and then back over a possible + * base register. Then scan the small expression up to that + * point. (Based on code in sparc.c...) + */ + for (sp = str; *sp && *sp != ','; sp++) + ; + if (sp - 4 >= str && sp[-1] == RP) + { + if (isdigit (sp[-2])) + { + for (sp -= 3; sp >= str && isdigit (*sp); sp--) + ; + if (*sp == '$' && sp > str && sp[-1] == LP) + { + sp--; + goto do_it; + } + } + else if (sp - 5 >= str + && sp[-5] == LP + && sp[-4] == '$' + && ((sp[-3] == 'f' && sp[-2] == 'p') + || (sp[-3] == 's' && sp[-2] == 'p') + || (sp[-3] == 'g' && sp[-2] == 'p') + || (sp[-3] == 'a' && sp[-2] == 't'))) + { + sp -= 5; + do_it: + if (sp == str) + { + /* no expression means zero offset */ + if (c) + { + /* %xx(reg) is an error */ + ep->X_op = O_absent; + expr_end = str - 3; + } + else + { + ep->X_op = O_constant; + expr_end = sp; + } + ep->X_add_symbol = NULL; + ep->X_op_symbol = NULL; + ep->X_add_number = 0; + } + else + { + *sp = '\0'; + my_getExpression (ep, str); + *sp = LP; + } + return c; + } + } + } + my_getExpression (ep, str); + return c; /* => %hi or %lo encountered */ +} + +static void +my_getExpression (ep, str) + expressionS *ep; + char *str; +{ + char *save_in; + + save_in = input_line_pointer; + input_line_pointer = str; + expression (ep); + expr_end = input_line_pointer; + input_line_pointer = save_in; + + /* If we are in mips16 mode, and this is an expression based on `.', + then we bump the value of the symbol by 1 since that is how other + text symbols are handled. We don't bother to handle complex + expressions, just `.' plus or minus a constant. */ + if (mips_opts.mips16 + && ep->X_op == O_symbol + && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 + && S_GET_SEGMENT (ep->X_add_symbol) == now_seg + && ep->X_add_symbol->sy_frag == frag_now + && ep->X_add_symbol->sy_value.X_op == O_constant + && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) + ++ep->X_add_symbol->sy_value.X_add_number; +} + +/* Turn a string in input_line_pointer into a floating point constant + of type type, and store the appropriate bytes in *litP. The number + of LITTLENUMS emitted is stored in *sizeP . An error message is + returned, or NULL on OK. */ + +char * +md_atof (type, litP, sizeP) + int type; + char *litP; + int *sizeP; +{ + int prec; + LITTLENUM_TYPE words[4]; + char *t; + int i; + + switch (type) + { + case 'f': + prec = 2; + break; + + case 'd': + prec = 4; + break; + + default: + *sizeP = 0; + return "bad call to md_atof"; + } + + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + + *sizeP = prec * 2; + + if (! target_big_endian) + { + for (i = prec - 1; i >= 0; i--) + { + md_number_to_chars (litP, (valueT) words[i], 2); + litP += 2; + } + } + else + { + for (i = 0; i < prec; i++) + { + md_number_to_chars (litP, (valueT) words[i], 2); + litP += 2; + } + } + + return NULL; +} + +void +md_number_to_chars (buf, val, n) + char *buf; + valueT val; + int n; +{ + if (target_big_endian) + number_to_chars_bigendian (buf, val, n); + else + number_to_chars_littleendian (buf, val, n); +} + +CONST char *md_shortopts = "O::g::G:"; + +struct option md_longopts[] = { +#define OPTION_MIPS1 (OPTION_MD_BASE + 1) + {"mips0", no_argument, NULL, OPTION_MIPS1}, + {"mips1", no_argument, NULL, OPTION_MIPS1}, +#define OPTION_MIPS2 (OPTION_MD_BASE + 2) + {"mips2", no_argument, NULL, OPTION_MIPS2}, +#define OPTION_MIPS3 (OPTION_MD_BASE + 3) + {"mips3", no_argument, NULL, OPTION_MIPS3}, +#define OPTION_MIPS4 (OPTION_MD_BASE + 4) + {"mips4", no_argument, NULL, OPTION_MIPS4}, +#define OPTION_MCPU (OPTION_MD_BASE + 5) + {"mcpu", required_argument, NULL, OPTION_MCPU}, +#define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) + {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, +#define OPTION_TRAP (OPTION_MD_BASE + 9) + {"trap", no_argument, NULL, OPTION_TRAP}, + {"no-break", no_argument, NULL, OPTION_TRAP}, +#define OPTION_BREAK (OPTION_MD_BASE + 10) + {"break", no_argument, NULL, OPTION_BREAK}, + {"no-trap", no_argument, NULL, OPTION_BREAK}, +#define OPTION_EB (OPTION_MD_BASE + 11) + {"EB", no_argument, NULL, OPTION_EB}, +#define OPTION_EL (OPTION_MD_BASE + 12) + {"EL", no_argument, NULL, OPTION_EL}, +#define OPTION_M4650 (OPTION_MD_BASE + 13) + {"m4650", no_argument, NULL, OPTION_M4650}, +#define OPTION_NO_M4650 (OPTION_MD_BASE + 14) + {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, +#define OPTION_M4010 (OPTION_MD_BASE + 15) + {"m4010", no_argument, NULL, OPTION_M4010}, +#define OPTION_NO_M4010 (OPTION_MD_BASE + 16) + {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, +#define OPTION_M4100 (OPTION_MD_BASE + 17) + {"m4100", no_argument, NULL, OPTION_M4100}, +#define OPTION_NO_M4100 (OPTION_MD_BASE + 18) + {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, +#define OPTION_MIPS16 (OPTION_MD_BASE + 22) + {"mips16", no_argument, NULL, OPTION_MIPS16}, +#define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) + {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, +#define OPTION_M3900 (OPTION_MD_BASE + 26) + {"m3900", no_argument, NULL, OPTION_M3900}, +#define OPTION_NO_M3900 (OPTION_MD_BASE + 27) + {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, + + +#define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) +#define OPTION_NON_SHARED (OPTION_MD_BASE + 8) +#define OPTION_XGOT (OPTION_MD_BASE + 19) +#define OPTION_32 (OPTION_MD_BASE + 20) +#define OPTION_64 (OPTION_MD_BASE + 21) +#ifdef OBJ_ELF + {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, + {"xgot", no_argument, NULL, OPTION_XGOT}, + {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, + {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, + {"32", no_argument, NULL, OPTION_32}, + {"64", no_argument, NULL, OPTION_64}, +#endif + + {NULL, no_argument, NULL, 0} +}; +size_t md_longopts_size = sizeof(md_longopts); + +int +md_parse_option (c, arg) + int c; + char *arg; +{ + switch (c) + { + case OPTION_TRAP: + mips_trap = 1; + break; + + case OPTION_BREAK: + mips_trap = 0; + break; + + case OPTION_EB: + target_big_endian = 1; + break; + + case OPTION_EL: + target_big_endian = 0; + break; + + case 'O': + if (arg && arg[1] == '0') + mips_optimize = 1; + else + mips_optimize = 2; + break; + + case 'g': + if (arg == NULL) + mips_debug = 2; + else + mips_debug = atoi (arg); + /* When the MIPS assembler sees -g or -g2, it does not do + optimizations which limit full symbolic debugging. We take + that to be equivalent to -O0. */ + if (mips_debug == 2) + mips_optimize = 1; + break; + + case OPTION_MIPS1: + mips_opts.isa = 1; + break; + + case OPTION_MIPS2: + mips_opts.isa = 2; + break; + + case OPTION_MIPS3: + mips_opts.isa = 3; + break; + + case OPTION_MIPS4: + mips_opts.isa = 4; + break; + + case OPTION_MCPU: + { + char *p; + + /* Identify the processor type */ + p = arg; + if (strcmp (p, "default") == 0 + || strcmp (p, "DEFAULT") == 0) + mips_cpu = -1; + else + { + int sv = 0; + + /* We need to cope with the various "vr" prefixes for the 4300 + processor. */ + if (*p == 'v' || *p == 'V') + { + sv = 1; + p++; + } + + if (*p == 'r' || *p == 'R') + p++; + + mips_cpu = -1; + switch (*p) + { + case '1': + if (strcmp (p, "10000") == 0 + || strcmp (p, "10k") == 0 + || strcmp (p, "10K") == 0) + mips_cpu = 10000; + break; + + case '2': + if (strcmp (p, "2000") == 0 + || strcmp (p, "2k") == 0 + || strcmp (p, "2K") == 0) + mips_cpu = 2000; + break; + + case '3': + if (strcmp (p, "3000") == 0 + || strcmp (p, "3k") == 0 + || strcmp (p, "3K") == 0) + mips_cpu = 3000; + else if (strcmp (p, "3900") == 0) + mips_cpu = 3900; + break; + + case '4': + if (strcmp (p, "4000") == 0 + || strcmp (p, "4k") == 0 + || strcmp (p, "4K") == 0) + mips_cpu = 4000; + else if (strcmp (p, "4100") == 0) + mips_cpu = 4100; + else if (strcmp (p, "4300") == 0) + mips_cpu = 4300; + else if (strcmp (p, "4400") == 0) + mips_cpu = 4400; + else if (strcmp (p, "4600") == 0) + mips_cpu = 4600; + else if (strcmp (p, "4650") == 0) + mips_cpu = 4650; + else if (strcmp (p, "4010") == 0) + mips_cpu = 4010; + break; + + case '5': + if (strcmp (p, "5000") == 0 + || strcmp (p, "5k") == 0 + || strcmp (p, "5K") == 0) + mips_cpu = 5000; + break; + + case '6': + if (strcmp (p, "6000") == 0 + || strcmp (p, "6k") == 0 + || strcmp (p, "6K") == 0) + mips_cpu = 6000; + break; + + case '8': + if (strcmp (p, "8000") == 0 + || strcmp (p, "8k") == 0 + || strcmp (p, "8K") == 0) + mips_cpu = 8000; + break; + + case 'o': + if (strcmp (p, "orion") == 0) + mips_cpu = 4600; + break; + } + + if (sv + && (mips_cpu != 4300 + && mips_cpu != 4100 + && mips_cpu != 5000)) + { + as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); + return 0; + } + + if (mips_cpu == -1) + { + as_bad ("invalid architecture -mcpu=%s", arg); + return 0; + } + } + } + break; + + case OPTION_M4650: + mips_4650 = 1; + break; + + case OPTION_NO_M4650: + mips_4650 = 0; + break; + + case OPTION_M4010: + mips_4010 = 1; + break; + + case OPTION_NO_M4010: + mips_4010 = 0; + break; + + case OPTION_M4100: + mips_4100 = 1; + break; + + case OPTION_NO_M4100: + mips_4100 = 0; + break; + + + case OPTION_M3900: + mips_3900 = 1; + break; + + case OPTION_NO_M3900: + mips_3900 = 0; + break; + + case OPTION_MIPS16: + mips_opts.mips16 = 1; + mips_no_prev_insn (false); + break; + + case OPTION_NO_MIPS16: + mips_opts.mips16 = 0; + mips_no_prev_insn (false); + break; + + case OPTION_MEMBEDDED_PIC: + mips_pic = EMBEDDED_PIC; + if (USE_GLOBAL_POINTER_OPT && g_switch_seen) + { + as_bad ("-G may not be used with embedded PIC code"); + return 0; + } + g_switch_value = 0x7fffffff; + break; + + /* When generating ELF code, we permit -KPIC and -call_shared to + select SVR4_PIC, and -non_shared to select no PIC. This is + intended to be compatible with Irix 5. */ + case OPTION_CALL_SHARED: + if (OUTPUT_FLAVOR != bfd_target_elf_flavour) + { + as_bad ("-call_shared is supported only for ELF format"); + return 0; + } + mips_pic = SVR4_PIC; + if (g_switch_seen && g_switch_value != 0) + { + as_bad ("-G may not be used with SVR4 PIC code"); + return 0; + } + g_switch_value = 0; + break; + + case OPTION_NON_SHARED: + if (OUTPUT_FLAVOR != bfd_target_elf_flavour) + { + as_bad ("-non_shared is supported only for ELF format"); + return 0; + } + mips_pic = NO_PIC; + break; + + /* The -xgot option tells the assembler to use 32 offsets when + accessing the got in SVR4_PIC mode. It is for Irix + compatibility. */ + case OPTION_XGOT: + mips_big_got = 1; + break; + + case 'G': + if (! USE_GLOBAL_POINTER_OPT) + { + as_bad ("-G is not supported for this configuration"); + return 0; + } + else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) + { + as_bad ("-G may not be used with SVR4 or embedded PIC code"); + return 0; + } + else + g_switch_value = atoi (arg); + g_switch_seen = 1; + break; + + /* The -32 and -64 options tell the assembler to output the 32 + bit or the 64 bit MIPS ELF format. */ + case OPTION_32: + mips_64 = 0; + break; + + case OPTION_64: + { + const char **list, **l; + + list = bfd_target_list (); + for (l = list; *l != NULL; l++) + if (strcmp (*l, "elf64-bigmips") == 0 + || strcmp (*l, "elf64-littlemips") == 0) + break; + if (*l == NULL) + as_fatal ("No compiled in support for 64 bit object file format"); + free (list); + mips_64 = 1; + } + break; + + default: + return 0; + } + + return 1; +} + +void +md_show_usage (stream) + FILE *stream; +{ + fprintf(stream, "\ +MIPS options:\n\ +-membedded-pic generate embedded position independent code\n\ +-EB generate big endian output\n\ +-EL generate little endian output\n\ +-g, -g2 do not remove uneeded NOPs or swap branches\n\ +-G NUM allow referencing objects up to NUM bytes\n\ + implicitly with the gp register [default 8]\n"); + fprintf(stream, "\ +-mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ +-mips2, -mcpu=r6000 generate code for r6000\n\ +-mips3, -mcpu=r4000 generate code for r4000\n\ +-mips4, -mcpu=r8000 generate code for r8000\n\ +-mcpu=vr4300 generate code for vr4300\n\ +-mcpu=vr4100 generate code for vr4100\n\ +-m4650 permit R4650 instructions\n\ +-no-m4650 do not permit R4650 instructions\n\ +-m4010 permit R4010 instructions\n\ +-no-m4010 do not permit R4010 instructions\n\ +-m4100 permit VR4100 instructions\n\ +-no-m4100 do not permit VR4100 instructions\n"); + fprintf(stream, "\ +-mips16 generate mips16 instructions\n\ +-no-mips16 do not generate mips16 instructions\n"); + fprintf(stream, "\ +-O0 remove unneeded NOPs, do not swap branches\n\ +-O remove unneeded NOPs and swap branches\n\ +--trap, --no-break trap exception on div by 0 and mult overflow\n\ +--break, --no-trap break exception on div by 0 and mult overflow\n"); +#ifdef OBJ_ELF + fprintf(stream, "\ +-KPIC, -call_shared generate SVR4 position independent code\n\ +-non_shared do not generate position independent code\n\ +-xgot assume a 32 bit GOT\n\ +-32 create 32 bit object file (default)\n\ +-64 create 64 bit object file\n"); +#endif +} + +void +mips_init_after_args () +{ + /* initialize opcodes */ + bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; + mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; +} + +long +md_pcrel_from (fixP) + fixS *fixP; +{ + if (OUTPUT_FLAVOR != bfd_target_aout_flavour + && fixP->fx_addsy != (symbolS *) NULL + && ! S_IS_DEFINED (fixP->fx_addsy)) + { + /* This makes a branch to an undefined symbol be a branch to the + current location. */ + return 4; + } + + /* return the address of the delay slot */ + return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; +} + +/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a + reloc for a cons. We could use the definition there, except that + we want to handle 64 bit relocs specially. */ + +void +cons_fix_new_mips (frag, where, nbytes, exp) + fragS *frag; + int where; + unsigned int nbytes; + expressionS *exp; +{ +#ifndef OBJ_ELF + /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a + 4 byte reloc. */ + if (nbytes == 8 && ! mips_64) + { + if (target_big_endian) + where += 4; + nbytes = 4; + } +#endif + + if (nbytes != 2 && nbytes != 4 && nbytes != 8) + as_bad ("Unsupported reloc size %d", nbytes); + + fix_new_exp (frag_now, where, (int) nbytes, exp, 0, + (nbytes == 2 + ? BFD_RELOC_16 + : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); +} + +/* This is called before the symbol table is processed. In order to + work with gcc when using mips-tfile, we must keep all local labels. + However, in other cases, we want to discard them. If we were + called with -g, but we didn't see any debugging information, it may + mean that gcc is smuggling debugging information through to + mips-tfile, in which case we must generate all local labels. */ + +void +mips_frob_file_before_adjust () +{ +#ifndef NO_ECOFF_DEBUGGING + if (ECOFF_DEBUGGING + && mips_debug != 0 + && ! ecoff_debugging_seen) + flag_keep_locals = 1; +#endif +} + +/* Sort any unmatched HI16_S relocs so that they immediately precede + the corresponding LO reloc. This is called before md_apply_fix and + tc_gen_reloc. Unmatched HI16_S relocs can only be generated by + explicit use of the %hi modifier. */ + +void +mips_frob_file () +{ + struct mips_hi_fixup *l; + + for (l = mips_hi_fixup_list; l != NULL; l = l->next) + { + segment_info_type *seginfo; + int pass; + + assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); + + /* Check quickly whether the next fixup happens to be a matching + %lo. */ + if (l->fixp->fx_next != NULL + && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 + && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy + && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) + continue; + + /* Look through the fixups for this segment for a matching %lo. + When we find one, move the %hi just in front of it. We do + this in two passes. In the first pass, we try to find a + unique %lo. In the second pass, we permit multiple %hi + relocs for a single %lo (this is a GNU extension). */ + seginfo = seg_info (l->seg); + for (pass = 0; pass < 2; pass++) + { + fixS *f, *prev; + + prev = NULL; + for (f = seginfo->fix_root; f != NULL; f = f->fx_next) + { + /* Check whether this is a %lo fixup which matches l->fixp. */ + if (f->fx_r_type == BFD_RELOC_LO16 + && f->fx_addsy == l->fixp->fx_addsy + && f->fx_offset == l->fixp->fx_offset + && (pass == 1 + || prev == NULL + || prev->fx_r_type != BFD_RELOC_HI16_S + || prev->fx_addsy != f->fx_addsy + || prev->fx_offset != f->fx_offset)) + { + fixS **pf; + + /* Move l->fixp before f. */ + for (pf = &seginfo->fix_root; + *pf != l->fixp; + pf = &(*pf)->fx_next) + assert (*pf != NULL); + + *pf = l->fixp->fx_next; + + l->fixp->fx_next = f; + if (prev == NULL) + seginfo->fix_root = l->fixp; + else + prev->fx_next = l->fixp; + + break; + } + + prev = f; + } + + if (f != NULL) + break; + + if (pass == 1) + as_warn_where (l->fixp->fx_file, l->fixp->fx_line, + "Unmatched %%hi reloc"); + } + } +} + +/* When generating embedded PIC code we need to use a special + relocation to represent the difference of two symbols in the .text + section (switch tables use a difference of this sort). See + include/coff/mips.h for details. This macro checks whether this + fixup requires the special reloc. */ +#define SWITCH_TABLE(fixp) \ + ((fixp)->fx_r_type == BFD_RELOC_32 \ + && (fixp)->fx_addsy != NULL \ + && (fixp)->fx_subsy != NULL \ + && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ + && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) + +/* When generating embedded PIC code we must keep all PC relative + relocations, in case the linker has to relax a call. We also need + to keep relocations for switch table entries. */ + +/*ARGSUSED*/ +int +mips_force_relocation (fixp) + fixS *fixp; +{ + return (mips_pic == EMBEDDED_PIC + && (fixp->fx_pcrel + || SWITCH_TABLE (fixp) + || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S + || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); +} + +/* Apply a fixup to the object file. */ + +int +md_apply_fix (fixP, valueP) + fixS *fixP; + valueT *valueP; +{ + unsigned char *buf; + long insn, value; + + assert (fixP->fx_size == 4 + || fixP->fx_r_type == BFD_RELOC_16 + || fixP->fx_r_type == BFD_RELOC_64); + + value = *valueP; + + /* If we aren't adjusting this fixup to be against the section + symbol, we need to adjust the value. */ +#ifdef OBJ_ELF + if (fixP->fx_addsy != NULL + && OUTPUT_FLAVOR == bfd_target_elf_flavour + && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) + { + value -= S_GET_VALUE (fixP->fx_addsy); + if (value != 0 && ! fixP->fx_pcrel) + { + /* In this case, the bfd_install_relocation routine will + incorrectly add the symbol value back in. We just want + the addend to appear in the object file. */ + value -= S_GET_VALUE (fixP->fx_addsy); + } + } +#endif + + fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ + + if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) + fixP->fx_done = 1; + + switch (fixP->fx_r_type) + { + case BFD_RELOC_MIPS_JMP: + case BFD_RELOC_HI16: + case BFD_RELOC_HI16_S: + case BFD_RELOC_MIPS_GPREL: + case BFD_RELOC_MIPS_LITERAL: + case BFD_RELOC_MIPS_CALL16: + case BFD_RELOC_MIPS_GOT16: + case BFD_RELOC_MIPS_GPREL32: + case BFD_RELOC_MIPS_GOT_HI16: + case BFD_RELOC_MIPS_GOT_LO16: + case BFD_RELOC_MIPS_CALL_HI16: + case BFD_RELOC_MIPS_CALL_LO16: + case BFD_RELOC_MIPS16_GPREL: + if (fixP->fx_pcrel) + as_bad_where (fixP->fx_file, fixP->fx_line, + "Invalid PC relative reloc"); + /* Nothing needed to do. The value comes from the reloc entry */ + break; + + case BFD_RELOC_MIPS16_JMP: + /* We currently always generate a reloc against a symbol, which + means that we don't want an addend even if the symbol is + defined. */ + fixP->fx_addnumber = 0; + break; + + case BFD_RELOC_PCREL_HI16_S: + /* The addend for this is tricky if it is internal, so we just + do everything here rather than in bfd_install_relocation. */ + if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) + { + /* For an external symbol adjust by the address to make it + pcrel_offset. We use the address of the RELLO reloc + which follows this one. */ + value += (fixP->fx_next->fx_frag->fr_address + + fixP->fx_next->fx_where); + } + if (value & 0x8000) + value += 0x10000; + value >>= 16; + buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; + if (target_big_endian) + buf += 2; + md_number_to_chars (buf, value, 2); + break; + + case BFD_RELOC_PCREL_LO16: + /* The addend for this is tricky if it is internal, so we just + do everything here rather than in bfd_install_relocation. */ + if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) + value += fixP->fx_frag->fr_address + fixP->fx_where; + buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; + if (target_big_endian) + buf += 2; + md_number_to_chars (buf, value, 2); + break; + + case BFD_RELOC_64: + /* This is handled like BFD_RELOC_32, but we output a sign + extended value if we are only 32 bits. */ + if (fixP->fx_done + || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) + { + if (8 <= sizeof (valueT)) + md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, + value, 8); + else + { + long w1, w2; + long hiv; + + w1 = w2 = fixP->fx_where; + if (target_big_endian) + w1 += 4; + else + w2 += 4; + md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); + if ((value & 0x80000000) != 0) + hiv = 0xffffffff; + else + hiv = 0; + md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); + } + } + break; + + case BFD_RELOC_32: + /* If we are deleting this reloc entry, we must fill in the + value now. This can happen if we have a .word which is not + resolved when it appears but is later defined. We also need + to fill in the value if this is an embedded PIC switch table + entry. */ + if (fixP->fx_done + || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) + md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, + value, 4); + break; + + case BFD_RELOC_16: + /* If we are deleting this reloc entry, we must fill in the + value now. */ + assert (fixP->fx_size == 2); + if (fixP->fx_done) + md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, + value, 2); + break; + + case BFD_RELOC_LO16: + /* When handling an embedded PIC switch statement, we can wind + up deleting a LO16 reloc. See the 'o' case in mips_ip. */ + if (fixP->fx_done) + { + if (value < -0x8000 || value > 0x7fff) + as_bad_where (fixP->fx_file, fixP->fx_line, + "relocation overflow"); + buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; + if (target_big_endian) + buf += 2; + md_number_to_chars (buf, value, 2); + } + break; + + case BFD_RELOC_16_PCREL_S2: + /* + * We need to save the bits in the instruction since fixup_segment() + * might be deleting the relocation entry (i.e., a branch within + * the current segment). + */ + if ((value & 0x3) != 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + "Branch to odd address (%lx)", value); + value >>= 2; + + /* update old instruction data */ + buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); + if (target_big_endian) + insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; + else + insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; + + if (value >= -0x8000 && value < 0x8000) + insn |= value & 0xffff; + else + { + /* The branch offset is too large. If this is an + unconditional branch, and we are not generating PIC code, + we can convert it to an absolute jump instruction. */ + if (mips_pic == NO_PIC + && fixP->fx_done + && fixP->fx_frag->fr_address >= text_section->vma + && (fixP->fx_frag->fr_address + < text_section->vma + text_section->_raw_size) + && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ + || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ + || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ + { + if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ + insn = 0x0c000000; /* jal */ + else + insn = 0x08000000; /* j */ + fixP->fx_r_type = BFD_RELOC_MIPS_JMP; + fixP->fx_done = 0; + fixP->fx_addsy = section_symbol (text_section); + fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); + } + else + { + /* FIXME. It would be possible in principle to handle + conditional branches which overflow. They could be + transformed into a branch around a jump. This would + require setting up variant frags for each different + branch type. The native MIPS assembler attempts to + handle these cases, but it appears to do it + incorrectly. */ + as_bad_where (fixP->fx_file, fixP->fx_line, + "Branch out of range"); + } + } + + md_number_to_chars ((char *) buf, (valueT) insn, 4); + break; + + default: + internalError (); + } + + return 1; +} + +#if 0 +void +printInsn (oc) + unsigned long oc; +{ + const struct mips_opcode *p; + int treg, sreg, dreg, shamt; + short imm; + const char *args; + int i; + + for (i = 0; i < NUMOPCODES; ++i) + { + p = &mips_opcodes[i]; + if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) + { + printf ("%08lx %s\t", oc, p->name); + treg = (oc >> 16) & 0x1f; + sreg = (oc >> 21) & 0x1f; + dreg = (oc >> 11) & 0x1f; + shamt = (oc >> 6) & 0x1f; + imm = oc; + for (args = p->args;; ++args) + { + switch (*args) + { + case '\0': + printf ("\n"); + break; + + case ',': + case '(': + case ')': + printf ("%c", *args); + continue; + + case 'r': + assert (treg == sreg); + printf ("$%d,$%d", treg, sreg); + continue; + + case 'd': + case 'G': + printf ("$%d", dreg); + continue; + + case 't': + case 'E': + printf ("$%d", treg); + continue; + + case 'k': + printf ("0x%x", treg); + continue; + + case 'b': + case 's': + printf ("$%d", sreg); + continue; + + case 'a': + printf ("0x%08lx", oc & 0x1ffffff); + continue; + + case 'i': + case 'j': + case 'o': + case 'u': + printf ("%d", imm); + continue; + + case '<': + case '>': + printf ("$%d", shamt); + continue; + + default: + internalError (); + } + break; + } + return; + } + } + printf ("%08lx UNDEFINED\n", oc); +} +#endif + +static symbolS * +get_symbol () +{ + int c; + char *name; + symbolS *p; + + name = input_line_pointer; + c = get_symbol_end (); + p = (symbolS *) symbol_find_or_make (name); + *input_line_pointer = c; + return p; +} + +/* Align the current frag to a given power of two. The MIPS assembler + also automatically adjusts any preceding label. */ + +static void +mips_align (to, fill, label) + int to; + int fill; + symbolS *label; +{ + mips_emit_delays (false); + frag_align (to, fill, 0); + record_alignment (now_seg, to); + if (label != NULL) + { + assert (S_GET_SEGMENT (label) == now_seg); + label->sy_frag = frag_now; + S_SET_VALUE (label, (valueT) frag_now_fix ()); + } +} + +/* Align to a given power of two. .align 0 turns off the automatic + alignment used by the data creating pseudo-ops. */ + +static void +s_align (x) + int x; +{ + register int temp; + register long temp_fill; + long max_alignment = 15; + + /* + + o Note that the assembler pulls down any immediately preceeding label + to the aligned address. + o It's not documented but auto alignment is reinstated by + a .align pseudo instruction. + o Note also that after auto alignment is turned off the mips assembler + issues an error on attempt to assemble an improperly aligned data item. + We don't. + + */ + + temp = get_absolute_expression (); + if (temp > max_alignment) + as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); + else if (temp < 0) + { + as_warn ("Alignment negative: 0 assumed."); + temp = 0; + } + if (*input_line_pointer == ',') + { + input_line_pointer++; + temp_fill = get_absolute_expression (); + } + else + temp_fill = 0; + if (temp) + { + auto_align = 1; + mips_align (temp, (int) temp_fill, + insn_labels != NULL ? insn_labels->label : NULL); + } + else + { + auto_align = 0; + } + + demand_empty_rest_of_line (); +} + +void +mips_flush_pending_output () +{ + mips_emit_delays (false); + mips_clear_insn_labels (); +} + +static void +s_change_sec (sec) + int sec; +{ + segT seg; + + /* When generating embedded PIC code, we only use the .text, .lit8, + .sdata and .sbss sections. We change the .data and .rdata + pseudo-ops to use .sdata. */ + if (mips_pic == EMBEDDED_PIC + && (sec == 'd' || sec == 'r')) + sec = 's'; + +#ifdef OBJ_ELF + /* The ELF backend needs to know that we are changing sections, so + that .previous works correctly. We could do something like check + for a obj_section_change_hook macro, but that might be confusing + as it would not be appropriate to use it in the section changing + functions in read.c, since obj-elf.c intercepts those. FIXME: + This should be cleaner, somehow. */ + obj_elf_section_change_hook (); +#endif + + mips_emit_delays (false); + switch (sec) + { + case 't': + s_text (0); + break; + case 'd': + s_data (0); + break; + case 'b': + subseg_set (bss_section, (subsegT) get_absolute_expression ()); + demand_empty_rest_of_line (); + break; + + case 'r': + if (USE_GLOBAL_POINTER_OPT) + { + seg = subseg_new (RDATA_SECTION_NAME, + (subsegT) get_absolute_expression ()); + if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + { + bfd_set_section_flags (stdoutput, seg, + (SEC_ALLOC + | SEC_LOAD + | SEC_READONLY + | SEC_RELOC + | SEC_DATA)); + if (strcmp (TARGET_OS, "elf") != 0) + bfd_set_section_alignment (stdoutput, seg, 4); + } + demand_empty_rest_of_line (); + } + else + { + as_bad ("No read only data section in this object file format"); + demand_empty_rest_of_line (); + return; + } + break; + + case 's': + if (USE_GLOBAL_POINTER_OPT) + { + seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); + if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + { + bfd_set_section_flags (stdoutput, seg, + SEC_ALLOC | SEC_LOAD | SEC_RELOC + | SEC_DATA); + if (strcmp (TARGET_OS, "elf") != 0) + bfd_set_section_alignment (stdoutput, seg, 4); + } + demand_empty_rest_of_line (); + break; + } + else + { + as_bad ("Global pointers not supported; recompile -G 0"); + demand_empty_rest_of_line (); + return; + } + } + + auto_align = 1; +} + +void +mips_enable_auto_align () +{ + auto_align = 1; +} + +static void +s_cons (log_size) + int log_size; +{ + symbolS *label; + + label = insn_labels != NULL ? insn_labels->label : NULL; + mips_emit_delays (false); + if (log_size > 0 && auto_align) + mips_align (log_size, 0, label); + mips_clear_insn_labels (); + cons (1 << log_size); +} + +static void +s_float_cons (type) + int type; +{ + symbolS *label; + + label = insn_labels != NULL ? insn_labels->label : NULL; + + mips_emit_delays (false); + + if (auto_align) + if (type == 'd') + mips_align (3, 0, label); + else + mips_align (2, 0, label); + + mips_clear_insn_labels (); + + float_cons (type); +} + +/* Handle .globl. We need to override it because on Irix 5 you are + permitted to say + .globl foo .text + where foo is an undefined symbol, to mean that foo should be + considered to be the address of a function. */ + +static void +s_mips_globl (x) + int x; +{ + char *name; + int c; + symbolS *symbolP; + flagword flag; + + name = input_line_pointer; + c = get_symbol_end (); + symbolP = symbol_find_or_make (name); + *input_line_pointer = c; + SKIP_WHITESPACE (); + + /* On Irix 5, every global symbol that is not explicitly labelled as + being a function is apparently labelled as being an object. */ + flag = BSF_OBJECT; + + if (! is_end_of_line[(unsigned char) *input_line_pointer]) + { + char *secname; + asection *sec; + + secname = input_line_pointer; + c = get_symbol_end (); + sec = bfd_get_section_by_name (stdoutput, secname); + if (sec == NULL) + as_bad ("%s: no such section", secname); + *input_line_pointer = c; + + if (sec != NULL && (sec->flags & SEC_CODE) != 0) + flag = BSF_FUNCTION; + } + + symbolP->bsym->flags |= flag; + + S_SET_EXTERNAL (symbolP); + demand_empty_rest_of_line (); +} + +static void +s_option (x) + int x; +{ + char *opt; + char c; + + opt = input_line_pointer; + c = get_symbol_end (); + + if (*opt == 'O') + { + /* FIXME: What does this mean? */ + } + else if (strncmp (opt, "pic", 3) == 0) + { + int i; + + i = atoi (opt + 3); + if (i == 0) + mips_pic = NO_PIC; + else if (i == 2) + mips_pic = SVR4_PIC; + else + as_bad (".option pic%d not supported", i); + + if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) + { + if (g_switch_seen && g_switch_value != 0) + as_warn ("-G may not be used with SVR4 PIC code"); + g_switch_value = 0; + bfd_set_gp_size (stdoutput, 0); + } + } + else + as_warn ("Unrecognized option \"%s\"", opt); + + *input_line_pointer = c; + demand_empty_rest_of_line (); +} + +/* This structure is used to hold a stack of .set values. */ + +struct mips_option_stack +{ + struct mips_option_stack *next; + struct mips_set_options options; +}; + +static struct mips_option_stack *mips_opts_stack; + +/* Handle the .set pseudo-op. */ + +static void +s_mipsset (x) + int x; +{ + char *name = input_line_pointer, ch; + + while (!is_end_of_line[(unsigned char) *input_line_pointer]) + input_line_pointer++; + ch = *input_line_pointer; + *input_line_pointer = '\0'; + + if (strcmp (name, "reorder") == 0) + { + if (mips_opts.noreorder && prev_nop_frag != NULL) + { + /* If we still have pending nops, we can discard them. The + usual nop handling will insert any that are still + needed. */ + prev_nop_frag->fr_fix -= (prev_nop_frag_holds + * (mips_opts.mips16 ? 2 : 4)); + prev_nop_frag = NULL; + } + mips_opts.noreorder = 0; + } + else if (strcmp (name, "noreorder") == 0) + { + mips_emit_delays (true); + mips_opts.noreorder = 1; + mips_any_noreorder = 1; + } + else if (strcmp (name, "at") == 0) + { + mips_opts.noat = 0; + } + else if (strcmp (name, "noat") == 0) + { + mips_opts.noat = 1; + } + else if (strcmp (name, "macro") == 0) + { + mips_opts.warn_about_macros = 0; + } + else if (strcmp (name, "nomacro") == 0) + { + if (mips_opts.noreorder == 0) + as_bad ("`noreorder' must be set before `nomacro'"); + mips_opts.warn_about_macros = 1; + } + else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) + { + mips_opts.nomove = 0; + } + else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) + { + mips_opts.nomove = 1; + } + else if (strcmp (name, "bopt") == 0) + { + mips_opts.nobopt = 0; + } + else if (strcmp (name, "nobopt") == 0) + { + mips_opts.nobopt = 1; + } + else if (strcmp (name, "mips16") == 0 + || strcmp (name, "MIPS-16") == 0) + mips_opts.mips16 = 1; + else if (strcmp (name, "nomips16") == 0 + || strcmp (name, "noMIPS-16") == 0) + mips_opts.mips16 = 0; + else if (strncmp (name, "mips", 4) == 0) + { + int isa; + + /* Permit the user to change the ISA on the fly. Needless to + say, misuse can cause serious problems. */ + isa = atoi (name + 4); + if (isa == 0) + mips_opts.isa = file_mips_isa; + else if (isa < 1 || isa > 4) + as_bad ("unknown ISA level"); + else + mips_opts.isa = isa; + } + else if (strcmp (name, "autoextend") == 0) + mips_opts.noautoextend = 0; + else if (strcmp (name, "noautoextend") == 0) + mips_opts.noautoextend = 1; + else if (strcmp (name, "push") == 0) + { + struct mips_option_stack *s; + + s = (struct mips_option_stack *) xmalloc (sizeof *s); + s->next = mips_opts_stack; + s->options = mips_opts; + mips_opts_stack = s; + } + else if (strcmp (name, "pop") == 0) + { + struct mips_option_stack *s; + + s = mips_opts_stack; + if (s == NULL) + as_bad (".set pop with no .set push"); + else + { + /* If we're changing the reorder mode we need to handle + delay slots correctly. */ + if (s->options.noreorder && ! mips_opts.noreorder) + mips_emit_delays (true); + else if (! s->options.noreorder && mips_opts.noreorder) + { + if (prev_nop_frag != NULL) + { + prev_nop_frag->fr_fix -= (prev_nop_frag_holds + * (mips_opts.mips16 ? 2 : 4)); + prev_nop_frag = NULL; + } + } + + mips_opts = s->options; + mips_opts_stack = s->next; + free (s); + } + } + else + { + as_warn ("Tried to set unrecognized symbol: %s\n", name); + } + *input_line_pointer = ch; + demand_empty_rest_of_line (); +} + +/* Handle the .abicalls pseudo-op. I believe this is equivalent to + .option pic2. It means to generate SVR4 PIC calls. */ + +static void +s_abicalls (ignore) + int ignore; +{ + mips_pic = SVR4_PIC; + if (USE_GLOBAL_POINTER_OPT) + { + if (g_switch_seen && g_switch_value != 0) + as_warn ("-G may not be used with SVR4 PIC code"); + g_switch_value = 0; + } + bfd_set_gp_size (stdoutput, 0); + demand_empty_rest_of_line (); +} + +/* Handle the .cpload pseudo-op. This is used when generating SVR4 + PIC code. It sets the $gp register for the function based on the + function address, which is in the register named in the argument. + This uses a relocation against _gp_disp, which is handled specially + by the linker. The result is: + lui $gp,%hi(_gp_disp) + addiu $gp,$gp,%lo(_gp_disp) + addu $gp,$gp,.cpload argument + The .cpload argument is normally $25 == $t9. */ + +static void +s_cpload (ignore) + int ignore; +{ + expressionS ex; + int icnt = 0; + + /* If we are not generating SVR4 PIC code, .cpload is ignored. */ + if (mips_pic != SVR4_PIC) + { + s_ignore (0); + return; + } + + /* .cpload should be a in .set noreorder section. */ + if (mips_opts.noreorder == 0) + as_warn (".cpload not in noreorder section"); + + ex.X_op = O_symbol; + ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); + ex.X_op_symbol = NULL; + ex.X_add_number = 0; + + /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ + ex.X_add_symbol->bsym->flags |= BSF_OBJECT; + + macro_build_lui ((char *) NULL, &icnt, &ex, GP); + macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, + (int) BFD_RELOC_LO16); + + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", + GP, GP, tc_get_register (0)); + + demand_empty_rest_of_line (); +} + +/* Handle the .cprestore pseudo-op. This stores $gp into a given + offset from $sp. The offset is remembered, and after making a PIC + call $gp is restored from that location. */ + +static void +s_cprestore (ignore) + int ignore; +{ + expressionS ex; + int icnt = 0; + + /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ + if (mips_pic != SVR4_PIC) + { + s_ignore (0); + return; + } + + mips_cprestore_offset = get_absolute_expression (); + + ex.X_op = O_constant; + ex.X_add_symbol = NULL; + ex.X_op_symbol = NULL; + ex.X_add_number = mips_cprestore_offset; + + macro_build ((char *) NULL, &icnt, &ex, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "sw" : "sd"), + "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); + + demand_empty_rest_of_line (); +} + +/* Handle the .gpword pseudo-op. This is used when generating PIC + code. It generates a 32 bit GP relative reloc. */ + +static void +s_gpword (ignore) + int ignore; +{ + symbolS *label; + expressionS ex; + char *p; + + /* When not generating PIC code, this is treated as .word. */ + if (mips_pic != SVR4_PIC) + { + s_cons (2); + return; + } + + label = insn_labels != NULL ? insn_labels->label : NULL; + mips_emit_delays (true); + if (auto_align) + mips_align (2, 0, label); + mips_clear_insn_labels (); + + expression (&ex); + + if (ex.X_op != O_symbol || ex.X_add_number != 0) + { + as_bad ("Unsupported use of .gpword"); + ignore_rest_of_line (); + } + + p = frag_more (4); + md_number_to_chars (p, (valueT) 0, 4); + fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, + BFD_RELOC_MIPS_GPREL32); + + demand_empty_rest_of_line (); +} + +/* Handle the .cpadd pseudo-op. This is used when dealing with switch + tables in SVR4 PIC code. */ + +static void +s_cpadd (ignore) + int ignore; +{ + int icnt = 0; + int reg; + + /* This is ignored when not generating SVR4 PIC code. */ + if (mips_pic != SVR4_PIC) + { + s_ignore (0); + return; + } + + /* Add $gp to the register named as an argument. */ + reg = tc_get_register (0); + macro_build ((char *) NULL, &icnt, (expressionS *) NULL, + ((bfd_arch_bits_per_address (stdoutput) == 32 + || mips_opts.isa < 3) + ? "addu" : "daddu"), + "d,v,t", reg, reg, GP); + + demand_empty_rest_of_line (); +} + +/* Handle the .insn pseudo-op. This marks instruction labels in + mips16 mode. This permits the linker to handle them specially, + such as generating jalx instructions when needed. We also make + them odd for the duration of the assembly, in order to generate the + right sort of code. We will make them even in the adjust_symtab + routine, while leaving them marked. This is convenient for the + debugger and the disassembler. The linker knows to make them odd + again. */ + +static void +s_insn (ignore) + int ignore; +{ + if (mips_opts.mips16) + mips16_mark_labels (); + + demand_empty_rest_of_line (); +} + +/* Handle a .stabn directive. We need these in order to mark a label + as being a mips16 text label correctly. Sometimes the compiler + will emit a label, followed by a .stabn, and then switch sections. + If the label and .stabn are in mips16 mode, then the label is + really a mips16 text label. */ + +static void +s_mips_stab (type) + int type; +{ + if (type == 'n' && mips_opts.mips16) + mips16_mark_labels (); + + s_stab (type); +} + +/* Parse a register string into a number. Called from the ECOFF code + to parse .frame. The argument is non-zero if this is the frame + register, so that we can record it in mips_frame_reg. */ + +int +tc_get_register (frame) + int frame; +{ + int reg; + + SKIP_WHITESPACE (); + if (*input_line_pointer++ != '$') + { + as_warn ("expected `$'"); + reg = 0; + } + else if (isdigit ((unsigned char) *input_line_pointer)) + { + reg = get_absolute_expression (); + if (reg < 0 || reg >= 32) + { + as_warn ("Bad register number"); + reg = 0; + } + } + else + { + if (strncmp (input_line_pointer, "fp", 2) == 0) + reg = FP; + else if (strncmp (input_line_pointer, "sp", 2) == 0) + reg = SP; + else if (strncmp (input_line_pointer, "gp", 2) == 0) + reg = GP; + else if (strncmp (input_line_pointer, "at", 2) == 0) + reg = AT; + else + { + as_warn ("Unrecognized register name"); + reg = 0; + } + input_line_pointer += 2; + } + if (frame) + mips_frame_reg = reg != 0 ? reg : SP; + return reg; +} + +valueT +md_section_align (seg, addr) + asection *seg; + valueT addr; +{ + int align = bfd_get_section_alignment (stdoutput, seg); + +#ifdef OBJ_ELF + /* We don't need to align ELF sections to the full alignment. + However, Irix 5 may prefer that we align them at least to a 16 + byte boundary. We don't bother to align the sections if we are + targeted for an embedded system. */ + if (strcmp (TARGET_OS, "elf") == 0) + return addr; + if (align > 4) + align = 4; +#endif + + return ((addr + (1 << align) - 1) & (-1 << align)); +} + +/* Utility routine, called from above as well. If called while the + input file is still being read, it's only an approximation. (For + example, a symbol may later become defined which appeared to be + undefined earlier.) */ + +static int +nopic_need_relax (sym, before_relaxing) + symbolS *sym; + int before_relaxing; +{ + if (sym == 0) + return 0; + + if (USE_GLOBAL_POINTER_OPT) + { + const char *symname; + int change; + + /* Find out whether this symbol can be referenced off the GP + register. It can be if it is smaller than the -G size or if + it is in the .sdata or .sbss section. Certain symbols can + not be referenced off the GP, although it appears as though + they can. */ + symname = S_GET_NAME (sym); + if (symname != (const char *) NULL + && (strcmp (symname, "eprol") == 0 + || strcmp (symname, "etext") == 0 + || strcmp (symname, "_gp") == 0 + || strcmp (symname, "edata") == 0 + || strcmp (symname, "_fbss") == 0 + || strcmp (symname, "_fdata") == 0 + || strcmp (symname, "_ftext") == 0 + || strcmp (symname, "end") == 0 + || strcmp (symname, "_gp_disp") == 0)) + change = 1; + else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) + && (0 +#ifndef NO_ECOFF_DEBUGGING + || (sym->ecoff_extern_size != 0 + && sym->ecoff_extern_size <= g_switch_value) +#endif + /* We must defer this decision until after the whole + file has been read, since there might be a .extern + after the first use of this symbol. */ + || (before_relaxing +#ifndef NO_ECOFF_DEBUGGING + && sym->ecoff_extern_size == 0 +#endif + && S_GET_VALUE (sym) == 0) + || (S_GET_VALUE (sym) != 0 + && S_GET_VALUE (sym) <= g_switch_value))) + change = 0; + else + { + const char *segname; + + segname = segment_name (S_GET_SEGMENT (sym)); + assert (strcmp (segname, ".lit8") != 0 + && strcmp (segname, ".lit4") != 0); + change = (strcmp (segname, ".sdata") != 0 + && strcmp (segname, ".sbss") != 0); + } + return change; + } + else + /* We are not optimizing for the GP register. */ + return 1; +} + +/* Given a mips16 variant frag FRAGP, return non-zero if it needs an + extended opcode. SEC is the section the frag is in. */ + +static int +mips16_extended_frag (fragp, sec, stretch) + fragS *fragp; + asection *sec; + long stretch; +{ + int type; + register const struct mips16_immed_operand *op; + offsetT val; + int mintiny, maxtiny; + segT symsec; + + if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) + return 0; + if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) + return 1; + + type = RELAX_MIPS16_TYPE (fragp->fr_subtype); + op = mips16_immed_operands; + while (op->type != type) + { + ++op; + assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); + } + + if (op->unsp) + { + if (type == '<' || type == '>' || type == '[' || type == ']') + { + mintiny = 1; + maxtiny = 1 << op->nbits; + } + else + { + mintiny = 0; + maxtiny = (1 << op->nbits) - 1; + } + } + else + { + mintiny = - (1 << (op->nbits - 1)); + maxtiny = (1 << (op->nbits - 1)) - 1; + } + + /* We can't call S_GET_VALUE here, because we don't want to lock in + a particular frag address. */ + if (fragp->fr_symbol->sy_value.X_op == O_constant) + { + val = (fragp->fr_symbol->sy_value.X_add_number + + fragp->fr_symbol->sy_frag->fr_address); + symsec = S_GET_SEGMENT (fragp->fr_symbol); + } + else if (fragp->fr_symbol->sy_value.X_op == O_symbol + && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op + == O_constant)) + { + val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number + + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address + + fragp->fr_symbol->sy_value.X_add_number + + fragp->fr_symbol->sy_frag->fr_address); + symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); + } + else + return 1; + + if (op->pcrel) + { + addressT addr; + + /* We won't have the section when we are called from + mips_relax_frag. However, we will always have been called + from md_estimate_size_before_relax first. If this is a + branch to a different section, we mark it as such. If SEC is + NULL, and the frag is not marked, then it must be a branch to + the same section. */ + if (sec == NULL) + { + if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) + return 1; + } + else + { + if (symsec != sec) + { + fragp->fr_subtype = + RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); + + /* FIXME: We should support this, and let the linker + catch branches and loads that are out of range. */ + as_bad_where (fragp->fr_file, fragp->fr_line, + "unsupported PC relative reference to different section"); + + return 1; + } + } + + /* In this case, we know for sure that the symbol fragment is in + the same section. If the fr_address of the symbol fragment + is greater then the address of this fragment we want to add + in STRETCH in order to get a better estimate of the address. + This particularly matters because of the shift bits. */ + if (stretch != 0 + && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) + { + fragS *f; + + /* Adjust stretch for any alignment frag. Note that if have + been expanding the earlier code, the symbol may be + defined in what appears to be an earlier frag. FIXME: + This doesn't handle the fr_subtype field, which specifies + a maximum number of bytes to skip when doing an + alignment. */ + for (f = fragp; + f != NULL && f != fragp->fr_symbol->sy_frag; + f = f->fr_next) + { + if (f->fr_type == rs_align || f->fr_type == rs_align_code) + { + if (stretch < 0) + stretch = - ((- stretch) + & ~ ((1 << (int) f->fr_offset) - 1)); + else + stretch &= ~ ((1 << (int) f->fr_offset) - 1); + if (stretch == 0) + break; + } + } + if (f != NULL) + val += stretch; + } + + addr = fragp->fr_address + fragp->fr_fix; + + /* The base address rules are complicated. The base address of + a branch is the following instruction. The base address of a + PC relative load or add is the instruction itself, but if it + is in a delay slot (in which case it can not be extended) use + the address of the instruction whose delay slot it is in. */ + if (type == 'p' || type == 'q') + { + addr += 2; + + /* If we are currently assuming that this frag should be + extended, then, the current address is two bytes + higher. */ + if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) + addr += 2; + + /* Ignore the low bit in the target, since it will be set + for a text label. */ + if ((val & 1) != 0) + --val; + } + else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) + addr -= 4; + else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) + addr -= 2; + + val -= addr & ~ ((1 << op->shift) - 1); + + /* Branch offsets have an implicit 0 in the lowest bit. */ + if (type == 'p' || type == 'q') + val /= 2; + + /* If any of the shifted bits are set, we must use an extended + opcode. If the address depends on the size of this + instruction, this can lead to a loop, so we arrange to always + use an extended opcode. We only check this when we are in + the main relaxation loop, when SEC is NULL. */ + if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) + { + fragp->fr_subtype = + RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); + return 1; + } + + /* If we are about to mark a frag as extended because the value + is precisely maxtiny + 1, then there is a chance of an + infinite loop as in the following code: + la $4,foo + .skip 1020 + .align 2 + foo: + In this case when the la is extended, foo is 0x3fc bytes + away, so the la can be shrunk, but then foo is 0x400 away, so + the la must be extended. To avoid this loop, we mark the + frag as extended if it was small, and is about to become + extended with a value of maxtiny + 1. */ + if (val == ((maxtiny + 1) << op->shift) + && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) + && sec == NULL) + { + fragp->fr_subtype = + RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); + return 1; + } + } + else if (symsec != absolute_section && sec != NULL) + as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); + + if ((val & ((1 << op->shift) - 1)) != 0 + || val < (mintiny << op->shift) + || val > (maxtiny << op->shift)) + return 1; + else + return 0; +} + +/* Estimate the size of a frag before relaxing. Unless this is the + mips16, we are not really relaxing here, and the final size is + encoded in the subtype information. For the mips16, we have to + decide whether we are using an extended opcode or not. */ + +/*ARGSUSED*/ +int +md_estimate_size_before_relax (fragp, segtype) + fragS *fragp; + asection *segtype; +{ + int change; + + if (RELAX_MIPS16_P (fragp->fr_subtype)) + { + if (mips16_extended_frag (fragp, segtype, 0)) + { + fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); + return 4; + } + else + { + fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); + return 2; + } + } + + if (mips_pic == NO_PIC) + { + change = nopic_need_relax (fragp->fr_symbol, 0); + } + else if (mips_pic == SVR4_PIC) + { + symbolS *sym; + asection *symsec; + + sym = fragp->fr_symbol; + + /* Handle the case of a symbol equated to another symbol. */ + while (sym->sy_value.X_op == O_symbol + && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) + { + symbolS *n; + + /* It's possible to get a loop here in a badly written + program. */ + n = sym->sy_value.X_add_symbol; + if (n == sym) + break; + sym = n; + } + + symsec = S_GET_SEGMENT (sym); + + /* This must duplicate the test in adjust_reloc_syms. */ + change = (symsec != &bfd_und_section + && symsec != &bfd_abs_section + && ! bfd_is_com_section (symsec)); + } + else + abort (); + + if (change) + { + /* Record the offset to the first reloc in the fr_opcode field. + This lets md_convert_frag and tc_gen_reloc know that the code + must be expanded. */ + fragp->fr_opcode = (fragp->fr_literal + + fragp->fr_fix + - RELAX_OLD (fragp->fr_subtype) + + RELAX_RELOC1 (fragp->fr_subtype)); + /* FIXME: This really needs as_warn_where. */ + if (RELAX_WARN (fragp->fr_subtype)) + as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); + } + + if (! change) + return 0; + else + return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); +} + +/* This is called to see whether a reloc against a defined symbol + should be converted into a reloc against a section. Don't adjust + MIPS16 jump relocations, so we don't have to worry about the format + of the offset in the .o file. Don't adjust relocations against + mips16 symbols, so that the linker can find them if it needs to set + up a stub. */ + +int +mips_fix_adjustable (fixp) + fixS *fixp; +{ + if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) + return 0; + if (fixp->fx_addsy == NULL) + return 1; +#ifdef OBJ_ELF + if (OUTPUT_FLAVOR == bfd_target_elf_flavour + && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 + && fixp->fx_subsy == NULL) + return 0; +#endif + return 1; +} + +/* Translate internal representation of relocation info to BFD target + format. */ + +arelent ** +tc_gen_reloc (section, fixp) + asection *section; + fixS *fixp; +{ + static arelent *retval[4]; + arelent *reloc; + bfd_reloc_code_real_type code; + + reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); + retval[1] = NULL; + + reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + + if (mips_pic == EMBEDDED_PIC + && SWITCH_TABLE (fixp)) + { + /* For a switch table entry we use a special reloc. The addend + is actually the difference between the reloc address and the + subtrahend. */ + reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); + if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) + as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); + fixp->fx_r_type = BFD_RELOC_GPREL32; + } + else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) + { + /* We use a special addend for an internal RELLO reloc. */ + if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) + reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); + else + reloc->addend = fixp->fx_addnumber + reloc->address; + } + else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) + { + assert (fixp->fx_next != NULL + && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); + /* We use a special addend for an internal RELHI reloc. The + reloc is relative to the RELLO; adjust the addend + accordingly. */ + if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) + reloc->addend = (fixp->fx_next->fx_frag->fr_address + + fixp->fx_next->fx_where + - S_GET_VALUE (fixp->fx_subsy)); + else + reloc->addend = (fixp->fx_addnumber + + fixp->fx_next->fx_frag->fr_address + + fixp->fx_next->fx_where); + } + else if (fixp->fx_pcrel == 0) + reloc->addend = fixp->fx_addnumber; + else + { + if (OUTPUT_FLAVOR != bfd_target_aout_flavour) + /* A gruesome hack which is a result of the gruesome gas reloc + handling. */ + reloc->addend = reloc->address; + else + reloc->addend = -reloc->address; + } + + /* If this is a variant frag, we may need to adjust the existing + reloc and generate a new one. */ + if (fixp->fx_frag->fr_opcode != NULL + && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL + || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 + || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 + || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 + || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 + || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 + || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) + { + arelent *reloc2; + + assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); + + /* If this is not the last reloc in this frag, then we have two + GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a + CALL_HI16/CALL_LO16, both of which are being replaced. Let + the second one handle all of them. */ + if (fixp->fx_next != NULL + && fixp->fx_frag == fixp->fx_next->fx_frag) + { + assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL + && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) + || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 + && (fixp->fx_next->fx_r_type + == BFD_RELOC_MIPS_GOT_LO16)) + || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 + && (fixp->fx_next->fx_r_type + == BFD_RELOC_MIPS_CALL_LO16))); + retval[0] = NULL; + return retval; + } + + fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); + retval[2] = NULL; + reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; + reloc2->address = (reloc->address + + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) + - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); + reloc2->addend = fixp->fx_addnumber; + reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); + assert (reloc2->howto != NULL); + + if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) + { + arelent *reloc3; + + reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); + retval[3] = NULL; + *reloc3 = *reloc2; + reloc3->address += 4; + } + + if (mips_pic == NO_PIC) + { + assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); + fixp->fx_r_type = BFD_RELOC_HI16_S; + } + else if (mips_pic == SVR4_PIC) + { + switch (fixp->fx_r_type) + { + default: + abort (); + case BFD_RELOC_MIPS_GOT16: + break; + case BFD_RELOC_MIPS_CALL16: + case BFD_RELOC_MIPS_GOT_LO16: + case BFD_RELOC_MIPS_CALL_LO16: + fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; + break; + } + } + else + abort (); + } + + /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that + fixup_segment converted a non-PC relative reloc into a PC + relative reloc. In such a case, we need to convert the reloc + code. */ + code = fixp->fx_r_type; + if (fixp->fx_pcrel) + { + switch (code) + { + case BFD_RELOC_8: + code = BFD_RELOC_8_PCREL; + break; + case BFD_RELOC_16: + code = BFD_RELOC_16_PCREL; + break; + case BFD_RELOC_32: + code = BFD_RELOC_32_PCREL; + break; + case BFD_RELOC_64: + code = BFD_RELOC_64_PCREL; + break; + case BFD_RELOC_8_PCREL: + case BFD_RELOC_16_PCREL: + case BFD_RELOC_32_PCREL: + case BFD_RELOC_64_PCREL: + case BFD_RELOC_16_PCREL_S2: + case BFD_RELOC_PCREL_HI16_S: + case BFD_RELOC_PCREL_LO16: + break; + default: + as_bad_where (fixp->fx_file, fixp->fx_line, + "Cannot make %s relocation PC relative", + bfd_get_reloc_code_name (code)); + } + } + + /* To support a PC relative reloc when generating embedded PIC code + for ECOFF, we use a Cygnus extension. We check for that here to + make sure that we don't let such a reloc escape normally. */ + if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour + && code == BFD_RELOC_16_PCREL_S2 + && mips_pic != EMBEDDED_PIC) + reloc->howto = NULL; + else + reloc->howto = bfd_reloc_type_lookup (stdoutput, code); + + if (reloc->howto == NULL) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + "Can not represent %s relocation in this object file format", + bfd_get_reloc_code_name (code)); + retval[0] = NULL; + } + + return retval; +} + +/* Relax a machine dependent frag. This returns the amount by which + the current size of the frag should change. */ + +int +mips_relax_frag (fragp, stretch) + fragS *fragp; + long stretch; +{ + if (! RELAX_MIPS16_P (fragp->fr_subtype)) + return 0; + + if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) + { + if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) + return 0; + fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); + return 2; + } + else + { + if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) + return 0; + fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); + return -2; + } + + return 0; +} + +/* Convert a machine dependent frag. */ + +void +md_convert_frag (abfd, asec, fragp) + bfd *abfd; + segT asec; + fragS *fragp; +{ + int old, new; + char *fixptr; + + if (RELAX_MIPS16_P (fragp->fr_subtype)) + { + int type; + register const struct mips16_immed_operand *op; + boolean small, ext; + offsetT val; + bfd_byte *buf; + unsigned long insn; + boolean use_extend; + unsigned short extend; + + type = RELAX_MIPS16_TYPE (fragp->fr_subtype); + op = mips16_immed_operands; + while (op->type != type) + ++op; + + if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) + { + small = false; + ext = true; + } + else + { + small = true; + ext = false; + } + + resolve_symbol_value (fragp->fr_symbol, 1); + val = S_GET_VALUE (fragp->fr_symbol); + if (op->pcrel) + { + addressT addr; + + addr = fragp->fr_address + fragp->fr_fix; + + /* The rules for the base address of a PC relative reloc are + complicated; see mips16_extended_frag. */ + if (type == 'p' || type == 'q') + { + addr += 2; + if (ext) + addr += 2; + /* Ignore the low bit in the target, since it will be + set for a text label. */ + if ((val & 1) != 0) + --val; + } + else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) + addr -= 4; + else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) + addr -= 2; + + addr &= ~ (addressT) ((1 << op->shift) - 1); + val -= addr; + + /* Make sure the section winds up with the alignment we have + assumed. */ + if (op->shift > 0) + record_alignment (asec, op->shift); + } + + if (ext + && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) + || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) + as_warn_where (fragp->fr_file, fragp->fr_line, + "extended instruction in delay slot"); + + buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); + + if (target_big_endian) + insn = bfd_getb16 (buf); + else + insn = bfd_getl16 (buf); + + mips16_immed (fragp->fr_file, fragp->fr_line, type, val, + RELAX_MIPS16_USER_EXT (fragp->fr_subtype), + small, ext, &insn, &use_extend, &extend); + + if (use_extend) + { + md_number_to_chars (buf, 0xf000 | extend, 2); + fragp->fr_fix += 2; + buf += 2; + } + + md_number_to_chars (buf, insn, 2); + fragp->fr_fix += 2; + buf += 2; + } + else + { + if (fragp->fr_opcode == NULL) + return; + + old = RELAX_OLD (fragp->fr_subtype); + new = RELAX_NEW (fragp->fr_subtype); + fixptr = fragp->fr_literal + fragp->fr_fix; + + if (new > 0) + memcpy (fixptr - old, fixptr, new); + + fragp->fr_fix += new - old; + } +} + +#ifdef OBJ_ELF + +/* This function is called after the relocs have been generated. + We've been storing mips16 text labels as odd. Here we convert them + back to even for the convenience of the debugger. */ + +void +mips_frob_file_after_relocs () +{ + asymbol **syms; + unsigned int count, i; + + if (OUTPUT_FLAVOR != bfd_target_elf_flavour) + return; + + syms = bfd_get_outsymbols (stdoutput); + count = bfd_get_symcount (stdoutput); + for (i = 0; i < count; i++, syms++) + { + if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 + && ((*syms)->value & 1) != 0) + { + (*syms)->value &= ~1; + /* If the symbol has an odd size, it was probably computed + incorrectly, so adjust that as well. */ + if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) + ++elf_symbol (*syms)->internal_elf_sym.st_size; + } + } +} + +#endif + +/* This function is called whenever a label is defined. It is used + when handling branch delays; if a branch has a label, we assume we + can not move it. */ + +void +mips_define_label (sym) + symbolS *sym; +{ + struct insn_label_list *l; + + if (free_insn_labels == NULL) + l = (struct insn_label_list *) xmalloc (sizeof *l); + else + { + l = free_insn_labels; + free_insn_labels = l->next; + } + + l->label = sym; + l->next = insn_labels; + insn_labels = l; +} + +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) + +/* Some special processing for a MIPS ELF file. */ + +void +mips_elf_final_processing () +{ + /* Write out the register information. */ + if (! mips_64) + { + Elf32_RegInfo s; + + s.ri_gprmask = mips_gprmask; + s.ri_cprmask[0] = mips_cprmask[0]; + s.ri_cprmask[1] = mips_cprmask[1]; + s.ri_cprmask[2] = mips_cprmask[2]; + s.ri_cprmask[3] = mips_cprmask[3]; + /* The gp_value field is set by the MIPS ELF backend. */ + + bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, + ((Elf32_External_RegInfo *) + mips_regmask_frag)); + } + else + { + Elf64_Internal_RegInfo s; + + s.ri_gprmask = mips_gprmask; + s.ri_pad = 0; + s.ri_cprmask[0] = mips_cprmask[0]; + s.ri_cprmask[1] = mips_cprmask[1]; + s.ri_cprmask[2] = mips_cprmask[2]; + s.ri_cprmask[3] = mips_cprmask[3]; + /* The gp_value field is set by the MIPS ELF backend. */ + + bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, + ((Elf64_External_RegInfo *) + mips_regmask_frag)); + } + + /* Set the MIPS ELF flag bits. FIXME: There should probably be some + sort of BFD interface for this. */ + if (mips_any_noreorder) + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; + if (mips_pic != NO_PIC) + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; +} + +#endif /* OBJ_ELF || OBJ_MAYBE_ELF */ + +/* These functions should really be defined by the object file format, + since they are related to debugging information. However, this + code has to work for the a.out format, which does not define them, + so we provide simple versions here. These don't actually generate + any debugging information, but they do simple checking and someday + somebody may make them useful. */ + +typedef struct loc +{ + struct loc *loc_next; + unsigned long loc_fileno; + unsigned long loc_lineno; + unsigned long loc_offset; + unsigned short loc_delta; + unsigned short loc_count; +#if 0 + fragS *loc_frag; +#endif +} +locS; + +typedef struct proc + { + struct proc *proc_next; + struct symbol *proc_isym; + struct symbol *proc_end; + unsigned long proc_reg_mask; + unsigned long proc_reg_offset; + unsigned long proc_fpreg_mask; + unsigned long proc_fpreg_offset; + unsigned long proc_frameoffset; + unsigned long proc_framereg; + unsigned long proc_pcreg; + locS *proc_iline; + struct file *proc_file; + int proc_index; + } +procS; + +typedef struct file + { + struct file *file_next; + unsigned long file_fileno; + struct symbol *file_symbol; + struct symbol *file_end; + struct proc *file_proc; + int file_numprocs; + } +fileS; + +static struct obstack proc_frags; +static procS *proc_lastP; +static procS *proc_rootP; +static int numprocs; + +static void +md_obj_begin () +{ + obstack_begin (&proc_frags, 0x2000); +} + +static void +md_obj_end () +{ + /* check for premature end, nesting errors, etc */ + if (proc_lastP && proc_lastP->proc_end == NULL) + as_warn ("missing `.end' at end of assembly"); +} + +static long +get_number () +{ + int negative = 0; + long val = 0; + + if (*input_line_pointer == '-') + { + ++input_line_pointer; + negative = 1; + } + if (!isdigit (*input_line_pointer)) + as_bad ("Expected simple number."); + if (input_line_pointer[0] == '0') + { + if (input_line_pointer[1] == 'x') + { + input_line_pointer += 2; + while (isxdigit (*input_line_pointer)) + { + val <<= 4; + val |= hex_value (*input_line_pointer++); + } + return negative ? -val : val; + } + else + { + ++input_line_pointer; + while (isdigit (*input_line_pointer)) + { + val <<= 3; + val |= *input_line_pointer++ - '0'; + } + return negative ? -val : val; + } + } + if (!isdigit (*input_line_pointer)) + { + printf (" *input_line_pointer == '%c' 0x%02x\n", + *input_line_pointer, *input_line_pointer); + as_warn ("Invalid number"); + return -1; + } + while (isdigit (*input_line_pointer)) + { + val *= 10; + val += *input_line_pointer++ - '0'; + } + return negative ? -val : val; +} + +/* The .file directive; just like the usual .file directive, but there + is an initial number which is the ECOFF file index. */ + +static void +s_file (x) + int x; +{ + int line; + + line = get_number (); + s_app_file (0); +} + + +/* The .end directive. */ + +static void +s_mipsend (x) + int x; +{ + symbolS *p; + + if (!is_end_of_line[(unsigned char) *input_line_pointer]) + { + p = get_symbol (); + demand_empty_rest_of_line (); + } + else + p = NULL; + if (now_seg != text_section) + as_warn (".end not in text section"); + if (!proc_lastP) + { + as_warn (".end and no .ent seen yet."); + return; + } + + if (p != NULL) + { + assert (S_GET_NAME (p)); + if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) + as_warn (".end symbol does not match .ent symbol."); + } + + proc_lastP->proc_end = (symbolS *) 1; +} + +/* The .aent and .ent directives. */ + +static void +s_ent (aent) + int aent; +{ + int number = 0; + procS *procP; + symbolS *symbolP; + + symbolP = get_symbol (); + if (*input_line_pointer == ',') + input_line_pointer++; + SKIP_WHITESPACE (); + if (isdigit (*input_line_pointer) || *input_line_pointer == '-') + number = get_number (); + if (now_seg != text_section) + as_warn (".ent or .aent not in text section."); + + if (!aent && proc_lastP && proc_lastP->proc_end == NULL) + as_warn ("missing `.end'"); + + if (!aent) + { + procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); + procP->proc_isym = symbolP; + procP->proc_reg_mask = 0; + procP->proc_reg_offset = 0; + procP->proc_fpreg_mask = 0; + procP->proc_fpreg_offset = 0; + procP->proc_frameoffset = 0; + procP->proc_framereg = 0; + procP->proc_pcreg = 0; + procP->proc_end = NULL; + procP->proc_next = NULL; + if (proc_lastP) + proc_lastP->proc_next = procP; + else + proc_rootP = procP; + proc_lastP = procP; + numprocs++; + } + demand_empty_rest_of_line (); +} + +/* The .frame directive. */ + +#if 0 +static void +s_frame (x) + int x; +{ + char str[100]; + symbolS *symP; + int frame_reg; + int frame_off; + int pcreg; + + frame_reg = tc_get_register (1); + if (*input_line_pointer == ',') + input_line_pointer++; + frame_off = get_absolute_expression (); + if (*input_line_pointer == ',') + input_line_pointer++; + pcreg = tc_get_register (0); + + /* bob third eye */ + assert (proc_rootP); + proc_rootP->proc_framereg = frame_reg; + proc_rootP->proc_frameoffset = frame_off; + proc_rootP->proc_pcreg = pcreg; + /* bob macho .frame */ + + /* We don't have to write out a frame stab for unoptimized code. */ + if (!(frame_reg == FP && frame_off == 0)) + { + if (!proc_lastP) + as_warn ("No .ent for .frame to use."); + (void) sprintf (str, "R%d;%d", frame_reg, frame_off); + symP = symbol_new (str, N_VFP, 0, frag_now); + S_SET_TYPE (symP, N_RMASK); + S_SET_OTHER (symP, 0); + S_SET_DESC (symP, 0); + symP->sy_forward = proc_lastP->proc_isym; + /* bob perhaps I should have used pseudo set */ + } + demand_empty_rest_of_line (); +} +#endif + +/* The .fmask and .mask directives. */ + +#if 0 +static void +s_mask (reg_type) + char reg_type; +{ + char str[100], *strP; + symbolS *symP; + int i; + unsigned int mask; + int off; + + mask = get_number (); + if (*input_line_pointer == ',') + input_line_pointer++; + off = get_absolute_expression (); + + /* bob only for coff */ + assert (proc_rootP); + if (reg_type == 'F') + { + proc_rootP->proc_fpreg_mask = mask; + proc_rootP->proc_fpreg_offset = off; + } + else + { + proc_rootP->proc_reg_mask = mask; + proc_rootP->proc_reg_offset = off; + } + + /* bob macho .mask + .fmask */ + + /* We don't have to write out a mask stab if no saved regs. */ + if (!(mask == 0)) + { + if (!proc_lastP) + as_warn ("No .ent for .mask to use."); + strP = str; + for (i = 0; i < 32; i++) + { + if (mask % 2) + { + sprintf (strP, "%c%d,", reg_type, i); + strP += strlen (strP); + } + mask /= 2; + } + sprintf (strP, ";%d,", off); + symP = symbol_new (str, N_RMASK, 0, frag_now); + S_SET_TYPE (symP, N_RMASK); + S_SET_OTHER (symP, 0); + S_SET_DESC (symP, 0); + symP->sy_forward = proc_lastP->proc_isym; + /* bob perhaps I should have used pseudo set */ + } +} +#endif + +/* The .loc directive. */ + +#if 0 +static void +s_loc (x) + int x; +{ + symbolS *symbolP; + int lineno; + int addroff; + + assert (now_seg == text_section); + + lineno = get_number (); + addroff = frag_now_fix (); + + symbolP = symbol_new ("", N_SLINE, addroff, frag_now); + S_SET_TYPE (symbolP, N_SLINE); + S_SET_OTHER (symbolP, 0); + S_SET_DESC (symbolP, lineno); + symbolP->sy_segment = now_seg; +} +#endif diff --git a/contrib/binutils/gas/config/tc-mips.h b/contrib/binutils/gas/config/tc-mips.h new file mode 100644 index 0000000000000..868aedea6a5e3 --- /dev/null +++ b/contrib/binutils/gas/config/tc-mips.h @@ -0,0 +1,153 @@ +/* tc-mips.h -- header file for tc-mips.c. + Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. + Contributed by the OSF and Ralph Campbell. + Written by Keith Knowles and Ralph Campbell, working independently. + Modified for ECOFF support by Ian Lance Taylor of Cygnus Support. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef TC_MIPS + +#define TC_MIPS + +#ifdef ANSI_PROTOTYPES +struct frag; +struct expressionS; +#endif + +/* Default to big endian. */ +#ifndef TARGET_BYTES_BIG_ENDIAN +#define TARGET_BYTES_BIG_ENDIAN 1 +#endif + +#define TARGET_ARCH bfd_arch_mips + +#define ONLY_STANDARD_ESCAPES +#define WORKING_DOT_WORD 1 +#define OLD_FLOAT_READS +#define REPEAT_CONS_EXPRESSIONS +#define RELOC_EXPANSION_POSSIBLE +#define MAX_RELOC_EXPANSION 3 +#define LOCAL_LABELS_FB 1 + +/* Maximum symbol offset that can be encoded in a BFD_RELOC_MIPS_GPREL + relocation: */ +#define MAX_GPREL_OFFSET (0x7FF4) + +#define md_relax_frag(fragp, stretch) mips_relax_frag(fragp, stretch) +extern int mips_relax_frag PARAMS ((struct frag *, long)); + +#define md_undefined_symbol(name) (0) +#define md_operand(x) + +/* We permit PC relative difference expressions when generating + embedded PIC code. */ +#define DIFF_EXPR_OK + +/* Tell assembler that we have an itbl_mips.h header file to include. */ +#define HAVE_ITBL_CPU + +/* The endianness of the target format may change based on command + line arguments. */ +#define TARGET_FORMAT mips_target_format() +extern const char *mips_target_format PARAMS ((void)); + +struct mips_cl_insn +{ + unsigned long insn_opcode; + const struct mips_opcode *insn_mo; + /* The next two fields are used when generating mips16 code. */ + boolean use_extend; + unsigned short extend; +}; + +extern int tc_get_register PARAMS ((int frame)); + +#define tc_init_after_args() mips_init_after_args() +extern void mips_init_after_args PARAMS ((void)); + +#define md_parse_long_option(arg) mips_parse_long_option (arg) +extern int mips_parse_long_option PARAMS ((const char *)); + +#define tc_frob_label(sym) mips_define_label (sym) +extern void mips_define_label PARAMS ((struct symbol *)); + +#define tc_frob_file_before_adjust() mips_frob_file_before_adjust () +extern void mips_frob_file_before_adjust PARAMS ((void)); + +#define tc_frob_file() mips_frob_file () +extern void mips_frob_file PARAMS ((void)); + +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) +#define tc_frob_file_after_relocs mips_frob_file_after_relocs +extern void mips_frob_file_after_relocs PARAMS ((void)); +#endif + +#define TC_CONS_FIX_NEW cons_fix_new_mips +extern void cons_fix_new_mips + PARAMS ((struct frag *, int, unsigned int, struct expressionS *)); + +#define tc_fix_adjustable(fixp) mips_fix_adjustable (fixp) +extern int mips_fix_adjustable PARAMS ((struct fix *)); + +/* When generating embedded PIC code we must keep PC relative + relocations. */ +#define TC_FORCE_RELOCATION(fixp) mips_force_relocation (fixp) +extern int mips_force_relocation PARAMS ((struct fix *)); + +/* md_apply_fix sets fx_done correctly. */ +#define TC_HANDLE_FX_DONE 1 + +/* Register mask variables. These are set by the MIPS assembly code + and used by ECOFF and possibly other object file formats. */ +extern unsigned long mips_gprmask; +extern unsigned long mips_cprmask[4]; + +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) + +#define elf_tc_final_processing mips_elf_final_processing +extern void mips_elf_final_processing PARAMS ((void)); + +#define ELF_TC_SPECIAL_SECTIONS \ + { ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, \ + { ".sbss", SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, \ + { ".lit4", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, \ + { ".lit8", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, \ + { ".ucode", SHT_MIPS_UCODE, 0 }, \ + { ".mdebug", SHT_MIPS_DEBUG, 0 }, +/* Other special sections not generated by the assembler: .reginfo, + .liblist, .conflict, .gptab, .got, .dynamic, .rel.dyn. */ + +#endif + +extern void md_mips_end PARAMS ((void)); +#define md_end() md_mips_end() + +#define USE_GLOBAL_POINTER_OPT (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ + || OUTPUT_FLAVOR == bfd_target_elf_flavour) + +extern void mips_pop_insert PARAMS ((void)); +#define md_pop_insert() mips_pop_insert() + +extern void mips_flush_pending_output PARAMS ((void)); +#define md_flush_pending_output mips_flush_pending_output + +extern void mips_enable_auto_align PARAMS ((void)); +#define md_elf_section_change_hook() mips_enable_auto_align() + +#endif /* TC_MIPS */ diff --git a/contrib/binutils/gas/doc/c-mips.texi b/contrib/binutils/gas/doc/c-mips.texi new file mode 100644 index 0000000000000..c3e12a0112558 --- /dev/null +++ b/contrib/binutils/gas/doc/c-mips.texi @@ -0,0 +1,229 @@ +@c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC +@page +@node MIPS-Dependent +@chapter MIPS Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter MIPS Dependent Features +@end ifclear + +@cindex MIPS processor +@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several +different @sc{mips} processors, and MIPS ISA levels I through IV. For +information about the @sc{mips} instruction set, see @cite{MIPS RISC +Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview +of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language +Programming'' in the same work. + +@menu +* MIPS Opts:: Assembler options +* MIPS Object:: ECOFF object code +* MIPS Stabs:: Directives for debugging information +* MIPS ISA:: Directives to override the ISA level +* MIPS autoextend:: Directives for extending MIPS 16 bit instructions +* MIPS insn:: Directive to mark data as an instruction +* MIPS option stack:: Directives to save and restore options +@end menu + +@node MIPS Opts +@section Assembler options + +The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these +special options: + +@table @code +@cindex @code{-G} option (MIPS) +@item -G @var{num} +This option sets the largest size of an object that can be referenced +implicitly with the @code{gp} register. It is only accepted for targets +that use @sc{ecoff} format. The default value is 8. + +@cindex @code{-EB} option (MIPS) +@cindex @code{-EL} option (MIPS) +@cindex MIPS big-endian output +@cindex MIPS little-endian output +@cindex big-endian output, MIPS +@cindex little-endian output, MIPS +@item -EB +@itemx -EL +Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or +little-endian output at run time (unlike the other @sc{gnu} development +tools, which must be configured for one or the other). Use @samp{-EB} +to select big-endian output, and @samp{-EL} for little-endian. + +@cindex MIPS architecture options +@item -mips1 +@itemx -mips2 +@itemx -mips3 +@itemx -mips4 +Generate code for a particular MIPS Instruction Set Architecture level. +@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, +@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the +@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and +@sc{r10000} processors. You can also switch instruction sets during the +assembly; see @ref{MIPS ISA,, Directives to override the ISA level}. + +@item -mips16 +@itemx -no-mips16 +Generate code for the MIPS 16 processor. This is equivalent to putting +@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} +turns off this option. + +@item -m4650 +@itemx -no-m4650 +Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept +the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} +instructions around accesses to the @samp{HI} and @samp{LO} registers. +@samp{-no-m4650} turns off this option. + +@item -m4010 +@itemx -no-m4010 +Generate code for the LSI @sc{r4010} chip. This tells the assembler to +accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, +etc.), and to not schedule @samp{nop} instructions around accesses to +the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this +option. + +@item -mcpu=@var{CPU} +Generate code for a particular MIPS cpu. This has little effect on the +assembler, but it is passed by @code{@value{GCC}}. + +@cindex @code{-nocpp} ignored (MIPS) +@item -nocpp +This option is ignored. It is accepted for command-line compatibility with +other assemblers, which use it to turn off C style preprocessing. With +@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the +@sc{gnu} assembler itself never runs the C preprocessor. + +@item --trap +@itemx --no-break +@c FIXME! (1) reflect these options (next item too) in option summaries; +@c (2) stop teasing, say _which_ instructions expanded _how_. +@code{@value{AS}} automatically macro expands certain division and +multiplication instructions to check for overflow and division by zero. This +option causes @code{@value{AS}} to generate code to take a trap exception +rather than a break exception when an error is detected. The trap instructions +are only supported at Instruction Set Architecture level 2 and higher. + +@item --break +@itemx --no-trap +Generate code to take a break exception rather than a trap exception when an +error is detected. This is the default. +@end table + +@node MIPS Object +@section MIPS ECOFF object code + +@cindex ECOFF sections +@cindex MIPS ECOFF sections +Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections +besides the usual @code{.text}, @code{.data} and @code{.bss}. The +additional sections are @code{.rdata}, used for read-only data, +@code{.sdata}, used for small data, and @code{.sbss}, used for small +common objects. + +@cindex small objects, MIPS ECOFF +@cindex @code{gp} register, MIPS +When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) +register to form the address of a ``small object''. Any object in the +@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. +For external objects, or for objects in the @code{.bss} section, you can use +the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via +@code{$gp}; the default value is 8, meaning that a reference to any object +eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to +@code{@value{AS}} prevents it from using the @code{$gp} register on the basis +of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} +or @code{sbss} in any case). The size of an object in the @code{.bss} section +is set by the @code{.comm} or @code{.lcomm} directive that defines it. The +size of an external object may be set with the @code{.extern} directive. For +example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes +in length, whie leaving @code{sym} otherwise undefined. + +Using small @sc{ecoff} objects requires linker support, and assumes that the +@code{$gp} register is correctly initialized (normally done automatically by +the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the +@code{$gp} register. + +@node MIPS Stabs +@section Directives for debugging information + +@cindex MIPS debugging directives +@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for +generating debugging information which are not support by traditional @sc{mips} +assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, +@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, +@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information +generated by the three @code{.stab} directives can only be read by @sc{gdb}, +not by traditional @sc{mips} debuggers (this enhancement is required to fully +support C++ debugging). These directives are primarily used by compilers, not +assembly language programmers! + +@node MIPS ISA +@section Directives to override the ISA level + +@cindex MIPS ISA override +@kindex @code{.set mips@var{n}} +@sc{gnu} @code{@value{AS}} supports an additional directive to change +the @sc{mips} Instruction Set Architecture level on the fly: @code{.set +mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1 +to 4 makes the assembler accept instructions for the corresponding +@sc{isa} level, from that point on in the assembly. @code{.set +mips@var{n}} affects not only which instructions are permitted, but also +how certain macros are expanded. @code{.set mips0} restores the +@sc{isa} level to its original level: either the level you selected with +command line options, or the default for your configuration. You can +use this feature to permit specific @sc{r4000} instructions while +assembling in 32 bit mode. Use this directive with care! + +The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, +in which it will assemble instructions for the MIPS 16 processor. Use +@samp{.set nomips16} to return to normal 32 bit mode. + +Traditional @sc{mips} assemblers do not support this directive. + +@node MIPS autoextend +@section Directives for extending MIPS 16 bit instructions + +@kindex @code{.set autoextend} +@kindex @code{.set noautoextend} +By default, MIPS 16 instructions are automatically extended to 32 bits +when necessary. The directive @samp{.set noautoextend} will turn this +off. When @samp{.set noautoextend} is in effect, any 32 bit instruction +must be explicitly extended with the @samp{.e} modifier (e.g., +@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used +to once again automatically extend instructions when necessary. + +This directive is only meaningful when in MIPS 16 mode. Traditional +@sc{mips} assemblers do not support this directive. + +@node MIPS insn +@section Directive to mark data as an instruction + +@kindex @code{.insn} +The @code{.insn} directive tells @code{@value{AS}} that the following +data is actually instructions. This makes a difference in MIPS 16 mode: +when loading the address of a label which precedes instructions, +@code{@value{AS}} automatically adds 1 to the value, so that jumping to +the loaded address will do the right thing. + +@node MIPS option stack +@section Directives to save and restore options + +@cindex MIPS option stack +@kindex @code{.set push} +@kindex @code{.set pop} +The directives @code{.set push} and @code{.set pop} may be used to save +and restore the current settings for all the options which are +controlled by @code{.set}. The @code{.set push} directive saves the +current settings on a stack. The @code{.set pop} directive pops the +stack and restores the settings. + +These directives can be useful inside an macro which must change an +option such as the ISA level or instruction reordering but does not want +to change the state of the code which invoked the macro. + +Traditional @sc{mips} assemblers do not support these directives. diff --git a/contrib/binutils/include/coff/mips.h b/contrib/binutils/include/coff/mips.h new file mode 100644 index 0000000000000..d4665b1f3964b --- /dev/null +++ b/contrib/binutils/include/coff/mips.h @@ -0,0 +1,369 @@ +/* ECOFF support on MIPS machines. + coff/ecoff.h must be included before this file. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + unsigned char f_magic[2]; /* magic number */ + unsigned char f_nscns[2]; /* number of sections */ + unsigned char f_timdat[4]; /* time & date stamp */ + unsigned char f_symptr[4]; /* file pointer to symtab */ + unsigned char f_nsyms[4]; /* number of symtab entries */ + unsigned char f_opthdr[2]; /* sizeof(optional hdr) */ + unsigned char f_flags[2]; /* flags */ +}; + +/* Magic numbers are defined in coff/ecoff.h. */ +#define MIPS_ECOFF_BADMAG(x) (((x).f_magic!=MIPS_MAGIC_1) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE) &&\ + ((x).f_magic!=MIPS_MAGIC_BIG) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE2) && \ + ((x).f_magic!=MIPS_MAGIC_BIG2) && \ + ((x).f_magic!=MIPS_MAGIC_LITTLE3) && \ + ((x).f_magic!=MIPS_MAGIC_BIG3)) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct external_aouthdr +{ + unsigned char magic[2]; /* type of file */ + unsigned char vstamp[2]; /* version stamp */ + unsigned char tsize[4]; /* text size in bytes, padded to FW bdry*/ + unsigned char dsize[4]; /* initialized data " " */ + unsigned char bsize[4]; /* uninitialized data " " */ + unsigned char entry[4]; /* entry pt. */ + unsigned char text_start[4]; /* base of text used for this file */ + unsigned char data_start[4]; /* base of data used for this file */ + unsigned char bss_start[4]; /* base of bss used for this file */ + unsigned char gprmask[4]; /* ?? */ + unsigned char cprmask[4][4]; /* ?? */ + unsigned char gp_value[4]; /* value for gp register */ +} AOUTHDR; + +/* compute size of a header */ + +#define AOUTSZ 56 +#define AOUTHDRSZ 56 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr { + unsigned char s_name[8]; /* section name */ + unsigned char s_paddr[4]; /* physical address, aliased s_nlib */ + unsigned char s_vaddr[4]; /* virtual address */ + unsigned char s_size[4]; /* section size */ + unsigned char s_scnptr[4]; /* file ptr to raw data for section */ + unsigned char s_relptr[4]; /* file ptr to relocation */ + unsigned char s_lnnoptr[4]; /* file ptr to line numbers */ + unsigned char s_nreloc[2]; /* number of relocation entries */ + unsigned char s_nlnno[2]; /* number of line number entries*/ + unsigned char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc { + unsigned char r_vaddr[4]; + unsigned char r_bits[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 8 + +/* MIPS ECOFF uses a packed 8 byte format for relocs. These constants + are used to unpack the r_bits field. */ + +#define RELOC_BITS0_SYMNDX_SH_LEFT_BIG 16 +#define RELOC_BITS0_SYMNDX_SH_LEFT_LITTLE 0 + +#define RELOC_BITS1_SYMNDX_SH_LEFT_BIG 8 +#define RELOC_BITS1_SYMNDX_SH_LEFT_LITTLE 8 + +#define RELOC_BITS2_SYMNDX_SH_LEFT_BIG 0 +#define RELOC_BITS2_SYMNDX_SH_LEFT_LITTLE 16 + +/* Originally, ECOFF used four bits for the reloc type and had three + reserved bits. Irix 4 added another bit for the reloc type, which + was easy because it was big endian and one of the spare bits became + the new most significant bit. To make this also work for little + endian ECOFF, we need to wrap one of the reserved bits around to + become the most significant bit of the reloc type. */ +#define RELOC_BITS3_TYPE_BIG 0x3E +#define RELOC_BITS3_TYPE_SH_BIG 1 +#define RELOC_BITS3_TYPE_LITTLE 0x78 +#define RELOC_BITS3_TYPE_SH_LITTLE 3 +#define RELOC_BITS3_TYPEHI_LITTLE 0x04 +#define RELOC_BITS3_TYPEHI_SH_LITTLE 2 + +#define RELOC_BITS3_EXTERN_BIG 0x01 +#define RELOC_BITS3_EXTERN_LITTLE 0x80 + +/* The r_type field in a reloc is one of the following values. I + don't know if any other values can appear. These seem to be all + that occur in the Ultrix 4.2 libraries. */ +#define MIPS_R_IGNORE 0 +#define MIPS_R_REFHALF 1 +#define MIPS_R_REFWORD 2 +#define MIPS_R_JMPADDR 3 +#define MIPS_R_REFHI 4 +#define MIPS_R_REFLO 5 +#define MIPS_R_GPREL 6 +#define MIPS_R_LITERAL 7 + +/* These reloc types are a Cygnus extension used when generating + position independent code for embedded systems. The numbers are + taken from Irix 4, but at least for internal relocs Irix 5 does not + give them the same meaning. For an internal reloc the symbol index + of RELHI and RELLO is modified as described below for + MIPS_R_SWITCH. */ +#define MIPS_R_PCREL16 12 +#define MIPS_R_RELHI 13 +#define MIPS_R_RELLO 14 + +/* This reloc type is a Cygnus extension used when generating position + independent code for embedded systems. It is used for an entry in + a switch table, which looks like this: + .word $L3-$LS12 + The object file will contain the correct difference, and does not + require adjustment. However, when the linker is relaxing PC + relative calls, it is possible for $L3 to move farther away. This + reloc always appears in the .text section, and is always against + the .text section. However, the symbol index is not + RELOC_SECTION_TEXT. It is, instead, the distance between this + switch table entry and $LS12. Thus, the original value of $L12 is + vaddr - symndx + and the original value of $L3 is + vaddr - symndx + addend + where addend is the value in the object file. Knowing this, the + linker can know whether the addend in the object file must be + adjusted. */ +#define MIPS_R_SWITCH 22 + +/********************** STABS **********************/ + +#define MIPS_IS_STAB ECOFF_IS_STAB +#define MIPS_MARK_STAB ECOFF_MARK_STAB +#define MIPS_UNMARK_STAB ECOFF_UNMARK_STAB + +/********************** SYMBOLIC INFORMATION **********************/ + +/* Written by John Gilmore. */ + +/* ECOFF uses COFF-like section structures, but its own symbol format. + This file defines the symbol format in fields whose size and alignment + will not vary on different host systems. */ + +/* File header as a set of bytes */ + +struct hdr_ext { + unsigned char h_magic[2]; + unsigned char h_vstamp[2]; + unsigned char h_ilineMax[4]; + unsigned char h_cbLine[4]; + unsigned char h_cbLineOffset[4]; + unsigned char h_idnMax[4]; + unsigned char h_cbDnOffset[4]; + unsigned char h_ipdMax[4]; + unsigned char h_cbPdOffset[4]; + unsigned char h_isymMax[4]; + unsigned char h_cbSymOffset[4]; + unsigned char h_ioptMax[4]; + unsigned char h_cbOptOffset[4]; + unsigned char h_iauxMax[4]; + unsigned char h_cbAuxOffset[4]; + unsigned char h_issMax[4]; + unsigned char h_cbSsOffset[4]; + unsigned char h_issExtMax[4]; + unsigned char h_cbSsExtOffset[4]; + unsigned char h_ifdMax[4]; + unsigned char h_cbFdOffset[4]; + unsigned char h_crfd[4]; + unsigned char h_cbRfdOffset[4]; + unsigned char h_iextMax[4]; + unsigned char h_cbExtOffset[4]; +}; + +/* File descriptor external record */ + +struct fdr_ext { + unsigned char f_adr[4]; + unsigned char f_rss[4]; + unsigned char f_issBase[4]; + unsigned char f_cbSs[4]; + unsigned char f_isymBase[4]; + unsigned char f_csym[4]; + unsigned char f_ilineBase[4]; + unsigned char f_cline[4]; + unsigned char f_ioptBase[4]; + unsigned char f_copt[4]; + unsigned char f_ipdFirst[2]; + unsigned char f_cpd[2]; + unsigned char f_iauxBase[4]; + unsigned char f_caux[4]; + unsigned char f_rfdBase[4]; + unsigned char f_crfd[4]; + unsigned char f_bits1[1]; + unsigned char f_bits2[3]; + unsigned char f_cbLineOffset[4]; + unsigned char f_cbLine[4]; +}; + +#define FDR_BITS1_LANG_BIG 0xF8 +#define FDR_BITS1_LANG_SH_BIG 3 +#define FDR_BITS1_LANG_LITTLE 0x1F +#define FDR_BITS1_LANG_SH_LITTLE 0 + +#define FDR_BITS1_FMERGE_BIG 0x04 +#define FDR_BITS1_FMERGE_LITTLE 0x20 + +#define FDR_BITS1_FREADIN_BIG 0x02 +#define FDR_BITS1_FREADIN_LITTLE 0x40 + +#define FDR_BITS1_FBIGENDIAN_BIG 0x01 +#define FDR_BITS1_FBIGENDIAN_LITTLE 0x80 + +#define FDR_BITS2_GLEVEL_BIG 0xC0 +#define FDR_BITS2_GLEVEL_SH_BIG 6 +#define FDR_BITS2_GLEVEL_LITTLE 0x03 +#define FDR_BITS2_GLEVEL_SH_LITTLE 0 + +/* We ignore the `reserved' field in bits2. */ + +/* Procedure descriptor external record */ + +struct pdr_ext { + unsigned char p_adr[4]; + unsigned char p_isym[4]; + unsigned char p_iline[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_iopt[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; + unsigned char p_lnLow[4]; + unsigned char p_lnHigh[4]; + unsigned char p_cbLineOffset[4]; +}; + +/* Runtime procedure table */ + +struct rpdr_ext { + unsigned char p_adr[4]; + unsigned char p_regmask[4]; + unsigned char p_regoffset[4]; + unsigned char p_fregmask[4]; + unsigned char p_fregoffset[4]; + unsigned char p_frameoffset[4]; + unsigned char p_framereg[2]; + unsigned char p_pcreg[2]; + unsigned char p_irpss[4]; + unsigned char p_reserved[4]; + unsigned char p_exception_info[4]; +}; + +/* Line numbers */ + +struct line_ext { + unsigned char l_line[4]; +}; + +/* Symbol external record */ + +struct sym_ext { + unsigned char s_iss[4]; + unsigned char s_value[4]; + unsigned char s_bits1[1]; + unsigned char s_bits2[1]; + unsigned char s_bits3[1]; + unsigned char s_bits4[1]; +}; + +#define SYM_BITS1_ST_BIG 0xFC +#define SYM_BITS1_ST_SH_BIG 2 +#define SYM_BITS1_ST_LITTLE 0x3F +#define SYM_BITS1_ST_SH_LITTLE 0 + +#define SYM_BITS1_SC_BIG 0x03 +#define SYM_BITS1_SC_SH_LEFT_BIG 3 +#define SYM_BITS1_SC_LITTLE 0xC0 +#define SYM_BITS1_SC_SH_LITTLE 6 + +#define SYM_BITS2_SC_BIG 0xE0 +#define SYM_BITS2_SC_SH_BIG 5 +#define SYM_BITS2_SC_LITTLE 0x07 +#define SYM_BITS2_SC_SH_LEFT_LITTLE 2 + +#define SYM_BITS2_RESERVED_BIG 0x10 +#define SYM_BITS2_RESERVED_LITTLE 0x08 + +#define SYM_BITS2_INDEX_BIG 0x0F +#define SYM_BITS2_INDEX_SH_LEFT_BIG 16 +#define SYM_BITS2_INDEX_LITTLE 0xF0 +#define SYM_BITS2_INDEX_SH_LITTLE 4 + +#define SYM_BITS3_INDEX_SH_LEFT_BIG 8 +#define SYM_BITS3_INDEX_SH_LEFT_LITTLE 4 + +#define SYM_BITS4_INDEX_SH_LEFT_BIG 0 +#define SYM_BITS4_INDEX_SH_LEFT_LITTLE 12 + +/* External symbol external record */ + +struct ext_ext { + unsigned char es_bits1[1]; + unsigned char es_bits2[1]; + unsigned char es_ifd[2]; + struct sym_ext es_asym; +}; + +#define EXT_BITS1_JMPTBL_BIG 0x80 +#define EXT_BITS1_JMPTBL_LITTLE 0x01 + +#define EXT_BITS1_COBOL_MAIN_BIG 0x40 +#define EXT_BITS1_COBOL_MAIN_LITTLE 0x02 + +#define EXT_BITS1_WEAKEXT_BIG 0x20 +#define EXT_BITS1_WEAKEXT_LITTLE 0x04 + +/* Dense numbers external record */ + +struct dnr_ext { + unsigned char d_rfd[4]; + unsigned char d_index[4]; +}; + +/* Relative file descriptor */ + +struct rfd_ext { + unsigned char rfd[4]; +}; + +/* Optimizer symbol external record */ + +struct opt_ext { + unsigned char o_bits1[1]; + unsigned char o_bits2[1]; + unsigned char o_bits3[1]; + unsigned char o_bits4[1]; + struct rndx_ext o_rndx; + unsigned char o_offset[4]; +}; + +#define OPT_BITS2_VALUE_SH_LEFT_BIG 16 +#define OPT_BITS2_VALUE_SH_LEFT_LITTLE 0 + +#define OPT_BITS3_VALUE_SH_LEFT_BIG 8 +#define OPT_BITS3_VALUE_SH_LEFT_LITTLE 8 + +#define OPT_BITS4_VALUE_SH_LEFT_BIG 0 +#define OPT_BITS4_VALUE_SH_LEFT_LITTLE 16 diff --git a/contrib/binutils/install.sh b/contrib/binutils/install.sh new file mode 100755 index 0000000000000..4b883b386de25 --- /dev/null +++ b/contrib/binutils/install.sh @@ -0,0 +1,247 @@ +#!/bin/sh +# +# install - install a program, script, or datafile +# This comes from X11R5 (mit/util/scripts/install.sh). +# +# Copyright 1991 by the Massachusetts Institute of Technology +# +# Permission to use, copy, modify, distribute, and sell this software and its +# documentation for any purpose is hereby granted without fee, provided that +# the above copyright notice appear in all copies and that both that +# copyright notice and this permission notice appear in supporting +# documentation, and that the name of M.I.T. not be used in advertising or +# publicity pertaining to distribution of the software without specific, +# written prior permission. M.I.T. makes no representations about the +# suitability of this software for any purpose. It is provided "as is" +# without express or implied warranty. +# +# This script is compatible with the BSD install script, but was written +# from scratch. +# + + +# set DOITPROG to echo to test this script + +# Don't use :- since 4.3BSD and earlier shells don't like it. +doit="${DOITPROG-}" + + +# put in absolute paths if you don't have them in your path; or use env. vars. + +mvprog="${MVPROG-mv}" +cpprog="${CPPROG-cp}" +chmodprog="${CHMODPROG-chmod}" +chownprog="${CHOWNPROG-chown}" +chgrpprog="${CHGRPPROG-chgrp}" +stripprog="${STRIPPROG-strip}" +rmprog="${RMPROG-rm}" +mkdirprog="${MKDIRPROG-mkdir}" + +transformbasename="" +transform_arg="" +instcmd="$mvprog" +chmodcmd="$chmodprog 0755" +chowncmd="" +chgrpcmd="" +stripcmd="" +rmcmd="$rmprog -f" +mvcmd="$mvprog" +src="" +dst="" +dir_arg="" + +while [ x"$1" != x ]; do + case $1 in + -c) instcmd="$cpprog" + shift + continue;; + + -d) dir_arg=true + shift + continue;; + + -m) chmodcmd="$chmodprog $2" + shift + shift + continue;; + + -o) chowncmd="$chownprog $2" + shift + shift + continue;; + + -g) chgrpcmd="$chgrpprog $2" + shift + shift + continue;; + + -s) stripcmd="$stripprog" + shift + continue;; + + -t=*) transformarg=`echo $1 | sed 's/-t=//'` + shift + continue;; + + -b=*) transformbasename=`echo $1 | sed 's/-b=//'` + shift + continue;; + + *) if [ x"$src" = x ] + then + src=$1 + else + # this colon is to work around a 386BSD /bin/sh bug + : + dst=$1 + fi + shift + continue;; + esac +done + +if [ x"$src" = x ] +then + echo "install: no input file specified" + exit 1 +else + true +fi + +if [ x"$dir_arg" != x ]; then + dst=$src + src="" + + if [ -d $dst ]; then + instcmd=: + chmodcmd="" + else + instcmd=mkdir + fi +else + +# Waiting for this to be detected by the "$instcmd $src $dsttmp" command +# might cause directories to be created, which would be especially bad +# if $src (and thus $dsttmp) contains '*'. + + if [ -f $src -o -d $src ] + then + true + else + echo "install: $src does not exist" + exit 1 + fi + + if [ x"$dst" = x ] + then + echo "install: no destination specified" + exit 1 + else + true + fi + +# If destination is a directory, append the input filename; if your system +# does not like double slashes in filenames, you may need to add some logic + + if [ -d $dst ] + then + dst="$dst"/`basename $src` + else + true + fi +fi + +## this sed command emulates the dirname command +dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'` + +# Make sure that the destination directory exists. +# this part is taken from Noah Friedman's mkinstalldirs script + +# Skip lots of stat calls in the usual case. +if [ ! -d "$dstdir" ]; then +defaultIFS=' +' +IFS="${IFS-${defaultIFS}}" + +oIFS="${IFS}" +# Some sh's can't handle IFS=/ for some reason. +IFS='%' +set - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'` +IFS="${oIFS}" + +pathcomp='' + +while [ $# -ne 0 ] ; do + pathcomp="${pathcomp}${1}" + shift + + if [ ! -d "${pathcomp}" ] ; + then + $mkdirprog "${pathcomp}" + else + true + fi + + pathcomp="${pathcomp}/" +done +fi + +if [ x"$dir_arg" != x ] +then + $doit $instcmd $dst && + + if [ x"$chowncmd" != x ]; then $doit $chowncmd $dst; else true ; fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dst; else true ; fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd $dst; else true ; fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dst; else true ; fi +else + +# If we're going to rename the final executable, determine the name now. + + if [ x"$transformarg" = x ] + then + dstfile=`basename $dst` + else + dstfile=`basename $dst $transformbasename | + sed $transformarg`$transformbasename + fi + +# don't allow the sed command to completely eliminate the filename + + if [ x"$dstfile" = x ] + then + dstfile=`basename $dst` + else + true + fi + +# Make a temp file name in the proper directory. + + dsttmp=$dstdir/#inst.$$# + +# Move or copy the file name to the temp name + + $doit $instcmd $src $dsttmp && + + trap "rm -f ${dsttmp}" 0 && + +# and set any options; do chmod last to preserve setuid bits + +# If any of these fail, we abort the whole thing. If we want to +# ignore errors from any of these, just make sure not to ignore +# errors from the above "$doit $instcmd $src $dsttmp" command. + + if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi && + +# Now rename the file to the real destination. + + $doit $rmcmd -f $dstdir/$dstfile && + $doit $mvcmd $dsttmp $dstdir/$dstfile + +fi && + + +exit 0 diff --git a/contrib/binutils/ld/emulparams/mipsbig.sh b/contrib/binutils/ld/emulparams/mipsbig.sh new file mode 100644 index 0000000000000..9fe29538f452c --- /dev/null +++ b/contrib/binutils/ld/emulparams/mipsbig.sh @@ -0,0 +1,6 @@ +SCRIPT_NAME=mips +OUTPUT_FORMAT="ecoff-bigmips" +BIG_OUTPUT_FORMAT="ecoff-bigmips" +LITTLE_OUTPUT_FORMAT="ecoff-littlemips" +TARGET_PAGE_SIZE=0x1000000 +ARCH=mips diff --git a/contrib/binutils/ld/emulparams/mipsbsd.sh b/contrib/binutils/ld/emulparams/mipsbsd.sh new file mode 100644 index 0000000000000..e8fb35beca68d --- /dev/null +++ b/contrib/binutils/ld/emulparams/mipsbsd.sh @@ -0,0 +1,7 @@ +SCRIPT_NAME=mipsbsd +OUTPUT_FORMAT="a.out-mips-little" +BIG_OUTPUT_FORMAT="a.out-mips-big" +LITTLE_OUTPUT_FORMAT="a.out-mips-little" +TEXT_START_ADDR=0x1020 +TARGET_PAGE_SIZE=4096 +ARCH=mips diff --git a/contrib/binutils/ld/emulparams/mipsidt.sh b/contrib/binutils/ld/emulparams/mipsidt.sh new file mode 100644 index 0000000000000..63176f5fdeae1 --- /dev/null +++ b/contrib/binutils/ld/emulparams/mipsidt.sh @@ -0,0 +1,11 @@ +SCRIPT_NAME=mips +OUTPUT_FORMAT="ecoff-bigmips" +BIG_OUTPUT_FORMAT="ecoff-bigmips" +LITTLE_OUTPUT_FORMAT="ecoff-littlemips" +TARGET_PAGE_SIZE=0x1000000 +ARCH=mips +ENTRY=start +TEXT_START_ADDR=0xa0012000 +DATA_ADDR=. +TEMPLATE_NAME=mipsecoff +EMBEDDED=yes diff --git a/contrib/binutils/ld/emulparams/mipsidtl.sh b/contrib/binutils/ld/emulparams/mipsidtl.sh new file mode 100644 index 0000000000000..02279ded6359d --- /dev/null +++ b/contrib/binutils/ld/emulparams/mipsidtl.sh @@ -0,0 +1,11 @@ +SCRIPT_NAME=mips +OUTPUT_FORMAT="ecoff-littlemips" +BIG_OUTPUT_FORMAT="ecoff-bigmips" +LITTLE_OUTPUT_FORMAT="ecoff-littlemips" +TARGET_PAGE_SIZE=0x1000000 +ARCH=mips +ENTRY=start +TEXT_START_ADDR=0xa0012000 +DATA_ADDR=. +TEMPLATE_NAME=mipsecoff +EMBEDDED=yes diff --git a/contrib/binutils/ld/emulparams/mipslit.sh b/contrib/binutils/ld/emulparams/mipslit.sh new file mode 100644 index 0000000000000..acb234464be4a --- /dev/null +++ b/contrib/binutils/ld/emulparams/mipslit.sh @@ -0,0 +1,6 @@ +SCRIPT_NAME=mips +OUTPUT_FORMAT="ecoff-littlemips" +BIG_OUTPUT_FORMAT="ecoff-bigmips" +LITTLE_OUTPUT_FORMAT="ecoff-littlemips" +TARGET_PAGE_SIZE=0x1000000 +ARCH=mips diff --git a/contrib/binutils/ld/emultempl/mipsecoff.em b/contrib/binutils/ld/emultempl/mipsecoff.em new file mode 100644 index 0000000000000..d1200c46d7041 --- /dev/null +++ b/contrib/binutils/ld/emultempl/mipsecoff.em @@ -0,0 +1,229 @@ +# This shell script emits a C file. -*- C -*- +# It does some substitutions. +cat >e${EMULATION_NAME}.c < based on generic.em. + +This file is part of GLD, the Gnu Linker. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define TARGET_IS_${EMULATION_NAME} + +#include "bfd.h" +#include "sysdep.h" +#include "bfdlink.h" + +#include "ld.h" +#include "ldmain.h" +#include "ldemul.h" +#include "ldfile.h" +#include "ldmisc.h" + +static void gld${EMULATION_NAME}_before_parse PARAMS ((void)); +static void gld${EMULATION_NAME}_after_open PARAMS ((void)); +static void check_sections PARAMS ((bfd *, asection *, PTR)); +static void gld${EMULATION_NAME}_after_allocation PARAMS ((void)); +static char *gld${EMULATION_NAME}_get_script PARAMS ((int *isfile)); + +static void +gld${EMULATION_NAME}_before_parse() +{ +#ifndef TARGET_ /* I.e., if not generic. */ + ldfile_output_architecture = bfd_arch_${ARCH}; +#endif /* not TARGET_ */ +} + +/* This function is run after all the input files have been opened. + We create a .rel.sdata section for each input file with a non zero + .sdata section. The BFD backend will fill in these sections with + magic numbers which can be used to relocate the data section at run + time. This will only do the right thing if all the input files + have been compiled using -membedded-pic. */ + +static void +gld${EMULATION_NAME}_after_open () +{ + bfd *abfd; + + if (! command_line.embedded_relocs + || link_info.relocateable) + return; + + for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next) + { + asection *datasec; + + datasec = bfd_get_section_by_name (abfd, ".sdata"); + + /* Note that we assume that the reloc_count field has already + been set up. We could call bfd_get_reloc_upper_bound, but + that returns the size of a memory buffer rather than a reloc + count. We do not want to call bfd_canonicalize_reloc, + because although it would always work it would force us to + read in the relocs into BFD canonical form, which would waste + a significant amount of time and memory. */ + if (datasec != NULL && datasec->reloc_count > 0) + { + asection *relsec; + + relsec = bfd_make_section (abfd, ".rel.sdata"); + if (relsec == NULL + || ! bfd_set_section_flags (abfd, relsec, + (SEC_ALLOC + | SEC_LOAD + | SEC_HAS_CONTENTS + | SEC_IN_MEMORY)) + || ! bfd_set_section_alignment (abfd, relsec, 2) + || ! bfd_set_section_size (abfd, relsec, + datasec->reloc_count * 4)) + einfo ("%F%B: can not create .rel.sdata section: %E\n"); + } + + /* Double check that all other data sections are empty, as is + required for embedded PIC code. */ + bfd_map_over_sections (abfd, check_sections, (PTR) datasec); + } +} + +/* Check that of the data sections, only the .sdata section has + relocs. This is called via bfd_map_over_sections. */ + +static void +check_sections (abfd, sec, sdatasec) + bfd *abfd; + asection *sec; + PTR sdatasec; +{ + if ((bfd_get_section_flags (abfd, sec) & SEC_CODE) == 0 + && sec != (asection *) sdatasec + && sec->reloc_count != 0) + einfo ("%P%X: section %s has relocs; can not use --embedded-relocs\n", + abfd, bfd_get_section_name (abfd, sec)); +} + +/* This function is called after the section sizes and offsets have + been set. If we are generating embedded relocs, it calls a special + BFD backend routine to do the work. */ + +static void +gld${EMULATION_NAME}_after_allocation () +{ + bfd *abfd; + + if (! command_line.embedded_relocs + || link_info.relocateable) + return; + + for (abfd = link_info.input_bfds; abfd != NULL; abfd = abfd->link_next) + { + asection *datasec, *relsec; + char *errmsg; + + datasec = bfd_get_section_by_name (abfd, ".sdata"); + + if (datasec == NULL || datasec->reloc_count == 0) + continue; + + relsec = bfd_get_section_by_name (abfd, ".rel.sdata"); + ASSERT (relsec != NULL); + + if (! bfd_mips_ecoff_create_embedded_relocs (abfd, &link_info, + datasec, relsec, + &errmsg)) + { + if (errmsg == NULL) + einfo ("%B%X: can not create runtime reloc information: %E\n", + abfd); + else + einfo ("%X%B: can not create runtime reloc information: %s\n", + abfd, errmsg); + } + } +} + +static char * +gld${EMULATION_NAME}_get_script(isfile) + int *isfile; +EOF + +if test -n "$COMPILE_IN" +then +# Scripts compiled in. + +# sed commands to quote an ld script as a C string. +sc="-f ${srcdir}/emultempl/stringify.sed" + +cat >>e${EMULATION_NAME}.c <> e${EMULATION_NAME}.c +echo ' ; else if (link_info.relocateable == true) return' >> e${EMULATION_NAME}.c +sed $sc ldscripts/${EMULATION_NAME}.xr >> e${EMULATION_NAME}.c +echo ' ; else if (!config.text_read_only) return' >> e${EMULATION_NAME}.c +sed $sc ldscripts/${EMULATION_NAME}.xbn >> e${EMULATION_NAME}.c +echo ' ; else if (!config.magic_demand_paged) return' >> e${EMULATION_NAME}.c +sed $sc ldscripts/${EMULATION_NAME}.xn >> e${EMULATION_NAME}.c +echo ' ; else return' >> e${EMULATION_NAME}.c +sed $sc ldscripts/${EMULATION_NAME}.x >> e${EMULATION_NAME}.c +echo '; }' >> e${EMULATION_NAME}.c + +else +# Scripts read from the filesystem. + +cat >>e${EMULATION_NAME}.c <>e${EMULATION_NAME}.c <. +# These variables may be overridden by the emulation file. The +# defaults are appropriate for a DECstation running Ultrix. +test -z "$ENTRY" && ENTRY=__start + +if [ -z "$EMBEDDED" ]; then + test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x400000 + SIZEOF_HEADERS" +else + test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x400000" +fi +if test "x$LD_FLAG" = "xn" -o "x$LD_FLAG" = "xN"; then + DATA_ADDR=. +else + test -z "$DATA_ADDR" && DATA_ADDR=0x10000000 +fi +cat < +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/mips.h" + +/* FIXME: These are needed to figure out if this is a mips16 symbol or + not. It would be better to think of a cleaner way to do this. */ +#include "elf-bfd.h" +#include "elf/mips.h" + +static int print_insn_mips16 PARAMS ((bfd_vma, struct disassemble_info *)); +static void print_mips16_insn_arg + PARAMS ((int, const struct mips_opcode *, int, boolean, int, bfd_vma, + struct disassemble_info *)); + +/* Mips instructions are never longer than this many bytes. */ +#define MAXLEN 4 + +static void print_insn_arg PARAMS ((const char *, unsigned long, bfd_vma, + struct disassemble_info *)); +static int _print_insn_mips PARAMS ((bfd_vma, unsigned long int, + struct disassemble_info *)); + + +/* FIXME: This should be shared with gdb somehow. */ +#define REGISTER_NAMES \ + { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \ + "sr", "lo", "hi", "bad", "cause","pc", \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\ + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\ + "fsr", "fir", "fp", "inx", "rand", "tlblo","ctxt", "tlbhi",\ + "epc", "prid"\ + } + +static CONST char * CONST reg_names[] = REGISTER_NAMES; + +/* The mips16 register names. */ +static const char * const mips16_reg_names[] = +{ + "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" +}; + +/* subroutine */ +static void +print_insn_arg (d, l, pc, info) + const char *d; + register unsigned long int l; + bfd_vma pc; + struct disassemble_info *info; +{ + int delta; + + switch (*d) + { + case ',': + case '(': + case ')': + (*info->fprintf_func) (info->stream, "%c", *d); + break; + + case 's': + case 'b': + case 'r': + case 'v': + (*info->fprintf_func) (info->stream, "$%s", + reg_names[(l >> OP_SH_RS) & OP_MASK_RS]); + break; + + case 't': + case 'w': + (*info->fprintf_func) (info->stream, "$%s", + reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); + break; + + case 'i': + case 'u': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); + break; + + case 'j': /* same as i, but sign-extended */ + case 'o': + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + (*info->fprintf_func) (info->stream, "%d", + delta); + break; + + case 'h': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_PREFX) + & OP_MASK_PREFX)); + break; + + case 'k': + (*info->fprintf_func) (info->stream, "0x%x", + (unsigned int) ((l >> OP_SH_CACHE) + & OP_MASK_CACHE)); + break; + + case 'a': + (*info->print_address_func) + (((pc & 0xF0000000) | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)), + info); + break; + + case 'p': + /* sign extend the displacement */ + delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; + if (delta & 0x8000) + delta |= ~0xffff; + (*info->print_address_func) + ((delta << 2) + pc + 4, + info); + break; + + case 'd': + (*info->fprintf_func) (info->stream, "$%s", + reg_names[(l >> OP_SH_RD) & OP_MASK_RD]); + break; + + case 'z': + (*info->fprintf_func) (info->stream, "$%s", reg_names[0]); + break; + + case '<': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); + break; + + case 'c': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_CODE) & OP_MASK_CODE); + break; + + case 'C': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_COPZ) & OP_MASK_COPZ); + break; + + case 'B': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL); + break; + + case 'S': + case 'V': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FS) & OP_MASK_FS); + break; + + + case 'T': + case 'W': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FT) & OP_MASK_FT); + break; + + case 'D': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FD) & OP_MASK_FD); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "$f%d", + (l >> OP_SH_FR) & OP_MASK_FR); + break; + + case 'E': + (*info->fprintf_func) (info->stream, "$%d", + (l >> OP_SH_RT) & OP_MASK_RT); + break; + + case 'G': + (*info->fprintf_func) (info->stream, "$%d", + (l >> OP_SH_RD) & OP_MASK_RD); + break; + + case 'N': + (*info->fprintf_func) (info->stream, "$fcc%d", + (l >> OP_SH_BCC) & OP_MASK_BCC); + break; + + case 'M': + (*info->fprintf_func) (info->stream, "$fcc%d", + (l >> OP_SH_CCC) & OP_MASK_CCC); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "%d", + (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); + break; + + + default: + (*info->fprintf_func) (info->stream, + "# internal error, undefined modifier(%c)", *d); + break; + } +} + +/* Print the mips instruction at address MEMADDR in debugged memory, + on using INFO. Returns length of the instruction, in bytes, which is + always 4. BIGENDIAN must be 1 if this is big-endian code, 0 if + this is little-endian code. */ + +static int +_print_insn_mips (memaddr, word, info) + bfd_vma memaddr; + unsigned long int word; + struct disassemble_info *info; +{ + register const struct mips_opcode *op; + int target_processor, mips_isa; + static boolean init = 0; + static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; + + /* Build a hash table to shorten the search time. */ + if (! init) + { + unsigned int i; + + for (i = 0; i <= OP_MASK_OP; i++) + { + for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo == INSN_MACRO) + continue; + if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) + { + mips_hash[i] = op; + break; + } + } + } + + init = 1; + } + + switch (info->mach) + { + case bfd_mach_mips3000: + target_processor = 3000; + mips_isa = 1; + break; + case bfd_mach_mips3900: + target_processor = 3900; + mips_isa = 1; + break; + case bfd_mach_mips4000: + target_processor = 4000; + mips_isa = 3; + break; + case bfd_mach_mips4010: + target_processor = 4010; + mips_isa = 2; + break; + case bfd_mach_mips4100: + target_processor = 4100; + mips_isa = 3; + break; + case bfd_mach_mips4300: + target_processor = 4300; + mips_isa = 3; + break; + case bfd_mach_mips4400: + target_processor = 4400; + mips_isa = 3; + break; + case bfd_mach_mips4600: + target_processor = 4600; + mips_isa = 3; + break; + case bfd_mach_mips4650: + target_processor = 4650; + mips_isa = 3; + break; + case bfd_mach_mips5000: + target_processor = 5000; + mips_isa = 4; + break; + case bfd_mach_mips6000: + target_processor = 6000; + mips_isa = 2; + break; + case bfd_mach_mips8000: + target_processor = 8000; + mips_isa = 4; + break; + case bfd_mach_mips10000: + target_processor = 10000; + mips_isa = 4; + break; + case bfd_mach_mips16: + target_processor = 16; + mips_isa = 3; + break; + default: + target_processor = 3000; + mips_isa = 3; + break; + + } + + info->bytes_per_chunk = 4; + info->display_endian = info->endian; + + op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; + if (op != NULL) + { + for (; op < &mips_opcodes[NUMOPCODES]; op++) + { + if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) + { + register const char *d; + int insn_isa; + + if ((op->membership & INSN_ISA) == INSN_ISA1) + insn_isa = 1; + else if ((op->membership & INSN_ISA) == INSN_ISA2) + insn_isa = 2; + else if ((op->membership & INSN_ISA) == INSN_ISA3) + insn_isa = 3; + else if ((op->membership & INSN_ISA) == INSN_ISA4) + insn_isa = 4; + else + insn_isa = 15; + + if (insn_isa > mips_isa + && (target_processor == 4650 + && op->membership & INSN_4650) == 0 + && (target_processor == 4010 + && op->membership & INSN_4010) == 0 + && (target_processor == 4100 + && op->membership & INSN_4100) == 0 + && (target_processor == 3900 + && op->membership & INSN_3900) == 0) + continue; + + (*info->fprintf_func) (info->stream, "%s", op->name); + + d = op->args; + if (d != NULL && *d != '\0') + { + (*info->fprintf_func) (info->stream, "\t"); + for (; *d != '\0'; d++) + print_insn_arg (d, word, memaddr, info); + } + + return 4; + } + } + } + + /* Handle undefined instructions. */ + (*info->fprintf_func) (info->stream, "0x%x", word); + return 4; +} + +int +print_insn_big_mips (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + bfd_byte buffer[4]; + int status; + + if (info->mach == 16 + || (info->flavour == bfd_target_elf_flavour + && info->symbols != NULL + && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other + == STO_MIPS16))) + return print_insn_mips16 (memaddr, info); + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status == 0) + return _print_insn_mips (memaddr, (unsigned long) bfd_getb32 (buffer), + info); + else + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } +} + +int +print_insn_little_mips (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + bfd_byte buffer[4]; + int status; + + + if (info->mach == 16 + || (info->flavour == bfd_target_elf_flavour + && info->symbols != NULL + && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other + == STO_MIPS16))) + return print_insn_mips16 (memaddr, info); + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status == 0) + return _print_insn_mips (memaddr, (unsigned long) bfd_getl32 (buffer), + info); + else + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } +} + +/* Disassemble mips16 instructions. */ + +static int +print_insn_mips16 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status; + bfd_byte buffer[2]; + int length; + int insn; + boolean use_extend; + int extend = 0; + const struct mips_opcode *op, *opend; + + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + length = 2; + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Handle the extend opcode specially. */ + use_extend = false; + if ((insn & 0xf800) == 0xf000) + { + use_extend = true; + extend = insn & 0x7ff; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Check for an extend opcode followed by an extend opcode. */ + if ((insn & 0xf800) == 0xf000) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length; + } + + length += 2; + } + + /* FIXME: Should probably use a hash table on the major opcode here. */ + + opend = mips16_opcodes + bfd_mips16_num_opcodes; + for (op = mips16_opcodes; op < opend; op++) + { + if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match) + { + const char *s; + + if (strchr (op->args, 'a') != NULL) + { + if (use_extend) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length - 2; + } + + use_extend = false; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, + info); + if (status == 0) + { + use_extend = true; + if (info->endian == BFD_ENDIAN_BIG) + extend = bfd_getb16 (buffer); + else + extend = bfd_getl16 (buffer); + length += 2; + } + } + + (*info->fprintf_func) (info->stream, "%s", op->name); + if (op->args[0] != '\0') + (*info->fprintf_func) (info->stream, "\t"); + + for (s = op->args; *s != '\0'; s++) + { + if (*s == ',' + && s[1] == 'w' + && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) + == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + if (*s == ',' + && s[1] == 'v' + && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) + == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, + info); + } + + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + info->branch_delay_insns = 1; + if (info->insn_type != dis_jsr) + info->insn_type = dis_branch; + } + + return length; + } + } + + if (use_extend) + (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); + (*info->fprintf_func) (info->stream, "0x%x", insn); + info->insn_type = dis_noninsn; + + return length; +} + +/* Disassemble an operand for a mips16 instruction. */ + +static void +print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) + int type; + const struct mips_opcode *op; + int l; + boolean use_extend; + int extend; + bfd_vma memaddr; + struct disassemble_info *info; +{ + switch (type) + { + case ',': + case '(': + case ')': + (*info->fprintf_func) (info->stream, "%c", type); + break; + + case 'y': + case 'w': + (*info->fprintf_func) (info->stream, "$%s", + mips16_reg_names[((l >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY)]); + break; + + case 'x': + case 'v': + (*info->fprintf_func) (info->stream, "$%s", + mips16_reg_names[((l >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX)]); + break; + + case 'z': + (*info->fprintf_func) (info->stream, "$%s", + mips16_reg_names[((l >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ)]); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "$%s", + mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z)]); + break; + + case '0': + (*info->fprintf_func) (info->stream, "$%s", reg_names[0]); + break; + + case 'S': + (*info->fprintf_func) (info->stream, "$%s", reg_names[29]); + break; + + case 'P': + (*info->fprintf_func) (info->stream, "$pc"); + break; + + case 'R': + (*info->fprintf_func) (info->stream, "$%s", reg_names[31]); + break; + + case 'X': + (*info->fprintf_func) (info->stream, "$%s", + reg_names[((l >> MIPS16OP_SH_REGR32) + & MIPS16OP_MASK_REGR32)]); + break; + + case 'Y': + (*info->fprintf_func) (info->stream, "$%s", + reg_names[MIPS16OP_EXTRACT_REG32R (l)]); + break; + + case '<': + case '>': + case '[': + case ']': + case '4': + case '5': + case 'H': + case 'W': + case 'D': + case 'j': + case '6': + case '8': + case 'V': + case 'C': + case 'U': + case 'k': + case 'K': + case 'p': + case 'q': + case 'A': + case 'B': + case 'E': + { + int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; + + shift = 0; + signedp = 0; + extbits = 16; + pcrel = 0; + extu = 0; + branch = 0; + switch (type) + { + case '<': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 5; + extu = 1; + break; + case '>': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 5; + extu = 1; + break; + case '[': + nbits = 3; + immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; + extbits = 6; + extu = 1; + break; + case ']': + nbits = 3; + immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; + extbits = 6; + extu = 1; + break; + case '4': + nbits = 4; + immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; + signedp = 1; + extbits = 15; + break; + case '5': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 1; + break; + case 'H': + nbits = 5; + shift = 1; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 2; + break; + case 'W': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 + && (op->pinfo & MIPS16_INSN_READ_SP) == 0) + { + info->insn_type = dis_dref; + info->data_size = 4; + } + break; + case 'D': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'j': + nbits = 5; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + signedp = 1; + break; + case '6': + nbits = 6; + immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + break; + case '8': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + break; + case 'V': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + /* FIXME: This might be lw, or it might be addiu to $sp or + $pc. We assume it's load. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'C': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'U': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + extu = 1; + break; + case 'k': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'K': + nbits = 8; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + break; + case 'p': + nbits = 8; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + signedp = 1; + pcrel = 1; + branch = 1; + info->insn_type = dis_condbranch; + break; + case 'q': + nbits = 11; + immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; + signedp = 1; + pcrel = 1; + branch = 1; + info->insn_type = dis_branch; + break; + case 'A': + nbits = 8; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; + pcrel = 1; + /* FIXME: This can be lw or la. We assume it is lw. */ + info->insn_type = dis_dref; + info->data_size = 4; + break; + case 'B': + nbits = 5; + shift = 3; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + info->insn_type = dis_dref; + info->data_size = 8; + break; + case 'E': + nbits = 5; + shift = 2; + immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; + pcrel = 1; + break; + default: + abort (); + } + + if (! use_extend) + { + if (signedp && immed >= (1 << (nbits - 1))) + immed -= 1 << nbits; + immed <<= shift; + if ((type == '<' || type == '>' || type == '[' || type == '[') + && immed == 0) + immed = 8; + } + else + { + if (extbits == 16) + immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); + else if (extbits == 15) + immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); + else + immed = ((extend >> 6) & 0x1f) | (extend & 0x20); + immed &= (1 << extbits) - 1; + if (! extu && immed >= (1 << (extbits - 1))) + immed -= 1 << extbits; + } + + if (! pcrel) + (*info->fprintf_func) (info->stream, "%d", immed); + else + { + bfd_vma baseaddr; + bfd_vma val; + + if (branch) + { + immed *= 2; + baseaddr = memaddr + 2; + } + else if (use_extend) + baseaddr = memaddr - 2; + else + { + int status; + bfd_byte buffer[2]; + + baseaddr = memaddr; + + /* If this instruction is in the delay slot of a jr + instruction, the base address is the address of the + jr instruction. If it is in the delay slot of jalr + instruction, the base address is the address of the + jalr instruction. This test is unreliable: we have + no way of knowing whether the previous word is + instruction or data. */ + status = (*info->read_memory_func) (memaddr - 4, buffer, 2, + info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf800) == 0x1800)) + baseaddr = memaddr - 4; + else + { + status = (*info->read_memory_func) (memaddr - 2, buffer, + 2, info); + if (status == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf81f) == 0xe800)) + baseaddr = memaddr - 2; + } + } + val = (baseaddr & ~ ((1 << shift) - 1)) + immed; + (*info->print_address_func) (val, info); + info->target = val; + } + } + break; + + case 'a': + if (! use_extend) + extend = 0; + l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + (*info->print_address_func) ((memaddr & 0xf0000000) | l, info); + info->insn_type = dis_jsr; + info->target = (memaddr & 0xf0000000) | l; + info->branch_delay_insns = 1; + break; + + case 'l': + case 'L': + { + int need_comma, amask, smask; + + need_comma = 0; + + l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; + + amask = (l >> 3) & 7; + + if (amask > 0 && amask < 5) + { + (*info->fprintf_func) (info->stream, "$%s", reg_names[4]); + if (amask > 1) + (*info->fprintf_func) (info->stream, "-$%s", + reg_names[amask + 3]); + need_comma = 1; + } + + smask = (l >> 1) & 3; + if (smask == 3) + { + (*info->fprintf_func) (info->stream, "%s??", + need_comma ? "," : ""); + need_comma = 1; + } + else if (smask > 0) + { + (*info->fprintf_func) (info->stream, "%s$%s", + need_comma ? "," : "", + reg_names[16]); + if (smask > 1) + (*info->fprintf_func) (info->stream, "-$%s", + reg_names[smask + 15]); + need_comma = 1; + } + + if (l & 1) + { + (*info->fprintf_func) (info->stream, "%s$%s", + need_comma ? "," : "", + reg_names[31]); + need_comma = 1; + } + + if (amask == 5 || amask == 6) + { + (*info->fprintf_func) (info->stream, "%s$f0", + need_comma ? "," : ""); + if (amask == 6) + (*info->fprintf_func) (info->stream, "-$f1"); + } + } + break; + + default: + abort (); + } +} diff --git a/contrib/binutils/opcodes/mips-opc.c b/contrib/binutils/opcodes/mips-opc.c new file mode 100644 index 0000000000000..7e73285957aea --- /dev/null +++ b/contrib/binutils/opcodes/mips-opc.c @@ -0,0 +1,759 @@ +/* mips.h. Mips opcode list for GDB, the GNU debugger. + Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Ralph Campbell and OSF + Commented and modified by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "ansidecl.h" +#include "opcode/mips.h" + +/* Short hand so the lines aren't too long. */ + +#define LDD INSN_LOAD_MEMORY_DELAY +#define LCD INSN_LOAD_COPROC_DELAY +#define UBD INSN_UNCOND_BRANCH_DELAY +#define CBD INSN_COND_BRANCH_DELAY +#define COD INSN_COPROC_MOVE_DELAY +#define CLD INSN_COPROC_MEMORY_DELAY +#define CBL INSN_COND_BRANCH_LIKELY +#define TRAP INSN_TRAP +#define SM INSN_STORE_MEMORY + +#define WR_d INSN_WRITE_GPR_D +#define WR_t INSN_WRITE_GPR_T +#define WR_31 INSN_WRITE_GPR_31 +#define WR_D INSN_WRITE_FPR_D +#define WR_T INSN_WRITE_FPR_T +#define WR_S INSN_WRITE_FPR_S +#define RD_s INSN_READ_GPR_S +#define RD_b INSN_READ_GPR_S +#define RD_t INSN_READ_GPR_T +#define RD_S INSN_READ_FPR_S +#define RD_T INSN_READ_FPR_T +#define RD_R INSN_READ_FPR_R +#define WR_CC INSN_WRITE_COND_CODE +#define RD_CC INSN_READ_COND_CODE +#define RD_C0 INSN_COP +#define RD_C1 INSN_COP +#define RD_C2 INSN_COP +#define RD_C3 INSN_COP +#define WR_C0 INSN_COP +#define WR_C1 INSN_COP +#define WR_C2 INSN_COP +#define WR_C3 INSN_COP + +#define WR_HI INSN_WRITE_HI +#define RD_HI INSN_READ_HI +#define MOD_HI WR_HI|RD_HI + +#define WR_LO INSN_WRITE_LO +#define RD_LO INSN_READ_LO +#define MOD_LO WR_LO|RD_LO + +#define WR_HILO WR_HI|WR_LO +#define RD_HILO RD_HI|RD_LO +#define MOD_HILO WR_HILO|RD_HILO + + +#define I1 INSN_ISA1 +#define I2 INSN_ISA2 +#define I3 INSN_ISA3 +#define I4 INSN_ISA4 +#define P3 INSN_4650 +#define L1 INSN_4010 +#define V1 INSN_4100 +#define T3 INSN_3900 + +#define G1 (T3 \ + ) + +#define G2 (T3 \ + ) + +#define G3 (I4 \ + ) + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Many instructions are short hand for other instructions (i.e., The + jal instruction is short for jalr ). */ + +const struct mips_opcode mips_builtin_opcodes[] = { +/* These instructions appear first so that the disassembler will find + them first. The assemblers uses a hash table based on the + instruction name anyhow. */ +/* name, args, mask, match, pinfo */ +{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, +{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ +{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ +{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, +{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ +{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ +{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ +{"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ +{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ +{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ + + +{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, +{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, +{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1}, +{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1}, +{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, +{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, +{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, +{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, +{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, +/* b is at the top of the table. */ +/* bal is at the top of the table. */ +{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, +{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, +{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, +{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, +{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, +{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, +{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, +{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, +{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 }, +{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, +{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, +{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, +{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2 }, +{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, +{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, +{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2 }, +{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2 }, +{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, +{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, +{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2 }, +{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2 }, +{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, +{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, +{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, +{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2 }, +{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2 }, +{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, +{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, +{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2 }, +{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2 }, +{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, +{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, +{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2 }, +{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2 }, +{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, +{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, +{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2 }, +{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2 }, +{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, +{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, +{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2 }, +{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2 }, +{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, +{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, +{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2 }, +{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2 }, +{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, +{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, +{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, +{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, +{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, +{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 }, +{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, +{"break", "c", 0x0000000d, 0xfc00003f, TRAP, I1 }, +{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, +{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, +{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3 }, +{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, +{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, +{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, +{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, +{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, +{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, +{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, +{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, +{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, +{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, +{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, +{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 }, +{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 }, +{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 }, +{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, +{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, +{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, +/* dctr and dctw are used on the r5000. */ +{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, +{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, +{"deret", "", 0x4200001f, 0xffffffff, 0, G2 }, +/* For ddiv, see the comments about div. */ +{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, +{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, +{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 }, +/* For ddivu, see the comments about div. */ +{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, +{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 }, +{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, +/* The MIPS assembler treats the div opcode with two operands as + though the first operand appeared twice (the first operand is both + a source and a destination). To get the div machine instruction, + you must use an explicit destination of $0. */ +{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, +{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, +{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 }, +{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, +{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +/* For divu, see the comments about div. */ +{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, +{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, +{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, +{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, +{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, +{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ +{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ +{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 }, +{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 }, +{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, +{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, +{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, +{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, +{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, +{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, +{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, +{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 }, +{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 }, +{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 }, +{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, +{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3}, +{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */ +{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/ +{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, +{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 }, +{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 }, +{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 }, +{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, +{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, +{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, +{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ +{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */ +{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, +{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */ +{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */ +{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, +{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */ +{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */ +{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 }, +{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 }, +{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, +{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, +{"eret", "", 0x42000018, 0xffffffff, 0, I3 }, +{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 }, +{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 }, +{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 }, +{"hibernate","", 0x42000023, 0xffffffff, 0, V1 }, +{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, +{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */ +/* SVR4 PIC code requires special handling for j, so it must be a + macro. */ +{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 }, +/* This form of j is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"j", "a", 0x08000000, 0xfc000000, UBD, I1 }, +{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 }, +{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 }, +/* SVR4 PIC code requires special handling for jal, so it must be a + macro. */ +{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 }, +{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 }, +{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 }, +/* This form of jal is used by the disassembler and internally by the + assembler, but will never match user input (because the line above + will match first). */ +{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, + /* jalx really should only be avaliable if mips16 is available, + but for now make it I1. */ +{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 }, +{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, +{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 }, +{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 }, +{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 }, +{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 }, +{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 }, +{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, +{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, +{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, +{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, +{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */ +{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 }, +{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 }, +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 }, +{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, +{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 }, +{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, +{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 }, +{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, +{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 }, +{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, +{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 }, +{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 }, +/* li is at the start of the table. */ +{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 }, +{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 }, +{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 }, +{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 }, +{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, +{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 }, +{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, +{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 }, +{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, +{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 }, +{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, +{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 }, +{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, +{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, +{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, +{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, +{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */ +{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 }, +{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, +{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 }, +{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 }, +{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ +{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */ +{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, +{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 }, +{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ +{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */ +{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, +{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 }, +{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, +{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, +{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 }, +{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, G1 }, +{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1 }, +{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, G1 }, +{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1 }, +{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 }, +{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, +{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, +{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, +{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, +{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, +{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, +{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4 }, +{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 }, +{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 }, +{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4 }, +{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 }, +{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, +{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, +{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4 }, +{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4 }, +{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4 }, +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4 }, +{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 }, +{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4 }, +{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4 }, +/* move is at the top of the table. */ +{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, +{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 }, +{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, +{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, +{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, +{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, +{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 }, +{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, +{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3}, +{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 }, +{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 }, +{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 }, +{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 }, +{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 }, +{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 }, +{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1}, +{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1}, +{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1}, +{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1}, +{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */ +{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */ +{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 }, +{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 }, +{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, +{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, +/* nop is at the start of the table. */ +{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 }, +{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/ +{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 }, +{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, + + +{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3 }, +{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, + + +{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, +{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, +{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, +{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, +{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 }, +{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 }, +{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 }, +{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 }, +{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 }, +{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 }, +{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 }, +{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 }, +{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, +{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, +{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, +{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 }, +{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 }, +{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 }, +{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 }, +{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 }, +{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 }, +{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 }, +{"sdbbp", "c", 0x0000000e, 0xfc00003f, TRAP, G2 }, +{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, +{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, +{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, +{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 }, +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 }, +{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 }, +{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 }, +{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, +{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 }, +{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 }, +{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 }, +{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 }, +{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 }, +{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 }, +{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, +{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, +{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,L1 }, +{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 }, +{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 }, +{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 }, +{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 }, +{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 }, +{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 }, +{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 }, +{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 }, +{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 }, +{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 }, +{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 }, +{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, +{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, +{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, +{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 }, +{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, +{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */ +{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 }, +{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 }, +{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, +{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 }, +{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 }, +{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 }, +{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, +{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, +{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ +{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, +{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, +{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ +{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, +{"standby", "", 0x42000021, 0xffffffff, 0, V1 }, +{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, +{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 }, +{"suspend", "", 0x42000022, 0xffffffff, 0, V1 }, +{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 }, +{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 }, +{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 }, +{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, +{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, +{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, +{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, +{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ +{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 }, +{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 }, +{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 }, +{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 }, +{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ +{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */ +{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, +{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 }, +{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ +{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */ +{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, +{"sync", "", 0x0000000f, 0xffffffff, 0, I2|T3 }, +{"sync.p", "", 0x0000000f, 0xffffffff, 0, I2 }, +{"sync.l", "", 0x0000040f, 0xffffffff, 0, I2 }, +{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 }, +{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */ +{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */ +{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */ +{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 }, +{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 }, +{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 }, +{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 }, +{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */ +{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */ +{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, +{"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */ +{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 }, +{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 }, +{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 }, +{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, +{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 }, +{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 }, +{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 }, +{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 }, +{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 }, +{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 }, +{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 }, +{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 }, +{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 }, +{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 }, +{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 }, +{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 }, +{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 }, +{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, +{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, +{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, +{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, +{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, +{"wait", "", 0x42000020, 0xffffffff, TRAP, I3 }, +{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, +{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, +/* No hazard protection on coprocessor instructions--they shouldn't + change the state of the processor and if they do it's up to the + user to put in nops as necessary. These are at the end so that the + disasembler recognizes more specific versions first. */ +{"c0", "C", 0x42000000, 0xfe000000, 0, I1 }, +{"c1", "C", 0x46000000, 0xfe000000, 0, I1 }, +{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 }, +{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 }, +{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 }, +{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 }, +{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 }, +{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 }, + + /* Conflicts with the 4650's "mul" instruction. Nobody's using the + 4010 any more, so move this insn out of the way. If the object + format gave us more info, we could do this right. */ +{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 }, +}; + +#define MIPS_NUM_OPCODES \ + ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) +const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; + +/* const removed from the following to allow for dynamic extensions to the + * built-in instruction set. */ +struct mips_opcode *mips_opcodes = + (struct mips_opcode *) mips_builtin_opcodes; +int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; +#undef MIPS_NUM_OPCODES + diff --git a/contrib/binutils/opcodes/mips16-opc.c b/contrib/binutils/opcodes/mips16-opc.c new file mode 100644 index 0000000000000..f523822079d16 --- /dev/null +++ b/contrib/binutils/opcodes/mips16-opc.c @@ -0,0 +1,225 @@ +/* mips16-opc.c. Mips16 opcode table. + Copyright 1996, 1997 Free Software Foundation, Inc. + Contributed by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#include +#include "ansidecl.h" +#include "opcode/mips.h" + +/* This is the opcodes table for the mips16 processor. The format of + this table is intentionally identical to the one in mips-opc.c. + However, the special letters that appear in the argument string are + different, and the table uses some different flags. */ + +/* Use some short hand macros to keep down the length of the lines in + the opcodes table. */ + +#define UBD INSN_UNCOND_BRANCH_DELAY + +#define WR_x MIPS16_INSN_WRITE_X +#define WR_y MIPS16_INSN_WRITE_Y +#define WR_z MIPS16_INSN_WRITE_Z +#define WR_T MIPS16_INSN_WRITE_T +#define WR_SP MIPS16_INSN_WRITE_SP +#define WR_31 MIPS16_INSN_WRITE_31 +#define WR_Y MIPS16_INSN_WRITE_GPR_Y + +#define RD_x MIPS16_INSN_READ_X +#define RD_y MIPS16_INSN_READ_Y +#define RD_Z MIPS16_INSN_READ_Z +#define RD_T MIPS16_INSN_READ_T +#define RD_SP MIPS16_INSN_READ_SP +#define RD_31 MIPS16_INSN_READ_31 +#define RD_PC MIPS16_INSN_READ_PC +#define RD_X MIPS16_INSN_READ_GPR_X + +#define WR_HI INSN_WRITE_HI +#define WR_LO INSN_WRITE_LO +#define RD_HI INSN_READ_HI +#define RD_LO INSN_READ_LO + +#define TRAP INSN_TRAP + +#define I3 INSN_ISA3 + +#define T3 INSN_3900 + +const struct mips_opcode mips16_opcodes[] = { +{"nop", "", 0x6500, 0xffff, RD_Z }, /* move $0,$Z */ +{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC }, +{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO }, +{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x }, +{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x }, +{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP }, +{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP }, +{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC }, +{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP }, +{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y }, +{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x }, +{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x }, +{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP }, +{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP }, +{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC }, +{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP }, +{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y }, +{"b", "q", 0x1000, 0xf800, 0 }, +{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO }, +{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO }, +{"beqz", "x,p", 0x2000, 0xf800, RD_x }, +{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO }, +{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO }, +{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO }, +{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO }, +{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO }, +{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO }, +{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO }, +{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO }, +{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO }, +{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO }, +{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO }, +{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO }, +{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO }, +{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO }, +{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO }, +{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO }, +{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO }, +{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO }, +{"bnez", "x,p", 0x2800, 0xf800, RD_x }, +{"break", "6", 0xe805, 0xf81f, TRAP }, +{"bteqz", "p", 0x6000, 0xff00, RD_T }, +{"btnez", "p", 0x6100, 0xff00, RD_T }, +{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x }, +{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y }, +{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x }, +{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, +{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, +{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, +{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, I3 }, +{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, +{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, +{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, +{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, +{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, +{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO }, +{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO }, +{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, +{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO }, +{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, +{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO }, +{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, I3 }, +{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO }, +{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, +{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO }, +{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, I3 }, +{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, I3 }, +{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, I3 }, +{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, +{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, I3 }, +{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO }, +{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO }, +{"exit", "L", 0xed09, 0xff1f, TRAP }, +{"exit", "L", 0xee09, 0xff1f, TRAP }, +{"exit", "L", 0xef09, 0xff1f, TRAP }, +{"entry", "l", 0xe809, 0xf81f, TRAP }, +{"extend", "e", 0xf000, 0xf800, 0 }, +{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, +{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, +{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, +{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x }, +{"jal", "a", 0x1800, 0xfc00, UBD|WR_31 }, +{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31 }, +{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x }, +{"jr", "R", 0xe820, 0xffff, UBD|RD_31 }, +{"j", "x", 0xe800, 0xf8ff, UBD|RD_x }, +{"j", "R", 0xe820, 0xffff, UBD|RD_31 }, +{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x }, +{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x }, +{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 }, +{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, +{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, +{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, I3 }, +{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x }, +{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x }, +{"li", "x,U", 0x6800, 0xf800, WR_x }, +{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x }, +{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC }, +{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC }, +{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP }, +{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, I3 }, +{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI }, +{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO }, +{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X }, +{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z }, +{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO }, +{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, +{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, +{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y }, +{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y }, +{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y }, +{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, +{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO }, +{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO }, +{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO }, +{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x }, +{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, I3 }, +{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, I3 }, +{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC }, +{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x }, +{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x }, +{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y }, +{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x }, +{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x }, +{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y }, +{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x }, +{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x }, +{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y }, +{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x }, +{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x }, +{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y }, +{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x }, +{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x }, +{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y }, +{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x }, +{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y }, +{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO }, +{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO }, +{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x }, +{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP }, +{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP }, +{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y }, +}; + +const int bfd_mips16_num_opcodes = + ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0]))); diff --git a/contrib/com_err/com_err.3 b/contrib/com_err/com_err.3 index e6eeea13b8525..7f6685e4a63c4 100644 --- a/contrib/com_err/com_err.3 +++ b/contrib/com_err/com_err.3 @@ -1,7 +1,7 @@ .\" Copyright (c) 1988 Massachusetts Institute of Technology, .\" Student Information Processing Board. All rights reserved. .\" -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/com_err/com_err.3,v 1.1 1999/09/04 09:48:58 markm Exp $ .\" .TH COM_ERR 3 "22 Nov 1988" SIPB .SH NAME diff --git a/contrib/com_err/com_err.h b/contrib/com_err/com_err.h index 19cf034d68406..b19a12385b38e 100644 --- a/contrib/com_err/com_err.h +++ b/contrib/com_err/com_err.h @@ -37,7 +37,7 @@ */ /* $Id: com_err.h,v 1.3 1998/05/02 20:13:28 assar Exp $ */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/com_err/com_err.h,v 1.2 2000/01/14 18:28:23 bde Exp $ */ /* MIT compatible com_err library */ diff --git a/contrib/com_err/com_right.h b/contrib/com_err/com_right.h index c329bced9785c..7084ec1be6a1a 100644 --- a/contrib/com_err/com_right.h +++ b/contrib/com_err/com_right.h @@ -37,7 +37,7 @@ */ /* $Id: com_right.h,v 1.8 1998/02/17 21:19:43 bg Exp $ */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/com_err/com_right.h,v 1.2 2000/01/14 18:51:30 bde Exp $ */ #ifndef __COM_RIGHT_H__ #define __COM_RIGHT_H__ diff --git a/contrib/com_err/compile_et.1 b/contrib/com_err/compile_et.1 index 091038079535a..31607f8661414 100644 --- a/contrib/com_err/compile_et.1 +++ b/contrib/com_err/compile_et.1 @@ -1,7 +1,7 @@ .\" Copyright (c) 1988 Massachusetts Institute of Technology, .\" Student Information Processing Board. All rights reserved. .\" -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/com_err/compile_et.1,v 1.1 1999/09/04 09:48:59 markm Exp $ .\" .Dd November 22, 1988 .Os diff --git a/contrib/cpio/FREEBSD-upgrade b/contrib/cpio/FREEBSD-upgrade index 8e2bf3600b97c..c3964828f4855 100644 --- a/contrib/cpio/FREEBSD-upgrade +++ b/contrib/cpio/FREEBSD-upgrade @@ -1,4 +1,4 @@ -$FreeBSD$ +$FreeBSD: src/contrib/cpio/FREEBSD-upgrade,v 1.3 1999/09/08 11:16:36 obrien Exp $ GNU cpio 2.4.2 originals can be found at: ftp://prep.ai.mit.edu/pub/gnu diff --git a/contrib/cpio/main.c b/contrib/cpio/main.c index 20829ef50e1a3..6309973999e4e 100644 --- a/contrib/cpio/main.c +++ b/contrib/cpio/main.c @@ -19,7 +19,7 @@ David MacKenzie , and John Oleynick . */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/cpio/main.c,v 1.3 1999/09/15 01:47:13 peter Exp $ */ #include #include diff --git a/contrib/cvs/FREEBSD-upgrade b/contrib/cvs/FREEBSD-upgrade index d40330c19d5d0..bc0800c074459 100644 --- a/contrib/cvs/FREEBSD-upgrade +++ b/contrib/cvs/FREEBSD-upgrade @@ -1,4 +1,4 @@ -$FreeBSD$ +$FreeBSD: src/contrib/cvs/FREEBSD-upgrade,v 1.7 1999/12/11 13:11:47 peter Exp $ MAINTAINER= peter@FreeBSD.org diff --git a/contrib/cvs/contrib/log.pl b/contrib/cvs/contrib/log.pl index 676d6c9fbe167..62c06e839d9ac 100644 --- a/contrib/cvs/contrib/log.pl +++ b/contrib/cvs/contrib/log.pl @@ -5,7 +5,7 @@ # # XXX -- I HATE Perl! This *will* be re-written in shell/awk/sed soon! # -# $FreeBSD$ +# $FreeBSD: src/contrib/cvs/contrib/log.pl,v 1.4 1999/12/11 12:42:49 peter Exp $ # Usage: log.pl [[-m user] ...] [-s] -f logfile 'dirname file ...' # diff --git a/contrib/cvs/diff/diff3.c b/contrib/cvs/diff/diff3.c index c2997e92cb5f3..a95d07d5995be 100644 --- a/contrib/cvs/diff/diff3.c +++ b/contrib/cvs/diff/diff3.c @@ -13,7 +13,7 @@ */ /* - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/diff/diff3.c,v 1.2 1999/12/11 14:58:00 peter Exp $ */ /* Written by Randy Smith */ diff --git a/contrib/cvs/lib/md5.h b/contrib/cvs/lib/md5.h index 3b5ba05891f27..f9d886b61a8cc 100644 --- a/contrib/cvs/lib/md5.h +++ b/contrib/cvs/lib/md5.h @@ -1,7 +1,7 @@ /* See md5.c for explanation and copyright information. */ /* - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/lib/md5.h,v 1.2 1999/12/11 15:10:02 peter Exp $ */ #ifndef MD5_H diff --git a/contrib/cvs/man/cvs.1 b/contrib/cvs/man/cvs.1 index fe9e30a2e7561..464da017da2dd 100644 --- a/contrib/cvs/man/cvs.1 +++ b/contrib/cvs/man/cvs.1 @@ -1,4 +1,4 @@ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/cvs/man/cvs.1,v 1.15 1999/12/04 02:15:30 peter Exp $ .de Id .ds Rv \\$3 .ds Dt \\$4 diff --git a/contrib/cvs/src/client.c b/contrib/cvs/src/client.c index eafe916777b60..e131d6f3f5b19 100644 --- a/contrib/cvs/src/client.c +++ b/contrib/cvs/src/client.c @@ -11,7 +11,7 @@ GNU General Public License for more details. */ /* - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/client.c,v 1.2 2000/01/06 17:57:24 peter Exp $ */ #ifdef HAVE_CONFIG_H diff --git a/contrib/cvs/src/commit.c b/contrib/cvs/src/commit.c index 6dfd4a80602ef..f903c508010c4 100644 --- a/contrib/cvs/src/commit.c +++ b/contrib/cvs/src/commit.c @@ -12,7 +12,7 @@ * * The call is: cvs commit [options] files... * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/commit.c,v 1.8 1999/12/11 12:50:07 peter Exp $ */ #include diff --git a/contrib/cvs/src/cvs.h b/contrib/cvs/src/cvs.h index b889c9a8501eb..d1f087af89fd1 100644 --- a/contrib/cvs/src/cvs.h +++ b/contrib/cvs/src/cvs.h @@ -9,7 +9,7 @@ /* * basic information used in all source files * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/cvs.h,v 1.11 1999/12/11 12:50:08 peter Exp $ */ diff --git a/contrib/cvs/src/diff.c b/contrib/cvs/src/diff.c index 15353e63f61ca..df060570f12a4 100644 --- a/contrib/cvs/src/diff.c +++ b/contrib/cvs/src/diff.c @@ -13,7 +13,7 @@ * Without any file arguments, runs diff against all the currently modified * files. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/diff.c,v 1.14 1999/12/11 12:50:08 peter Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/filesubr.c b/contrib/cvs/src/filesubr.c index 75725586cf1eb..ded5ac85d5348 100644 --- a/contrib/cvs/src/filesubr.c +++ b/contrib/cvs/src/filesubr.c @@ -18,7 +18,7 @@ file system semantics. */ /* - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/filesubr.c,v 1.6 2000/01/10 08:56:01 kris Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/import.c b/contrib/cvs/src/import.c index a449842623c26..a5871be793ebe 100644 --- a/contrib/cvs/src/import.c +++ b/contrib/cvs/src/import.c @@ -15,7 +15,7 @@ * * Additional arguments specify more Vendor Release Tags. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/import.c,v 1.7 1999/12/11 12:50:08 peter Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/lock.c b/contrib/cvs/src/lock.c index a0c0a343ebd78..747c5bfd948a4 100644 --- a/contrib/cvs/src/lock.c +++ b/contrib/cvs/src/lock.c @@ -9,7 +9,7 @@ * * Lock file support for CVS. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/lock.c,v 1.7 1999/12/11 12:50:08 peter Exp $ */ /* The node Concurrency in doc/cvs.texinfo has a brief introduction to diff --git a/contrib/cvs/src/login.c b/contrib/cvs/src/login.c index 708dfc8d15d56..a1634a85414c2 100644 --- a/contrib/cvs/src/login.c +++ b/contrib/cvs/src/login.c @@ -6,7 +6,7 @@ * * Allow user to log in for an authenticating server. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/login.c,v 1.3 1999/12/11 12:50:08 peter Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/logmsg.c b/contrib/cvs/src/logmsg.c index e1b8ed04e8b10..323ea494f000f 100644 --- a/contrib/cvs/src/logmsg.c +++ b/contrib/cvs/src/logmsg.c @@ -5,7 +5,7 @@ * You may distribute under the terms of the GNU General Public License as * specified in the README file that comes with the CVS source distribution. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/logmsg.c,v 1.6 1999/12/11 12:50:08 peter Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/main.c b/contrib/cvs/src/main.c index 39bfaa2cc39c7..55496d6a83d19 100644 --- a/contrib/cvs/src/main.c +++ b/contrib/cvs/src/main.c @@ -10,7 +10,7 @@ * Credit to Dick Grune, Vrije Universiteit, Amsterdam, for writing * the shell-script CVS system that this is based on. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/main.c,v 1.18 1999/12/11 13:00:18 peter Exp $ */ #include diff --git a/contrib/cvs/src/mkmodules.c b/contrib/cvs/src/mkmodules.c index 966fb3285e16e..404a56a5a41c4 100644 --- a/contrib/cvs/src/mkmodules.c +++ b/contrib/cvs/src/mkmodules.c @@ -5,7 +5,7 @@ * You may distribute under the terms of the GNU General Public License as * specified in the README file that comes with the CVS kit. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/mkmodules.c,v 1.9 1999/12/11 12:50:08 peter Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/prepend_args.c b/contrib/cvs/src/prepend_args.c index 12322ce48bdf9..7be868a258155 100644 --- a/contrib/cvs/src/prepend_args.c +++ b/contrib/cvs/src/prepend_args.c @@ -16,7 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/cvs/src/prepend_args.c,v 1.2 1999/12/04 08:44:05 obrien Exp $ */ #ifdef HAVE_CONFIG_H diff --git a/contrib/cvs/src/prepend_args.h b/contrib/cvs/src/prepend_args.h index 6708442ec1240..feabbe6b70580 100644 --- a/contrib/cvs/src/prepend_args.h +++ b/contrib/cvs/src/prepend_args.h @@ -16,7 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/cvs/src/prepend_args.h,v 1.1 1999/12/04 01:23:26 obrien Exp $ */ /* This code, taken from GNU Grep, originally used the "PARAM" macro, as the current GNU coding standards requires. Older GNU code used the "PROTO" diff --git a/contrib/cvs/src/rcs.c b/contrib/cvs/src/rcs.c index 48be8e5ccb0a6..a2d192101b7d2 100644 --- a/contrib/cvs/src/rcs.c +++ b/contrib/cvs/src/rcs.c @@ -7,7 +7,7 @@ * The routines contained in this file do all the rcs file parsing and * manipulation * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/rcs.c,v 1.19 1999/12/11 13:19:17 peter Exp $ */ #include diff --git a/contrib/cvs/src/rcs.h b/contrib/cvs/src/rcs.h index 7aee90ac61ae2..1d8ea8742e1f6 100644 --- a/contrib/cvs/src/rcs.h +++ b/contrib/cvs/src/rcs.h @@ -7,7 +7,7 @@ * * RCS source control definitions needed by rcs.c and friends * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/rcs.h,v 1.7 1999/12/11 12:50:09 peter Exp $ */ /* String which indicates a conflict if it occurs at the start of a line. */ diff --git a/contrib/cvs/src/rcscmds.c b/contrib/cvs/src/rcscmds.c index bcdffd5ad3125..a6b742237a5a5 100644 --- a/contrib/cvs/src/rcscmds.c +++ b/contrib/cvs/src/rcscmds.c @@ -8,7 +8,7 @@ * The functions in this file provide an interface for performing * operations directly on RCS files. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/rcscmds.c,v 1.7 1999/12/11 12:50:09 peter Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/recurse.c b/contrib/cvs/src/recurse.c index 209d324e44a7b..89ac5a19871ad 100644 --- a/contrib/cvs/src/recurse.c +++ b/contrib/cvs/src/recurse.c @@ -6,7 +6,7 @@ * * General recursion handler * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/recurse.c,v 1.6 1999/12/11 12:50:09 peter Exp $ */ #include "cvs.h" diff --git a/contrib/cvs/src/server.c b/contrib/cvs/src/server.c index 63fef8c74f0ce..ec2eac1f535d2 100644 --- a/contrib/cvs/src/server.c +++ b/contrib/cvs/src/server.c @@ -9,7 +9,7 @@ GNU General Public License for more details. */ /* - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/server.c,v 1.13 1999/12/11 12:50:09 peter Exp $ */ #include diff --git a/contrib/cvs/src/update.c b/contrib/cvs/src/update.c index 89e8323b91446..6572b29e99c97 100644 --- a/contrib/cvs/src/update.c +++ b/contrib/cvs/src/update.c @@ -32,7 +32,7 @@ * directories added to the repository are automatically created and updated * as well. * - * $FreeBSD$ + * $FreeBSD: src/contrib/cvs/src/update.c,v 1.6 1999/12/11 12:50:10 peter Exp $ */ #include "cvs.h" diff --git a/contrib/diff/diff.c b/contrib/diff/diff.c index 2b2eec0236f20..2e8f5c660b084 100644 --- a/contrib/diff/diff.c +++ b/contrib/diff/diff.c @@ -20,7 +20,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ /* GNU DIFF was written by Mike Haertel, David Hayes, Richard Stallman, Len Tower, and Paul Eggert. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/diff/diff.c,v 1.3 1999/11/26 02:51:44 obrien Exp $ */ #define GDIFF_MAIN #include "diff.h" diff --git a/contrib/diff/prepend_args.c b/contrib/diff/prepend_args.c index 27f6da47403fc..5bd7dfe926694 100644 --- a/contrib/diff/prepend_args.c +++ b/contrib/diff/prepend_args.c @@ -16,7 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/diff/prepend_args.c,v 1.1 1999/11/26 02:51:44 obrien Exp $ */ #ifdef HAVE_CONFIG_H diff --git a/contrib/diff/prepend_args.h b/contrib/diff/prepend_args.h index 3f72cc2fd1120..a46de62ff1ebe 100644 --- a/contrib/diff/prepend_args.h +++ b/contrib/diff/prepend_args.h @@ -16,6 +16,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/diff/prepend_args.h,v 1.1 1999/11/26 02:51:44 obrien Exp $ */ void prepend_default_options PARAMS ((char const *, int *, char ***)); diff --git a/contrib/gcc/INSTALL b/contrib/gcc/INSTALL new file mode 100644 index 0000000000000..a7c63d57de89b --- /dev/null +++ b/contrib/gcc/INSTALL @@ -0,0 +1,2188 @@ +This is Info file INSTALL, produced by Makeinfo version 1.68 from the +input file install1.texi. + + This file documents the installation of the GNU compiler. Copyright +(C) 1988, 1989, 1992, 1994, 1995 Free Software Foundation, Inc. You +may copy, distribute, and modify it freely as long as you preserve this +copyright notice and permission notice. + + +File: INSTALL, Node: Installation, Up: (dir) + +Installing GNU CC +***************** + + Note most of this information is out of date and superceded by the +EGCS install procedures. It is provided for historical reference only. + +* Menu: + +* Configurations:: Configurations Supported by GNU CC. +* Other Dir:: Compiling in a separate directory (not where the source is). +* Cross-Compiler:: Building and installing a cross-compiler. +* Sun Install:: See below for installation on the Sun. +* VMS Install:: See below for installation on VMS. +* Collect2:: How `collect2' works; how it finds `ld'. +* Header Dirs:: Understanding the standard header file directories. + + Here is the procedure for installing GNU CC on a Unix system. See +*Note VMS Install::, for VMS systems. In this section we assume you +compile in the same directory that contains the source files; see *Note +Other Dir::, to find out how to compile in a separate directory on Unix +systems. + + You cannot install GNU C by itself on MSDOS; it will not compile +under any MSDOS compiler except itself. You need to get the complete +compilation package DJGPP, which includes binaries as well as sources, +and includes all the necessary compilation tools and libraries. + + 1. If you have built GNU CC previously in the same directory for a + different target machine, do `make distclean' to delete all files + that might be invalid. One of the files this deletes is + `Makefile'; if `make distclean' complains that `Makefile' does not + exist, it probably means that the directory is already suitably + clean. + + 2. On a System V release 4 system, make sure `/usr/bin' precedes + `/usr/ucb' in `PATH'. The `cc' command in `/usr/ucb' uses + libraries which have bugs. + + 3. Specify the host, build and target machine configurations. You do + this by running the file `configure'. + + The "build" machine is the system which you are using, the "host" + machine is the system where you want to run the resulting compiler + (normally the build machine), and the "target" machine is the + system for which you want the compiler to generate code. + + If you are building a compiler to produce code for the machine it + runs on (a native compiler), you normally do not need to specify + any operands to `configure'; it will try to guess the type of + machine you are on and use that as the build, host and target + machines. So you don't need to specify a configuration when + building a native compiler unless `configure' cannot figure out + what your configuration is or guesses wrong. + + In those cases, specify the build machine's "configuration name" + with the `--host' option; the host and target will default to be + the same as the host machine. (If you are building a + cross-compiler, see *Note Cross-Compiler::.) + + Here is an example: + + ./configure --host=sparc-sun-sunos4.1 + + A configuration name may be canonical or it may be more or less + abbreviated. + + A canonical configuration name has three parts, separated by + dashes. It looks like this: `CPU-COMPANY-SYSTEM'. (The three + parts may themselves contain dashes; `configure' can figure out + which dashes serve which purpose.) For example, + `m68k-sun-sunos4.1' specifies a Sun 3. + + You can also replace parts of the configuration by nicknames or + aliases. For example, `sun3' stands for `m68k-sun', so + `sun3-sunos4.1' is another way to specify a Sun 3. You can also + use simply `sun3-sunos', since the version of SunOS is assumed by + default to be version 4. + + You can specify a version number after any of the system types, + and some of the CPU types. In most cases, the version is + irrelevant, and will be ignored. So you might as well specify the + version if you know it. + + See *Note Configurations::, for a list of supported configuration + names and notes on many of the configurations. You should check + the notes in that section before proceeding any further with the + installation of GNU CC. + + There are four additional options you can specify independently to + describe variant hardware and software configurations. These are + `--with-gnu-as', `--with-gnu-ld', `--with-stabs' and `--nfp'. + + `--with-gnu-as' + If you will use GNU CC with the GNU assembler (GAS), you + should declare this by using the `--with-gnu-as' option when + you run `configure'. + + Using this option does not install GAS. It only modifies the + output of GNU CC to work with GAS. Building and installing + GAS is up to you. + + Conversely, if you *do not* wish to use GAS and do not specify + `--with-gnu-as' when building GNU CC, it is up to you to make + sure that GAS is not installed. GNU CC searches for a + program named `as' in various directories; if the program it + finds is GAS, then it runs GAS. If you are not sure where + GNU CC finds the assembler it is using, try specifying `-v' + when you run it. + + The systems where it makes a difference whether you use GAS + are + `hppa1.0-ANY-ANY', `hppa1.1-ANY-ANY', `i386-ANY-sysv', + `i386-ANY-isc', + `i860-ANY-bsd', `m68k-bull-sysv', + `m68k-hp-hpux', `m68k-sony-bsd', + `m68k-altos-sysv', `m68000-hp-hpux', + `m68000-att-sysv', `ANY-lynx-lynxos', and `mips-ANY'). On + any other system, `--with-gnu-as' has no effect. + + On the systems listed above (except for the HP-PA, for ISC on + the 386, and for `mips-sgi-irix5.*'), if you use GAS, you + should also use the GNU linker (and specify `--with-gnu-ld'). + + `--with-gnu-ld' + Specify the option `--with-gnu-ld' if you plan to use the GNU + linker with GNU CC. + + This option does not cause the GNU linker to be installed; it + just modifies the behavior of GNU CC to work with the GNU + linker. + + `--with-stabs' + On MIPS based systems and on Alphas, you must specify whether + you want GNU CC to create the normal ECOFF debugging format, + or to use BSD-style stabs passed through the ECOFF symbol + table. The normal ECOFF debug format cannot fully handle + languages other than C. BSD stabs format can handle other + languages, but it only works with the GNU debugger GDB. + + Normally, GNU CC uses the ECOFF debugging format by default; + if you prefer BSD stabs, specify `--with-stabs' when you + configure GNU CC. + + No matter which default you choose when you configure GNU CC, + the user can use the `-gcoff' and `-gstabs+' options to + specify explicitly the debug format for a particular + compilation. + + `--with-stabs' is meaningful on the ISC system on the 386, + also, if `--with-gas' is used. It selects use of stabs + debugging information embedded in COFF output. This kind of + debugging information supports C++ well; ordinary COFF + debugging information does not. + + `--with-stabs' is also meaningful on 386 systems running + SVR4. It selects use of stabs debugging information embedded + in ELF output. The C++ compiler currently (2.6.0) does not + support the DWARF debugging information normally used on 386 + SVR4 platforms; stabs provide a workable alternative. This + requires gas and gdb, as the normal SVR4 tools can not + generate or interpret stabs. + + `--nfp' + On certain systems, you must specify whether the machine has + a floating point unit. These systems include + `m68k-sun-sunosN' and `m68k-isi-bsd'. On any other system, + `--nfp' currently has no effect, though perhaps there are + other systems where it could usefully make a difference. + + `--enable-haifa' + `--disable-haifa' + Use `--enable-haifa' to enable use of an experimental + instruction scheduler (from IBM Haifa). This may or may not + produce better code. Some targets on which it is known to be + a win enable it by default; use `--disable-haifa' to disable + it in these cases. `configure' will print out whether the + Haifa scheduler is enabled when it is run. + + `--enable-threads=TYPE' + Certain systems, notably Linux-based GNU systems, can't be + relied on to supply a threads facility for the Objective C + runtime and so will default to single-threaded runtime. They + may, however, have a library threads implementation + available, in which case threads can be enabled with this + option by supplying a suitable TYPE, probably `posix'. The + possibilities for TYPE are `single', `posix', `win32', + `solaris', `irix' and `mach'. + + `--enable-checking' + When you specify this option, the compiler is built to + perform checking of tree node types when referencing fields + of that node. This does not change the generated code, but + adds error checking within the compiler. This will slow down + the compiler and may only work properly if you are building + the compiler with GNU C. + + The `configure' script searches subdirectories of the source + directory for other compilers that are to be integrated into GNU + CC. The GNU compiler for C++, called G++ is in a subdirectory + named `cp'. `configure' inserts rules into `Makefile' to build + all of those compilers. + + Here we spell out what files will be set up by `configure'. + Normally you need not be concerned with these files. + + * A file named `config.h' is created that contains a `#include' + of the top-level config file for the machine you will run the + compiler on (*note The Configuration File: + (gcc.info)Config.). This file is responsible for defining + information about the host machine. It includes `tm.h'. + + The top-level config file is located in the subdirectory + `config'. Its name is always `xm-SOMETHING.h'; usually + `xm-MACHINE.h', but there are some exceptions. + + If your system does not support symbolic links, you might + want to set up `config.h' to contain a `#include' command + which refers to the appropriate file. + + * A file named `tconfig.h' is created which includes the + top-level config file for your target machine. This is used + for compiling certain programs to run on that machine. + + * A file named `tm.h' is created which includes the + machine-description macro file for your target machine. It + should be in the subdirectory `config' and its name is often + `MACHINE.h'. + + * The command file `configure' also constructs the file + `Makefile' by adding some text to the template file + `Makefile.in'. The additional text comes from files in the + `config' directory, named `t-TARGET' and `x-HOST'. If these + files do not exist, it means nothing needs to be added for a + given target or host. + + 4. The standard directory for installing GNU CC is `/usr/local/lib'. + If you want to install its files somewhere else, specify + `--prefix=DIR' when you run `configure'. Here DIR is a directory + name to use instead of `/usr/local' for all purposes with one + exception: the directory `/usr/local/include' is searched for + header files no matter where you install the compiler. To override + this name, use the `--with-local-prefix' option below. The + directory you specify need not exist, but its parent directory + must exist. + + 5. Specify `--with-local-prefix=DIR' if you want the compiler to + search directory `DIR/include' for locally installed header files + *instead* of `/usr/local/include'. + + You should specify `--with-local-prefix' *only* if your site has a + different convention (not `/usr/local') for where to put + site-specific files. + + The default value for `--with-local-prefix' is `/usr/local' + regardless of the value of `--prefix'. Specifying `--prefix' has + no effect on which directory GNU CC searches for local header + files. This may seem counterintuitive, but actually it is logical. + + The purpose of `--prefix' is to specify where to *install GNU CC*. + The local header files in `/usr/local/include'--if you put any in + that directory--are not part of GNU CC. They are part of other + programs--perhaps many others. (GNU CC installs its own header + files in another directory which is based on the `--prefix' value.) + + *Do not* specify `/usr' as the `--with-local-prefix'! The + directory you use for `--with-local-prefix' *must not* contain any + of the system's standard header files. If it did contain them, + certain programs would be miscompiled (including GNU Emacs, on + certain targets), because this would override and nullify the + header file corrections made by the `fixincludes' script. + + Indications are that people who use this option use it based on + mistaken ideas of what it is for. People use it as if it specified + where to install part of GNU CC. Perhaps they make this assumption + because installing GNU CC creates the directory. + + 6. Make sure the Bison parser generator is installed. (This is + unnecessary if the Bison output files `c-parse.c' and `cexp.c' are + more recent than `c-parse.y' and `cexp.y' and you do not plan to + change the `.y' files.) + + Bison versions older than Sept 8, 1988 will produce incorrect + output for `c-parse.c'. + + 7. If you have chosen a configuration for GNU CC which requires other + GNU tools (such as GAS or the GNU linker) instead of the standard + system tools, install the required tools in the build directory + under the names `as', `ld' or whatever is appropriate. This will + enable the compiler to find the proper tools for compilation of + the program `enquire'. + + Alternatively, you can do subsequent compilation using a value of + the `PATH' environment variable such that the necessary GNU tools + come before the standard system tools. + + 8. Build the compiler. Just type `make LANGUAGES=c' in the compiler + directory. + + `LANGUAGES=c' specifies that only the C compiler should be + compiled. The makefile normally builds compilers for all the + supported languages; currently, C, C++ and Objective C. However, + C is the only language that is sure to work when you build with + other non-GNU C compilers. In addition, building anything but C + at this stage is a waste of time. + + In general, you can specify the languages to build by typing the + argument `LANGUAGES="LIST"', where LIST is one or more words from + the list `c', `c++', and `objective-c'. If you have any + additional GNU compilers as subdirectories of the GNU CC source + directory, you may also specify their names in this list. + + Ignore any warnings you may see about "statement not reached" in + `insn-emit.c'; they are normal. Also, warnings about "unknown + escape sequence" are normal in `genopinit.c' and perhaps some + other files. Likewise, you should ignore warnings about "constant + is so large that it is unsigned" in `insn-emit.c' and + `insn-recog.c', a warning about a comparison always being zero in + `enquire.o', and warnings about shift counts exceeding type widths + in `cexp.y'. Any other compilation errors may represent bugs in + the port to your machine or operating system, and should be + investigated and reported. + + Some commercial compilers fail to compile GNU CC because they have + bugs or limitations. For example, the Microsoft compiler is said + to run out of macro space. Some Ultrix compilers run out of + expression space; then you need to break up the statement where + the problem happens. + + 9. If you are building a cross-compiler, stop here. *Note + Cross-Compiler::. + + 10. Move the first-stage object files and executables into a + subdirectory with this command: + + make stage1 + + The files are moved into a subdirectory named `stage1'. Once + installation is complete, you may wish to delete these files with + `rm -r stage1'. + + 11. If you have chosen a configuration for GNU CC which requires other + GNU tools (such as GAS or the GNU linker) instead of the standard + system tools, install the required tools in the `stage1' + subdirectory under the names `as', `ld' or whatever is + appropriate. This will enable the stage 1 compiler to find the + proper tools in the following stage. + + Alternatively, you can do subsequent compilation using a value of + the `PATH' environment variable such that the necessary GNU tools + come before the standard system tools. + + 12. Recompile the compiler with itself, with this command: + + make CC="stage1/xgcc -Bstage1/" CFLAGS="-g -O2" + + This is called making the stage 2 compiler. + + The command shown above builds compilers for all the supported + languages. If you don't want them all, you can specify the + languages to build by typing the argument `LANGUAGES="LIST"'. LIST + should contain one or more words from the list `c', `c++', + `objective-c', and `proto'. Separate the words with spaces. + `proto' stands for the programs `protoize' and `unprotoize'; they + are not a separate language, but you use `LANGUAGES' to enable or + disable their installation. + + If you are going to build the stage 3 compiler, then you might + want to build only the C language in stage 2. + + Once you have built the stage 2 compiler, if you are short of disk + space, you can delete the subdirectory `stage1'. + + On a 68000 or 68020 system lacking floating point hardware, unless + you have selected a `tm.h' file that expects by default that there + is no such hardware, do this instead: + + make CC="stage1/xgcc -Bstage1/" CFLAGS="-g -O2 -msoft-float" + + 13. If you wish to test the compiler by compiling it with itself one + more time, install any other necessary GNU tools (such as GAS or + the GNU linker) in the `stage2' subdirectory as you did in the + `stage1' subdirectory, then do this: + + make stage2 + make CC="stage2/xgcc -Bstage2/" CFLAGS="-g -O2" + + This is called making the stage 3 compiler. Aside from the `-B' + option, the compiler options should be the same as when you made + the stage 2 compiler. But the `LANGUAGES' option need not be the + same. The command shown above builds compilers for all the + supported languages; if you don't want them all, you can specify + the languages to build by typing the argument `LANGUAGES="LIST"', + as described above. + + If you do not have to install any additional GNU tools, you may + use the command + + make bootstrap LANGUAGES=LANGUAGE-LIST BOOT_CFLAGS=OPTION-LIST + + instead of making `stage1', `stage2', and performing the two + compiler builds. + + 14. Then compare the latest object files with the stage 2 object + files--they ought to be identical, aside from time stamps (if any). + + On some systems, meaningful comparison of object files is + impossible; they always appear "different." This is currently + true on Solaris and some systems that use ELF object file format. + On some versions of Irix on SGI machines and DEC Unix (OSF/1) on + Alpha systems, you will not be able to compare the files without + specifying `-save-temps'; see the description of individual + systems above to see if you get comparison failures. You may have + similar problems on other systems. + + Use this command to compare the files: + + make compare + + This will mention any object files that differ between stage 2 and + stage 3. Any difference, no matter how innocuous, indicates that + the stage 2 compiler has compiled GNU CC incorrectly, and is + therefore a potentially serious bug which you should investigate + and report. + + If your system does not put time stamps in the object files, then + this is a faster way to compare them (using the Bourne shell): + + for file in *.o; do + cmp $file stage2/$file + done + + If you have built the compiler with the `-mno-mips-tfile' option on + MIPS machines, you will not be able to compare the files. + + 15. Install the compiler driver, the compiler's passes and run-time + support with `make install'. Use the same value for `CC', + `CFLAGS' and `LANGUAGES' that you used when compiling the files + that are being installed. One reason this is necessary is that + some versions of Make have bugs and recompile files gratuitously + when you do this step. If you use the same variable values, those + files will be recompiled properly. + + For example, if you have built the stage 2 compiler, you can use + the following command: + + make install CC="stage2/xgcc -Bstage2/" CFLAGS="-g -O" LANGUAGES="LIST" + + This copies the files `cc1', `cpp' and `libgcc.a' to files `cc1', + `cpp' and `libgcc.a' in the directory + `/usr/local/lib/gcc-lib/TARGET/VERSION', which is where the + compiler driver program looks for them. Here TARGET is the + canonicalized form of target machine type specified when you ran + `configure', and VERSION is the version number of GNU CC. This + naming scheme permits various versions and/or cross-compilers to + coexist. It also copies the executables for compilers for other + languages (e.g., `cc1plus' for C++) to the same directory. + + This also copies the driver program `xgcc' into + `/usr/local/bin/gcc', so that it appears in typical execution + search paths. It also copies `gcc.1' into `/usr/local/man/man1' + and info pages into `/usr/local/info'. + + On some systems, this command causes recompilation of some files. + This is usually due to bugs in `make'. You should either ignore + this problem, or use GNU Make. + + *Warning: there is a bug in `alloca' in the Sun library. To avoid + this bug, be sure to install the executables of GNU CC that were + compiled by GNU CC. (That is, the executables from stage 2 or 3, + not stage 1.) They use `alloca' as a built-in function and never + the one in the library.* + + (It is usually better to install GNU CC executables from stage 2 + or 3, since they usually run faster than the ones compiled with + some other compiler.) + + 16. If you're going to use C++, it's likely that you need to also + install a C++ runtime library. Just as GNU C does not distribute + a C runtime library, it also does not include a C++ runtime + library. All I/O functionality, special class libraries, etc., are + provided by the C++ runtime library. + + The standard C++ runtime library for GNU CC is called `libstdc++'. + An obsolescent library `libg++' may also be available, but it's + necessary only for older software that hasn't been converted yet; + if you don't know whether you need `libg++' then you probably don't + need it. + + Here's one way to build and install `libstdc++' for GNU CC: + + * Build and install GNU CC, so that invoking `gcc' obtains the + GNU CC that was just built. + + * Obtain a copy of a compatible `libstdc++' distribution. For + example, the `libstdc++-2.8.0.tar.gz' distribution should be + compatible with GCC 2.8.0. GCC distributors normally + distribute `libstdc++' as well. + + * Set the `CXX' environment variable to `gcc' while running the + `libstdc++' distribution's `configure' command. Use the same + `configure' options that you used when you invoked GCC's + `configure' command. + + * Invoke `make' to build the C++ runtime. + + * Invoke `make install' to install the C++ runtime. + + To summarize, after building and installing GNU CC, invoke the + following shell commands in the topmost directory of the C++ + library distribution. For CONFIGURE-OPTIONS, use the same options + that you used to configure GNU CC. + + $ CXX=gcc ./configure CONFIGURE-OPTIONS + $ make + $ make install + + 17. GNU CC includes a runtime library for Objective-C because it is an + integral part of the language. You can find the files associated + with the library in the subdirectory `objc'. The GNU Objective-C + Runtime Library requires header files for the target's C library in + order to be compiled,and also requires the header files for the + target's thread library if you want thread support. *Note + Cross-Compilers and Header Files: Cross Headers, for discussion + about header files issues for cross-compilation. + + When you run `configure', it picks the appropriate Objective-C + thread implementation file for the target platform. In some + situations, you may wish to choose a different back-end as some + platforms support multiple thread implementations or you may wish + to disable thread support completely. You do this by specifying a + value for the OBJC_THREAD_FILE makefile variable on the command + line when you run make, for example: + + make CC="stage2/xgcc -Bstage2/" CFLAGS="-g -O2" OBJC_THREAD_FILE=thr-single + + Below is a list of the currently available back-ends. + + * thr-single Disable thread support, should work for all + platforms. + + * thr-decosf1 DEC OSF/1 thread support. + + * thr-irix SGI IRIX thread support. + + * thr-mach Generic MACH thread support, known to work on + NEXTSTEP. + + * thr-os2 IBM OS/2 thread support. + + * thr-posix Generix POSIX thread support. + + * thr-pthreads PCThreads on Linux-based GNU systems. + + * thr-solaris SUN Solaris thread support. + + * thr-win32 Microsoft Win32 API thread support. + + +File: INSTALL, Node: Configurations, Next: Other Dir, Up: Installation + +Configurations Supported by GNU CC +================================== + + Here are the possible CPU types: + + 1750a, a29k, alpha, arm, cN, clipper, dsp16xx, elxsi, h8300, + hppa1.0, hppa1.1, i370, i386, i486, i586, i860, i960, m32r, + m68000, m68k, m88k, mips, mipsel, mips64, mips64el, ns32k, + powerpc, powerpcle, pyramid, romp, rs6000, sh, sparc, sparclite, + sparc64, vax, we32k. + + Here are the recognized company names. As you can see, customary +abbreviations are used rather than the longer official names. + + acorn, alliant, altos, apollo, apple, att, bull, cbm, convergent, + convex, crds, dec, dg, dolphin, elxsi, encore, harris, hitachi, + hp, ibm, intergraph, isi, mips, motorola, ncr, next, ns, omron, + plexus, sequent, sgi, sony, sun, tti, unicom, wrs. + + The company name is meaningful only to disambiguate when the rest of +the information supplied is insufficient. You can omit it, writing +just `CPU-SYSTEM', if it is not needed. For example, `vax-ultrix4.2' +is equivalent to `vax-dec-ultrix4.2'. + + Here is a list of system types: + + 386bsd, aix, acis, amigaos, aos, aout, aux, bosx, bsd, clix, coff, + ctix, cxux, dgux, dynix, ebmon, ecoff, elf, esix, freebsd, hms, + genix, gnu, linux-gnu, hiux, hpux, iris, irix, isc, luna, lynxos, + mach, minix, msdos, mvs, netbsd, newsos, nindy, ns, osf, osfrose, + ptx, riscix, riscos, rtu, sco, sim, solaris, sunos, sym, sysv, + udi, ultrix, unicos, uniplus, unos, vms, vsta, vxworks, winnt, + xenix. + +You can omit the system type; then `configure' guesses the operating +system from the CPU and company. + + You can add a version number to the system type; this may or may not +make a difference. For example, you can write `bsd4.3' or `bsd4.4' to +distinguish versions of BSD. In practice, the version number is most +needed for `sysv3' and `sysv4', which are often treated differently. + + If you specify an impossible combination such as `i860-dg-vms', then +you may get an error message from `configure', or it may ignore part of +the information and do the best it can with the rest. `configure' +always prints the canonical name for the alternative that it used. GNU +CC does not support all possible alternatives. + + Often a particular model of machine has a name. Many machine names +are recognized as aliases for CPU/company combinations. Thus, the +machine name `sun3', mentioned above, is an alias for `m68k-sun'. +Sometimes we accept a company name as a machine name, when the name is +popularly used for a particular machine. Here is a table of the known +machine names: + + 3300, 3b1, 3bN, 7300, altos3068, altos, apollo68, att-7300, + balance, convex-cN, crds, decstation-3100, decstation, delta, + encore, fx2800, gmicro, hp7NN, hp8NN, hp9k2NN, hp9k3NN, hp9k7NN, + hp9k8NN, iris4d, iris, isi68, m3230, magnum, merlin, miniframe, + mmax, news-3600, news800, news, next, pbd, pc532, pmax, powerpc, + powerpcle, ps2, risc-news, rtpc, sun2, sun386i, sun386, sun3, + sun4, symmetry, tower-32, tower. + +Remember that a machine name specifies both the cpu type and the company +name. If you want to install your own homemade configuration files, +you can use `local' as the company name to access them. If you use +configuration `CPU-local', the configuration name without the cpu prefix +is used to form the configuration file names. + + Thus, if you specify `m68k-local', configuration uses files +`m68k.md', `local.h', `m68k.c', `xm-local.h', `t-local', and `x-local', +all in the directory `config/m68k'. + + Here is a list of configurations that have special treatment or +special things you must know: + +`1750a-*-*' + MIL-STD-1750A processors. + + The MIL-STD-1750A cross configuration produces output for + `as1750', an assembler/linker available under the GNU Public + License for the 1750A. `as1750' can be obtained at + *ftp://ftp.fta-berlin.de/pub/crossgcc/1750gals/*. A similarly + licensed simulator for the 1750A is available from same address. + + You should ignore a fatal error during the building of libgcc + (libgcc is not yet implemented for the 1750A.) + + The `as1750' assembler requires the file `ms1750.inc', which is + found in the directory `config/1750a'. + + GNU CC produced the same sections as the Fairchild F9450 C + Compiler, namely: + + `Normal' + The program code section. + + `Static' + The read/write (RAM) data section. + + `Konst' + The read-only (ROM) constants section. + + `Init' + Initialization section (code to copy KREL to SREL). + + The smallest addressable unit is 16 bits (BITS_PER_UNIT is 16). + This means that type `char' is represented with a 16-bit word per + character. The 1750A's "Load/Store Upper/Lower Byte" instructions + are not used by GNU CC. + +`alpha-*-osf1' + Systems using processors that implement the DEC Alpha architecture + and are running the DEC Unix (OSF/1) operating system, for example + the DEC Alpha AXP systems.CC.) + + GNU CC writes a `.verstamp' directive to the assembler output file + unless it is built as a cross-compiler. It gets the version to + use from the system header file `/usr/include/stamp.h'. If you + install a new version of DEC Unix, you should rebuild GCC to pick + up the new version stamp. + + Note that since the Alpha is a 64-bit architecture, + cross-compilers from 32-bit machines will not generate code as + efficient as that generated when the compiler is running on a + 64-bit machine because many optimizations that depend on being + able to represent a word on the target in an integral value on the + host cannot be performed. Building cross-compilers on the Alpha + for 32-bit machines has only been tested in a few cases and may + not work properly. + + `make compare' may fail on old versions of DEC Unix unless you add + `-save-temps' to `CFLAGS'. On these systems, the name of the + assembler input file is stored in the object file, and that makes + comparison fail if it differs between the `stage1' and `stage2' + compilations. The option `-save-temps' forces a fixed name to be + used for the assembler input file, instead of a randomly chosen + name in `/tmp'. Do not add `-save-temps' unless the comparisons + fail without that option. If you add `-save-temps', you will have + to manually delete the `.i' and `.s' files after each series of + compilations. + + GNU CC now supports both the native (ECOFF) debugging format used + by DBX and GDB and an encapsulated STABS format for use only with + GDB. See the discussion of the `--with-stabs' option of + `configure' above for more information on these formats and how to + select them. + + There is a bug in DEC's assembler that produces incorrect line + numbers for ECOFF format when the `.align' directive is used. To + work around this problem, GNU CC will not emit such alignment + directives while writing ECOFF format debugging information even + if optimization is being performed. Unfortunately, this has the + very undesirable side-effect that code addresses when `-O' is + specified are different depending on whether or not `-g' is also + specified. + + To avoid this behavior, specify `-gstabs+' and use GDB instead of + DBX. DEC is now aware of this problem with the assembler and + hopes to provide a fix shortly. + +`arc-*-elf' + Argonaut ARC processor. This configuration is intended for + embedded systems. + +`arm-*-aout' + Advanced RISC Machines ARM-family processors. These are often + used in embedded applications. There are no standard Unix + configurations. This configuration corresponds to the basic + instruction sequences and will produce `a.out' format object + modules. + + You may need to make a variant of the file `arm.h' for your + particular configuration. + +`arm-*-linuxaout' + Any of the ARM family processors running the Linux-based GNU + system with the `a.out' binary format (ELF is not yet supported). + You must use version 2.8.1.0.7 or later of the GNU/Linux binutils, + which you can download from `sunsite.unc.edu:/pub/Linux/GCC' and + other mirror sites for Linux-based GNU systems. + +`arm-*-riscix' + The ARM2 or ARM3 processor running RISC iX, Acorn's port of BSD + Unix. If you are running a version of RISC iX prior to 1.2 then + you must specify the version number during configuration. Note + that the assembler shipped with RISC iX does not support stabs + debugging information; a new version of the assembler, with stabs + support included, is now available from Acorn and via ftp + `ftp.acorn.com:/pub/riscix/as+xterm.tar.Z'. To enable stabs + debugging, pass `--with-gnu-as' to configure. + + You will need to install GNU `sed' before you can run configure. + +`a29k' + AMD Am29k-family processors. These are normally used in embedded + applications. There are no standard Unix configurations. This + configuration corresponds to AMD's standard calling sequence and + binary interface and is compatible with other 29k tools. + + You may need to make a variant of the file `a29k.h' for your + particular configuration. + +`a29k-*-bsd' + AMD Am29050 used in a system running a variant of BSD Unix. + +`decstation-*' + MIPS-based DECstations can support three different personalities: + Ultrix, DEC OSF/1, and OSF/rose. (Alpha-based DECstation products + have a configuration name beginning with `alpha-dec'.) To + configure GCC for these platforms use the following configurations: + + `decstation-ultrix' + Ultrix configuration. + + `decstation-osf1' + Dec's version of OSF/1. + + `decstation-osfrose' + Open Software Foundation reference port of OSF/1 which uses + the OSF/rose object file format instead of ECOFF. Normally, + you would not select this configuration. + + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + +`elxsi-elxsi-bsd' + The Elxsi's C compiler has known limitations that prevent it from + compiling GNU C. Please contact `mrs@cygnus.com' for more details. + +`dsp16xx' + A port to the AT&T DSP1610 family of processors. + +`h8300-*-*' + Hitachi H8/300 series of processors. + + The calling convention and structure layout has changed in release + 2.6. All code must be recompiled. The calling convention now + passes the first three arguments in function calls in registers. + Structures are no longer a multiple of 2 bytes. + +`hppa*-*-*' + There are several variants of the HP-PA processor which run a + variety of operating systems. GNU CC must be configured to use + the correct processor type and operating system, or GNU CC will + not function correctly. The easiest way to handle this problem is + to *not* specify a target when configuring GNU CC, the `configure' + script will try to automatically determine the right processor + type and operating system. + + `-g' does not work on HP-UX, since that system uses a peculiar + debugging format which GNU CC does not know about. However, `-g' + will work if you also use GAS and GDB in conjunction with GCC. We + highly recommend using GAS for all HP-PA configurations. + + You should be using GAS-2.6 (or later) along with GDB-4.16 (or + later). These can be retrieved from all the traditional GNU ftp + archive sites. + + On some versions of HP-UX, you will need to install GNU `sed'. + + You will need to be install GAS into a directory before `/bin', + `/usr/bin', and `/usr/ccs/bin' in your search path. You should + install GAS before you build GNU CC. + + To enable debugging, you must configure GNU CC with the + `--with-gnu-as' option before building. + +`i370-*-*' + This port is very preliminary and has many known bugs. We hope to + have a higher-quality port for this machine soon. + +`i386-*-linux-gnuoldld' + Use this configuration to generate `a.out' binaries on Linux-based + GNU systems if you do not have gas/binutils version 2.5.2 or later + installed. This is an obsolete configuration. + +`i386-*-linux-gnuaout' + Use this configuration to generate `a.out' binaries on Linux-based + GNU systems. This configuration is being superseded. You must use + gas/binutils version 2.5.2 or later. + +`i386-*-linux-gnu' + Use this configuration to generate ELF binaries on Linux-based GNU + systems. You must use gas/binutils version 2.5.2 or later. + +`i386-*-sco' + Compilation with RCC is recommended. Also, it may be a good idea + to link with GNU malloc instead of the malloc that comes with the + system. + +`i386-*-sco3.2v4' + Use this configuration for SCO release 3.2 version 4. + +`i386-*-sco3.2v5*' + Use this for the SCO OpenServer Release family including 5.0.0, + 5.0.2, 5.0.4, 5.0.5, Internet FastStart 1.0, and Internet + FastStart 1.1. + + GNU CC can generate COFF binaries if you specify `-mcoff' or ELF + binaries, the default. A full `make bootstrap' is recommended + so that an ELF compiler that builds ELF is generated. + + You must have TLS597 from `ftp://ftp.sco.com/TLS' installed for ELF + C++ binaries to work correctly on releases before 5.0.4. + + The native SCO assembler that is provided with the OS at no charge + is normally required. If, however, you must be able to use the GNU + assembler (perhaps you have complex asms) you must configure this + package `--with-gnu-as'. To do this, install (cp or symlink) + gcc/as to your copy of the GNU assembler. You must use a recent + version of GNU binutils; version 2.9.1 seems to work well. If you + select this option, you will be unable to build COFF images. + Trying to do so will result in non-obvious failures. In general, + the "-with-gnu-as" option isn't as well tested as the native + assembler. + + *NOTE:* If you are building C++, you must follow the instructions + about invoking `make bootstrap' because the native OpenServer + compiler may build a `cc1plus' that will not correctly parse many + valid C++ programs. You must do a `make bootstrap' if you are + building with the native compiler. + +`i386-*-isc' + It may be a good idea to link with GNU malloc instead of the + malloc that comes with the system. + + In ISC version 4.1, `sed' core dumps when building `deduced.h'. + Use the version of `sed' from version 4.0. + +`i386-*-esix' + It may be good idea to link with GNU malloc instead of the malloc + that comes with the system. + +`i386-ibm-aix' + You need to use GAS version 2.1 or later, and LD from GNU binutils + version 2.2 or later. + +`i386-sequent-bsd' + Go to the Berkeley universe before compiling. + +`i386-sequent-ptx1*' +`i386-sequent-ptx2*' + You must install GNU `sed' before running `configure'. + +`i386-sun-sunos4' + You may find that you need another version of GNU CC to begin + bootstrapping with, since the current version when built with the + system's own compiler seems to get an infinite loop compiling part + of `libgcc2.c'. GNU CC version 2 compiled with GNU CC (any + version) seems not to have this problem. + + See *Note Sun Install::, for information on installing GNU CC on + Sun systems. + +`i[345]86-*-winnt3.5' + This version requires a GAS that has not yet been released. Until + it is, you can get a prebuilt binary version via anonymous ftp from + `cs.washington.edu:pub/gnat' or `cs.nyu.edu:pub/gnat'. You must + also use the Microsoft header files from the Windows NT 3.5 SDK. + Find these on the CDROM in the `/mstools/h' directory dated + 9/4/94. You must use a fixed version of Microsoft linker made + especially for NT 3.5, which is also is available on the NT 3.5 + SDK CDROM. If you do not have this linker, can you also use the + linker from Visual C/C++ 1.0 or 2.0. + + Installing GNU CC for NT builds a wrapper linker, called `ld.exe', + which mimics the behaviour of Unix `ld' in the specification of + libraries (`-L' and `-l'). `ld.exe' looks for both Unix and + Microsoft named libraries. For example, if you specify `-lfoo', + `ld.exe' will look first for `libfoo.a' and then for `foo.lib'. + + You may install GNU CC for Windows NT in one of two ways, + depending on whether or not you have a Unix-like shell and various + Unix-like utilities. + + 1. If you do not have a Unix-like shell and few Unix-like + utilities, you will use a DOS style batch script called + `configure.bat'. Invoke it as `configure winnt' from an + MSDOS console window or from the program manager dialog box. + `configure.bat' assumes you have already installed and have + in your path a Unix-like `sed' program which is used to + create a working `Makefile' from `Makefile.in'. + + `Makefile' uses the Microsoft Nmake program maintenance + utility and the Visual C/C++ V8.00 compiler to build GNU CC. + You need only have the utilities `sed' and `touch' to use + this installation method, which only automatically builds the + compiler itself. You must then examine what `fixinc.winnt' + does, edit the header files by hand and build `libgcc.a' + manually. + + 2. The second type of installation assumes you are running a + Unix-like shell, have a complete suite of Unix-like utilities + in your path, and have a previous version of GNU CC already + installed, either through building it via the above + installation method or acquiring a pre-built binary. In this + case, use the `configure' script in the normal fashion. + +`i860-intel-osf1' + This is the Paragon. If you have version 1.0 of the operating + system, you need to take special steps to build GNU CC due to + peculiarities of the system. Newer system versions have no + problem. See the section `Installation Problems' in the GNU CC + Manual. + +`*-lynx-lynxos' + LynxOS 2.2 and earlier comes with GNU CC 1.x already installed as + `/bin/gcc'. You should compile with this instead of `/bin/cc'. + You can tell GNU CC to use the GNU assembler and linker, by + specifying `--with-gnu-as --with-gnu-ld' when configuring. These + will produce COFF format object files and executables; otherwise + GNU CC will use the installed tools, which produce `a.out' format + executables. + +`m32r-*-elf' + Mitsubishi M32R processor. This configuration is intended for + embedded systems. + +`m68000-hp-bsd' + HP 9000 series 200 running BSD. Note that the C compiler that + comes with this system cannot compile GNU CC; contact + `law@cygnus.com' to get binaries of GNU CC for bootstrapping. + +`m68k-altos' + Altos 3068. You must use the GNU assembler, linker and debugger. + Also, you must fix a kernel bug. Details in the file + `README.ALTOS'. + +`m68k-apple-aux' + Apple Macintosh running A/UX. You may configure GCC to use + either the system assembler and linker or the GNU assembler and + linker. You should use the GNU configuration if you can, + especially if you also want to use GNU C++. You enabled that + configuration with + the `--with-gnu-as' and `--with-gnu-ld' + options to `configure'. + + Note the C compiler that comes with this system cannot compile GNU + CC. You can find binaries of GNU CC for bootstrapping on + `jagubox.gsfc.nasa.gov'. You will also a patched version of + `/bin/ld' there that raises some of the arbitrary limits found in + the original. + +`m68k-att-sysv' + AT&T 3b1, a.k.a. 7300 PC. Special procedures are needed to + compile GNU CC with this machine's standard C compiler, due to + bugs in that compiler. You can bootstrap it more easily with + previous versions of GNU CC if you have them. + + Installing GNU CC on the 3b1 is difficult if you do not already + have GNU CC running, due to bugs in the installed C compiler. + However, the following procedure might work. We are unable to + test it. + + 1. Comment out the `#include "config.h"' line near the start of + `cccp.c' and do `make cpp'. This makes a preliminary version + of GNU cpp. + + 2. Save the old `/lib/cpp' and copy the preliminary GNU cpp to + that file name. + + 3. Undo your change in `cccp.c', or reinstall the original + version, and do `make cpp' again. + + 4. Copy this final version of GNU cpp into `/lib/cpp'. + + 5. Replace every occurrence of `obstack_free' in the file + `tree.c' with `_obstack_free'. + + 6. Run `make' to get the first-stage GNU CC. + + 7. Reinstall the original version of `/lib/cpp'. + + 8. Now you can compile GNU CC with itself and install it in the + normal fashion. + +`m68k-bull-sysv' + Bull DPX/2 series 200 and 300 with BOS-2.00.45 up to BOS-2.01. GNU + CC works either with native assembler or GNU assembler. You can use + GNU assembler with native coff generation by providing + `--with-gnu-as' to the configure script or use GNU assembler with + dbx-in-coff encapsulation by providing `--with-gnu-as --stabs'. + For any problem with native assembler or for availability of the + DPX/2 port of GAS, contact `F.Pierresteguy@frcl.bull.fr'. + +`m68k-crds-unox' + Use `configure unos' for building on Unos. + + The Unos assembler is named `casm' instead of `as'. For some + strange reason linking `/bin/as' to `/bin/casm' changes the + behavior, and does not work. So, when installing GNU CC, you + should install the following script as `as' in the subdirectory + where the passes of GCC are installed: + + #!/bin/sh + casm $* + + The default Unos library is named `libunos.a' instead of `libc.a'. + To allow GNU CC to function, either change all references to + `-lc' in `gcc.c' to `-lunos' or link `/lib/libc.a' to + `/lib/libunos.a'. + + When compiling GNU CC with the standard compiler, to overcome bugs + in the support of `alloca', do not use `-O' when making stage 2. + Then use the stage 2 compiler with `-O' to make the stage 3 + compiler. This compiler will have the same characteristics as the + usual stage 2 compiler on other systems. Use it to make a stage 4 + compiler and compare that with stage 3 to verify proper + compilation. + + (Perhaps simply defining `ALLOCA' in `x-crds' as described in the + comments there will make the above paragraph superfluous. Please + inform us of whether this works.) + + Unos uses memory segmentation instead of demand paging, so you + will need a lot of memory. 5 Mb is barely enough if no other + tasks are running. If linking `cc1' fails, try putting the object + files into a library and linking from that library. + +`m68k-hp-hpux' + HP 9000 series 300 or 400 running HP-UX. HP-UX version 8.0 has a + bug in the assembler that prevents compilation of GNU CC. To fix + it, get patch PHCO_4484 from HP. + + In addition, if you wish to use gas `--with-gnu-as' you must use + gas version 2.1 or later, and you must use the GNU linker version + 2.1 or later. Earlier versions of gas relied upon a program which + converted the gas output into the native HP-UX format, but that + program has not been kept up to date. gdb does not understand + that native HP-UX format, so you must use gas if you wish to use + gdb. + +`m68k-sun' + Sun 3. We do not provide a configuration file to use the Sun FPA + by default, because programs that establish signal handlers for + floating point traps inherently cannot work with the FPA. + + See *Note Sun Install::, for information on installing GNU CC on + Sun systems. + +`m88k-*-svr3' + Motorola m88k running the AT&T/Unisoft/Motorola V.3 reference port. + These systems tend to use the Green Hills C, revision 1.8.5, as the + standard C compiler. There are apparently bugs in this compiler + that result in object files differences between stage 2 and stage + 3. If this happens, make the stage 4 compiler and compare it to + the stage 3 compiler. If the stage 3 and stage 4 object files are + identical, this suggests you encountered a problem with the + standard C compiler; the stage 3 and 4 compilers may be usable. + + It is best, however, to use an older version of GNU CC for + bootstrapping if you have one. + +`m88k-*-dgux' + Motorola m88k running DG/UX. To build 88open BCS native or cross + compilers on DG/UX, specify the configuration name as + `m88k-*-dguxbcs' and build in the 88open BCS software development + environment. To build ELF native or cross compilers on DG/UX, + specify `m88k-*-dgux' and build in the DG/UX ELF development + environment. You set the software development environment by + issuing `sde-target' command and specifying either `m88kbcs' or + `m88kdguxelf' as the operand. + + If you do not specify a configuration name, `configure' guesses the + configuration based on the current software development + environment. + +`m88k-tektronix-sysv3' + Tektronix XD88 running UTekV 3.2e. Do not turn on optimization + while building stage1 if you bootstrap with the buggy Green Hills + compiler. Also, The bundled LAI System V NFS is buggy so if you + build in an NFS mounted directory, start from a fresh reboot, or + avoid NFS all together. Otherwise you may have trouble getting + clean comparisons between stages. + +`mips-mips-bsd' + MIPS machines running the MIPS operating system in BSD mode. It's + possible that some old versions of the system lack the functions + `memcpy', `memcmp', and `memset'. If your system lacks these, you + must remove or undo the definition of `TARGET_MEM_FUNCTIONS' in + `mips-bsd.h'. + + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + +`mips-mips-riscos*' + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + + MIPS computers running RISC-OS can support four different + personalities: default, BSD 4.3, System V.3, and System V.4 (older + versions of RISC-OS don't support V.4). To configure GCC for + these platforms use the following configurations: + + `mips-mips-riscos`rev'' + Default configuration for RISC-OS, revision `rev'. + + `mips-mips-riscos`rev'bsd' + BSD 4.3 configuration for RISC-OS, revision `rev'. + + `mips-mips-riscos`rev'sysv4' + System V.4 configuration for RISC-OS, revision `rev'. + + `mips-mips-riscos`rev'sysv' + System V.3 configuration for RISC-OS, revision `rev'. + + The revision `rev' mentioned above is the revision of RISC-OS to + use. You must reconfigure GCC when going from a RISC-OS revision + 4 to RISC-OS revision 5. This has the effect of avoiding a linker + bug. + +`mips-sgi-*' + In order to compile GCC on an SGI running IRIX 4, the "c.hdr.lib" + option must be installed from the CD-ROM supplied from Silicon + Graphics. This is found on the 2nd CD in release 4.0.1. + + In order to compile GCC on an SGI running IRIX 5, the + "compiler_dev.hdr" subsystem must be installed from the IDO CD-ROM + supplied by Silicon Graphics. + + `make compare' may fail on version 5 of IRIX unless you add + `-save-temps' to `CFLAGS'. On these systems, the name of the + assembler input file is stored in the object file, and that makes + comparison fail if it differs between the `stage1' and `stage2' + compilations. The option `-save-temps' forces a fixed name to be + used for the assembler input file, instead of a randomly chosen + name in `/tmp'. Do not add `-save-temps' unless the comparisons + fail without that option. If you do you `-save-temps', you will + have to manually delete the `.i' and `.s' files after each series + of compilations. + + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + + On Irix version 4.0.5F, and perhaps on some other versions as well, + there is an assembler bug that reorders instructions incorrectly. + To work around it, specify the target configuration + `mips-sgi-irix4loser'. This configuration inhibits assembler + optimization. + + In a compiler configured with target `mips-sgi-irix4', you can turn + off assembler optimization by using the `-noasmopt' option. This + compiler option passes the option `-O0' to the assembler, to + inhibit reordering. + + The `-noasmopt' option can be useful for testing whether a problem + is due to erroneous assembler reordering. Even if a problem does + not go away with `-noasmopt', it may still be due to assembler + reordering--perhaps GNU CC itself was miscompiled as a result. + + To enable debugging under Irix 5, you must use GNU as 2.5 or later, + and use the `--with-gnu-as' configure option when configuring gcc. + GNU as is distributed as part of the binutils package. + +`mips-sony-sysv' + Sony MIPS NEWS. This works in NEWSOS 5.0.1, but not in 5.0.2 + (which uses ELF instead of COFF). Support for 5.0.2 will probably + be provided soon by volunteers. In particular, the linker does + not like the code generated by GCC when shared libraries are + linked in. + +`ns32k-encore' + Encore ns32000 system. Encore systems are supported only under + BSD. + +`ns32k-*-genix' + National Semiconductor ns32000 system. Genix has bugs in `alloca' + and `malloc'; you must get the compiled versions of these from GNU + Emacs. + +`ns32k-sequent' + Go to the Berkeley universe before compiling. + +`ns32k-utek' + UTEK ns32000 system ("merlin"). The C compiler that comes with + this system cannot compile GNU CC; contact `tektronix!reed!mason' + to get binaries of GNU CC for bootstrapping. + +`romp-*-aos' +`romp-*-mach' + The only operating systems supported for the IBM RT PC are AOS and + MACH. GNU CC does not support AIX running on the RT. We + recommend you compile GNU CC with an earlier version of itself; if + you compile GNU CC with `hc', the Metaware compiler, it will work, + but you will get mismatches between the stage 2 and stage 3 + compilers in various files. These errors are minor differences in + some floating-point constants and can be safely ignored; the stage + 3 compiler is correct. + +`rs6000-*-aix' +`powerpc-*-aix' + Various early versions of each release of the IBM XLC compiler + will not bootstrap GNU CC. Symptoms include differences between + the stage2 and stage3 object files, and errors when compiling + `libgcc.a' or `enquire'. Known problematic releases include: + xlc-1.2.1.8, xlc-1.3.0.0 (distributed with AIX 3.2.5), and + xlc-1.3.0.19. Both xlc-1.2.1.28 and xlc-1.3.0.24 (PTF 432238) are + known to produce working versions of GNU CC, but most other recent + releases correctly bootstrap GNU CC. + + Release 4.3.0 of AIX and ones prior to AIX 3.2.4 include a version + of the IBM assembler which does not accept debugging directives: + assembler updates are available as PTFs. Also, if you are using + AIX 3.2.5 or greater and the GNU assembler, you must have a + version modified after October 16th, 1995 in order for the GNU C + compiler to build. See the file `README.RS6000' for more details + on any of these problems. + + GNU CC does not yet support the 64-bit PowerPC instructions. + + Objective C does not work on this architecture because it makes + assumptions that are incompatible with the calling conventions. + + AIX on the RS/6000 provides support (NLS) for environments outside + of the United States. Compilers and assemblers use NLS to support + locale-specific representations of various objects including + floating-point numbers ("." vs "," for separating decimal + fractions). There have been problems reported where the library + linked with GNU CC does not produce the same floating-point + formats that the assembler accepts. If you have this problem, set + the LANG environment variable to "C" or "En_US". + + Due to changes in the way that GNU CC invokes the binder (linker) + for AIX 4.1, you may now receive warnings of duplicate symbols + from the link step that were not reported before. The assembly + files generated by GNU CC for AIX have always included multiple + symbol definitions for certain global variable and function + declarations in the original program. The warnings should not + prevent the linker from producing a correct library or runnable + executable. + + By default, AIX 4.1 produces code that can be used on either Power + or PowerPC processors. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-elf' +`powerpc-*-sysv4' + PowerPC system in big endian mode, running System V.4. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-linux-gnu' + PowerPC system in big endian mode, running the Linux-based GNU + system. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-eabiaix' + Embedded PowerPC system in big endian mode with -mcall-aix + selected as the default. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-eabisim' + Embedded PowerPC system in big endian mode for use in running + under the PSIM simulator. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-eabi' + Embedded PowerPC system in big endian mode. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpcle-*-elf' +`powerpcle-*-sysv4' + PowerPC system in little endian mode, running System V.4. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpcle-*-solaris2*' + PowerPC system in little endian mode, running Solaris 2.5.1 or + higher. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. Beta + versions of the Sun 4.0 compiler do not seem to be able to build + GNU CC correctly. There are also problems with the host assembler + and linker that are fixed by using the GNU versions of these tools. + +`powerpcle-*-eabisim' + Embedded PowerPC system in little endian mode for use in running + under the PSIM simulator. + +`powerpcle-*-eabi' + Embedded PowerPC system in little endian mode. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpcle-*-winnt' +`powerpcle-*-pe' + PowerPC system in little endian mode running Windows NT. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`vax-dec-ultrix' + Don't try compiling with Vax C (`vcc'). It produces incorrect code + in some cases (for example, when `alloca' is used). + + Meanwhile, compiling `cp/parse.c' with pcc does not work because of + an internal table size limitation in that compiler. To avoid this + problem, compile just the GNU C compiler first, and use it to + recompile building all the languages that you want to run. + +`sparc-sun-*' + See *Note Sun Install::, for information on installing GNU CC on + Sun systems. + +`vax-dec-vms' + See *Note VMS Install::, for details on how to install GNU CC on + VMS. + +`we32k-*-*' + These computers are also known as the 3b2, 3b5, 3b20 and other + similar names. (However, the 3b1 is actually a 68000; see *Note + Configurations::.) + + Don't use `-g' when compiling with the system's compiler. The + system's linker seems to be unable to handle such a large program + with debugging information. + + The system's compiler runs out of capacity when compiling `stmt.c' + in GNU CC. You can work around this by building `cpp' in GNU CC + first, then use that instead of the system's preprocessor with the + system's C compiler to compile `stmt.c'. Here is how: + + mv /lib/cpp /lib/cpp.att + cp cpp /lib/cpp.gnu + echo '/lib/cpp.gnu -traditional ${1+"$@"}' > /lib/cpp + chmod +x /lib/cpp + + The system's compiler produces bad code for some of the GNU CC + optimization files. So you must build the stage 2 compiler without + optimization. Then build a stage 3 compiler with optimization. + That executable should work. Here are the necessary commands: + + make LANGUAGES=c CC=stage1/xgcc CFLAGS="-Bstage1/ -g" + make stage2 + make CC=stage2/xgcc CFLAGS="-Bstage2/ -g -O" + + You may need to raise the ULIMIT setting to build a C++ compiler, + as the file `cc1plus' is larger than one megabyte. + + +File: INSTALL, Node: Other Dir, Next: Cross-Compiler, Prev: Configurations, Up: Installation + +Compilation in a Separate Directory +=================================== + + If you wish to build the object files and executables in a directory +other than the one containing the source files, here is what you must +do differently: + + 1. Make sure you have a version of Make that supports the `VPATH' + feature. (GNU Make supports it, as do Make versions on most BSD + systems.) + + 2. If you have ever run `configure' in the source directory, you must + undo the configuration. Do this by running: + + make distclean + + 3. Go to the directory in which you want to build the compiler before + running `configure': + + mkdir gcc-sun3 + cd gcc-sun3 + + On systems that do not support symbolic links, this directory must + be on the same file system as the source code directory. + + 4. Specify where to find `configure' when you run it: + + ../gcc/configure ... + + This also tells `configure' where to find the compiler sources; + `configure' takes the directory from the file name that was used to + invoke it. But if you want to be sure, you can specify the source + directory with the `--srcdir' option, like this: + + ../gcc/configure --srcdir=../gcc OTHER OPTIONS + + The directory you specify with `--srcdir' need not be the same as + the one that `configure' is found in. + + Now, you can run `make' in that directory. You need not repeat the +configuration steps shown above, when ordinary source files change. You +must, however, run `configure' again when the configuration files +change, if your system does not support symbolic links. + + +File: INSTALL, Node: Cross-Compiler, Next: Sun Install, Prev: Other Dir, Up: Installation + +Building and Installing a Cross-Compiler +======================================== + + GNU CC can function as a cross-compiler for many machines, but not +all. + + * Cross-compilers for the Mips as target using the Mips assembler + currently do not work, because the auxiliary programs + `mips-tdump.c' and `mips-tfile.c' can't be compiled on anything + but a Mips. It does work to cross compile for a Mips if you use + the GNU assembler and linker. + + * Cross-compilers between machines with different floating point + formats have not all been made to work. GNU CC now has a floating + point emulator with which these can work, but each target machine + description needs to be updated to take advantage of it. + + * Cross-compilation between machines of different word sizes is + somewhat problematic and sometimes does not work. + + Since GNU CC generates assembler code, you probably need a +cross-assembler that GNU CC can run, in order to produce object files. +If you want to link on other than the target machine, you need a +cross-linker as well. You also need header files and libraries suitable +for the target machine that you can install on the host machine. + +* Menu: + +* Steps of Cross:: Using a cross-compiler involves several steps + that may be carried out on different machines. +* Configure Cross:: Configuring a cross-compiler. +* Tools and Libraries:: Where to put the linker and assembler, and the C library. +* Cross Headers:: Finding and installing header files + for a cross-compiler. +* Cross Runtime:: Supplying arithmetic runtime routines (`libgcc1.a'). +* Build Cross:: Actually compiling the cross-compiler. + + +File: INSTALL, Node: Steps of Cross, Next: Configure Cross, Up: Cross-Compiler + +Steps of Cross-Compilation +-------------------------- + + To compile and run a program using a cross-compiler involves several +steps: + + * Run the cross-compiler on the host machine to produce assembler + files for the target machine. This requires header files for the + target machine. + + * Assemble the files produced by the cross-compiler. You can do this + either with an assembler on the target machine, or with a + cross-assembler on the host machine. + + * Link those files to make an executable. You can do this either + with a linker on the target machine, or with a cross-linker on the + host machine. Whichever machine you use, you need libraries and + certain startup files (typically `crt....o') for the target + machine. + + It is most convenient to do all of these steps on the same host +machine, since then you can do it all with a single invocation of GNU +CC. This requires a suitable cross-assembler and cross-linker. For +some targets, the GNU assembler and linker are available. + + +File: INSTALL, Node: Configure Cross, Next: Tools and Libraries, Prev: Steps of Cross, Up: Cross-Compiler + +Configuring a Cross-Compiler +---------------------------- + + To build GNU CC as a cross-compiler, you start out by running +`configure'. Use the `--target=TARGET' to specify the target type. If +`configure' was unable to correctly identify the system you are running +on, also specify the `--build=BUILD' option. For example, here is how +to configure for a cross-compiler that produces code for an HP 68030 +system running BSD on a system that `configure' can correctly identify: + + ./configure --target=m68k-hp-bsd4.3 + + +File: INSTALL, Node: Tools and Libraries, Next: Cross Headers, Prev: Configure Cross, Up: Cross-Compiler + +Tools and Libraries for a Cross-Compiler +---------------------------------------- + + If you have a cross-assembler and cross-linker available, you should +install them now. Put them in the directory `/usr/local/TARGET/bin'. +Here is a table of the tools you should put in this directory: + +`as' + This should be the cross-assembler. + +`ld' + This should be the cross-linker. + +`ar' + This should be the cross-archiver: a program which can manipulate + archive files (linker libraries) in the target machine's format. + +`ranlib' + This should be a program to construct a symbol table in an archive + file. + + The installation of GNU CC will find these programs in that +directory, and copy or link them to the proper place to for the +cross-compiler to find them when run later. + + The easiest way to provide these files is to build the Binutils +package and GAS. Configure them with the same `--host' and `--target' +options that you use for configuring GNU CC, then build and install +them. They install their executables automatically into the proper +directory. Alas, they do not support all the targets that GNU CC +supports. + + If you want to install libraries to use with the cross-compiler, +such as a standard C library, put them in the directory +`/usr/local/TARGET/lib'; installation of GNU CC copies all the files in +that subdirectory into the proper place for GNU CC to find them and +link with them. Here's an example of copying some libraries from a +target machine: + + ftp TARGET-MACHINE + lcd /usr/local/TARGET/lib + cd /lib + get libc.a + cd /usr/lib + get libg.a + get libm.a + quit + +The precise set of libraries you'll need, and their locations on the +target machine, vary depending on its operating system. + + Many targets require "start files" such as `crt0.o' and `crtn.o' +which are linked into each executable; these too should be placed in +`/usr/local/TARGET/lib'. There may be several alternatives for +`crt0.o', for use with profiling or other compilation options. Check +your target's definition of `STARTFILE_SPEC' to find out what start +files it uses. Here's an example of copying these files from a target +machine: + + ftp TARGET-MACHINE + lcd /usr/local/TARGET/lib + prompt + cd /lib + mget *crt*.o + cd /usr/lib + mget *crt*.o + quit + + +File: INSTALL, Node: Cross Runtime, Next: Build Cross, Prev: Cross Headers, Up: Cross-Compiler + +`libgcc.a' and Cross-Compilers +------------------------------ + + Code compiled by GNU CC uses certain runtime support functions +implicitly. Some of these functions can be compiled successfully with +GNU CC itself, but a few cannot be. These problem functions are in the +source file `libgcc1.c'; the library made from them is called +`libgcc1.a'. + + When you build a native compiler, these functions are compiled with +some other compiler-the one that you use for bootstrapping GNU CC. +Presumably it knows how to open code these operations, or else knows how +to call the run-time emulation facilities that the machine comes with. +But this approach doesn't work for building a cross-compiler. The +compiler that you use for building knows about the host system, not the +target system. + + So, when you build a cross-compiler you have to supply a suitable +library `libgcc1.a' that does the job it is expected to do. + + To compile `libgcc1.c' with the cross-compiler itself does not work. +The functions in this file are supposed to implement arithmetic +operations that GNU CC does not know how to open code for your target +machine. If these functions are compiled with GNU CC itself, they will +compile into infinite recursion. + + On any given target, most of these functions are not needed. If GNU +CC can open code an arithmetic operation, it will not call these +functions to perform the operation. It is possible that on your target +machine, none of these functions is needed. If so, you can supply an +empty library as `libgcc1.a'. + + Many targets need library support only for multiplication and +division. If you are linking with a library that contains functions for +multiplication and division, you can tell GNU CC to call them directly +by defining the macros `MULSI3_LIBCALL', and the like. These macros +need to be defined in the target description macro file. For some +targets, they are defined already. This may be sufficient to avoid the +need for libgcc1.a; if so, you can supply an empty library. + + Some targets do not have floating point instructions; they need other +functions in `libgcc1.a', which do floating arithmetic. Recent +versions of GNU CC have a file which emulates floating point. With a +certain amount of work, you should be able to construct a floating +point emulator that can be used as `libgcc1.a'. Perhaps future +versions will contain code to do this automatically and conveniently. +That depends on whether someone wants to implement it. + + Some embedded targets come with all the necessary `libgcc1.a' +routines written in C or assembler. These targets build `libgcc1.a' +automatically and you do not need to do anything special for them. +Other embedded targets do not need any `libgcc1.a' routines since all +the necessary operations are supported by the hardware. + + If your target system has another C compiler, you can configure GNU +CC as a native compiler on that machine, build just `libgcc1.a' with +`make libgcc1.a' on that machine, and use the resulting file with the +cross-compiler. To do this, execute the following on the target +machine: + + cd TARGET-BUILD-DIR + ./configure --host=sparc --target=sun3 + make libgcc1.a + +And then this on the host machine: + + ftp TARGET-MACHINE + binary + cd TARGET-BUILD-DIR + get libgcc1.a + quit + + Another way to provide the functions you need in `libgcc1.a' is to +define the appropriate `perform_...' macros for those functions. If +these definitions do not use the C arithmetic operators that they are +meant to implement, you should be able to compile them with the +cross-compiler you are building. (If these definitions already exist +for your target file, then you are all set.) + + To build `libgcc1.a' using the perform macros, use +`LIBGCC1=libgcc1.a OLDCC=./xgcc' when building the compiler. +Otherwise, you should place your replacement library under the name +`libgcc1.a' in the directory in which you will build the +cross-compiler, before you run `make'. + + +File: INSTALL, Node: Cross Headers, Next: Cross Runtime, Prev: Tools and Libraries, Up: Cross-Compiler + +Cross-Compilers and Header Files +-------------------------------- + + If you are cross-compiling a standalone program or a program for an +embedded system, then you may not need any header files except the few +that are part of GNU CC (and those of your program). However, if you +intend to link your program with a standard C library such as `libc.a', +then you probably need to compile with the header files that go with +the library you use. + + The GNU C compiler does not come with these files, because (1) they +are system-specific, and (2) they belong in a C library, not in a +compiler. + + If the GNU C library supports your target machine, then you can get +the header files from there (assuming you actually use the GNU library +when you link your program). + + If your target machine comes with a C compiler, it probably comes +with suitable header files also. If you make these files accessible +from the host machine, the cross-compiler can use them also. + + Otherwise, you're on your own in finding header files to use when +cross-compiling. + + When you have found suitable header files, put them in the directory +`/usr/local/TARGET/include', before building the cross compiler. Then +installation will run fixincludes properly and install the corrected +versions of the header files where the compiler will use them. + + Provide the header files before you build the cross-compiler, because +the build stage actually runs the cross-compiler to produce parts of +`libgcc.a'. (These are the parts that *can* be compiled with GNU CC.) +Some of them need suitable header files. + + Here's an example showing how to copy the header files from a target +machine. On the target machine, do this: + + (cd /usr/include; tar cf - .) > tarfile + + Then, on the host machine, do this: + + ftp TARGET-MACHINE + lcd /usr/local/TARGET/include + get tarfile + quit + tar xf tarfile + + +File: INSTALL, Node: Build Cross, Prev: Cross Runtime, Up: Cross-Compiler + +Actually Building the Cross-Compiler +------------------------------------ + + Now you can proceed just as for compiling a single-machine compiler +through the step of building stage 1. If you have not provided some +sort of `libgcc1.a', then compilation will give up at the point where +it needs that file, printing a suitable error message. If you do +provide `libgcc1.a', then building the compiler will automatically +compile and link a test program called `libgcc1-test'; if you get +errors in the linking, it means that not all of the necessary routines +in `libgcc1.a' are available. + + You must provide the header file `float.h'. One way to do this is +to compile `enquire' and run it on your target machine. The job of +`enquire' is to run on the target machine and figure out by experiment +the nature of its floating point representation. `enquire' records its +findings in the header file `float.h'. If you can't produce this file +by running `enquire' on the target machine, then you will need to come +up with a suitable `float.h' in some other way (or else, avoid using it +in your programs). + + Do not try to build stage 2 for a cross-compiler. It doesn't work to +rebuild GNU CC as a cross-compiler using the cross-compiler, because +that would produce a program that runs on the target machine, not on the +host. For example, if you compile a 386-to-68030 cross-compiler with +itself, the result will not be right either for the 386 (because it was +compiled into 68030 code) or for the 68030 (because it was configured +for a 386 as the host). If you want to compile GNU CC into 68030 code, +whether you compile it on a 68030 or with a cross-compiler on a 386, you +must specify a 68030 as the host when you configure it. + + To install the cross-compiler, use `make install', as usual. + + +File: INSTALL, Node: Sun Install, Next: VMS Install, Prev: Cross-Compiler, Up: Installation + +Installing GNU CC on the Sun +============================ + + On Solaris, do not use the linker or other tools in `/usr/ucb' to +build GNU CC. Use `/usr/ccs/bin'. + + If the assembler reports `Error: misaligned data' when bootstrapping, +you are probably using an obsolete version of the GNU assembler. +Upgrade to the latest version of GNU `binutils', or use the Solaris +assembler. + + Make sure the environment variable `FLOAT_OPTION' is not set when +you compile `libgcc.a'. If this option were set to `f68881' when +`libgcc.a' is compiled, the resulting code would demand to be linked +with a special startup file and would not link properly without special +pains. + + There is a bug in `alloca' in certain versions of the Sun library. +To avoid this bug, install the binaries of GNU CC that were compiled by +GNU CC. They use `alloca' as a built-in function and never the one in +the library. + + Some versions of the Sun compiler crash when compiling GNU CC. The +problem is a segmentation fault in cpp. This problem seems to be due to +the bulk of data in the environment variables. You may be able to avoid +it by using the following command to compile GNU CC with Sun CC: + + make CC="TERMCAP=x OBJS=x LIBFUNCS=x STAGESTUFF=x cc" + + SunOS 4.1.3 and 4.1.3_U1 have bugs that can cause intermittent core +dumps when compiling GNU CC. A common symptom is an internal compiler +error which does not recur if you run it again. To fix the problem, +install Sun recommended patch 100726 (for SunOS 4.1.3) or 101508 (for +SunOS 4.1.3_U1), or upgrade to a later SunOS release. + + +File: INSTALL, Node: VMS Install, Next: Collect2, Prev: Sun Install, Up: Installation + +Installing GNU CC on VMS +======================== + + The VMS version of GNU CC is distributed in a backup saveset +containing both source code and precompiled binaries. + + To install the `gcc' command so you can use the compiler easily, in +the same manner as you use the VMS C compiler, you must install the VMS +CLD file for GNU CC as follows: + + 1. Define the VMS logical names `GNU_CC' and `GNU_CC_INCLUDE' to + point to the directories where the GNU CC executables + (`gcc-cpp.exe', `gcc-cc1.exe', etc.) and the C include files are + kept respectively. This should be done with the commands: + + $ assign /system /translation=concealed - + disk:[gcc.] gnu_cc + $ assign /system /translation=concealed - + disk:[gcc.include.] gnu_cc_include + + with the appropriate disk and directory names. These commands can + be placed in your system startup file so they will be executed + whenever the machine is rebooted. You may, if you choose, do this + via the `GCC_INSTALL.COM' script in the `[GCC]' directory. + + 2. Install the `GCC' command with the command line: + + $ set command /table=sys$common:[syslib]dcltables - + /output=sys$common:[syslib]dcltables gnu_cc:[000000]gcc + $ install replace sys$common:[syslib]dcltables + + 3. To install the help file, do the following: + + $ library/help sys$library:helplib.hlb gcc.hlp + + Now you can invoke the compiler with a command like `gcc /verbose + file.c', which is equivalent to the command `gcc -v -c file.c' in + Unix. + + If you wish to use GNU C++ you must first install GNU CC, and then +perform the following steps: + + 1. Define the VMS logical name `GNU_GXX_INCLUDE' to point to the + directory where the preprocessor will search for the C++ header + files. This can be done with the command: + + $ assign /system /translation=concealed - + disk:[gcc.gxx_include.] gnu_gxx_include + + with the appropriate disk and directory name. If you are going to + be using a C++ runtime library, this is where its install + procedure will install its header files. + + 2. Obtain the file `gcc-cc1plus.exe', and place this in the same + directory that `gcc-cc1.exe' is kept. + + The GNU C++ compiler can be invoked with a command like `gcc /plus + /verbose file.cc', which is equivalent to the command `g++ -v -c + file.cc' in Unix. + + We try to put corresponding binaries and sources on the VMS +distribution tape. But sometimes the binaries will be from an older +version than the sources, because we don't always have time to update +them. (Use the `/version' option to determine the version number of +the binaries and compare it with the source file `version.c' to tell +whether this is so.) In this case, you should use the binaries you get +to recompile the sources. If you must recompile, here is how: + + 1. Execute the command procedure `vmsconfig.com' to set up the files + `tm.h', `config.h', `aux-output.c', and `md.', and to create files + `tconfig.h' and `hconfig.h'. This procedure also creates several + linker option files used by `make-cc1.com' and a data file used by + `make-l2.com'. + + $ @vmsconfig.com + + 2. Setup the logical names and command tables as defined above. In + addition, define the VMS logical name `GNU_BISON' to point at the + to the directories where the Bison executable is kept. This + should be done with the command: + + $ assign /system /translation=concealed - + disk:[bison.] gnu_bison + + You may, if you choose, use the `INSTALL_BISON.COM' script in the + `[BISON]' directory. + + 3. Install the `BISON' command with the command line: + + $ set command /table=sys$common:[syslib]dcltables - + /output=sys$common:[syslib]dcltables - + gnu_bison:[000000]bison + $ install replace sys$common:[syslib]dcltables + + 4. Type `@make-gcc' to recompile everything (alternatively, submit + the file `make-gcc.com' to a batch queue). If you wish to build + the GNU C++ compiler as well as the GNU CC compiler, you must + first edit `make-gcc.com' and follow the instructions that appear + in the comments. + + 5. In order to use GCC, you need a library of functions which GCC + compiled code will call to perform certain tasks, and these + functions are defined in the file `libgcc2.c'. To compile this + you should use the command procedure `make-l2.com', which will + generate the library `libgcc2.olb'. `libgcc2.olb' should be built + using the compiler built from the same distribution that + `libgcc2.c' came from, and `make-gcc.com' will automatically do + all of this for you. + + To install the library, use the following commands: + + $ library gnu_cc:[000000]gcclib/delete=(new,eprintf) + $ library gnu_cc:[000000]gcclib/delete=L_* + $ library libgcc2/extract=*/output=libgcc2.obj + $ library gnu_cc:[000000]gcclib libgcc2.obj + + The first command simply removes old modules that will be replaced + with modules from `libgcc2' under different module names. The + modules `new' and `eprintf' may not actually be present in your + `gcclib.olb'--if the VMS librarian complains about those modules + not being present, simply ignore the message and continue on with + the next command. The second command removes the modules that + came from the previous version of the library `libgcc2.c'. + + Whenever you update the compiler on your system, you should also + update the library with the above procedure. + + 6. You may wish to build GCC in such a way that no files are written + to the directory where the source files reside. An example would + be the when the source files are on a read-only disk. In these + cases, execute the following DCL commands (substituting your + actual path names): + + $ assign dua0:[gcc.build_dir.]/translation=concealed, - + dua1:[gcc.source_dir.]/translation=concealed gcc_build + $ set default gcc_build:[000000] + + where the directory `dua1:[gcc.source_dir]' contains the source + code, and the directory `dua0:[gcc.build_dir]' is meant to contain + all of the generated object files and executables. Once you have + done this, you can proceed building GCC as described above. (Keep + in mind that `gcc_build' is a rooted logical name, and thus the + device names in each element of the search list must be an actual + physical device name rather than another rooted logical name). + + 7. *If you are building GNU CC with a previous version of GNU CC, you + also should check to see that you have the newest version of the + assembler*. In particular, GNU CC version 2 treats global constant + variables slightly differently from GNU CC version 1, and GAS + version 1.38.1 does not have the patches required to work with GCC + version 2. If you use GAS 1.38.1, then `extern const' variables + will not have the read-only bit set, and the linker will generate + warning messages about mismatched psect attributes for these + variables. These warning messages are merely a nuisance, and can + safely be ignored. + + If you are compiling with a version of GNU CC older than 1.33, + specify `/DEFINE=("inline=")' as an option in all the + compilations. This requires editing all the `gcc' commands in + `make-cc1.com'. (The older versions had problems supporting + `inline'.) Once you have a working 1.33 or newer GNU CC, you can + change this file back. + + 8. If you want to build GNU CC with the VAX C compiler, you will need + to make minor changes in `make-cccp.com' and `make-cc1.com' to + choose alternate definitions of `CC', `CFLAGS', and `LIBS'. See + comments in those files. However, you must also have a working + version of the GNU assembler (GNU as, aka GAS) as it is used as + the back-end for GNU CC to produce binary object modules and is + not included in the GNU CC sources. GAS is also needed to compile + `libgcc2' in order to build `gcclib' (see above); `make-l2.com' + expects to be able to find it operational in + `gnu_cc:[000000]gnu-as.exe'. + + To use GNU CC on VMS, you need the VMS driver programs `gcc.exe', + `gcc.com', and `gcc.cld'. They are distributed with the VMS + binaries (`gcc-vms') rather than the GNU CC sources. GAS is also + included in `gcc-vms', as is Bison. + + Once you have successfully built GNU CC with VAX C, you should use + the resulting compiler to rebuild itself. Before doing this, be + sure to restore the `CC', `CFLAGS', and `LIBS' definitions in + `make-cccp.com' and `make-cc1.com'. The second generation + compiler will be able to take advantage of many optimizations that + must be suppressed when building with other compilers. + + Under previous versions of GNU CC, the generated code would +occasionally give strange results when linked with the sharable +`VAXCRTL' library. Now this should work. + + Even with this version, however, GNU CC itself should not be linked +with the sharable `VAXCRTL'. The version of `qsort' in `VAXCRTL' has a +bug (known to be present in VMS versions V4.6 through V5.5) which +causes the compiler to fail. + + The executables are generated by `make-cc1.com' and `make-cccp.com' +use the object library version of `VAXCRTL' in order to make use of the +`qsort' routine in `gcclib.olb'. If you wish to link the compiler +executables with the shareable image version of `VAXCRTL', you should +edit the file `tm.h' (created by `vmsconfig.com') to define the macro +`QSORT_WORKAROUND'. + + `QSORT_WORKAROUND' is always defined when GNU CC is compiled with +VAX C, to avoid a problem in case `gcclib.olb' is not yet available. + + +File: INSTALL, Node: Collect2, Next: Header Dirs, Prev: VMS Install, Up: Installation + +`collect2' +========== + + GNU CC uses a utility called `collect2' on nearly all systems to +arrange to call various initialization functions at start time. + + The program `collect2' works by linking the program once and looking +through the linker output file for symbols with particular names +indicating they are constructor functions. If it finds any, it creates +a new temporary `.c' file containing a table of them, compiles it, and +links the program a second time including that file. + + The actual calls to the constructors are carried out by a subroutine +called `__main', which is called (automatically) at the beginning of +the body of `main' (provided `main' was compiled with GNU CC). Calling +`__main' is necessary, even when compiling C code, to allow linking C +and C++ object code together. (If you use `-nostdlib', you get an +unresolved reference to `__main', since it's defined in the standard +GCC library. Include `-lgcc' at the end of your compiler command line +to resolve this reference.) + + The program `collect2' is installed as `ld' in the directory where +the passes of the compiler are installed. When `collect2' needs to +find the *real* `ld', it tries the following file names: + + * `real-ld' in the directories listed in the compiler's search + directories. + + * `real-ld' in the directories listed in the environment variable + `PATH'. + + * The file specified in the `REAL_LD_FILE_NAME' configuration macro, + if specified. + + * `ld' in the compiler's search directories, except that `collect2' + will not execute itself recursively. + + * `ld' in `PATH'. + + "The compiler's search directories" means all the directories where +`gcc' searches for passes of the compiler. This includes directories +that you specify with `-B'. + + Cross-compilers search a little differently: + + * `real-ld' in the compiler's search directories. + + * `TARGET-real-ld' in `PATH'. + + * The file specified in the `REAL_LD_FILE_NAME' configuration macro, + if specified. + + * `ld' in the compiler's search directories. + + * `TARGET-ld' in `PATH'. + + `collect2' explicitly avoids running `ld' using the file name under +which `collect2' itself was invoked. In fact, it remembers up a list +of such names--in case one copy of `collect2' finds another copy (or +version) of `collect2' installed as `ld' in a second place in the +search path. + + `collect2' searches for the utilities `nm' and `strip' using the +same algorithm as above for `ld'. + + +File: INSTALL, Node: Header Dirs, Prev: Collect2, Up: Installation + +Standard Header File Directories +================================ + + `GCC_INCLUDE_DIR' means the same thing for native and cross. It is +where GNU CC stores its private include files, and also where GNU CC +stores the fixed include files. A cross compiled GNU CC runs +`fixincludes' on the header files in `$(tooldir)/include'. (If the +cross compilation header files need to be fixed, they must be installed +before GNU CC is built. If the cross compilation header files are +already suitable for ANSI C and GNU CC, nothing special need be done). + + `GPLUS_INCLUDE_DIR' means the same thing for native and cross. It +is where `g++' looks first for header files. The C++ library installs +only target independent header files in that directory. + + `LOCAL_INCLUDE_DIR' is used only for a native compiler. It is +normally `/usr/local/include'. GNU CC searches this directory so that +users can install header files in `/usr/local/include'. + + `CROSS_INCLUDE_DIR' is used only for a cross compiler. GNU CC +doesn't install anything there. + + `TOOL_INCLUDE_DIR' is used for both native and cross compilers. It +is the place for other packages to install header files that GNU CC will +use. For a cross-compiler, this is the equivalent of `/usr/include'. +When you build a cross-compiler, `fixincludes' processes any header +files in this directory. + + + +Tag Table: +Node: Installation351 +Node: Configurations26618 +Node: Other Dir65739 +Node: Cross-Compiler67454 +Node: Steps of Cross69284 +Node: Configure Cross70401 +Node: Tools and Libraries71037 +Node: Cross Runtime73475 +Node: Cross Headers77555 +Node: Build Cross79553 +Node: Sun Install81428 +Node: VMS Install83099 +Node: Collect293028 +Node: Header Dirs95592 + +End Tag Table diff --git a/contrib/gcc/LITERATURE b/contrib/gcc/LITERATURE new file mode 100644 index 0000000000000..2cbe780df8468 --- /dev/null +++ b/contrib/gcc/LITERATURE @@ -0,0 +1,99 @@ +Collected papers/sites on standards, compilers, optimization, etc. + +- Massively Scalar Compiler Project + + ftp://cs.rice.edu/public/preston/optimizer + +- http://www.lpac.ac.uk/SEL-HPC/Articles/CompilersArchive.html + +- David M Keaton's site + + http://www.dmk.com, ftp://ftp.dmk.com + c9x stuff is in ftp://ftp.dmk.com/DMK/sc22wg14/c9x + +- Some information about optimizing for x86 processors, links to + x86 manuals and documentation. + + http://www.goof.com/pcg/docs.html + + +- AMD site with optimization guide for x86 + + http://www.amd.com/K6/k6docs/pdf/21828a.pdf + +- Links related to many compiler topics + + http://www.nullstone.com/htmls/connections.htm + +- HPPA information: + + http://www.hp.com/computing/framed/technology/micropro + +- New compiler book. Online appendix includes some compiler links + + http://www.mkp.com/books_catalog/1-55860-320-4.asp + +- Various MIPS stuff: + + http://www.sgi.com/MIPS/arch/mips4docs/mipsiv_3_2.pdf (*) + http://www.sgi.com/MIPS/arch/MIPS16/MIPS16.whitepaper.pdf + http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf + http://www.sgi.com/MIPS/arch/ISA5/isa5_tech_brf.pdf + http://www.sgi.com/MIPS/arch/ISA5/MDMXspec.pdf + http://www.sgi.com/MIPS/arch/ISA5/MIPSVspec.pdf + + +- IBM Journal of Research and Development + + http://www.almaden.ibm.com/journal/ + + +- System V PowerPC ABI + + http://www.esofta.com/softspecs.html + +- C9X draft + + http://www.dkuug.dk/JTC1/SC22/WG14/www/docs/n794.htm + +- DWARF v2 spec and sample implementation + + ftp://sgigate.sgi.com/pub/dwarf/ + + +- Various m68k info (including user guides in pdf format) + + http://www.mot.com/SPS/HPESD/prod/0X0 + + +- Modula 3 Stuff + + http://www.cmass.com + http://www.cl.cam.ac.uk/m3doc/linux/cambridge.html + ftp://ftp.freebsd.org/pub/FreeBSD/distfiles/LOCAL_PORTS/m3-fbsd-m3cc-3.6.tar.gz + http://www.m3.org + +- Comp.compilers archive + + http://www.iecc.com/compilers + +- Intel Pentium design info: + + http://developer.intel.com/design/litcentr/index.htm + +- comp.std.c++ FAQ: + + http://reality.sgi.com/employees/austern_mti/std-c++/faq.html + +- EG3 maintains a list of compiler Internet resources, including FAQ's, +papers, hot list pages, potential software/shareware, all known companies, etc. + + http://www.eg3.com/ulc/compulc.htm + http://www.eg3.com/softd/compiler.htm + http://www.eg3.com/softdv/compiler.htm + + These resource pages are published as part of EG3's + Free Electronic Engineers' Toolbox at: + + http://www.eg3.com/ebox.htm + diff --git a/contrib/gcc/Makefile.in b/contrib/gcc/Makefile.in index b1f7b0808c751..1a140c4ec2bdb 100644 --- a/contrib/gcc/Makefile.in +++ b/contrib/gcc/Makefile.in @@ -18,7 +18,7 @@ #the Free Software Foundation, 59 Temple Place - Suite 330, #Boston MA 02111-1307, USA. -# $FreeBSD$ +# $FreeBSD: src/contrib/gcc/Makefile.in,v 1.4 1999/10/16 08:21:54 obrien Exp $ # The targets for external use include: # all, doc, proto, install, install-cross, install-cross-rest, diff --git a/contrib/gcc/c-common.c b/contrib/gcc/c-common.c index 9ab5c5f8e19a8..dd716b24c4206 100644 --- a/contrib/gcc/c-common.c +++ b/contrib/gcc/c-common.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/c-common.c,v 1.8 1999/11/01 18:41:09 obrien Exp $ */ #include "config.h" #include "system.h" diff --git a/contrib/gcc/c-tree.h b/contrib/gcc/c-tree.h index 40c2f2dbac5bb..d8cec4751657b 100644 --- a/contrib/gcc/c-tree.h +++ b/contrib/gcc/c-tree.h @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/c-tree.h,v 1.4 1999/10/16 08:34:33 obrien Exp $ */ #ifndef _C_TREE_H #define _C_TREE_H diff --git a/contrib/gcc/cccp.1 b/contrib/gcc/cccp.1 index 442f0ab748e97..a056a7e10f64e 100644 --- a/contrib/gcc/cccp.1 +++ b/contrib/gcc/cccp.1 @@ -1,4 +1,4 @@ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/gcc/cccp.1,v 1.3 1999/09/19 08:18:18 obrien Exp $ .\" Copyright (c) 1991, 1992, 1993 Free Software Foundation \-*-Text-*- .\" See section COPYING for conditions for redistribution .TH cpp 1 "April 30, 1993" "FreeBSD" "GNU Tools" diff --git a/contrib/gcc/cccp.c b/contrib/gcc/cccp.c index 69cd93d3e88b7..a26e6bcdb1bee 100644 --- a/contrib/gcc/cccp.c +++ b/contrib/gcc/cccp.c @@ -18,7 +18,7 @@ along with this program; if not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/cccp.c,v 1.6 2000/03/09 10:11:07 obrien Exp $ */ #include "config.h" diff --git a/contrib/gcc/choose-temp.c b/contrib/gcc/choose-temp.c index 018f7d92a89f3..22678f19cce15 100644 --- a/contrib/gcc/choose-temp.c +++ b/contrib/gcc/choose-temp.c @@ -22,7 +22,7 @@ Boston, MA 02111-1307, USA. */ /* This file lives in at least two places: libiberty and gcc. Don't change one without the other. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/choose-temp.c,v 1.3 1999/11/04 10:23:25 obrien Exp $ */ #ifdef HAVE_CONFIG_H #include "config.h" diff --git a/contrib/gcc/config.sub b/contrib/gcc/config.sub new file mode 100755 index 0000000000000..b491c9f5ce053 --- /dev/null +++ b/contrib/gcc/config.sub @@ -0,0 +1,976 @@ +#! /bin/sh +# Configuration validation subroutine script, version 1.1. +# Copyright (C) 1991, 92-97, 1998 Free Software Foundation, Inc. +# This file is (in principle) common to ALL GNU software. +# The presence of a machine in this file suggests that SOME GNU software +# can handle that machine. It does not imply ALL GNU software can. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +if [ x$1 = x ] +then + echo Configuration name missing. 1>&2 + echo "Usage: $0 CPU-MFR-OPSYS" 1>&2 + echo "or $0 ALIAS" 1>&2 + echo where ALIAS is a recognized configuration type. 1>&2 + exit 1 +fi + +# First pass through any local machine types. +case $1 in + *local*) + echo $1 + exit 0 + ;; + *) + ;; +esac + +# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). +# Here we must recognize all the valid KERNEL-OS combinations. +maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` +case $maybe_os in + linux-gnu*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] + then os=`echo $1 | sed 's/.*-/-/'` + else os=; fi + ;; +esac + +### Let's recognize common machines as not being operating systems so +### that things like config.sub decstation-3100 work. We also +### recognize some manufacturers as not being operating systems, so we +### can provide default operating systems below. +case $os in + -sun*os*) + # Prevent following clause from handling this invalid input. + ;; + -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ + -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ + -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ + -apple) + os= + basic_machine=$1 + ;; + -hiux*) + os=-hiuxwe2 + ;; + -sco5) + os=-sco3.2v5 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco4) + os=-sco3.2v4 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2.[4-9]*) + os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2v[4-9]*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco*) + os=-sco3.2v2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -isc) + os=-isc2.2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -clix*) + basic_machine=clipper-intergraph + ;; + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -lynx*) + os=-lynxos + ;; + -ptx*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` + ;; + -windowsnt*) + os=`echo $os | sed -e 's/windowsnt/winnt/'` + ;; + -psos*) + os=-psos + ;; +esac + +# Decode aliases for certain CPU-COMPANY combinations. +case $basic_machine in + # Recognize the basic CPU types without company name. + # Some are omitted here because they have special meanings below. + tahoe | i860 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \ + | arme[lb] | pyramid | mn10200 | mn10300 \ + | tron | a29k | 580 | i960 | h8300 | hppa | hppa1.0 | hppa1.1 \ + | alpha | alphaev5 | alphaev56 | we32k | ns16k | clipper \ + | i370 | sh | powerpc | powerpcle | 1750a | dsp16xx | pdp11 \ + | mips64 | mipsel | mips64el | mips64orion | mips64orionel \ + | mipstx39 | mipstx39el \ + | sparc | sparclet | sparclite | sparc64 | v850) + basic_machine=$basic_machine-unknown + ;; + thumb | thumbel) + basic_machine=$basic_machine-unknown + ;; + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i[34567]86) + basic_machine=$basic_machine-pc + ;; + # Object if more than one company name word. + *-*-*) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; + # Recognize the basic CPU types with company name. + vax-* | tahoe-* | i[34567]86-* | i860-* | m32r-* | m68k-* | m68000-* \ + | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | arm-* | c[123]* \ + | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \ + | power-* | none-* | 580-* | cray2-* | h8300-* | i960-* \ + | xmp-* | ymp-* | hppa-* | hppa1.0-* | hppa1.1-* \ + | alpha-* | alphaev5-* | alphaev56-* | we32k-* | cydra-* \ + | ns16k-* | pn-* | np1-* | xps100-* | clipper-* | orion-* \ + | sparclite-* | pdp11-* | sh-* | powerpc-* | powerpcle-* \ + | sparc64-* | mips64-* | mipsel-* \ + | mips64el-* | mips64orion-* | mips64orionel-* \ + | mipstx39-* | mipstx39el-* \ + | f301-*) + ;; + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + basic_machine=m68000-att + ;; + 3b*) + basic_machine=we32k-att + ;; + alliant | fx80) + basic_machine=fx80-alliant + ;; + altos | altos3068) + basic_machine=m68k-altos + ;; + am29k) + basic_machine=a29k-none + os=-bsd + ;; + amdahl) + basic_machine=580-amdahl + os=-sysv + ;; + amiga | amiga-*) + basic_machine=m68k-cbm + ;; + amigaos | amigados) + basic_machine=m68k-cbm + os=-amigaos + ;; + amigaunix | amix) + basic_machine=m68k-cbm + os=-sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + os=-sysv + ;; + aux) + basic_machine=m68k-apple + os=-aux + ;; + balance) + basic_machine=ns32k-sequent + os=-dynix + ;; + convex-c1) + basic_machine=c1-convex + os=-bsd + ;; + convex-c2) + basic_machine=c2-convex + os=-bsd + ;; + convex-c32) + basic_machine=c32-convex + os=-bsd + ;; + convex-c34) + basic_machine=c34-convex + os=-bsd + ;; + convex-c38) + basic_machine=c38-convex + os=-bsd + ;; + cray | ymp) + basic_machine=ymp-cray + os=-unicos + ;; + cray2) + basic_machine=cray2-cray + os=-unicos + ;; + [ctj]90-cray) + basic_machine=c90-cray + os=-unicos + ;; + crds | unos) + basic_machine=m68k-crds + ;; + da30 | da30-*) + basic_machine=m68k-da30 + ;; + decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) + basic_machine=mips-dec + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + basic_machine=m68k-motorola + ;; + delta88) + basic_machine=m88k-motorola + os=-sysv3 + ;; + dpx20 | dpx20-*) + basic_machine=rs6000-bull + os=-bosx + ;; + dpx2* | dpx2*-bull) + basic_machine=m68k-bull + os=-sysv3 + ;; + ebmon29k) + basic_machine=a29k-amd + os=-ebmon + ;; + elxsi) + basic_machine=elxsi-elxsi + os=-bsd + ;; + encore | umax | mmax) + basic_machine=ns32k-encore + ;; + fx2800) + basic_machine=i860-alliant + ;; + genix) + basic_machine=ns32k-ns + ;; + gmicro) + basic_machine=tron-gmicro + os=-sysv + ;; + h3050r* | hiux*) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + h8300hms) + basic_machine=h8300-hitachi + os=-hms + ;; + harris) + basic_machine=m88k-harris + os=-sysv3 + ;; + hp300-*) + basic_machine=m68k-hp + ;; + hp300bsd) + basic_machine=m68k-hp + os=-bsd + ;; + hp300hpux) + basic_machine=m68k-hp + os=-hpux + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + basic_machine=m68000-hp + ;; + hp9k3[2-9][0-9]) + basic_machine=m68k-hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9] ) + basic_machine=hppa1.0-hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9] ) + basic_machine=hppa1.1-hp + ;; + hp9k78[0-9] | hp78[0-9] ) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | \ + hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893 ) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679] ) + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hppa-next) + os=-nextstep3 + ;; + i370-ibm* | ibm*) + basic_machine=i370-ibm + os=-mvs + ;; +# I'm not sure what "Sysv32" means. Should this be sysv3.2? + i[34567]86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 + ;; + i[34567]86v4*) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv4 + ;; + i[34567]86v) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv + ;; + i[34567]86sol2) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-solaris2 + ;; + iris | iris4d) + basic_machine=mips-sgi + case $os in + -irix*) + ;; + *) + os=-irix4 + ;; + esac + ;; + isi68 | isi) + basic_machine=m68k-isi + os=-sysv + ;; + m88k-omron*) + basic_machine=m88k-omron + ;; + magnum | m3230) + basic_machine=mips-mips + os=-sysv + ;; + merlin) + basic_machine=ns32k-utek + os=-sysv + ;; + miniframe) + basic_machine=m68000-convergent + ;; + mipsel*-linux*) + basic_machine=mipsel-unknown + os=-linux-gnu + ;; + mips*-linux*) + basic_machine=mips-unknown + os=-linux-gnu + ;; + mips3*-*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` + ;; + mips3*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown + ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + os=-newsos + ;; + news1000) + basic_machine=m68030-sony + os=-newsos + ;; + news-3600 | risc-news) + basic_machine=mips-sony + os=-newsos + ;; + next | m*-next ) + basic_machine=m68k-next + case $os in + -nextstep* ) + ;; + -ns2*) + os=-nextstep2 + ;; + *) + os=-nextstep3 + ;; + esac + ;; + nh3000) + basic_machine=m68k-harris + os=-cxux + ;; + nh[45]000) + basic_machine=m88k-harris + os=-cxux + ;; + nindy960) + basic_machine=i960-intel + os=-nindy + ;; + np1) + basic_machine=np1-gould + ;; + pa-hitachi) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + paragon) + basic_machine=i860-intel + os=-osf + ;; + pbd) + basic_machine=sparc-tti + ;; + pbb) + basic_machine=m68k-tti + ;; + pc532 | pc532-*) + basic_machine=ns32k-pc532 + ;; + pentium | p5 | k5 | nexen) + basic_machine=i586-pc + ;; + pentiumpro | p6 | k6 | 6x86) + basic_machine=i686-pc + ;; + pentiumii | pentium2) + basic_machine=i786-pc + ;; + pentium-* | p5-* | k5-* | nexen-*) + basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumpro-* | p6-* | k6-* | 6x86-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumii-* | pentium2-*) + basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pn) + basic_machine=pn-gould + ;; + power) basic_machine=rs6000-ibm + ;; + ppc) basic_machine=powerpc-unknown + ;; + ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle | ppc-le | powerpc-little) + basic_machine=powerpcle-unknown + ;; + ppcle-* | powerpclittle-*) + basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ps2) + basic_machine=i386-ibm + ;; + rm[46]00) + basic_machine=mips-siemens + ;; + rtpc | rtpc-*) + basic_machine=romp-ibm + ;; + sequent) + basic_machine=i386-sequent + ;; + sh) + basic_machine=sh-hitachi + os=-hms + ;; + sps7) + basic_machine=m68k-bull + os=-sysv2 + ;; + spur) + basic_machine=spur-unknown + ;; + sun2) + basic_machine=m68000-sun + ;; + sun2os3) + basic_machine=m68000-sun + os=-sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + os=-sunos4 + ;; + sun3os3) + basic_machine=m68k-sun + os=-sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + os=-sunos4 + ;; + sun4os3) + basic_machine=sparc-sun + os=-sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + os=-sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + os=-solaris2 + ;; + sun3 | sun3-*) + basic_machine=m68k-sun + ;; + sun4) + basic_machine=sparc-sun + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + ;; + symmetry) + basic_machine=i386-sequent + os=-dynix + ;; + tx39) + basic_machine=mipstx39-unknown + ;; + tx39el) + basic_machine=mipstx39el-unknown + ;; + tower | tower-32) + basic_machine=m68k-ncr + ;; + udi29k) + basic_machine=a29k-amd + os=-udi + ;; + ultra3) + basic_machine=a29k-nyu + os=-sym1 + ;; + vaxv) + basic_machine=vax-dec + os=-sysv + ;; + vms) + basic_machine=vax-dec + os=-vms + ;; + vpp*|vx|vx-*) + basic_machine=f301-fujitsu + ;; + vxworks960) + basic_machine=i960-wrs + os=-vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + os=-vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + os=-vxworks + ;; + xmp) + basic_machine=xmp-cray + os=-unicos + ;; + xps | xps100) + basic_machine=xps100-honeywell + ;; + none) + basic_machine=none-none + os=-none + ;; + +# Here we handle the default manufacturer of certain CPU types. It is in +# some cases the only manufacturer, in others, it is the most popular. + mips) + if [ x$os = x-linux-gnu ]; then + basic_machine=mips-unknown + else + basic_machine=mips-mips + fi + ;; + romp) + basic_machine=romp-ibm + ;; + rs6000) + basic_machine=rs6000-ibm + ;; + vax) + basic_machine=vax-dec + ;; + pdp11) + basic_machine=pdp11-dec + ;; + we32k) + basic_machine=we32k-att + ;; + sparc) + basic_machine=sparc-sun + ;; + cydra) + basic_machine=cydra-cydrome + ;; + orion) + basic_machine=orion-highlevel + ;; + orion105) + basic_machine=clipper-highlevel + ;; + *) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $basic_machine in + *-digital*) + basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` + ;; + *-commodore*) + basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if [ x"$os" != x"" ] +then +case $os in + # First match some system type aliases + # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; + -solaris) + os=-solaris2 + ;; + -svr4*) + os=-sysv4 + ;; + -unixware*) + os=-sysv4.2uw + ;; + -gnu/linux*) + os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` + ;; + # First accept the basic system types. + # The portable systems comes first. + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -netbsd* | -openbsd* | -freebsd* | -riscix* \ + | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -cygwin32* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ + | -mingw32* | -linux-gnu* | -uxpv* | -beos* ) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -linux*) + os=`echo $os | sed -e 's|linux|linux-gnu|'` + ;; + -sunos5*) + os=`echo $os | sed -e 's|sunos5|solaris2|'` + ;; + -sunos6*) + os=`echo $os | sed -e 's|sunos6|solaris3|'` + ;; + -osfrose*) + os=-osfrose + ;; + -osf*) + os=-osf + ;; + -utek*) + os=-bsd + ;; + -dynix*) + os=-bsd + ;; + -acis*) + os=-aos + ;; + -ctix* | -uts*) + os=-sysv + ;; + -ns2 ) + os=-nextstep2 + ;; + # Preserve the version number of sinix5. + -sinix5.*) + os=`echo $os | sed -e 's|sinix|sysv|'` + ;; + -sinix*) + os=-sysv4 + ;; + -triton*) + os=-sysv3 + ;; + -oss*) + os=-sysv3 + ;; + -svr4) + os=-sysv4 + ;; + -svr3) + os=-sysv3 + ;; + -sysvr4) + os=-sysv4 + ;; + # This must come after -sysvr4. + -sysv*) + ;; + -xenix) + os=-xenix + ;; + -none) + ;; + *) + # Get rid of the `-' at the beginning of $os. + os=`echo $os | sed 's/[^-]*-//'` + echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 + exit 1 + ;; +esac +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +case $basic_machine in + *-acorn) + os=-riscix1.2 + ;; + arm*-semi) + os=-aout + ;; + pdp11-*) + os=-none + ;; + *-dec | vax-*) + os=-ultrix4.2 + ;; + m68*-apollo) + os=-domain + ;; + i386-sun) + os=-sunos4.0.2 + ;; + m68000-sun) + os=-sunos3 + # This also exists in the configure program, but was not the + # default. + # os=-sunos4 + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=-sysv3 + ;; + sparc-* | *-sun) + os=-sunos4.1.1 + ;; + *-ibm) + os=-aix + ;; + *-hp) + os=-hpux + ;; + *-hitachi) + os=-hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=-sysv + ;; + *-cbm) + os=-amigaos + ;; + *-dg) + os=-dgux + ;; + *-dolphin) + os=-sysv3 + ;; + m68k-ccur) + os=-rtu + ;; + m88k-omron*) + os=-luna + ;; + *-next ) + os=-nextstep + ;; + *-sequent) + os=-ptx + ;; + *-crds) + os=-unos + ;; + *-ns) + os=-genix + ;; + i370-*) + os=-mvs + ;; + *-next) + os=-nextstep3 + ;; + *-gould) + os=-sysv + ;; + *-highlevel) + os=-bsd + ;; + *-encore) + os=-bsd + ;; + *-sgi) + os=-irix + ;; + *-siemens) + os=-sysv4 + ;; + *-masscomp) + os=-rtu + ;; + f301-fujitsu) + os=-uxpv + ;; + *-be) + os=-beos + ;; + *) + os=-none + ;; +esac +fi + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +vendor=unknown +case $basic_machine in + *-unknown) + case $os in + -riscix*) + vendor=acorn + ;; + -sunos*) + vendor=sun + ;; + -aix*) + vendor=ibm + ;; + -hpux*) + vendor=hp + ;; + -hiux*) + vendor=hitachi + ;; + -unos*) + vendor=crds + ;; + -dgux*) + vendor=dg + ;; + -luna*) + vendor=omron + ;; + -genix*) + vendor=ns + ;; + -mvs*) + vendor=ibm + ;; + -ptx*) + vendor=sequent + ;; + -vxsim* | -vxworks*) + vendor=wrs + ;; + -aux*) + vendor=apple + ;; + -beos*) + vendor=be + ;; + esac + basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` + ;; +esac + +echo $basic_machine$os diff --git a/contrib/gcc/config/alpha/elf.h b/contrib/gcc/config/alpha/elf.h index 24af9d3d03135..a226a6a460f53 100644 --- a/contrib/gcc/config/alpha/elf.h +++ b/contrib/gcc/config/alpha/elf.h @@ -19,7 +19,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/alpha/elf.h,v 1.3 1999/10/16 08:13:35 obrien Exp $ */ #undef OBJECT_FORMAT_COFF #undef EXTENDED_COFF diff --git a/contrib/gcc/config/alpha/freebsd.h b/contrib/gcc/config/alpha/freebsd.h index a3052d83c06ce..1d9efb20801ca 100644 --- a/contrib/gcc/config/alpha/freebsd.h +++ b/contrib/gcc/config/alpha/freebsd.h @@ -22,7 +22,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ This was taken from the NetBSD configuration, and modified for FreeBSD/Alpha by Hidetoshi Shimokawa */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/alpha/freebsd.h,v 1.9 1999/12/19 06:42:23 obrien Exp $ */ /* Make gcc agree with */ diff --git a/contrib/gcc/config/alpha/gdb-osf12.h b/contrib/gcc/config/alpha/gdb-osf12.h new file mode 100644 index 0000000000000..98c2897140177 --- /dev/null +++ b/contrib/gcc/config/alpha/gdb-osf12.h @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha, using + encapsulated stabs and OSF V1.2. + Copyright (C) 1994 Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "alpha/osf12.h" + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG diff --git a/contrib/gcc/config/alpha/gdb-osf2.h b/contrib/gcc/config/alpha/gdb-osf2.h new file mode 100644 index 0000000000000..5ddb7981b34d7 --- /dev/null +++ b/contrib/gcc/config/alpha/gdb-osf2.h @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha, using + encapsulated stabs. + Copyright (C) 1992, 1993 Free Software Foundation, Inc. + Contributed by Peter Schauer (pes@regent.e-technik.tu-muenchen.de). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "alpha/osf2.h" + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG diff --git a/contrib/gcc/config/alpha/gdb.h b/contrib/gcc/config/alpha/gdb.h new file mode 100644 index 0000000000000..ecdbe40a9a45c --- /dev/null +++ b/contrib/gcc/config/alpha/gdb.h @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha, using + encapsulated stabs. + Copyright (C) 1992, 1993 Free Software Foundation, Inc. + Contributed by Peter Schauer (pes@regent.e-technik.tu-muenchen.de). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "alpha/alpha.h" + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG diff --git a/contrib/gcc/config/alpha/osf2.h b/contrib/gcc/config/alpha/osf2.h new file mode 100644 index 0000000000000..169af5a01c970 --- /dev/null +++ b/contrib/gcc/config/alpha/osf2.h @@ -0,0 +1,32 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha. + Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#include "alpha/alpha.h" + +/* In OSF 2.0, the size of wchar_t was changed from short unsigned + to unsigned int. */ + +#undef WCHAR_TYPE +#define WCHAR_TYPE "unsigned int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 32 diff --git a/contrib/gcc/config/freebsd.h b/contrib/gcc/config/freebsd.h index 16ddd83d66059..054d32a078bdf 100644 --- a/contrib/gcc/config/freebsd.h +++ b/contrib/gcc/config/freebsd.h @@ -24,7 +24,7 @@ Boston, MA 02111-1307, USA. */ Adapted from /usr/src/contrib/gcc/config/i386/freebsd.h & egcs/gcc/config/i386/freebsd-elf.h version by David O'Brien */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/freebsd.h,v 1.25 2000/01/27 23:12:38 obrien Exp $ */ /* Don't assume anything about the header files. */ diff --git a/contrib/gcc/config/i386/cygwin32.asm b/contrib/gcc/config/i386/cygwin32.asm new file mode 100644 index 0000000000000..4ac4c91a3b18d --- /dev/null +++ b/contrib/gcc/config/i386/cygwin32.asm @@ -0,0 +1,32 @@ +/* stuff needed for libgcc1 on win32. */ + +#ifdef L_chkstk + + .global ___chkstk + .global __alloca +___chkstk: +__alloca: + pushl %ecx /* save temp */ + movl %esp,%ecx /* get sp */ + addl $0x8,%ecx /* and point to return addr */ + +probe: cmpl $0x1000,%eax /* > 4k ?*/ + jb done + + subl $0x1000,%ecx /* yes, move pointer down 4k*/ + orl $0x0,(%ecx) /* probe there */ + subl $0x1000,%eax /* decrement count */ + jmp probe /* and do it again */ + +done: subl %eax,%ecx + orl $0x0,(%ecx) /* less that 4k, just peek here */ + + movl %esp,%eax + movl %ecx,%esp /* decrement stack */ + + movl (%eax),%ecx /* recover saved temp */ + movl 4(%eax),%eax /* get return address */ + jmp *%eax + + +#endif diff --git a/contrib/gcc/config/i386/cygwin32.h b/contrib/gcc/config/i386/cygwin32.h new file mode 100644 index 0000000000000..3fe7df9f15362 --- /dev/null +++ b/contrib/gcc/config/i386/cygwin32.h @@ -0,0 +1,453 @@ +/* Operating system specific defines to be used when targeting GCC for + hosting on Windows NT 3.x, using a Unix style C library and tools, + as distinct from winnt.h, which is used to build GCC for use with a + windows style library and tool set and uses the Microsoft tools. + Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define YES_UNDERSCORES + +#define DBX_DEBUGGING_INFO +#define SDB_DEBUGGING_INFO +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "i386/gas.h" +#include "dbxcoff.h" + +/* Support the __declspec keyword by turning them into attributes. + We currently only support: dllimport and dllexport. + Note that the current way we do this may result in a collision with + predefined attributes later on. This can be solved by using one attribute, + say __declspec__, and passing args to it. The problem with that approach + is that args are not accumulated: each new appearance would clobber any + existing args. */ + +#ifdef CPP_PREDEFINES +#undef CPP_PREDEFINES +#endif + +#define CPP_PREDEFINES "-Di386 -D_WIN32 \ + -D__CYGWIN32__ -DWINNT -D_X86_=1 -D__STDC__=1\ + -D__stdcall=__attribute__((__stdcall__)) \ + -D__cdecl=__attribute__((__cdecl__)) \ + -D__declspec(x)=__attribute__((x)) \ + -Asystem(winnt) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC "-remap %(cpp_cpu) %{posix:-D_POSIX_SOURCE}" + +/* We have to dynamic link to get to the system DLLs. All of libc, libm and + the Unix stuff is in cygwin.dll. The import library is called + 'libcygwin.a'. For Windows applications, include more libraries, but + always include kernel32. We'd like to specific subsystem windows to + ld, but that doesn't work just yet. */ + +#undef LIB_SPEC +#define LIB_SPEC "-lcygwin %{mwindows:-luser32 -lgdi32 -lcomdlg32} -lkernel32 \ + -ladvapi32 -lshell32" + +#define LINK_SPEC "%{mwindows:--subsystem windows}" + +/* Normally, -lgcc is not needed since everything in it is in the DLL, but we + want to allow things to be added to it when installing new versions of + GCC without making a new CYGWIN.DLL, so we leave it. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crt0%O%s" + +#define SIZE_TYPE "unsigned int" +#define PTRDIFF_TYPE "int" +#define WCHAR_UNSIGNED 1 +#define WCHAR_TYPE_SIZE 16 +#define WCHAR_TYPE "short unsigned int" +#define HAVE_ATEXIT 1 + + +/* Ignore dllimport for functions. */ +#define TARGET_NOP_FUN_DLLIMPORT (target_flags & 0x20000) + +#undef SUBTARGET_SWITCHES +#define SUBTARGET_SWITCHES \ + { "nop-fun-dllimport", 0x20000 }, \ + { "no-nop-fun-dllimport", -0x20000 }, \ + { "windows", 0x0 }, + +/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS + is a valid machine specific attribute for DECL. + The attributes in ATTRIBUTES have previously been assigned to DECL. */ +extern int i386_pe_valid_decl_attribute_p (); + +#undef VALID_MACHINE_DECL_ATTRIBUTE +#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \ + i386_pe_valid_decl_attribute_p (DECL, ATTRIBUTES, IDENTIFIER, ARGS) + +/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS + is a valid machine specific attribute for TYPE. + The attributes in ATTRIBUTES have previously been assigned to TYPE. */ + +#undef VALID_MACHINE_TYPE_ATTRIBUTE +#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, IDENTIFIER, ARGS) \ + i386_pe_valid_type_attribute_p (TYPE, ATTRIBUTES, IDENTIFIER, ARGS) +extern int i386_pe_valid_type_attribute_p (); + +extern union tree_node *i386_pe_merge_decl_attributes (); +#define MERGE_MACHINE_DECL_ATTRIBUTES(OLD, NEW) \ + i386_pe_merge_decl_attributes ((OLD), (NEW)) + +/* Used to implement dllexport overriding dllimport semantics. It's also used + to handle vtables - the first pass won't do anything because + DECL_CONTEXT (DECL) will be 0 so i386_pe_dll{ex,im}port_p will return 0. + It's also used to handle dllimport override semantics. */ +#if 0 +#define REDO_SECTION_INFO_P(DECL) \ + ((DECL_MACHINE_ATTRIBUTES (DECL) != NULL_TREE) \ + || (TREE_CODE (DECL) == VAR_DECL && DECL_VIRTUAL_P (DECL))) +#else +#define REDO_SECTION_INFO_P(DECL) 1 +#endif + + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_ctor, in_dtor, in_drectve + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CTOR_SECTION_FUNCTION \ + DTOR_SECTION_FUNCTION \ + DRECTVE_SECTION_FUNCTION \ + SWITCH_TO_SECTION_FUNCTION + +#define CTOR_SECTION_FUNCTION \ +void \ +ctor_section () \ +{ \ + if (in_section != in_ctor) \ + { \ + fprintf (asm_out_file, "\t.section .ctor\n"); \ + in_section = in_ctor; \ + } \ +} + +#define DTOR_SECTION_FUNCTION \ +void \ +dtor_section () \ +{ \ + if (in_section != in_dtor) \ + { \ + fprintf (asm_out_file, "\t.section .dtor\n"); \ + in_section = in_dtor; \ + } \ +} + +#define DRECTVE_SECTION_FUNCTION \ +void \ +drectve_section () \ +{ \ + if (in_section != in_drectve) \ + { \ + fprintf (asm_out_file, "%s\n", "\t.section .drectve\n"); \ + in_section = in_drectve; \ + } \ +} + +/* Switch to SECTION (an `enum in_section'). + + ??? This facility should be provided by GCC proper. + The problem is that we want to temporarily switch sections in + ASM_DECLARE_OBJECT_NAME and then switch back to the original section + afterwards. */ +#define SWITCH_TO_SECTION_FUNCTION \ +void \ +switch_to_section (section, decl) \ + enum in_section section; \ + tree decl; \ +{ \ + switch (section) \ + { \ + case in_text: text_section (); break; \ + case in_data: data_section (); break; \ + case in_named: named_section (decl, NULL, 0); break; \ + case in_ctor: ctor_section (); break; \ + case in_dtor: dtor_section (); break; \ + case in_drectve: drectve_section (); break; \ + default: abort (); break; \ + } \ +} + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + On i386 running Windows NT, modify the assembler name with a suffix + consisting of an atsign (@) followed by string of digits that represents + the number of bytes of arguments passed to the function, if it has the + attribute STDCALL. + + In addition, we must mark dll symbols specially. Definitions of + dllexport'd objects install some info in the .drectve section. + References to dllimport'd objects are fetched indirectly via + _imp__. If both are declared, dllexport overrides. This is also + needed to implement one-only vtables: they go into their own + section and we need to set DECL_SECTION_NAME so we do that here. + Note that we can be called twice on the same decl. */ + +extern void i386_pe_encode_section_info (); + +#ifdef ENCODE_SECTION_INFO +#undef ENCODE_SECTION_INFO +#endif +#define ENCODE_SECTION_INFO(DECL) i386_pe_encode_section_info (DECL) + +/* Utility used only in this file. */ +#define I386_PE_STRIP_ENCODING(SYM_NAME) \ + ((SYM_NAME) + ((SYM_NAME)[0] == '@' ? 3 : 0)) + +/* This macro gets just the user-specified name + out of the string in a SYMBOL_REF. Discard + trailing @[NUM] encoded by ENCODE_SECTION_INFO. */ +#undef STRIP_NAME_ENCODING +#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \ +do { \ + char *_p; \ + char *_name = I386_PE_STRIP_ENCODING (SYMBOL_NAME); \ + for (_p = _name; *_p && *_p != '@'; ++_p) \ + ; \ + if (*_p == '@') \ + { \ + int _len = _p - _name; \ + (VAR) = (char *) alloca (_len + 1); \ + strncpy ((VAR), _name, _len); \ + (VAR)[_len] = '\0'; \ + } \ + else \ + (VAR) = _name; \ +} while (0) + + +/* Output a reference to a label. */ +#undef ASM_OUTPUT_LABELREF +#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ + fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \ + I386_PE_STRIP_ENCODING (NAME)) \ + +/* Output a common block. */ +#undef ASM_OUTPUT_COMMON +#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ +do { \ + if (i386_pe_dllexport_name_p (NAME)) \ + { \ + drectve_section (); \ + fprintf ((STREAM), "\t.ascii \" -export:%s\"\n", \ + I386_PE_STRIP_ENCODING (NAME)); \ + } \ + if (! i386_pe_dllimport_name_p (NAME)) \ + { \ + fprintf ((STREAM), "\t.comm\t"); \ + assemble_name ((STREAM), (NAME)); \ + fprintf ((STREAM), ", %d\t%s %d\n", \ + (ROUNDED), ASM_COMMENT_START, (SIZE)); \ + } \ +} while (0) + +/* Output the label for an initialized variable. */ +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ +do { \ + if (i386_pe_dllexport_name_p (NAME)) \ + { \ + enum in_section save_section = in_section; \ + drectve_section (); \ + fprintf ((STREAM), "\t.ascii \" -export:%s\"\n", \ + I386_PE_STRIP_ENCODING (NAME)); \ + switch_to_section (save_section, (DECL)); \ + } \ + ASM_OUTPUT_LABEL ((STREAM), (NAME)); \ +} while (0) + + +/* Emit code to check the stack when allocating more that 4000 + bytes in one go. */ + +#define CHECK_STACK_LIMIT 4000 + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387 and needs stack probes */ +#undef TARGET_DEFAULT + +#define TARGET_DEFAULT \ + (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) + +/* Define this macro if in some cases global symbols from one translation + unit may not be bound to undefined symbols in another translation unit + without user intervention. For instance, under Microsoft Windows + symbols must be explicitly imported from shared libraries (DLLs). */ +#define MULTIPLE_SYMBOL_SPACES + +#define UNIQUE_SECTION_P(DECL) DECL_ONE_ONLY (DECL) +extern void i386_pe_unique_section (); +#define UNIQUE_SECTION(DECL,RELOC) i386_pe_unique_section (DECL, RELOC) + +#define SUPPORTS_ONE_ONLY 1 + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. */ +#undef ASM_OUTPUT_SECTION_NAME +#define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME, RELOC) \ +do { \ + static struct section_info \ + { \ + struct section_info *next; \ + char *name; \ + enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type; \ + } *sections; \ + struct section_info *s; \ + char *mode; \ + enum sect_enum type; \ + \ + for (s = sections; s; s = s->next) \ + if (!strcmp (NAME, s->name)) \ + break; \ + \ + if (DECL && TREE_CODE (DECL) == FUNCTION_DECL) \ + type = SECT_EXEC, mode = "x"; \ + else if (DECL && DECL_READONLY_SECTION (DECL, RELOC)) \ + type = SECT_RO, mode = ""; \ + else \ + type = SECT_RW, mode = "w"; \ + \ + if (s == 0) \ + { \ + s = (struct section_info *) xmalloc (sizeof (struct section_info)); \ + s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME)); \ + strcpy (s->name, NAME); \ + s->type = type; \ + s->next = sections; \ + sections = s; \ + fprintf (STREAM, ".section\t%s,\"%s\"\n", NAME, mode); \ + /* Functions may have been compiled at various levels of \ + optimization so we can't use `same_size' here. Instead, \ + have the linker pick one. */ \ + if ((DECL) && DECL_ONE_ONLY (DECL)) \ + fprintf (STREAM, "\t.linkonce %s\n", \ + TREE_CODE (DECL) == FUNCTION_DECL \ + ? "discard" : "same_size"); \ + } \ + else \ + { \ + fprintf (STREAM, ".section\t%s,\"%s\"\n", NAME, mode); \ + } \ +} while (0) + +/* Write the extra assembler code needed to declare a function + properly. If we are generating SDB debugging information, this + will happen automatically, so we only need to handle other cases. */ +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ + do \ + { \ + if (i386_pe_dllexport_name_p (NAME)) \ + { \ + drectve_section (); \ + fprintf ((FILE), "\t.ascii \" -export:%s\"\n", \ + I386_PE_STRIP_ENCODING (NAME)); \ + function_section (DECL); \ + } \ + if (write_symbols != SDB_DEBUG) \ + i386_pe_declare_function_type (FILE, NAME, TREE_PUBLIC (DECL)); \ + ASM_OUTPUT_LABEL (FILE, NAME); \ + } \ + while (0) + +/* Add an external function to the list of functions to be declared at + the end of the file. */ +#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ + do \ + { \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + i386_pe_record_external_function (NAME); \ + } \ + while (0) + +/* Declare the type properly for any external libcall. */ +#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ + i386_pe_declare_function_type (FILE, XSTR (FUN, 0), 1) + +/* Output function declarations at the end of the file. */ +#define ASM_FILE_END(FILE) \ + i386_pe_asm_file_end (FILE) + +#undef ASM_COMMENT_START +#define ASM_COMMENT_START " #" + +/* DWARF2 Unwinding doesn't work with exception handling yet. */ +#define DWARF2_UNWIND_INFO 0 + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +/* External function declarations. */ + +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif + +#ifdef BUFSIZ /* stdio.h has been included, ok to use FILE * */ +#define STDIO_PROTO(ARGS) PROTO(ARGS) +#else +#define STDIO_PROTO(ARGS) () +#endif + +extern void i386_pe_record_external_function PROTO((char *)); +extern void i386_pe_declare_function_type STDIO_PROTO((FILE *, char *, int)); +extern void i386_pe_asm_file_end STDIO_PROTO((FILE *)); + +/* For Win32 ABI compatibility */ +#undef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 0 + diff --git a/contrib/gcc/config/i386/freebsd.h b/contrib/gcc/config/i386/freebsd.h index c1b41a55d6aac..17e5b6e8ba819 100644 --- a/contrib/gcc/config/i386/freebsd.h +++ b/contrib/gcc/config/i386/freebsd.h @@ -23,7 +23,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/i386/freebsd.h,v 1.34 2000/01/29 13:06:32 obrien Exp $ */ #undef TARGET_VERSION diff --git a/contrib/gcc/config/i386/freebsd.h.fixed b/contrib/gcc/config/i386/freebsd.h.fixed deleted file mode 100644 index c1b41a55d6aac..0000000000000 --- a/contrib/gcc/config/i386/freebsd.h.fixed +++ /dev/null @@ -1,584 +0,0 @@ -/* Definitions for Intel 386 running FreeBSD with either a.out or ELF format - Copyright (C) 1996 Free Software Foundation, Inc. - Contributed by Eric Youngdale. - Modified for stabs-in-ELF by H.J. Lu. - Adapted from GNU/Linux version by John Polstra. - Added support for generating "old a.out gas" on the fly by Peter Wemm. - Continued development by David O'Brien - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* $FreeBSD$ */ - - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (i386 FreeBSD/ELF)"); - -#define MASK_PROFILER_EPILOGUE 010000000000 -#define MASK_AOUT 004000000000 /* a.out not elf */ -#define MASK_UNDERSCORES 002000000000 /* use leading _ */ - -#define TARGET_PROFILER_EPILOGUE (target_flags & MASK_PROFILER_EPILOGUE) -#define TARGET_AOUT (target_flags & MASK_AOUT) -#define TARGET_ELF ((target_flags & MASK_AOUT) == 0) -#define TARGET_UNDERSCORES ((target_flags & MASK_UNDERSCORES) != 0) - -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES \ - { "profiler-epilogue", MASK_PROFILER_EPILOGUE}, \ - { "no-profiler-epilogue", -MASK_PROFILER_EPILOGUE}, \ - { "aout", MASK_AOUT}, \ - { "no-aout", -MASK_AOUT}, \ - { "underscores", MASK_UNDERSCORES}, \ - { "no-underscores", -MASK_UNDERSCORES}, - -/* Prefix for internally generated assembler labels. If we aren't using - underscores, we are using prefix `.'s to identify labels that should - be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ -#undef LPREFIX -#define LPREFIX ((TARGET_UNDERSCORES) ? "L" : ".L") - -/* Override the default comment-starter of "/". */ -#undef ASM_COMMENT_START -#define ASM_COMMENT_START "#" - -#undef ASM_APP_ON -#define ASM_APP_ON "#APP\n" - -#undef ASM_APP_OFF -#define ASM_APP_OFF "#NO_APP\n" - -#undef SET_ASM_OP -#define SET_ASM_OP ".set" - -/* Output at beginning of assembler file. */ -/* The .file command should always begin the output. */ - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ - do { \ - output_file_directive ((FILE), main_input_filename); \ - if (TARGET_ELF) \ - fprintf ((FILE), "\t.version\t\"01.01\"\n"); \ - } while (0) - -/* Identify the front-end which produced this file. To keep symbol - space down, and not confuse kdb, only do this if the language is - not C. (svr4.h defines ASM_IDENTIFY_GCC but neglects this) */ -#undef ASM_IDENTIFY_LANGUAGE -#define ASM_IDENTIFY_LANGUAGE(STREAM) \ -{ \ - if (strcmp (lang_identify (), "c") != 0) \ - output_lang_identify (STREAM); \ -} - -/* This is how to store into the string BUF - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. */ -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ - sprintf ((BUF), "*%s%s%d", (TARGET_UNDERSCORES) ? "" : ".", \ - (PREFIX), (NUMBER)) - -/* This is how to output an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. */ -#undef ASM_OUTPUT_INTERNAL_LABEL -#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ - fprintf ((FILE), "%s%s%d:\n", (TARGET_UNDERSCORES) ? "" : ".", \ - (PREFIX), (NUM)) - -/* This is how to hack on the symbol code of certain relcalcitrant - symbols to modify their output in output_pic_addr_const (). */ - -#undef ASM_HACK_SYMBOLREF_CODE -#define ASM_HACK_SYMBOLREF_CODE(NAME, CODE) \ -do { \ - /* Part of hack to avoid writing lots of rtl in \ - FUNCTION_PROFILER_EPILOGUE (). */ \ - char *_name = (NAME); \ - if (*_name == '.' && strcmp(_name + 1, "mexitcount") == 0) \ - (CODE) = 'X'; \ -} while (0) - -/* This is how to output a reference to a user-level label named NAME. */ - -#undef ASM_OUTPUT_LABELREF -#define ASM_OUTPUT_LABELREF(FILE, NAME) \ -do { \ - char *_name = (NAME); \ - /* Hack to avoid writing lots of rtl in \ - FUNCTION_PROFILER_EPILOGUE (). */ \ - if (*_name == '.' && strcmp(_name + 1, "mexitcount") == 0) \ - { \ - if (TARGET_AOUT) \ - _name++; \ - if (flag_pic) \ - fprintf ((FILE), "*%s@GOT(%%ebx)", _name); \ - else \ - fprintf ((FILE), "%s", _name); \ - } \ - else \ - fprintf (FILE, "%s%s", TARGET_UNDERSCORES ? "_" : "", _name); \ -} while (0) - -/* This is how to output an element of a case-vector that is relative. - This is only used for PIC code. See comments by the `casesi' insn in - i386.md for an explanation of the expression this outputs. */ -#undef ASM_OUTPUT_ADDR_DIFF_ELT -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - fprintf ((FILE), "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, (VALUE)) - -#undef ASM_OUTPUT_ALIGN -#define ASM_OUTPUT_ALIGN(FILE, LOG) \ - if ((LOG)!=0) { \ - if (in_text_section()) \ - fprintf ((FILE), "\t.p2align %d,0x90\n", (LOG)); \ - else \ - fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ - } - -/* conditionalize the use of ".section rodata" on elf mode - otherwise .text */ -#undef USE_CONST_SECTION -#define USE_CONST_SECTION TARGET_ELF - -/* The a.out tools do not support "linkonce" sections. */ -#undef SUPPORTS_ONE_ONLY -#define SUPPORTS_ONE_ONLY TARGET_ELF - -/* The a.out tools do not support "Lscope" .stabs symbols. */ -#undef NO_DBX_FUNCTION_END -#define NO_DBX_FUNCTION_END TARGET_AOUT - -/* A C statement (sans semicolon) to output an element in the table of - global constructors. */ -#undef ASM_OUTPUT_CONSTRUCTOR -#define ASM_OUTPUT_CONSTRUCTOR(FILE, NAME) \ - do { \ - if (TARGET_ELF) { \ - ctors_section (); \ - fprintf ((FILE), "\t%s\t ", INT_ASM_OP); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), "\n"); \ - } else { \ - fprintf (asm_out_file, "%s \"%s__CTOR_LIST__\",22,0,0,", ASM_STABS_OP, \ - (TARGET_UNDERSCORES) ? "_" : ""); \ - assemble_name (asm_out_file, name); \ - fputc ('\n', asm_out_file); \ - } \ - } while (0) - -/* A C statement (sans semicolon) to output an element in the table of - global destructors. */ -#undef ASM_OUTPUT_DESTRUCTOR -#define ASM_OUTPUT_DESTRUCTOR(FILE, NAME) \ - do { \ - if (TARGET_ELF) { \ - dtors_section (); \ - fprintf ((FILE), "\t%s\t ", INT_ASM_OP); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), "\n"); \ - } else { \ - fprintf (asm_out_file, "%s \"%s__DTOR_LIST__\",22,0,0,", ASM_STABS_OP, \ - (TARGET_UNDERSCORES) ? "_" : ""); \ - assemble_name (asm_out_file, name); \ - fputc ('\n', asm_out_file); \ - } \ - } while (0) - -/* This says how to output assembler code to declare an - uninitialized internal linkage data object. Under SVR4, - the linker seems to want the alignment of data objects - to depend on their types. We do exactly that here. */ - -#undef ASM_OUTPUT_ALIGNED_LOCAL -#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ -do { \ - if (TARGET_ELF) { \ - fprintf ((FILE), "\t%s\t", LOCAL_ASM_OP); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), "\n"); \ - ASM_OUTPUT_ALIGNED_COMMON ((FILE), (NAME), (SIZE), (ALIGN)); \ - } else { \ - int rounded = (SIZE); \ - if (rounded == 0) rounded = 1; \ - rounded += (BIGGEST_ALIGNMENT / BITS_PER_UNIT) - 1; \ - rounded = (rounded / (BIGGEST_ALIGNMENT / BITS_PER_UNIT) \ - * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); \ - fputs (".lcomm ", (FILE)); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ",%u\n", (rounded)); \ - } \ -} while (0) - -#undef ASM_OUTPUT_ALIGNED_COMMON -#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ -do { \ - if (TARGET_ELF) { \ - fprintf ((FILE), "\t%s\t", COMMON_ASM_OP); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \ - } else { \ - int rounded = (SIZE); \ - if (rounded == 0) rounded = 1; \ - rounded += (BIGGEST_ALIGNMENT / BITS_PER_UNIT) - 1; \ - rounded = (rounded / (BIGGEST_ALIGNMENT / BITS_PER_UNIT) \ - * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); \ - fputs (".comm ", (FILE)); \ - assemble_name ((FILE), (NAME)); \ - fprintf ((FILE), ",%u\n", (rounded)); \ - } \ -} while (0) - -/* Turn off svr4.h version, it chokes the old gas. The old layout - works fine under new gas anyway. */ -#undef ASM_OUTPUT_ASCII - -/* How to output some space */ -#undef ASM_OUTPUT_SKIP -#define ASM_OUTPUT_SKIP(FILE, SIZE) \ -do { \ - if (TARGET_ELF) { \ - fprintf ((FILE), "\t%s\t%u\n", SKIP_ASM_OP, (SIZE)); \ - } else { \ - fprintf ((FILE), "\t.space %u\n", (SIZE)); \ - } \ -} while (0) - -#undef ASM_OUTPUT_SOURCE_LINE -#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ -do { \ - static int sym_lineno = 1; \ - if (TARGET_ELF) { \ - fprintf ((FILE), ".stabn 68,0,%d,.LM%d-", (LINE), sym_lineno); \ - assemble_name ((FILE), XSTR (XEXP (DECL_RTL (current_function_decl),\ - 0), 0)); \ - fprintf ((FILE), "\n.LM%d:\n", sym_lineno); \ - sym_lineno += 1; \ - } else { \ - fprintf ((FILE), "\t%s %d,0,%d\n", ASM_STABD_OP, N_SLINE, lineno); \ - } \ -} while (0) - -/* in elf, the function stabs come first, before the relative offsets */ -#undef DBX_FUNCTION_FIRST -#define DBX_CHECK_FUNCTION_FIRST TARGET_ELF - -/* tag end of file in elf mode */ -#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END -#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \ -do { \ - if (TARGET_ELF) { \ - fprintf ((FILE), "\t.text\n\t.stabs \"\",%d,0,0,.Letext\n.Letext:\n", \ - N_SO); \ - } \ -} while (0) - -/* stabs-in-elf has offsets relative to function beginning */ -#undef DBX_OUTPUT_LBRAC -#define DBX_OUTPUT_LBRAC(FILE, NAME) \ -do { \ - fprintf (asmfile, "%s %d,0,0,", ASM_STABN_OP, N_LBRAC); \ - assemble_name (asmfile, buf); \ - if (TARGET_ELF) { \ - fputc ('-', asmfile); \ - assemble_name (asmfile, XSTR (XEXP (DECL_RTL (current_function_decl),\ - 0), 0)); \ - } \ - fprintf (asmfile, "\n"); \ -} while (0) - -#undef DBX_OUTPUT_RBRAC -#define DBX_OUTPUT_RBRAC(FILE, NAME) \ -do { \ - fprintf (asmfile, "%s %d,0,0,", ASM_STABN_OP, N_RBRAC); \ - assemble_name (asmfile, buf); \ - if (TARGET_ELF) { \ - fputc ('-', asmfile); \ - assemble_name (asmfile, XSTR (XEXP (DECL_RTL (current_function_decl),\ - 0), 0)); \ - } \ - fprintf (asmfile, "\n"); \ -} while (0) - - -/* Define macro used to output shift-double opcodes when the shift - count is in %cl. Some assemblers require %cl as an argument; - some don't. - - *OLD* GAS requires the %cl argument, so override i386/unix.h. */ - -#undef AS3_SHIFT_DOUBLE -#define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) - -/* Indicate that jump tables go in the text section. This is - necessary when compiling PIC code. */ -#undef JUMP_TABLES_IN_TEXT_SECTION -#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) - -/* override the exception table positioning */ -#undef EXCEPTION_SECTION -#define EXCEPTION_SECTION() \ -do { \ - if (TARGET_ELF) { \ - named_section (NULL_TREE, ".gcc_except_table", 0); \ - } else { \ - if (flag_pic) \ - data_section (); \ - else \ - readonly_data_section (); \ - } \ -} while (0); - -/* supply our own hook for calling __main() from main() */ -#undef INVOKE__main -#define INVOKE__main -#undef GEN_CALL__MAIN -#define GEN_CALL__MAIN \ - do { \ - if (!(TARGET_ELF)) \ - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, NAME__MAIN), 0, \ - VOIDmode, 0); \ - } while (0) - -/* Copy this from the svr4 specifications... */ -/* Define the register numbers to be used in Dwarf debugging information. - The SVR4 reference port C compiler uses the following register numbers - in its Dwarf output code: - 0 for %eax (gnu regno = 0) - 1 for %ecx (gnu regno = 2) - 2 for %edx (gnu regno = 1) - 3 for %ebx (gnu regno = 3) - 4 for %esp (gnu regno = 7) - 5 for %ebp (gnu regno = 6) - 6 for %esi (gnu regno = 4) - 7 for %edi (gnu regno = 5) - The following three DWARF register numbers are never generated by - the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 - believes these numbers have these meanings. - 8 for %eip (no gnu equivalent) - 9 for %eflags (no gnu equivalent) - 10 for %trapno (no gnu equivalent) - It is not at all clear how we should number the FP stack registers - for the x86 architecture. If the version of SDB on x86/svr4 were - a bit less brain dead with respect to floating-point then we would - have a precedent to follow with respect to DWARF register numbers - for x86 FP registers, but the SDB on x86/svr4 is so completely - broken with respect to FP registers that it is hardly worth thinking - of it as something to strive for compatibility with. - The version of x86/svr4 SDB I have at the moment does (partially) - seem to believe that DWARF register number 11 is associated with - the x86 register %st(0), but that's about all. Higher DWARF - register numbers don't seem to be associated with anything in - particular, and even for DWARF regno 11, SDB only seems to under- - stand that it should say that a variable lives in %st(0) (when - asked via an `=' command) if we said it was in DWARF regno 11, - but SDB still prints garbage when asked for the value of the - variable in question (via a `/' command). - (Also note that the labels SDB prints for various FP stack regs - when doing an `x' command are all wrong.) - Note that these problems generally don't affect the native SVR4 - C compiler because it doesn't allow the use of -O with -g and - because when it is *not* optimizing, it allocates a memory - location for each floating-point variable, and the memory - location is what gets described in the DWARF AT_location - attribute for the variable in question. - Regardless of the severe mental illness of the x86/svr4 SDB, we - do something sensible here and we use the following DWARF - register numbers. Note that these are all stack-top-relative - numbers. - 11 for %st(0) (gnu regno = 8) - 12 for %st(1) (gnu regno = 9) - 13 for %st(2) (gnu regno = 10) - 14 for %st(3) (gnu regno = 11) - 15 for %st(4) (gnu regno = 12) - 16 for %st(5) (gnu regno = 13) - 17 for %st(6) (gnu regno = 14) - 18 for %st(7) (gnu regno = 15) -*/ -#undef DWARF_DBX_REGISTER_NUMBER -#define DWARF_DBX_REGISTER_NUMBER(n) \ -((n) == 0 ? 0 \ - : (n) == 1 ? 2 \ - : (n) == 2 ? 1 \ - : (n) == 3 ? 3 \ - : (n) == 4 ? 6 \ - : (n) == 5 ? 7 \ - : (n) == 6 ? 5 \ - : (n) == 7 ? 4 \ - : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ - : (-1)) - -/* Now what stabs expects in the register. */ -#undef STABS_DBX_REGISTER_NUMBER -#define STABS_DBX_REGISTER_NUMBER(n) \ -((n) == 0 ? 0 : \ - (n) == 1 ? 2 : \ - (n) == 2 ? 1 : \ - (n) == 3 ? 3 : \ - (n) == 4 ? 6 : \ - (n) == 5 ? 7 : \ - (n) == 6 ? 4 : \ - (n) == 7 ? 5 : \ - (n) + 4) - -#undef DBX_REGISTER_NUMBER -#define DBX_REGISTER_NUMBER(n) ((write_symbols == DWARF_DEBUG) \ - ? DWARF_DBX_REGISTER_NUMBER(n) \ - : STABS_DBX_REGISTER_NUMBER(n)) - -/* Tell final.c that we don't need a label passed to mcount. */ -#define NO_PROFILE_DATA - -/* Output assembler code to FILE to begin profiling of the current function. - LABELNO is an optional label. */ - -#undef FUNCTION_PROFILER -#define FUNCTION_PROFILER(FILE, LABELNO) \ -do { \ - char *_name = TARGET_AOUT ? "mcount" : ".mcount"; \ - if (flag_pic) \ - fprintf ((FILE), "\tcall *%s@GOT(%%ebx)\n", _name); \ - else \ - fprintf ((FILE), "\tcall %s\n", _name); \ -} while (0) - -/* Output assembler code to FILE to end profiling of the current function. */ - -#undef FUNCTION_PROFILER_EPILOGUE -#define FUNCTION_PROFILER_EPILOGUE(FILE, DO_RTL) \ -do { \ - if (TARGET_PROFILER_EPILOGUE) \ - { \ - if (DO_RTL) \ - { \ - /* ".mexitcount" is specially handled in \ - ASM_HACK_SYMBOLREF () so that we don't need to handle \ - flag_pic or TARGET_AOUT here. */ \ - rtx xop; \ - xop = gen_rtx_MEM (FUNCTION_MODE, \ - gen_rtx_SYMBOL_REF (Pmode, ".mexitcount")); \ - emit_call_insn (gen_rtx (CALL, VOIDmode, xop, const0_rtx)); \ - } \ - else \ - { \ - /* XXX this !DO_RTL case is broken but not actually used. */ \ - char *_name = TARGET_AOUT ? "mcount" : ".mcount"; \ - if (flag_pic) \ - fprintf (FILE, "\tcall *%s@GOT(%%ebx)\n", _name); \ - else \ - fprintf (FILE, "\tcall %s\n", _name); \ - } \ - } \ -} while (0) - -#undef SIZE_TYPE -#define SIZE_TYPE "unsigned int" - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "int" - -#undef WCHAR_TYPE -#define WCHAR_TYPE "int" - -#undef WCHAR_UNSIGNED -#define WCHAR_UNSIGNED 0 - -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE BITS_PER_WORD - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Di386 -Acpu(i386) -Amachine(i386)" CPP_FBSD_PREDEFINES - -#undef CC1_SPEC -#define CC1_SPEC "\ -%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ -%{maout: %{!mno-underscores: %{!munderscores: -munderscores }}}" - -#undef ASM_SPEC -#define ASM_SPEC "%{v*: -v} %{maout: %{fpic:-k} %{fPIC:-k}}" - -/* Provide a LINK_SPEC appropriate for FreeBSD. Here we provide support - for the special GCC options -static and -shared, which allow us to - link things in one of these three modes by applying the appropriate - combinations of options at link-time. We like to support here for - as many of the other GNU linker options as possible. But I don't - have the time to search for those flags. I am sure how to add - support for -soname shared_object_name. H.J. - - I took out %{v:%{!V:-V}}. It is too much :-(. They can use - -Wl,-V. - - When the -shared link option is used a final link is not being - done. */ - -#undef LINK_SPEC -#define LINK_SPEC "\ - %{p:%e`-p' not supported; use `-pg' and gprof(1)} \ - %{maout: %{shared:-Bshareable} \ - %{!shared:%{!nostdlib:%{!r:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} \ - %{pg:-Bstatic} %{Z}} \ - %{assert*} %{R*}} \ - %{!maout: \ - -m elf_i386 \ - %{Wl,*:%*} \ - %{assert*} %{R*} %{rpath*} %{defsym*} \ - %{shared:-Bshareable %{h*} %{soname*}} \ - %{symbolic:-Bsymbolic} \ - %{!shared: \ - %{!static: \ - %{rdynamic: -export-dynamic} \ - %{!dynamic-linker: -dynamic-linker /usr/libexec/ld-elf.so.1}} \ - %{static:-Bstatic}}}" - -/* A C statement to output to the stdio stream FILE an assembler - command to advance the location counter to a multiple of 1< #include "config.h" diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h index e492e04101eee..92f2f92aacecc 100644 --- a/contrib/gcc/config/i386/i386.h +++ b/contrib/gcc/config/i386/i386.h @@ -34,7 +34,7 @@ Boston, MA 02111-1307, USA. */ PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/i386/i386.h,v 1.5 1999/10/16 08:10:36 obrien Exp $ */ /* Names to predefine in the preprocessor for this target machine. */ diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md index b18c700e09927..583dfb3dc3444 100644 --- a/contrib/gcc/config/i386/i386.md +++ b/contrib/gcc/config/i386/i386.md @@ -71,7 +71,7 @@ ;; This shadows the processor_type enumeration, so changes must be made ;; to i386.h at the same time. -;; $FreeBSD$ +;; $FreeBSD: src/contrib/gcc/config/i386/i386.md,v 1.7 2000/01/22 16:31:39 obrien Exp $ (define_attr "type" "integer,binary,memory,test,compare,fcompare,idiv,imul,lea,fld,fpop,fpdiv,fpmul" diff --git a/contrib/gcc/config/i386/i386iscgas.h b/contrib/gcc/config/i386/i386iscgas.h new file mode 100644 index 0000000000000..526fe374e481d --- /dev/null +++ b/contrib/gcc/config/i386/i386iscgas.h @@ -0,0 +1,67 @@ +/* Definitions for Intel 386 running Interactive Unix System V, + producing stabs-in-coff output (using a slightly modified gas). + Specifically, this is for recent versions that support POSIX; + for version 2.0.2, use configuration option i386-sysv instead. */ + +/* Underscores are not used on ISC systems (probably not on any COFF + system), despite the comments in i386/gas.h. If this is not defined, + enquire (for example) will fail to link. --karl@cs.umb.edu */ +#define NO_UNDERSCORES + +/* Mostly like other gas-using systems. */ +#include "i386/gas.h" + +/* But with ISC-specific additions. */ +#include "i386/isc.h" + +/* We do not want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + + +/* The function `dbxout_init' in dbxout.c omits the first character of + `ltext_label_name' when outputting the main source directory and main + source filename. I don't understand why, but rather than making a + system-independent change there, I override dbxout.c's defaults. + Perhaps it would be better to use ".Ltext0" instead of + `ltext_label_name', but we've already generated the label, so we just + use it here. --karl@cs.umb.edu */ +#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(asmfile, cwd) \ + do { fprintf (asmfile, "%s ", ASM_STABS_OP); \ + output_quoted_string (asmfile, cwd); \ + fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ + } while (0) +#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(asmfile, input_file_name) \ + fprintf (asmfile, "%s ", ASM_STABS_OP); \ + output_quoted_string (input_file_name); \ + fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ + text_section (); \ + ASM_OUTPUT_INTERNAL_LABEL (asmfile, "Ltext", 0) + + +/* Because we don't include `svr3.h', we haven't yet defined SIZE_TYPE + and PTRDIFF_TYPE. ISC's definitions don't match GCC's defaults, so: */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + + +/* But we can't use crtbegin.o and crtend.o, because gas 1.38.1 doesn't + grok .section. The definitions here are otherwise identical to those + in i386/isc.h. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ + %{!posix:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\ + %{p:-L/lib/libp} %{pg:-L/lib/libp}}}\ + %{shlib:%{posix:crtp1.o%s}%{!posix:crt1.o%s}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtn.o%s" diff --git a/contrib/gcc/config/i386/next.c b/contrib/gcc/config/i386/next.c new file mode 100644 index 0000000000000..f249647ab5953 --- /dev/null +++ b/contrib/gcc/config/i386/next.c @@ -0,0 +1,7 @@ +/* next.c: Functions for NeXT as target machine for GNU C compiler. */ + +/* Note that the include below means that we can't debug routines in + i386.c when running on a COFF system. */ + +#include "i386/i386.c" +#include "nextstep.c" diff --git a/contrib/gcc/config/i386/sol2dbg.h b/contrib/gcc/config/i386/sol2dbg.h new file mode 100644 index 0000000000000..9f95333b4b993 --- /dev/null +++ b/contrib/gcc/config/i386/sol2dbg.h @@ -0,0 +1,27 @@ +/* Target definitions for GNU compiler for Intel 80386 running Solaris + with gas and gdb. + This file is added into the directory .../gcc-2.../config/i386 + Workability without "#undef DWARF_DEBUGGING_INFO" is not tested. */ + +/* Use stabs instead of DWARF debug format. */ +#ifdef PREFERRED_DEBUGGING_TYPE +#undef PREFERRED_DEBUGGING_TYPE +#endif +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "i386/sol2.h" + +#ifdef DWARF_DEBUGGING_INFO +#undef DWARF_DEBUGGING_INFO +#endif + +/* + Changed from config/svr4.h in the following ways: + + - Added "%{V}". + - Modified "{%v:-V}" to take into account "%{V}". + - Added "-s" so that stabs are saved in the final executable. */ + +#undef ASM_SPEC +#define ASM_SPEC \ + "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} -s" diff --git a/contrib/gcc/config/i386/sysv4gdb.h b/contrib/gcc/config/i386/sysv4gdb.h new file mode 100644 index 0000000000000..dd1e8f256f35a --- /dev/null +++ b/contrib/gcc/config/i386/sysv4gdb.h @@ -0,0 +1,7 @@ +/* Target definitions for GNU compiler for Intel 80386 running System V.4 + with gas and gdb. */ + +/* Use stabs instead of DWARF debug format. */ +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "i386/sysv4.h" diff --git a/contrib/gcc/config/i386/t-cygwin32 b/contrib/gcc/config/i386/t-cygwin32 new file mode 100644 index 0000000000000..20bc9803b1ecd --- /dev/null +++ b/contrib/gcc/config/i386/t-cygwin32 @@ -0,0 +1,16 @@ +LIBGCC1 = libgcc1-asm.a +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = i386/cygwin32.asm +LIB1ASMFUNCS = _chkstk + +# cygwin32 always has a limits.h, but, depending upon how we are doing +# the build, it may not be installed yet. +LIMITS_H_TEST = true + +# If we are building next to winsup, this will let us find the real +# limits.h when building libgcc2. Otherwise, winsup must be installed +# first. +LIBGCC2_INCLUDES = -I$(srcdir)/../winsup/include + +winnt.o: $(srcdir)/config/i386/winnt.c + $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/i386/winnt.c diff --git a/contrib/gcc/config/i386/t-go32 b/contrib/gcc/config/i386/t-go32 new file mode 100644 index 0000000000000..6160b7ec945d4 --- /dev/null +++ b/contrib/gcc/config/i386/t-go32 @@ -0,0 +1,2 @@ +LIBGCC1 = libgcc1.null +CROSS_LIBGCC1 = libgcc1.null diff --git a/contrib/gcc/config/i386/t-iscscodbx b/contrib/gcc/config/i386/t-iscscodbx new file mode 100644 index 0000000000000..928a7589f8c93 --- /dev/null +++ b/contrib/gcc/config/i386/t-iscscodbx @@ -0,0 +1,2 @@ +# The one that comes with the system is POSIX-compliant. +LIMITS_H = diff --git a/contrib/gcc/config/i386/x-cygwin32 b/contrib/gcc/config/i386/x-cygwin32 new file mode 100644 index 0000000000000..f251835bd3328 --- /dev/null +++ b/contrib/gcc/config/i386/x-cygwin32 @@ -0,0 +1,4 @@ +# Don't run fixproto +STMP_FIXPROTO = +# prefix.c wants to poke around the Registry +CLIB = -ladvapi32 diff --git a/contrib/gcc/config/i386/x-freebsd b/contrib/gcc/config/i386/x-freebsd new file mode 100644 index 0000000000000..47640c0a2c0de --- /dev/null +++ b/contrib/gcc/config/i386/x-freebsd @@ -0,0 +1,4 @@ +# Don't run fixproto +STMP_FIXPROTO = +# Use only native include files +USER_H = diff --git a/contrib/gcc/config/i386/xm-cygwin32.h b/contrib/gcc/config/i386/xm-cygwin32.h new file mode 100644 index 0000000000000..521a653099121 --- /dev/null +++ b/contrib/gcc/config/i386/xm-cygwin32.h @@ -0,0 +1,55 @@ +/* Configuration for GNU C-compiler for hosting on Windows NT. + using a unix style C library. + Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define EXECUTABLE_SUFFIX ".exe" +#define NO_SYS_SIGLIST 1 +#define HAVE_BCOPY 1 +#define HAVE_BZERO 1 +#define HAVE_BCMP 1 +#define HAVE_RINDEX 1 +#define HAVE_INDEX 1 + +/* Even though we support "/", allow "\" since everybody tests both. */ +#define DIR_SEPARATOR '\\' + +/* If we allow both '/' and '\' as dir separators, then + allow both unix and win32 PATH syntax */ +#undef GET_ENVIRONMENT +#define GET_ENVIRONMENT(ENV_VALUE,ENV_NAME) \ +{ \ + char *epath; \ + char *win32epath; \ + \ + epath = win32epath = getenv (ENV_NAME); \ + /* if we have a posix path list, convert to win32 path list */ \ + if (epath != NULL && *epath != 0 && cygwin32_posix_path_list_p (epath)) \ + { \ + win32epath = (char *) xmalloc \ + (cygwin32_posix_to_win32_path_list_buf_size (epath)); \ + cygwin32_posix_to_win32_path_list (epath, win32epath); \ + } \ + ENV_VALUE = win32epath; \ +} + +#define PATH_SEPARATOR ';' + +/* This is needed so that protoize will compile. */ +#define POSIX diff --git a/contrib/gcc/config/i386/xm-go32.h b/contrib/gcc/config/i386/xm-go32.h new file mode 100644 index 0000000000000..c44e73ea4211e --- /dev/null +++ b/contrib/gcc/config/i386/xm-go32.h @@ -0,0 +1,33 @@ +/* Configuration for GNU C-compiler for Intel 80386 running GO32. + Copyright (C) 1988, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define __MSDOS__ 1 + +#include "i386/xm-i386.h" + +/* Use semicolons to separate elements of a path. */ +#define PATH_SEPARATOR ';' + +#define EXECUTABLE_SUFFIX ".exe" + +/* Even though we support "/", allow "\" since everybody tests both. */ +#define DIR_SEPARATOR '\\' + +#define NO_SYS_SIGLIST 1 diff --git a/contrib/gcc/config/i386/xm-netbsd.h b/contrib/gcc/config/i386/xm-netbsd.h new file mode 100644 index 0000000000000..3a9f324199079 --- /dev/null +++ b/contrib/gcc/config/i386/xm-netbsd.h @@ -0,0 +1,4 @@ +/* Configuration for GCC for Intel i386 running NetBSD as host. */ + +#include +#include diff --git a/contrib/gcc/config/mips/abi64.h b/contrib/gcc/config/mips/abi64.h new file mode 100644 index 0000000000000..ce1e5fe3831fe --- /dev/null +++ b/contrib/gcc/config/mips/abi64.h @@ -0,0 +1,250 @@ +/* Definitions of target machine for GNU compiler. 64 bit ABI support. + Copyright (C) 1994, 1995, 1996, 1998, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Macros to implement the 64 bit ABI. This file is meant to be included + after mips.h. */ + +#undef SUBTARGET_TARGET_OPTIONS +#define SUBTARGET_TARGET_OPTIONS \ + { "abi=", &mips_abi_string, \ + "Speciy ABI to use"}, + +#undef STACK_BOUNDARY +#define STACK_BOUNDARY \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \ + ? 64 : 128) + +#undef MIPS_STACK_ALIGN +#define MIPS_STACK_ALIGN(LOC) \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \ + ? ((LOC) + 7) & ~7 \ + : ((LOC) + 15) & ~15) + +#undef GP_ARG_LAST +#define GP_ARG_LAST ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? GP_REG_FIRST + 7 : GP_REG_FIRST + 11) +#undef FP_ARG_LAST +#define FP_ARG_LAST ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? FP_REG_FIRST + 15 : FP_REG_FIRST + 19) + +#undef SUBTARGET_CONDITIONAL_REGISTER_USAGE +#define SUBTARGET_CONDITIONAL_REGISTER_USAGE \ +{ \ + /* fp20-23 are now caller saved. */ \ + if (mips_abi == ABI_64) \ + { \ + int regno; \ + for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) \ + call_used_regs[regno] = 1; \ + } \ + /* odd registers from fp21 to fp31 are now caller saved. */ \ + if (mips_abi == ABI_N32) \ + { \ + int regno; \ + for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) \ + call_used_regs[regno] = 1; \ + } \ +} + +#undef MAX_ARGS_IN_REGISTERS +#define MAX_ARGS_IN_REGISTERS ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? 4 : 8) + +#undef REG_PARM_STACK_SPACE +#define REG_PARM_STACK_SPACE(FNDECL) \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? (MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \ + : 0) + +#define FUNCTION_ARG_PADDING(MODE, TYPE) \ + (! BYTES_BIG_ENDIAN \ + ? upward \ + : (((MODE) == BLKmode \ + ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ + && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\ + : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \ + && (mips_abi == ABI_32 \ + || mips_abi == ABI_O64 \ + || mips_abi == ABI_EABI \ + || GET_MODE_CLASS (MODE) == MODE_INT))) \ + ? downward : upward)) + +#undef RETURN_IN_MEMORY +#define RETURN_IN_MEMORY(TYPE) \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? TYPE_MODE (TYPE) == BLKmode \ + : (int_size_in_bytes (TYPE) \ + > (mips_abi == ABI_EABI ? 2 * UNITS_PER_WORD : 16))) + +extern struct rtx_def *mips_function_value (); +#undef FUNCTION_VALUE +#define FUNCTION_VALUE(VALTYPE, FUNC) mips_function_value (VALTYPE, FUNC) + +/* For varargs, we must save the current argument, because it is the fake + argument va_alist, and will need to be converted to the real argument. + For stdarg, we do not need to save the current argument, because it + is a real argument. */ +#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ +{ int mips_off = (! current_function_varargs) && (! (CUM).last_arg_fp); \ + int mips_fp_off = (! current_function_varargs) && ((CUM).last_arg_fp); \ + if (((mips_abi != ABI_32 && mips_abi != ABI_O64) \ + && (CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off) \ + || (mips_abi == ABI_EABI \ + && ! TARGET_SOFT_FLOAT \ + && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off)) \ + { \ + int mips_save_gp_regs = \ + MAX_ARGS_IN_REGISTERS - (CUM).arg_words - mips_off; \ + int mips_save_fp_regs = \ + (mips_abi != ABI_EABI ? 0 \ + : MAX_ARGS_IN_REGISTERS - (CUM).fp_arg_words - mips_fp_off); \ + \ + if (mips_save_gp_regs < 0) \ + mips_save_gp_regs = 0; \ + if (mips_save_fp_regs < 0) \ + mips_save_fp_regs = 0; \ + PRETEND_SIZE = ((mips_save_gp_regs * UNITS_PER_WORD) \ + + (mips_save_fp_regs * UNITS_PER_FPREG)); \ + \ + if (! (NO_RTL)) \ + { \ + if ((CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off) \ + { \ + rtx ptr, mem; \ + if (mips_abi != ABI_EABI) \ + ptr = virtual_incoming_args_rtx; \ + else \ + ptr = plus_constant (virtual_incoming_args_rtx, \ + - (mips_save_gp_regs \ + * UNITS_PER_WORD)); \ + mem = gen_rtx (MEM, BLKmode, ptr); \ + /* va_arg is an array access in this case, which causes \ + it to get MEM_IN_STRUCT_P set. We must set it here \ + so that the insn scheduler won't assume that these \ + stores can't possibly overlap with the va_arg loads. */ \ + if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN) \ + MEM_SET_IN_STRUCT_P (mem, 1); \ + move_block_from_reg \ + ((CUM).arg_words + GP_ARG_FIRST + mips_off, \ + mem, \ + mips_save_gp_regs, \ + mips_save_gp_regs * UNITS_PER_WORD); \ + } \ + if (mips_abi == ABI_EABI \ + && ! TARGET_SOFT_FLOAT \ + && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off) \ + { \ + enum machine_mode mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; \ + int size = GET_MODE_SIZE (mode); \ + int off; \ + int i; \ + /* We can't use move_block_from_reg, because it will use \ + the wrong mode. */ \ + off = - (mips_save_gp_regs * UNITS_PER_WORD); \ + if (! TARGET_SINGLE_FLOAT) \ + off &= ~ 7; \ + if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) \ + off -= (mips_save_fp_regs / 2) * size; \ + else \ + off -= mips_save_fp_regs * size; \ + for (i = 0; i < mips_save_fp_regs; i++) \ + { \ + rtx tem = \ + gen_rtx (MEM, mode, \ + plus_constant (virtual_incoming_args_rtx, \ + off)); \ + emit_move_insn (tem, \ + gen_rtx (REG, mode, \ + ((CUM).fp_arg_words \ + + FP_ARG_FIRST \ + + i \ + + mips_fp_off))); \ + off += size; \ + if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) \ + ++i; \ + } \ + } \ + } \ + } \ +} + +#define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64) + +/* A C expression that indicates when an argument must be passed by + reference. If nonzero for an argument, a copy of that argument is + made in memory and a pointer to the argument is passed instead of the + argument itself. The pointer is passed in whatever way is appropriate + for passing a pointer to that type. */ +#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ + (mips_abi == ABI_EABI \ + && function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)) + +/* A C expression that indicates when it is the called function's + responsibility to make a copy of arguments passed by invisible + reference. Normally, the caller makes a copy and passes the + address of the copy to the routine being called. When + FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller + does not make a copy. Instead, it passes a pointer to the "live" + value. The called function must not modify this value. If it can + be determined that the value won't be modified, it need not make a + copy; otherwise a copy must be made. + + ??? The MIPS EABI says that the caller should copy in ``K&R mode.'' + I don't know how to detect that here, since flag_traditional is not + a back end flag. */ +#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ + (mips_abi == ABI_EABI && (NAMED) \ + && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED)) + +/* Define LONG_MAX correctly for all users. We need to handle 32 bit EABI, + 64 bit EABI, N32, and N64 as possible defaults. The checks performed here + are the same as the checks in override_options in mips.c that determines + whether MASK_LONG64 will be set. + + This does not handle inappropriate options or ununusal option + combinations. */ + +#undef LONG_MAX_SPEC +#if ((MIPS_ABI_DEFAULT == ABI_64) || ((MIPS_ABI_DEFAULT == ABI_EABI) && ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_64BIT))) +#define LONG_MAX_SPEC \ + "%{!mabi=32:%{!mabi=n32:%{!mlong32:%{!mgp32:%{!mips1:%{!mips2:-D__LONG_MAX__=9223372036854775807L}}}}}}" +#else +#define LONG_MAX_SPEC \ + "%{mabi=64:-D__LONG_MAX__=9223372036854775807L} \ + %{mlong64:-D__LONG_MAX__=9223372036854775807L} \ + %{mgp64:-D__LONG_MAX__=9223372036854775807L}" +#endif + +/* ??? Unimplemented stuff follows. */ + +/* ??? Add support for 16 byte/128 bit long doubles here when + mips_abi != ABI32. */ + +/* ??? Make main return zero if user did not specify return value. */ + +/* ??? Add support for .interfaces section, so as to get linker warnings + when stdarg functions called without prototype in scope? */ + +/* ??? Could optimize structure passing by putting the right register rtx + into the field decl, so that if we use the field, we can take the value from + a register instead of from memory. */ + + + diff --git a/contrib/gcc/config/mips/bsd-4.h b/contrib/gcc/config/mips/bsd-4.h new file mode 100644 index 0000000000000..c2aee83df7b55 --- /dev/null +++ b/contrib/gcc/config/mips/bsd-4.h @@ -0,0 +1,46 @@ +/* Definitions of target machine for GNU compiler. MIPS RISC-OS BSD version. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_BSD43 + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ +-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/bsd43/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +-systype /bsd43/" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" + +#define MACHINE_TYPE "RISC-OS BSD Mips" + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/" diff --git a/contrib/gcc/config/mips/bsd-5.h b/contrib/gcc/config/mips/bsd-5.h new file mode 100644 index 0000000000000..f97af5e1f80d5 --- /dev/null +++ b/contrib/gcc/config/mips/bsd-5.h @@ -0,0 +1,67 @@ +/* Definitions of target machine for GNU compiler. + MIPS RISC-OS, 5.0 BSD version. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_BSD43 + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ +-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/bsd43/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \ +-systype /bsd43/" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" + +#define MACHINE_TYPE "RISC-OS BSD Mips" + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/" + +#include "mips/mips.h" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/cross64.h b/contrib/gcc/config/mips/cross64.h new file mode 100644 index 0000000000000..4462e5ecc55c9 --- /dev/null +++ b/contrib/gcc/config/mips/cross64.h @@ -0,0 +1,34 @@ +/* Configuration for an Irix 5 host and Irix 6 target using SGI's cross64 + package. */ + +#define STANDARD_INCLUDE_DIR "/usr/cross64/usr/include" +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/cross64/usr/bin/" +#undef MD_STARTFILE_PREFIX +#define MD_STARTFILE_PREFIX "/usr/cross64/usr/lib/lib64/" + +/* Must add TOOLROOT to the environment, or else the assembler will not + work. */ +#define INIT_ENVIRONMENT \ + "TOOLROOT=/usr/cross64" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{mips1:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \ + %{mips2:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \ + %{!mips1:%{!mips2:%{pg:/usr/cross64/usr/lib64/mips4/gcrt1.o} \ + %{!pg:%{p:/usr/cross64/usr/lib64/mips4/mcrt1.o \ + /usr/cross64/usr/lib64/mips4/libprof1.a} \ + %{!p:/usr/cross64/usr/lib64/mips4/crt1.o}}}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "%{mips1:crtn.o%s}%{mips2:crtn.o%s}%{!mips1:%{!mips2:/usr/cross64/usr/lib64/mips4/crtn.o}}" + +#undef LINK_SPEC +#define LINK_SPEC "\ +-64 -_SYSTYPE_SVR4 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}} \ +%{!mips1:%{!mips2:-L/usr/cross64/usr/lib64/mips4 -L/usr/cross64/usr/lib64}}" diff --git a/contrib/gcc/config/mips/dec-bsd.h b/contrib/gcc/config/mips/dec-bsd.h new file mode 100644 index 0000000000000..126353b25dd70 --- /dev/null +++ b/contrib/gcc/config/mips/dec-bsd.h @@ -0,0 +1,53 @@ +/* Definitions for DECstation running BSD as target machine for GNU compiler. + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define DECSTATION + +#ifndef CPP_PREDEFINES +#define CPP_PREDEFINES "-D__ANSI_COMPAT \ +-DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_4 -Dhost_mips -Dmips \ +-Dunix -D_mips -D_unix -D_host_mips -D_MIPSEL -D_R3000 \ +-Asystem(unix) -Asystem(bsd) -Amachine(mips)" +#endif + +/* Always uses GNU ld. */ +#ifndef LINK_SPEC +#define LINK_SPEC "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3}" +#endif + +#define LIB_SPEC "" +#define STARTFILE_SPEC "" + +#ifndef MACHINE_TYPE +#define MACHINE_TYPE "DECstation running BSD 4.4" +#endif + +#define TARGET_DEFAULT MASK_GAS +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "mips/mips.h" + +/* Since gas and gld are standard on 4.4 BSD, we don't need these */ +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX +#undef ASM_FINAL_SPEC +#undef LIB_SPEC +#undef STARTFILE_SPEC + diff --git a/contrib/gcc/config/mips/dec-osf1.h b/contrib/gcc/config/mips/dec-osf1.h new file mode 100644 index 0000000000000..ee7e787353c4a --- /dev/null +++ b/contrib/gcc/config/mips/dec-osf1.h @@ -0,0 +1,55 @@ +/* Definitions of target machine for GNU compiler. DECstation (OSF/1) version. + Copyright (C) 1992, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define DEC_OSF1 + +#define CPP_PREDEFINES "\ +-D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \ +-Dbsd4_2 -Dhost_mips -Dmips -Dosf -Dunix \ +-Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}" + +#include "mips/ultrix.h" +#include "mips/mips.h" + +/* Specify size_t and wchar_t types. */ +#undef SIZE_TYPE +#undef WCHAR_TYPE +#undef WCHAR_TYPE_SIZE + +#define SIZE_TYPE "long unsigned int" +#define WCHAR_TYPE "short unsigned int" +#define WCHAR_TYPE_SIZE SHORT_TYPE_SIZE + +#undef SUBTARGET_CPP_SIZE_SPEC +#define SUBTARGET_CPP_SIZE_SPEC "\ +%{mlong64:-D__PTRDIFF_TYPE__=long\\ int} \ +%{!mlong64:-D__PTRDIFF_TYPE__=int}" + +/* turn off collect2 COFF support, since ldfcn now has elf declaration */ +#undef OBJECT_FORMAT_COFF + +#undef MACHINE_TYPE +#define MACHINE_TYPE "DECstation running DEC OSF/1" diff --git a/contrib/gcc/config/mips/ecoff.h b/contrib/gcc/config/mips/ecoff.h new file mode 100644 index 0000000000000..dcc00a4b4b843 --- /dev/null +++ b/contrib/gcc/config/mips/ecoff.h @@ -0,0 +1,35 @@ +/* Definitions of target machine for GNU compiler. MIPS version with + GOFAST floating point library. + Copyright (C) 1994, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* US Software GOFAST library support. */ +#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS + +#include "mips/mips.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR3000 -D_mips -D_MIPSEB -D_R3000" + +/* Use memcpy, et. al., rather than bcopy. */ +#define TARGET_MEM_FUNCTIONS + +/* Don't assume anything about startfiles. The linker script will load the + appropriate startfiles. */ +#define STARTFILE_SPEC "" diff --git a/contrib/gcc/config/mips/ecoffl.h b/contrib/gcc/config/mips/ecoffl.h new file mode 100644 index 0000000000000..9fe90e8484806 --- /dev/null +++ b/contrib/gcc/config/mips/ecoffl.h @@ -0,0 +1,30 @@ +/* Definitions of target machine for GNU compiler. Little endian MIPS + version with GOFAST floating point library. + Copyright (C) 1994, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a little endian version of ecoff.h. */ + +#define TARGET_ENDIAN_DEFAULT 0 + +#include "gofast.h" +#include "mips/ecoff.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000" diff --git a/contrib/gcc/config/mips/elf.h b/contrib/gcc/config/mips/elf.h new file mode 100644 index 0000000000000..53af04690760e --- /dev/null +++ b/contrib/gcc/config/mips/elf.h @@ -0,0 +1,329 @@ +/* Definitions of target machine for GNU compiler. MIPS R3000 version with + GOFAST floating point library. + Copyright (C) 1994, 1997, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Use ELF. */ +#define OBJECT_FORMAT_ELF + +/* Until we figure out what MIPS ELF targets normally use, just do + stabs in ELF. */ +#ifndef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG +#endif + +/* Mostly like ECOFF. */ +#include "gofast.h" +#include "mips/ecoff.h" + +/* We need to use .esize and .etype instead of .size and .type to + avoid conflicting with ELF directives. */ +#undef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.esize\t%d;", (a)); \ +} while (0) + +#undef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ +} while (0) + +/* Biggest alignment supported by the object file format of this + machine. Use this macro to limit the alignment which can be + specified using the `__attribute__ ((aligned (N)))' construct. If + not defined, the default value is `BIGGEST_ALIGNMENT'. */ + +#define MAX_OFILE_ALIGNMENT (32768*8) + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. */ + +#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \ +do { \ + extern FILE *asm_out_text_file; \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME)); \ + else \ + fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME)); \ +} while (0) + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#undef TYPE_ASM_OP +#undef SIZE_ASM_OP +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare an object properly. */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + mips_declare_object (FILE, NAME, "", ":\n", 0); \ + } while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#undef ASM_FINISH_DECLARE_OBJECT +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fputc ( '\t', FILE); \ + assemble_name (FILE, LABEL1); \ + fputs ( " = ", FILE); \ + assemble_name (FILE, LABEL2); \ + fputc ( '\n', FILE); \ + } while (0) + +/* Note about .weak vs. .weakext + The mips native assemblers support .weakext, but not .weak. + mips-elf gas supports .weak, but not .weakext. + mips-elf gas has been changed to support both .weak and .weakext, + but until that support is generally available, the 'if' below + should serve. */ + +#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) +#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE) \ + do { \ + if (TARGET_GAS) \ + fputs ("\t.weak\t", FILE); \ + else \ + fputs ("\t.weakext\t", FILE); \ + assemble_name (FILE, NAME); \ + if (VALUE) \ + { \ + fputc (' ', FILE); \ + assemble_name (FILE, VALUE); \ + } \ + fputc ('\n', FILE); \ + } while (0) + +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) +#undef UNIQUE_SECTION_P +#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL)) +#define UNIQUE_SECTION(DECL,RELOC) \ +do { \ + int len, size, sec; \ + char *name, *string, *prefix; \ + static char *prefixes[4][2] = { \ + { ".text.", ".gnu.linkonce.t." }, \ + { ".rodata.", ".gnu.linkonce.r." }, \ + { ".data.", ".gnu.linkonce.d." }, \ + { ".sdata.", ".gnu.linkonce.s." } \ + }; \ + \ + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \ + size = int_size_in_bytes (TREE_TYPE (decl)); \ + \ + /* Determine the base section we are interested in: \ + 0=text, 1=rodata, 2=data, 3=sdata. */ \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + sec = 0; \ + else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16) \ + && TREE_CODE (decl) == STRING_CST \ + && !flag_writable_strings) \ + { \ + /* For embedded position independent code, put constant strings \ + in the text section, because the data section is limited to \ + 64K in size. For mips16 code, put strings in the text \ + section so that a PC relative load instruction can be used to \ + get their address. */ \ + sec = 0; \ + } \ + else if (TARGET_EMBEDDED_DATA) \ + { \ + /* For embedded applications, always put an object in read-only data \ + if possible, in order to reduce RAM usage. */ \ + \ + if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else \ + sec = 2; \ + } \ + else \ + { \ + /* For hosted applications, always put an object in small data if \ + possible, as this gives the best performance. */ \ + \ + if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else \ + sec = 2; \ + } \ + \ + prefix = prefixes[sec][DECL_ONE_ONLY (DECL)]; \ + len = strlen (name) + strlen (prefix); \ + string = alloca (len + 1); \ + sprintf (string, "%s%s", prefix, name); \ + \ + DECL_SECTION_NAME (DECL) = build_string (len, string); \ +} while (0) + +/* Support the ctors/dtors and other sections. */ + +/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. + + Note that we want to give these sections the SHF_WRITE attribute + because these sections will actually contain data (i.e. tables of + addresses of functions in the current root executable or shared library + file) and, in the case of a shared library, the relocatable addresses + will have to be properly resolved/relocated (and then written into) by + the dynamic linker when it actually attaches the given shared library + to the executing process. (Note that on SVR4, you may wish to use the + `-z text' option to the ELF linker, when building a shared library, as + an additional check that you are doing everything right. But if you do + use the `-z text' option when building a shared library, you will get + errors unless the .ctors and .dtors sections are marked as writable + via the SHF_WRITE attribute.) */ + +#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\"" +#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\"" + +/* A list of other sections which the compiler might be "in" at any + given time. */ +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors + +#define INVOKE__main +#define NAME__MAIN "__gccmain" +#define SYMBOL__MAIN __gccmain + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP) + +#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP) \ +void FN () \ +{ \ + if (in_section != ENUM) \ + { \ + fprintf (asm_out_file, "%s\n", OP); \ + in_section = ENUM; \ + } \ +} + + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define CTOR_LIST_BEGIN \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) } + +#define CTOR_LIST_END \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_END__[1] = { (func_ptr) 0 }; + +#define DTOR_LIST_BEGIN \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) } + +#define DTOR_LIST_END \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_END__[1] = { (func_ptr) 0 }; + +/* Don't set the target flags, this is done by the linker script */ +#undef LIB_SPEC +#define LIB_SPEC "" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend%O%s" diff --git a/contrib/gcc/config/mips/elf64.h b/contrib/gcc/config/mips/elf64.h new file mode 100644 index 0000000000000..91c83103b9750 --- /dev/null +++ b/contrib/gcc/config/mips/elf64.h @@ -0,0 +1,355 @@ +/* Definitions of target machine for GNU compiler. MIPS R4000 version with + GOFAST floating point library. + Copyright (C) 1994, 1995, 1996, 1997, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define OBJECT_FORMAT_ELF + +/* Default to -mips3. */ +#define TARGET_DEFAULT MASK_FLOAT64|MASK_64BIT +#define MIPS_ISA_DEFAULT 3 + +/* Until we figure out what MIPS ELF targets normally use, just do + stabs in ELF. */ +#ifndef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG +#endif + +/* US Software GOFAST library support. */ +#include "gofast.h" +#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS + +#include "mips/mips.h" + +/* This must be done after mips.h, because mips.h defines + TARGET_ENDIAN_DEFAULT. */ +#undef MULTILIB_DEFAULTS +#if TARGET_ENDIAN_DEFAULT == 0 +#define MULTILIB_DEFAULTS { "EL", "mips3" } +#else +#define MULTILIB_DEFAULTS { "EB", "mips3" } +#endif + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000" + +/* I would rather put this in CPP_PREDEFINES, but the gcc driver + doesn't handle -U options in CPP_PREDEFINES. */ +#undef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "\ +%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}" + +/* Use memcpy, et. al., rather than bcopy. */ +#define TARGET_MEM_FUNCTIONS + +/* Biggest alignment supported by the object file format of this + machine. Use this macro to limit the alignment which can be + specified using the `__attribute__ ((aligned (N)))' construct. If + not defined, the default value is `BIGGEST_ALIGNMENT'. */ + +#define MAX_OFILE_ALIGNMENT (32768*8) + +/* We need to use .esize and .etype instead of .size and .type to + avoid conflicting with ELF directives. */ +#undef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.esize\t%d;", (a)); \ +} while (0) + +#undef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ +} while (0) + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. */ + +#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \ +do { \ + extern FILE *asm_out_text_file; \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME)); \ + else \ + fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME)); \ +} while (0) + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#undef TYPE_ASM_OP +#undef SIZE_ASM_OP +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare an object properly. */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + mips_declare_object (FILE, NAME, "", ":\n", 0); \ + } while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#undef ASM_FINISH_DECLARE_OBJECT +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fputc ( '\t', FILE); \ + assemble_name (FILE, LABEL1); \ + fputs ( " = ", FILE); \ + assemble_name (FILE, LABEL2); \ + fputc ( '\n', FILE); \ + } while (0) + +/* Note about .weak vs. .weakext + The mips native assemblers support .weakext, but not .weak. + mips-elf gas supports .weak, but not .weakext. + mips-elf gas has been changed to support both .weak and .weakext, + but until that support is generally available, the 'if' below + should serve. */ + +#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) +#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE) \ + do { \ + if (TARGET_GAS) \ + fputs ("\t.weak\t", FILE); \ + else \ + fputs ("\t.weakext\t", FILE); \ + assemble_name (FILE, NAME); \ + if (VALUE) \ + { \ + fputc (' ', FILE); \ + assemble_name (FILE, VALUE); \ + } \ + fputc ('\n', FILE); \ + } while (0) + +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) +#undef UNIQUE_SECTION_P +#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL)) +#define UNIQUE_SECTION(DECL,RELOC) \ +do { \ + int len, size, sec; \ + char *name, *string, *prefix; \ + static char *prefixes[4][2] = { \ + { ".text.", ".gnu.linkonce.t." }, \ + { ".rodata.", ".gnu.linkonce.r." }, \ + { ".data.", ".gnu.linkonce.d." }, \ + { ".sdata.", ".gnu.linkonce.s." } \ + }; \ + \ + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \ + size = int_size_in_bytes (TREE_TYPE (decl)); \ + \ + /* Determine the base section we are interested in: \ + 0=text, 1=rodata, 2=data, 3=sdata. */ \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + sec = 0; \ + else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16) \ + && TREE_CODE (decl) == STRING_CST \ + && !flag_writable_strings) \ + { \ + /* For embedded position independent code, put constant strings \ + in the text section, because the data section is limited to \ + 64K in size. For mips16 code, put strings in the text \ + section so that a PC relative load instruction can be used to \ + get their address. */ \ + sec = 0; \ + } \ + else if (TARGET_EMBEDDED_DATA) \ + { \ + /* For embedded applications, always put an object in read-only data \ + if possible, in order to reduce RAM usage. */ \ + \ + if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else \ + sec = 2; \ + } \ + else \ + { \ + /* For hosted applications, always put an object in small data if \ + possible, as this gives the best performance. */ \ + \ + if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else \ + sec = 2; \ + } \ + \ + prefix = prefixes[sec][DECL_ONE_ONLY (DECL)]; \ + len = strlen (name) + strlen (prefix); \ + string = alloca (len + 1); \ + sprintf (string, "%s%s", prefix, name); \ + \ + DECL_SECTION_NAME (DECL) = build_string (len, string); \ +} while (0) + +/* Support the ctors/dtors and other sections. */ + +/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. + + Note that we want to give these sections the SHF_WRITE attribute + because these sections will actually contain data (i.e. tables of + addresses of functions in the current root executable or shared library + file) and, in the case of a shared library, the relocatable addresses + will have to be properly resolved/relocated (and then written into) by + the dynamic linker when it actually attaches the given shared library + to the executing process. (Note that on SVR4, you may wish to use the + `-z text' option to the ELF linker, when building a shared library, as + an additional check that you are doing everything right. But if you do + use the `-z text' option when building a shared library, you will get + errors unless the .ctors and .dtors sections are marked as writable + via the SHF_WRITE attribute.) */ + +#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\"" +#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\"" + +/* A list of other sections which the compiler might be "in" at any + given time. */ +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors + +#define INVOKE__main +#define NAME__MAIN "__gccmain" +#define SYMBOL__MAIN __gccmain + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP) + +#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP) \ +void FN () \ +{ \ + if (in_section != ENUM) \ + { \ + fprintf (asm_out_file, "%s\n", OP); \ + in_section = ENUM; \ + } \ +} + + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define CTOR_LIST_BEGIN \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) } + +#define CTOR_LIST_END \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_END__[1] = { (func_ptr) 0 }; + +#define DTOR_LIST_BEGIN \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) } + +#define DTOR_LIST_END \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_END__[1] = { (func_ptr) 0 }; + +/* Don't set the target flags, this is done by the linker script */ +#undef LIB_SPEC +#define LIB_SPEC "" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend%O%s" diff --git a/contrib/gcc/config/mips/elfl.h b/contrib/gcc/config/mips/elfl.h new file mode 100644 index 0000000000000..7575e3da5d8d4 --- /dev/null +++ b/contrib/gcc/config/mips/elfl.h @@ -0,0 +1,29 @@ +/* Definitions of target machine for GNU compiler. Little endian MIPS + R3000 version with GOFAST floating point library. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a little endian version of elf.h. */ + +#define TARGET_ENDIAN_DEFAULT 0 + +#include "mips/elf.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000" diff --git a/contrib/gcc/config/mips/elfl64.h b/contrib/gcc/config/mips/elfl64.h new file mode 100644 index 0000000000000..5e18c0932086e --- /dev/null +++ b/contrib/gcc/config/mips/elfl64.h @@ -0,0 +1,29 @@ +/* Definitions of target machine for GNU compiler. Little endian MIPS + R4000 version with GOFAST floating point library. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a little endian version of elf64.h. */ + +#define TARGET_ENDIAN_DEFAULT 0 + +#include "mips/elf64.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4000 -D_mips -D_MIPSEL -D_R4000" diff --git a/contrib/gcc/config/mips/elflorion.h b/contrib/gcc/config/mips/elflorion.h new file mode 100644 index 0000000000000..4b7f111873ff4 --- /dev/null +++ b/contrib/gcc/config/mips/elflorion.h @@ -0,0 +1,24 @@ +/* Definitions of target machine for GNU compiler. MIPS ORION version with + GOFAST floating point library. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_CPU_STRING_DEFAULT "orion" + +#include "mips/elfl64.h" diff --git a/contrib/gcc/config/mips/elforion.h b/contrib/gcc/config/mips/elforion.h new file mode 100644 index 0000000000000..aa1a058b50d3c --- /dev/null +++ b/contrib/gcc/config/mips/elforion.h @@ -0,0 +1,22 @@ +/* Definitions of target machine for GNU compiler. MIPS ORION version with + GOFAST floating point library. + Copyright (C) 1994, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_CPU_STRING_DEFAULT "orion" diff --git a/contrib/gcc/config/mips/gnu.h b/contrib/gcc/config/mips/gnu.h new file mode 100644 index 0000000000000..734548b52115c --- /dev/null +++ b/contrib/gcc/config/mips/gnu.h @@ -0,0 +1,130 @@ +/* Definitions of target machine for GNU compiler. MIPS GNU Hurd version. + Copyright (C) 1995, 1996, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define TARGET_DEFAULT MASK_GAS + +#include + +#undef SWITCH_TAKES_ARG +#undef ASM_FILE_END +#undef ASM_OUTPUT_IDENT +#undef ASM_OUTPUT_SOURCE_LINE +#undef READONLY_DATA_SECTION +#undef SELECT_SECTION +#undef ASM_DECLARE_FUNCTION_NAME +#undef ASM_DECLARE_OBJECT_NAME +/* #undef PREFERRED_DEBUGGING_TYPE */ + +#include + +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (MIPS GNU/ELF)"); + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + mips_asm_file_start (FILE); \ + fprintf (FILE, "\t.version\t\"01.01\"\n"); \ + } while (0) + +#undef ASM_FILE_END +#define ASM_FILE_END(FILE) \ + do { \ + mips_asm_file_end(FILE); \ + if (!flag_no_ident) \ + fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n", \ + IDENT_ASM_OP, version_string); \ + } while (0) + +#undef ASM_OUTPUT_SOURCE_LINE +#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ + do { \ + ++sym_lineno; \ + fprintf ((FILE), ".LM%d:\n\t%s %d,0,%d,.LM%d\n", \ + sym_lineno, ASM_STABN_OP, N_SLINE, (LINE), sym_lineno); \ + } while (0) + +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ + do { \ + extern FILE *asm_out_text_file; \ + \ + if (TARGET_GP_OPT) \ + STREAM = asm_out_text_file; \ + fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (STREAM, NAME); \ + putc (',', STREAM); \ + fprintf (STREAM, TYPE_OPERAND_FMT, "function"); \ + putc ('\n', STREAM); \ + ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL)); \ + HALF_PIC_DECLARE (NAME); \ + } while (0) + +/* Switch Recognition by gcc.c. Add -G xx support */ +#undef SWITCH_TAKES_ARG +#define SWITCH_TAKES_ARG(CHAR) \ + (DEFAULT_SWITCH_TAKES_ARG(CHAR) || (CHAR) == 'G') + +#undef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 1 + +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] + +#define MIPS_GNU + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -Acpu(mips) -Amachine(mips) \ +-Dunix -Asystem(unix) -DMACH -Asystem(mach) -D__GNU__ -Asystem(gnu) \ +-DMIPSEB -DR3000 -D_MIPSEB -D_R3000 \ +-D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32" + +#undef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \ +-systype /gnu/ " + +#undef LIB_SPEC +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}" + +#undef MACHINE_TYPE +#define MACHINE_TYPE "GNU MIPS/ELF" + +#undef YES_UNDERSCORE + +#undef SDB_DEBUGGING_INFO +#undef DBX_DEBUGGING_INFO +#undef MIPS_DEBUGGING_INFO +#define DWARF_DEBUGGING_INFO + +#define NO_MIPS_SELECT_SECTION + +/* Get machine-independent configuration parameters for the GNU system. */ +#include diff --git a/contrib/gcc/config/mips/iris3.h b/contrib/gcc/config/mips/iris3.h new file mode 100644 index 0000000000000..1f690ffa466be --- /dev/null +++ b/contrib/gcc/config/mips/iris3.h @@ -0,0 +1,72 @@ +/* Definitions of target machine for GNU compiler. Iris version. + Copyright (C) 1991, 1993, 1995, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define SGI_TARGET 1 /* inform other mips files this is SGI */ + +/* Names to predefine in the preprocessor for this target machine. */ + +#define CPP_PREDEFINES "\ +-Dunix -Dmips -Dsgi -DSVR3 -Dhost_mips -DMIPSEB -DSYSTYPE_SYSV \ +-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)" + +#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" + +#define SUBTARGET_CPP_SPEC "\ +%{!ansi:-D__EXTENSIONS__} -D_MIPSEB -D_SYSTYPE_SYSV" + +#define LIB_SPEC \ + "%{!p:%{!pg:%{!static:%{!g*:-lc_s}} -lc}}%{p:-lc_p}%{pg:-lc_p} crtn.o%s" + +#define MACHINE_TYPE "Silicon Graphics Mips" + +/* Always use 1 for .file number. I [meissner@osf.org] wonder why + IRIS needs this. */ + +#define SET_FILE_NUMBER() num_source_filenames = 1 + +/* Put out a label after a .loc. I [meissner@osf.org] wonder why + IRIS needs this. */ + +#define LABEL_AFTER_LOC(STREAM) fprintf (STREAM, "LM%d:\n", ++sym_lineno) + +#define STACK_ARGS_ADJUST(SIZE) \ +{ \ + SIZE.constant += 4; \ + if (SIZE.constant < 32) \ + SIZE.constant = 32; \ +} + +/* Do not allow `$' in identifiers. */ + +#define DOLLARS_IN_IDENTIFIERS 0 + +/* Tell G++ not to create constructors or destructors with $'s in them. */ + +#define NO_DOLLAR_IN_LABEL 1 + +/* Specify wchar_t type. */ +#define WCHAR_TYPE "unsigned char" +#define WCHAR_TYPE_SIZE BITS_PER_UNIT + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Plain char is unsigned in the SGI compiler. */ +#define DEFAULT_SIGNED_CHAR 0 diff --git a/contrib/gcc/config/mips/iris4.h b/contrib/gcc/config/mips/iris4.h new file mode 100644 index 0000000000000..7ca0459c6254a --- /dev/null +++ b/contrib/gcc/config/mips/iris4.h @@ -0,0 +1,48 @@ +/* Definitions of target machine for GNU compiler. Iris version 4. + Copyright (C) 1991, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Profiling is supported via libprof1.a not -lc_p as in Irix 3. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}" + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{!p:%{!pg:%{!static:%{!g*:-lc_s}}}}%{p:libprof1.a%s}%{pg:libprof1.a%s} -lc crtn.o%s" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/iris4loser.h b/contrib/gcc/config/mips/iris4loser.h new file mode 100644 index 0000000000000..426c822b68a59 --- /dev/null +++ b/contrib/gcc/config/mips/iris4loser.h @@ -0,0 +1,5 @@ +/* Like iris4.h, but always inhibits assembler optimization for MIPS as. + Use this via mips-sgi-iris4loser if you need it. */ + +#define SUBTARGET_MIPS_AS_ASM_SPEC "-O0 %{v}" +#define SUBTARGET_ASM_OPTIMIZING_SPEC "" diff --git a/contrib/gcc/config/mips/iris5.h b/contrib/gcc/config/mips/iris5.h new file mode 100644 index 0000000000000..7910eef88d6dd --- /dev/null +++ b/contrib/gcc/config/mips/iris5.h @@ -0,0 +1,164 @@ +/* Definitions of target machine for GNU compiler. Iris version 5. + Copyright (C) 1993, 1995, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef TARGET_DEFAULT +#define TARGET_DEFAULT MASK_ABICALLS +#endif +#define ABICALLS_ASM_OP ".option pic2" + +#include "mips/iris3.h" +#include "mips/mips.h" +#include "mips/iris4.h" + +/* Irix 5 doesn't use COFF, so disable special COFF handling in collect2.c. */ +#undef OBJECT_FORMAT_COFF + +/* ??? This is correct, but not very useful, because there is no file that + uses this macro. */ +/* ??? The best way to handle global constructors under ELF is to use .init + and .fini sections. Unfortunately, there is apparently no way to get + the Irix 5.x (x <= 2) assembler to create these sections. So we instead + use collect. The linker can create these sections via -init and -fini + options, but using this would require modifying how crtstuff works, and + I will leave that for another time (or someone else). */ +#define OBJECT_FORMAT_ELF +#define HAS_INIT_SECTION +#define LD_INIT_SWITCH "-init" +#define LD_FINI_SWITCH "-fini" + +/* Specify wchar_t types. */ +#undef WCHAR_TYPE +#undef WCHAR_TYPE_SIZE +#undef MAX_WCHAR_TYPE_SIZE + +#define WCHAR_TYPE "long int" +#define WCHAR_TYPE_SIZE LONG_TYPE_SIZE +#define MAX_WCHAR_TYPE_SIZE MAX_LONG_TYPE_SIZE + +#define WORD_SWITCH_TAKES_ARG(STR) \ + (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ + || !strcmp (STR, "rpath")) + +#undef SUBTARGET_CC1_SPEC +#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}" + +/* ??? _MIPS_SIM and _MIPS_SZPTR should eventually depend on options when + options for them exist. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ + "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \ + -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \ + -D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZPTR=32 \ + -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)" + +#undef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "\ +%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE -D_LONGLONG} \ +%{!mfp64: -D_MIPS_FPSET=16}%{mfp64: -D_MIPS_FPSET=32} \ +%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \ +%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \ +%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \ +%{!mips1: %{!mips2: %{!mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS1}}} \ +%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \ +%{!mlong64: -D_MIPS_SZLONG=32}%{mlong64: -D_MIPS_SZLONG=64}" + +#undef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{static: -non_shared} \ +%{!static: \ + %{!shared:%{!non_shared:%{!call_shared: -call_shared -no_unresolved}}}} \ +%{rpath} \ +-_SYSTYPE_SVR4" + +/* We now support shared libraries. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "\ +%{!static: \ + %{!shared:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}}} \ +%{static: \ + %{pg:gcrt1.o%s} \ + %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s libprof1.a%s} \ + %{!p:/usr/lib/nonshared/crt1.o%s}}}" + +#undef LIB_SPEC +#define LIB_SPEC "%{!shared:%{p:-lprof1} %{pg:-lprof1} -lc}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "%{!shared:crtn.o%s}" + +/* We do not want to run mips-tfile! */ +#undef ASM_FINAL_SPEC + +/* The system header files are C++ aware. */ +/* ??? Unfortunately, most but not all of the headers are C++ aware. + Specifically, curses.h is not, and as a consequence, defining this + used to prevent libg++ building. This is no longer the case so + define it again to prevent other problems, e.g. with getopt in + unistd.h. We still need some way to fix just those files that need + fixing. */ +#define NO_IMPLICIT_EXTERN_C 1 + +/* We don't support debugging info for now. */ +#undef DBX_DEBUGGING_INFO +#undef SDB_DEBUGGING_INFO +#undef MIPS_DEBUGGING_INFO +#undef PREFERRED_DEBUGGING_TYPE + +/* Likewise, the assembler doesn't handle DWARF2 directives. */ +#define DWARF2_UNWIND_INFO 0 + +#undef MACHINE_TYPE +#define MACHINE_TYPE "SGI running IRIX 5.x" + + /* Dollar signs are OK in Irix5 but not in Irix3. */ +#undef DOLLARS_IN_IDENTIFIERS +#undef NO_DOLLAR_IN_LABEL + +/* -G is incompatible with -KPIC which is the default, so only allow objects + in the small data section if the user explicitly asks for it. */ +#undef MIPS_DEFAULT_GVALUE +#define MIPS_DEFAULT_GVALUE 0 + +/* In Irix 5, we must output a `.global name .text' directive for every used + but undefined function. If we don't, the linker may perform an optimization + (skipping over the insns that set $gp) when it is unsafe. This is used + indirectly by ASM_OUTPUT_EXTERNAL. */ +#define ASM_OUTPUT_UNDEF_FUNCTION(FILE, NAME) \ +do { \ + fputs ("\t.globl ", FILE); \ + assemble_name (FILE, NAME); \ + fputs (" .text\n", FILE); \ +} while (0) + +/* Also do this for libcalls. */ +#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ + mips_output_external_libcall (FILE, XSTR (FUN, 0)) + +/* This does for functions what ASM_DECLARE_OBJECT_NAME does for variables. + This is used indirectly by ASM_OUTPUT_EXTERNAL. */ +#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ +do { \ + tree name_tree = get_identifier (NAME); \ + TREE_ASM_WRITTEN (name_tree) = 1; \ +} while (0) diff --git a/contrib/gcc/config/mips/iris5gas.h b/contrib/gcc/config/mips/iris5gas.h new file mode 100644 index 0000000000000..477a55fb647c7 --- /dev/null +++ b/contrib/gcc/config/mips/iris5gas.h @@ -0,0 +1,34 @@ +/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */ + +/* Enable debugging. */ +#define DBX_DEBUGGING_INFO +#define SDB_DEBUGGING_INFO +#define MIPS_DEBUGGING_INFO +#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG + +/* GNU as does handle DWARF2 directives. */ +#undef DWARF2_UNWIND_INFO +#define DWARF2_UNWIND_INFO 1 + +/* Irix 5 does not have some strange restrictions that Irix 3 had. */ +#undef SET_FILE_NUMBER +#define SET_FILE_NUMBER() ++num_source_filenames +#undef LABEL_AFTER_LOC +#define LABEL_AFTER_LOC(STREAM) + +/* We need to use .esize and .etype instead of .size and .type to + avoid conflicting with ELF directives. These are only recognized + by gas, anyhow, not the native assembler. */ +#undef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.esize\t%d;", (a)); \ +} while (0) + +#undef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ +} while (0) diff --git a/contrib/gcc/config/mips/iris6.h b/contrib/gcc/config/mips/iris6.h new file mode 100644 index 0000000000000..9df7732e8b078 --- /dev/null +++ b/contrib/gcc/config/mips/iris6.h @@ -0,0 +1,567 @@ +/* Definitions of target machine for GNU compiler. Iris version 6. + Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Default to -mabi=n32 and -mips3. */ +#define MIPS_ISA_DEFAULT 3 +#define MIPS_ABI_DEFAULT ABI_N32 +#define MULTILIB_DEFAULTS { "mabi=n32" } + +#ifndef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_ABICALLS|MASK_FLOAT64|MASK_64BIT) +#endif + +#include "mips/iris5.h" +#include "mips/abi64.h" + +/* Irix6 assembler does handle DWARF2 directives. Override setting in + irix5.h file. */ +#undef DWARF2_UNWIND_INFO + +/* For Irix 6, -mabi=64 implies TARGET_LONG64. */ +/* This is handled in override_options. */ + +#undef SUBTARGET_CC1_SPEC +#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}" + +/* We must pass -D_LONGLONG always, even when -ansi is used, because irix6 + system header files require it. This is OK, because gcc never warns + when long long is used in system header files. Alternatively, we can + add support for the SGI builtin type __long_long. */ +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ + "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \ + -D_LONGLONG -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \ + -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)" + +#undef SUBTARGET_CPP_SIZE_SPEC +#define SUBTARGET_CPP_SIZE_SPEC "\ +%{mabi=32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \ +%{mabi=n32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \ +%{mabi=64: -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \ +%{!mabi*: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}" + +/* We must make -mips3 do what -mlong64 used to do. */ +/* ??? If no mipsX option given, but a mabi=X option is, then should set + _MIPS_ISA based on the mabi=X option. */ +/* ??? If no mabi=X option give, but a mipsX option is, then should set + _MIPS_SIM based on the mipsX option. */ +/* ??? Same for _MIPS_SZINT. */ +/* ??? Same for _MIPS_SZPTR. */ +/* ??? Same for __SIZE_TYPE and __PTRDIFF_TYPE. */ +#undef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "\ +%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} \ +%{mfp32: -D_MIPS_FPSET=16}%{!mfp32: -D_MIPS_FPSET=32} \ +%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \ +%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \ +%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \ +%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \ +%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \ +%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32} \ +%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \ +%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \ +%{!mabi*: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \ +%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \ +%{mabi=32: -D_MIPS_SZLONG=32} \ +%{mabi=n32: -D_MIPS_SZLONG=32} \ +%{mabi=64: -D_MIPS_SZLONG=64} \ +%{!mabi*: -D_MIPS_SZLONG=32} \ +%{mabi=32: -D_MIPS_SZPTR=32} \ +%{mabi=n32: -D_MIPS_SZPTR=32} \ +%{mabi=64: -D_MIPS_SZPTR=64} \ +%{!mabi*: -D_MIPS_SZPTR=32} \ +%{!mips1:%{!mips2: -D_COMPILER_VERSION=601}} \ +%{!mips*: -U__mips -D__mips=3} \ +%{mabi=32: -U__mips64} \ +%{mabi=n32: -D__mips64} \ +%{mabi=64: -D__mips64} \ +%{!mabi*: -D__mips64}" + +/* Irix 6 uses DWARF-2. */ +#define DWARF2_DEBUGGING_INFO +#define MIPS_DEBUGGING_INFO +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + +/* Force the generation of dwarf .debug_frame sections even if not + compiling -g. This guarantees that we can unwind the stack. */ +#define DWARF2_FRAME_INFO 1 +/* The size in bytes of a DWARF field indicating an offset or length + relative to a debug info section, specified to be 4 bytes in the DWARF-2 + specification. The SGI/MIPS ABI defines it to be the same as PTR_SIZE. */ +#define DWARF_OFFSET_SIZE PTR_SIZE + +/* There is no GNU as port for Irix6 yet, so we set MD_EXEC_PREFIX so that + gcc will automatically find SGI as instead of searching the user's path. + The latter can fail when building a cross compiler if the user has . in + the path before /usr/bin, since then gcc will find and try to use the link + to the cross assembler which can't possibly work. */ + +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/bin/" + +/* We have no need for MD_STARTFILE_PREFIX. */ +#undef MD_STARTFILE_PREFIX + +#undef MACHINE_TYPE +#define MACHINE_TYPE "SGI running IRIX 6.x" + +/* The Irix 6.0.1 assembler doesn't like labels in the text section, so + just avoid emitting them. */ +#define ASM_IDENTIFY_GCC(x) ((void)0) +#define ASM_IDENTIFY_LANGUAGE(x) ((void)0) + +/* Irix 5 stuff that we don't need for Irix 6. */ +/* ??? We do need this for the -mabi=32 switch though. */ +#undef ASM_OUTPUT_UNDEF_FUNCTION +#undef ASM_OUTPUT_EXTERNAL_LIBCALL +#undef ASM_DECLARE_FUNCTION_SIZE + +/* Stuff we need for Irix 6 that isn't in Irix 5. */ + +/* The SGI assembler doesn't like labels before the .ent, so we must output + the .ent and function name here, which is the normal place for it. */ + +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ + do { \ + fputs ("\t.ent\t", STREAM); \ + assemble_name (STREAM, NAME); \ + fputs ("\n", STREAM); \ + assemble_name (STREAM, NAME); \ + fputs (":\n", STREAM); \ + } while (0) + +/* Likewise, the SGI assembler doesn't like labels after the .end, so we + must output the .end here. */ +#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ + do { \ + fputs ("\t.end\t", STREAM); \ + assemble_name (STREAM, NAME); \ + fputs ("\n", STREAM); \ + } while (0) + +/* Tell function_prologue in mips.c that we have already output the .ent/.end + pseudo-ops. */ +#define FUNCTION_NAME_ALREADY_DECLARED + +#undef SET_ASM_OP /* Has no equivalent. See ASM_OUTPUT_DEF below. */ + +#if 0 +/* This is *NOT* how to equate one symbol to another symbol. The assembler + '=' syntax just equates a name to a constant expression. + See ASM_OUTPUT_WEAK_ALIAS. */ + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fprintf ((FILE), "\t"); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, " = "); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } while (0) +#endif + +/* Define the strings used for the special svr4 .type and .size directives. */ + +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* This is how we tell the assembler that a symbol is weak. */ + +#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE) \ + do { \ + ASM_GLOBALIZE_LABEL (FILE, NAME); \ + fputs ("\t.weakext\t", FILE); \ + assemble_name (FILE, NAME); \ + if (VALUE) \ + { \ + fputc (' ', FILE); \ + assemble_name (FILE, VALUE); \ + } \ + fputc ('\n', FILE); \ + } while (0) + +#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) + +#define POPSECTION_ASM_OP ".popsection" + +#define DEBUG_INFO_SECTION ".debug_info,0x7000001e,0,0,1" +#define DEBUG_LINE_SECTION ".debug_line,0x7000001e,0,0,1" +#define SFNAMES_SECTION ".debug_sfnames,0x7000001e,0,0,1" +#define SRCINFO_SECTION ".debug_srcinfo,0x7000001e,0,0,1" +#define MACINFO_SECTION ".debug_macinfo,0x7000001e,0,0,1" +#define PUBNAMES_SECTION ".debug_pubnames,0x7000001e,0,0,1" +#define ARANGES_SECTION ".debug_aranges,0x7000001e,0,0,1" +#define FRAME_SECTION ".debug_frame,0x7000001e,0x08000000,0,1" +#define ABBREV_SECTION ".debug_abbrev,0x7000001e,0,0,1" + +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef SUBTARGET_ASM_SPEC +#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32}" + +/* Must pass -g0 to the assembler, otherwise it may overwrite our + debug info with its own debug info. */ +/* Must pass -show instead of -v. */ +/* Must pass -G 0 to the assembler, otherwise we may get warnings about + GOT overflow. */ +/* ??? We pass -w to disable all assembler warnings. The `label should be + inside .ent/.end block' warning that we get for DWARF II debug info labels + is particularly annoying. */ +#undef SUBTARGET_MIPS_AS_ASM_SPEC +#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v:-show} -G 0 -w" + +#undef SUBTARGET_ASM_DEBUGGING_SPEC +#define SUBTARGET_ASM_DEBUGGING_SPEC "-g0" + +/* Stuff for constructors. Start here. */ + +/* The assembler now accepts .section pseudo-ops, but it does not allow + one to change the section in the middle of a function, so we can't use + the INIT_SECTION_ASM_OP code in crtstuff. But we can build up the ctor + and dtor lists this way, so we use -init and -fini to invoke the + do_global_* functions instead of running collect2. */ + +#define BSS_SECTION_ASM_OP ".section\t.bss" +#define CONST_SECTION_ASM_OP_32 "\t.rdata" +#define CONST_SECTION_ASM_OP_64 ".section\t.rodata" + +/* The IRIX 6 assembler .section directive takes four additional args: + section type, flags, entry size, and alignment. The alignment of the + .ctors and .dtors sections needs to be the same as the size of a pointer + so that the linker doesn't add padding between elements. */ +#if defined (CRT_BEGIN) || defined (CRT_END) + +/* If we are included from crtstuff.c, these need to be plain strings. + _MIPS_SZPTR is defined in SUBTARGET_CPP_SPEC above. */ +#if _MIPS_SZPTR == 64 +#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,8" +#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,8" +#else /* _MIPS_SZPTR != 64 */ +#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,4" +#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,4" +#endif /* _MIPS_SZPTR == 64 */ + +#else /* ! (defined (CRT_BEGIN) || defined (CRT_END)) */ + +/* If we are included from varasm.c, these need to depend on -mabi. */ +#define CTORS_SECTION_ASM_OP \ + (Pmode == DImode ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4") +#define DTORS_SECTION_ASM_OP \ + (Pmode == DImode ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4") +#endif /* defined (CRT_BEGIN) || defined (CRT_END) */ + +/* dwarf2out will handle padding this data properly. We definitely don't + want it 8-byte aligned on n32. */ +#define EH_FRAME_SECTION_ASM_OP ".section\t.eh_frame,1,2,0,1" + +/* A default list of other sections which we might be "in" at any given + time. For targets that use additional sections (e.g. .tdesc) you + should override this definition in the target-specific file which + includes this file. */ + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata, in_const, in_ctors, in_dtors + +/* A default list of extra section function definitions. For targets + that use additional sections (e.g. .tdesc) you should override this + definition in the target-specific file which includes this file. */ + +/* ??? rdata_section is now same as svr4 const_section. */ + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ +void \ +sdata_section () \ +{ \ + if (in_section != in_sdata) \ + { \ + fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \ + in_section = in_sdata; \ + } \ +} \ + \ +void \ +rdata_section () \ +{ \ + if (in_section != in_rdata) \ + { \ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) \ + fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_64); \ + else \ + fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_32); \ + in_section = in_rdata; \ + } \ +} \ + CTORS_SECTION_FUNCTION \ + DTORS_SECTION_FUNCTION + +#define CTORS_SECTION_FUNCTION \ +void \ +ctors_section () \ +{ \ + if (in_section != in_ctors) \ + { \ + fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ + in_section = in_ctors; \ + } \ +} + +#define DTORS_SECTION_FUNCTION \ +void \ +dtors_section () \ +{ \ + if (in_section != in_dtors) \ + { \ + fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ + in_section = in_dtors; \ + } \ +} + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t ", \ + (Pmode == DImode) ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t ", \ + (Pmode == DImode) ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. */ + +#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \ +do { \ + extern FILE *asm_out_text_file; \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (asm_out_text_file, "\t.section %s,1,6,4,4\n", (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (F, "\t.section %s,1,2,0,8\n", (NAME)); \ + else \ + fprintf (F, "\t.section %s,1,3,0,8\n", (NAME)); \ +} while (0) + +/* Stuff for constructors. End here. */ + +/* ??? Perhaps just include svr4.h in this file? */ + +/* ??? SGI assembler may core dump when compiling with -g. + Sometimes as succeeds, but then we get a linker error. (cmds.c in 072.sc) + Getting rid of .file solves both problems. */ +#undef ASM_OUTPUT_FILENAME +#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \ +do \ + { \ + fprintf (STREAM, "\t#.file\t%d ", NUM_SOURCE_FILENAMES); \ + output_quoted_string (STREAM, NAME); \ + fputs ("\n", STREAM); \ + } \ +while (0) + +/* ??? SGI assembler gives warning whenever .lcomm is used. */ +#undef ASM_OUTPUT_LOCAL +#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ +do \ + { \ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) \ + { \ + fprintf (STREAM, "%s\n", BSS_SECTION_ASM_OP); \ + mips_declare_object (STREAM, NAME, "", ":\n", 0); \ + ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \ + ASM_OUTPUT_SKIP (STREAM, SIZE); \ + fprintf (STREAM, "\t%s\n", POPSECTION_ASM_OP); \ + } \ + else \ + mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE)); \ + } \ +while (0) + +/* A C statement (sans semicolon) to output to the stdio stream + FILE the assembler definition of uninitialized global DECL named + NAME whose size is SIZE bytes and alignment is ALIGN bytes. + Try to use asm_output_aligned_bss to implement this macro. */ + +#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ + asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) + +/* Write the extra assembler code needed to declare an object properly. */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ +do \ + { \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (STREAM, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (STREAM, NAME); \ + fprintf (STREAM, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + mips_declare_object (STREAM, NAME, "", ":\n", 0); \ + } \ +while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +#undef LOCAL_LABEL_PREFIX +#define LOCAL_LABEL_PREFIX ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? "$" : ".") + +/* Profiling is supported via libprof1.a not -lc_p as in Irix 3. */ +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!static:%{!shared: \ + %{mabi=32:%{pg:gcrt1.o%s} \ + %{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \ + %{mabi=n32: \ + %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/crt1.o%s}}}} \ + %{mabi=64: \ + %{mips4:%{pg:/usr/lib64/mips4/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips4/mcrt1.o /usr/lib64/mips4/libprof1.a} \ + %{!p:/usr/lib64/mips4/crt1.o}}} \ + %{!mips4:%{pg:/usr/lib64/mips3/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips3/mcrt1.o /usr/lib64/mips3/libprof1.a} \ + %{!p:/usr/lib64/mips3/crt1.o}}}} \ + %{!mabi*: \ + %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/crt1.o%s}}}}}} \ + %{static: \ + %{mabi=32:%{pg:/usr/lib/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s /usr/lib/nonshared/libprof1.a%s} \ + %{!p:/usr/lib/nonshared/crt1.o%s}}} \ + %{mabi=n32: \ + %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \ + /usr/lib32/mips4/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \ + /usr/lib32/mips3/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}} \ + %{mabi=64: \ + %{mips4:%{pg:/usr/lib64/mips4/nonshared/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips4/nonshared/mcrt1.o \ + /usr/lib64/mips4/nonshared/libprof1.a} \ + %{!p:/usr/lib64/mips4/nonshared/crt1.o}}} \ + %{!mips4:%{pg:/usr/lib64/mips3/nonshared/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips3/nonshared/mcrt1.o \ + /usr/lib64/mips3/nonshared/libprof1.a} \ + %{!p:/usr/lib64/mips3/nonshared/crt1.o}}}} \ + %{!mabi*: \ + %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \ + /usr/lib32/mips4/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \ + /usr/lib32/mips3/nonshared/libprof1.a%s} \ + %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \ + /usr/lib32/mips3/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}}}} \ + crtbegin.o%s" + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{mabi=n32: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \ + -L/usr/lib32} \ + %{mabi=64: %{mips4:-L/usr/lib64/mips4} %{!mips4:-L/usr/lib64/mips3} \ + -L/usr/lib64} \ + %{!mabi*: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \ + -L/usr/lib32} \ + %{!shared: \ + -dont_warn_unused %{p:libprof1.a%s}%{pg:libprof1.a%s} -lc -warn_unused}" + +/* Avoid getting two warnings for libgcc.a everytime we link. */ +#undef LIBGCC_SPEC +#define LIBGCC_SPEC "-dont_warn_unused -lgcc -warn_unused" + +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "crtend.o%s \ + %{!shared: \ + %{mabi=32:crtn.o%s}\ + %{mabi=n32:%{mips4:/usr/lib32/mips4/crtn.o%s}\ + %{!mips4:/usr/lib32/mips3/crtn.o%s}}\ + %{mabi=64:%{mips4:/usr/lib64/mips4/crtn.o%s}\ + %{!mips4:/usr/lib64/mips3/crtn.o%s}}\ + %{!mabi*:%{mips4:/usr/lib32/mips4/crtn.o%s}\ + %{!mips4:/usr/lib32/mips3/crtn.o%s}}}" + +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} %{w} \ +%{static: -non_shared} \ +%{!static: \ + %{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}}} \ +%{rpath} -init __do_global_ctors -fini __do_global_dtors \ +%{shared:-hidden_symbol __do_global_ctors,__do_global_dtors,__EH_FRAME_BEGIN__,__frame_dummy} \ +-_SYSTYPE_SVR4 -woff 131 \ +%{mabi=32: -32}%{mabi=n32: -n32}%{mabi=64: -64}%{!mabi*: -n32}" diff --git a/contrib/gcc/config/mips/linux.h b/contrib/gcc/config/mips/linux.h new file mode 100644 index 0000000000000..f4ed424a60564 --- /dev/null +++ b/contrib/gcc/config/mips/linux.h @@ -0,0 +1,99 @@ +/* Definitions for MIPS running Linux-based GNU systems with ELF format. + Copyright (C) 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Required to keep collect2.c happy */ +#undef OBJECT_FORMAT_COFF + +#define HAVE_ATEXIT + +/* If we don't set MASK_ABICALLS, we can't default to PIC. */ +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS) + + +/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add + the GNU/Linux magical crtbegin.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main'. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shared: \ + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\ + crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" + +/* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on + the GNU/Linux magical crtend.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main', followed by a normal + GNU/Linux "finalizer" file, `crtn.o'. */ + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" + +/* From iris5.h */ +/* -G is incompatible with -KPIC which is the default, so only allow objects + in the small data section if the user explicitly asks for it. */ +#undef MIPS_DEFAULT_GVALUE +#define MIPS_DEFAULT_GVALUE 0 + +/* Borrowed from sparc/linux.h */ +#undef LINK_SPEC +#define LINK_SPEC "-Y P,/usr/lib %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}} \ + %{static:-static}}}" + + +#undef SUBTARGET_ASM_SPEC +#define SUBTARGET_ASM_SPEC "-KPIC" + +/* Undefine the following which were defined in elf.h. This will cause the linux + port to continue to use collect2 for constructors/destructors. These may be removed + when .ctor/.dtor section support is desired. */ + +#undef CTORS_SECTION_ASM_OP +#undef DTORS_SECTION_ASM_OP + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata + +#undef INVOKE__main +#undef NAME__MAIN +#undef SYMBOL__MAIN + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) + +#undef ASM_OUTPUT_CONSTRUCTOR +#undef ASM_OUTPUT_DESTRUCTOR + +#undef CTOR_LIST_BEGIN +#undef CTOR_LIST_END +#undef DTOR_LIST_BEGIN +#undef DTOR_LIST_END + +/* End of undefines to turn off .ctor/.dtor section support */ diff --git a/contrib/gcc/config/mips/mips-5.h b/contrib/gcc/config/mips/mips-5.h new file mode 100644 index 0000000000000..f8b0941b03511 --- /dev/null +++ b/contrib/gcc/config/mips/mips-5.h @@ -0,0 +1,46 @@ +/* Definitions of target machine for GNU compiler. MIPS RISC-OS 5.0 + default version. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" + +#include "mips/mips.h" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/mips.c b/contrib/gcc/config/mips/mips.c new file mode 100644 index 0000000000000..20caaa4417904 --- /dev/null +++ b/contrib/gcc/config/mips/mips.c @@ -0,0 +1,8522 @@ +/* Subroutines for insn-output.c for MIPS + Copyright (C) 1989, 90, 91, 93-98, 1999 Free Software Foundation, Inc. + Contributed by A. Lichnewsky, lich@inria.inria.fr. + Changes by Michael Meissner, meissner@osf.org. + 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and + Brendan Eich, brendan@microunity.com. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit + calling convention in 64 bit mode. It doesn't work though, and should + be replaced with something better designed. */ + +#include "config.h" +#include "system.h" +#include + +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "insn-attr.h" +#include "insn-codes.h" +#include "recog.h" +#include "toplev.h" + +#undef MAX /* sys/param.h may also define these */ +#undef MIN + +#include "tree.h" +#include "expr.h" +#include "flags.h" +#include "reload.h" +#include "output.h" + +#if defined(USG) || !defined(HAVE_STAB_H) +#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ +#else +#include /* On BSD, use the system's stab.h. */ +#endif /* not USG */ + +#ifdef __GNU_STAB__ +#define STAB_CODE_TYPE enum __stab_debug_code +#else +#define STAB_CODE_TYPE int +#endif + +extern char *mktemp (); +extern tree lookup_name (); + +/* Enumeration for all of the relational tests, so that we can build + arrays indexed by the test type, and not worry about the order + of EQ, NE, etc. */ + +enum internal_test { + ITEST_EQ, + ITEST_NE, + ITEST_GT, + ITEST_GE, + ITEST_LT, + ITEST_LE, + ITEST_GTU, + ITEST_GEU, + ITEST_LTU, + ITEST_LEU, + ITEST_MAX + }; + + +struct constant; +static enum internal_test map_test_to_internal_test PROTO ((enum rtx_code)); +static int mips16_simple_memory_operand PROTO ((rtx, rtx, + enum machine_mode)); +static int m16_check_op PROTO ((rtx, int, int, int)); +static void block_move_loop PROTO ((rtx, rtx, int, int, + rtx, rtx)); +static void block_move_call PROTO ((rtx, rtx, rtx)); +static FILE *make_temp_file PROTO ((void)); +static void save_restore_insns PROTO ((int, rtx, + long, FILE *)); +static void mips16_output_gp_offset PROTO ((FILE *, rtx)); +static void mips16_fp_args PROTO ((FILE *, int, int)); +static void build_mips16_function_stub PROTO ((FILE *)); +static void mips16_optimize_gp PROTO ((rtx)); +static rtx add_constant PROTO ((struct constant **, + rtx, + enum machine_mode)); +static void dump_constants PROTO ((struct constant *, + rtx)); +static rtx mips_find_symbol PROTO ((rtx)); +static void abort_with_insn PROTO ((rtx, const char *)) + ATTRIBUTE_NORETURN; + + +/* Global variables for machine-dependent things. */ + +/* Threshold for data being put into the small data/bss area, instead + of the normal data area (references to the small data/bss area take + 1 instruction, and use the global pointer, references to the normal + data area takes 2 instructions). */ +int mips_section_threshold = -1; + +/* Count the number of .file directives, so that .loc is up to date. */ +int num_source_filenames = 0; + +/* Count the number of sdb related labels are generated (to find block + start and end boundaries). */ +int sdb_label_count = 0; + +/* Next label # for each statement for Silicon Graphics IRIS systems. */ +int sym_lineno = 0; + +/* Non-zero if inside of a function, because the stupid MIPS asm can't + handle .files inside of functions. */ +int inside_function = 0; + +/* Files to separate the text and the data output, so that all of the data + can be emitted before the text, which will mean that the assembler will + generate smaller code, based on the global pointer. */ +FILE *asm_out_data_file; +FILE *asm_out_text_file; + +/* Linked list of all externals that are to be emitted when optimizing + for the global pointer if they haven't been declared by the end of + the program with an appropriate .comm or initialization. */ + +struct extern_list +{ + struct extern_list *next; /* next external */ + char *name; /* name of the external */ + int size; /* size in bytes */ +} *extern_head = 0; + +/* Name of the file containing the current function. */ +const char *current_function_file = ""; + +/* Warning given that Mips ECOFF can't support changing files + within a function. */ +int file_in_function_warning = FALSE; + +/* Whether to suppress issuing .loc's because the user attempted + to change the filename within a function. */ +int ignore_line_number = FALSE; + +/* Number of nested .set noreorder, noat, nomacro, and volatile requests. */ +int set_noreorder; +int set_noat; +int set_nomacro; +int set_volatile; + +/* The next branch instruction is a branch likely, not branch normal. */ +int mips_branch_likely; + +/* Count of delay slots and how many are filled. */ +int dslots_load_total; +int dslots_load_filled; +int dslots_jump_total; +int dslots_jump_filled; + +/* # of nops needed by previous insn */ +int dslots_number_nops; + +/* Number of 1/2/3 word references to data items (ie, not jal's). */ +int num_refs[3]; + +/* registers to check for load delay */ +rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4; + +/* Cached operands, and operator to compare for use in set/branch on + condition codes. */ +rtx branch_cmp[2]; + +/* what type of branch to use */ +enum cmp_type branch_type; + +/* Number of previously seen half-pic pointers and references. */ +static int prev_half_pic_ptrs = 0; +static int prev_half_pic_refs = 0; + +/* which cpu are we scheduling for */ +enum processor_type mips_cpu; + +/* which instruction set architecture to use. */ +int mips_isa; + +#ifdef MIPS_ABI_DEFAULT +/* Which ABI to use. This is defined to a constant in mips.h if the target + doesn't support multiple ABIs. */ +int mips_abi; +#endif + +/* Strings to hold which cpu and instruction set architecture to use. */ +const char *mips_cpu_string; /* for -mcpu= */ +const char *mips_isa_string; /* for -mips{1,2,3,4} */ +const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */ + +/* Whether we are generating mips16 code. This is a synonym for + TARGET_MIPS16, and exists for use as an attribute. */ +int mips16; + +/* This variable is set by -mno-mips16. We only care whether + -mno-mips16 appears or not, and using a string in this fashion is + just a way to avoid using up another bit in target_flags. */ +const char *mips_no_mips16_string; + +/* This is only used to determine if an type size setting option was + explicitly specified (-mlong64, -mint64, -mlong32). The specs + set this option if such an option is used. */ +const char *mips_explicit_type_size_string; + +/* Whether we are generating mips16 hard float code. In mips16 mode + we always set TARGET_SOFT_FLOAT; this variable is nonzero if + -msoft-float was not specified by the user, which means that we + should arrange to call mips32 hard floating point code. */ +int mips16_hard_float; + +/* This variable is set by -mentry. We only care whether -mentry + appears or not, and using a string in this fashion is just a way to + avoid using up another bit in target_flags. */ +const char *mips_entry_string; + +/* Whether we should entry and exit pseudo-ops in mips16 mode. */ +int mips_entry; + +/* If TRUE, we split addresses into their high and low parts in the RTL. */ +int mips_split_addresses; + +/* Generating calls to position independent functions? */ +enum mips_abicalls_type mips_abicalls; + +/* High and low marks for floating point values which we will accept + as legitimate constants for LEGITIMATE_CONSTANT_P. These are + initialized in override_options. */ +REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow; + +/* Mode used for saving/restoring general purpose registers. */ +static enum machine_mode gpr_mode; + +/* Array giving truth value on whether or not a given hard register + can support a given mode. */ +char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; + +/* Current frame information calculated by compute_frame_size. */ +struct mips_frame_info current_frame_info; + +/* Zero structure to initialize current_frame_info. */ +struct mips_frame_info zero_frame_info; + +/* Temporary filename used to buffer .text until end of program + for -mgpopt. */ +static char *temp_filename; + +/* Pseudo-reg holding the address of the current function when + generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used + by mips_finalize_pic if it was created. */ +rtx embedded_pic_fnaddr_rtx; + +/* The length of all strings seen when compiling for the mips16. This + is used to tell how many strings are in the constant pool, so that + we can see if we may have an overflow. This is reset each time the + constant pool is output. */ +int mips_string_length; + +/* Pseudo-reg holding the value of $28 in a mips16 function which + refers to GP relative global variables. */ +rtx mips16_gp_pseudo_rtx; + +/* In mips16 mode, we build a list of all the string constants we see + in a particular function. */ + +struct string_constant +{ + struct string_constant *next; + char *label; +}; + +static struct string_constant *string_constants; + +/* List of all MIPS punctuation characters used by print_operand. */ +char mips_print_operand_punct[256]; + +/* Map GCC register number to debugger register number. */ +int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; + +/* Buffer to use to enclose a load/store operation with %{ %} to + turn on .set volatile. */ +static char volatile_buffer[60]; + +/* Hardware names for the registers. If -mrnames is used, this + will be overwritten with mips_sw_reg_names. */ + +char mips_reg_names[][8] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", + "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", + "$fcc5","$fcc6","$fcc7","$rap" +}; + +/* Mips software names for the registers, used to overwrite the + mips_reg_names array. */ + +char mips_sw_reg_names[][8] = +{ + "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3", + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", + "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", + "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra", + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", + "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", + "$fcc5","$fcc6","$fcc7","$rap" +}; + +/* Map hard register number to register class */ +enum reg_class mips_regno_to_class[] = +{ + GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS, + M16_REGS, M16_REGS, M16_REGS, M16_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + T_REG, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + HI_REG, LO_REG, HILO_REG, ST_REGS, + ST_REGS, ST_REGS, ST_REGS, ST_REGS, + ST_REGS, ST_REGS, ST_REGS, GR_REGS +}; + +/* Map register constraint character to register class. */ +enum reg_class mips_char_to_class[256] = +{ + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, +}; + + +/* Return truth value of whether OP can be used as an operands + where a register or 16 bit unsigned integer is needed. */ + +int +uns_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op)) + return 1; + + return register_operand (op, mode); +} + +/* Return truth value of whether OP can be used as an operands + where a 16 bit integer is needed */ + +int +arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT && SMALL_INT (op)) + return 1; + + /* On the mips16, a GP relative value is a signed 16 bit offset. */ + if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op)) + return 1; + + return register_operand (op, mode); +} + +/* Return truth value of whether OP can be used as an operand in a two + address arithmetic insn (such as set 123456,%o4) of mode MODE. */ + +int +arith32_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT) + return 1; + + return register_operand (op, mode); +} + +/* Return truth value of whether OP is a integer which fits in 16 bits */ + +int +small_int (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); +} + +/* Return truth value of whether OP is a 32 bit integer which is too big to + be loaded with one instruction. */ + +int +large_int (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + HOST_WIDE_INT value; + + if (GET_CODE (op) != CONST_INT) + return 0; + + value = INTVAL (op); + + /* ior reg,$r0,value */ + if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0) + return 0; + + /* subu reg,$r0,value */ + if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767) + return 0; + + /* lui reg,value>>16 */ + if ((value & 0x0000ffff) == 0) + return 0; + + return 1; +} + +/* Return truth value of whether OP is a register or the constant 0. + In mips16 mode, we only accept a register, since the mips16 does + not have $0. */ + +int +reg_or_0_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case CONST_INT: + if (TARGET_MIPS16) + return 0; + return INTVAL (op) == 0; + + case CONST_DOUBLE: + if (TARGET_MIPS16) + return 0; + return op == CONST0_RTX (mode); + + case REG: + case SUBREG: + return register_operand (op, mode); + + default: + break; + } + + return 0; +} + +/* Return truth value of whether OP is a register or the constant 0, + even in mips16 mode. */ + +int +true_reg_or_0_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case CONST_INT: + return INTVAL (op) == 0; + + case CONST_DOUBLE: + return op == CONST0_RTX (mode); + + case REG: + case SUBREG: + return register_operand (op, mode); + + default: + break; + } + + return 0; +} + +/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ + +int +mips_const_double_ok (op, mode) + rtx op; + enum machine_mode mode; +{ + REAL_VALUE_TYPE d; + + if (GET_CODE (op) != CONST_DOUBLE) + return 0; + + if (mode == VOIDmode) + return 1; + + if (mode != SFmode && mode != DFmode) + return 0; + + if (op == CONST0_RTX (mode)) + return 1; + + /* ??? li.s does not work right with SGI's Irix 6 assembler. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI) + return 0; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + if (REAL_VALUE_ISNAN (d)) + return FALSE; + + if (REAL_VALUE_NEGATIVE (d)) + d = REAL_VALUE_NEGATE (d); + + if (mode == DFmode) + { + if (REAL_VALUES_LESS (d, dfhigh) + && REAL_VALUES_LESS (dflow, d)) + return 1; + } + else + { + if (REAL_VALUES_LESS (d, sfhigh) + && REAL_VALUES_LESS (sflow, d)) + return 1; + } + + return 0; +} + +/* Accept the floating point constant 1 in the appropriate mode. */ + +int +const_float_1_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + REAL_VALUE_TYPE d; + static REAL_VALUE_TYPE onedf; + static REAL_VALUE_TYPE onesf; + static int one_initialized; + + if (GET_CODE (op) != CONST_DOUBLE + || mode != GET_MODE (op) + || (mode != DFmode && mode != SFmode)) + return 0; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + /* We only initialize these values if we need them, since we will + never get called unless mips_isa >= 4. */ + if (! one_initialized) + { + onedf = REAL_VALUE_ATOF ("1.0", DFmode); + onesf = REAL_VALUE_ATOF ("1.0", SFmode); + one_initialized = 1; + } + + if (mode == DFmode) + return REAL_VALUES_EQUAL (d, onedf); + else + return REAL_VALUES_EQUAL (d, onesf); +} + +/* Return true if a memory load or store of REG plus OFFSET in MODE + can be represented in a single word on the mips16. */ + +static int +mips16_simple_memory_operand (reg, offset, mode) + rtx reg; + rtx offset; + enum machine_mode mode; +{ + int size, off; + + if (mode == BLKmode) + { + /* We can't tell, because we don't know how the value will + eventually be accessed. Returning 0 here does no great + harm; it just prevents some possible instruction scheduling. */ + return 0; + } + + size = GET_MODE_SIZE (mode); + + if (INTVAL (offset) % size != 0) + return 0; + if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4) + off = 0x100; + else + off = 0x20; + if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size) + return 1; + return 0; +} + +/* Return truth value if a memory operand fits in a single instruction + (ie, register + small offset). */ + +int +simple_memory_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + rtx addr, plus0, plus1; + + /* Eliminate non-memory operations */ + if (GET_CODE (op) != MEM) + return 0; + + /* dword operations really put out 2 instructions, so eliminate them. */ + /* ??? This isn't strictly correct. It is OK to accept multiword modes + here, since the length attributes are being set correctly, but only + if the address is offsettable. LO_SUM is not offsettable. */ + if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD) + return 0; + + /* Decode the address now. */ + addr = XEXP (op, 0); + switch (GET_CODE (addr)) + { + case REG: + case LO_SUM: + return 1; + + case CONST_INT: + if (TARGET_MIPS16) + return 0; + return SMALL_INT (op); + + case PLUS: + plus0 = XEXP (addr, 0); + plus1 = XEXP (addr, 1); + if (GET_CODE (plus0) == REG + && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1) + && (! TARGET_MIPS16 + || mips16_simple_memory_operand (plus0, plus1, mode))) + return 1; + + else if (GET_CODE (plus1) == REG + && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0) + && (! TARGET_MIPS16 + || mips16_simple_memory_operand (plus1, plus0, mode))) + return 1; + + else + return 0; + +#if 0 + /* We used to allow small symbol refs here (ie, stuff in .sdata + or .sbss), but this causes some bugs in G++. Also, it won't + interfere if the MIPS linker rewrites the store instruction + because the function is PIC. */ + + case LABEL_REF: /* never gp relative */ + break; + + case CONST: + /* If -G 0, we can never have a GP relative memory operation. + Also, save some time if not optimizing. */ + if (!TARGET_GP_OPT) + return 0; + + { + rtx offset = const0_rtx; + addr = eliminate_constant_term (XEXP (addr, 0), &offset); + if (GET_CODE (op) != SYMBOL_REF) + return 0; + + /* let's be paranoid.... */ + if (! SMALL_INT (offset)) + return 0; + } + + /* fall through */ + + case SYMBOL_REF: + return SYMBOL_REF_FLAG (addr); +#endif + + /* This SYMBOL_REF case is for the mips16. If the above case is + reenabled, this one should be merged in. */ + case SYMBOL_REF: + /* References to the constant pool on the mips16 use a small + offset if the function is small. The only time we care about + getting this right is during delayed branch scheduling, so + don't need to check until then. The machine_dependent_reorg + function will set the total length of the instructions used + in the function in current_frame_info. If that is small + enough, we know for sure that this is a small offset. It + would be better if we could take into account the location of + the instruction within the function, but we can't, because we + don't know where we are. */ + if (TARGET_MIPS16 + && CONSTANT_POOL_ADDRESS_P (addr) + && current_frame_info.insns_len > 0) + { + long size; + + size = current_frame_info.insns_len + get_pool_size (); + if (GET_MODE_SIZE (mode) == 4) + return size < 4 * 0x100; + else if (GET_MODE_SIZE (mode) == 8) + return size < 8 * 0x20; + else + return 0; + } + + return 0; + + default: + break; + } + + return 0; +} + +/* Return nonzero for a memory address that can be used to load or store + a doubleword. */ + +int +double_memory_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + rtx addr; + + if (GET_CODE (op) != MEM + || ! memory_operand (op, mode)) + { + /* During reload, we accept a pseudo register if it has an + appropriate memory address. If we don't do this, we will + wind up reloading into a register, and then reloading that + register from memory, when we could just reload directly from + memory. */ + if (reload_in_progress + && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (op)] < 0 + && reg_equiv_mem[REGNO (op)] != 0 + && double_memory_operand (reg_equiv_mem[REGNO (op)], mode)) + return 1; + + /* All reloaded addresses are valid in TARGET_64BIT mode. This is + the same test performed for 'm' in find_reloads. */ + + if (reload_in_progress + && TARGET_64BIT + && (GET_CODE (op) == MEM + || (GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (op)] < 0))) + return 1; + + if (reload_in_progress + && TARGET_MIPS16 + && GET_CODE (op) == MEM) + { + rtx addr; + + addr = XEXP (op, 0); + + /* During reload on the mips16, we accept a large offset + from the frame pointer or the stack pointer. This large + address will get reloaded anyhow. */ + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 0)) == REG + && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM + || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM) + && ((GET_CODE (XEXP (addr, 1)) == CONST_INT + && ! SMALL_INT (XEXP (addr, 1))) + || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1))))) + return 1; + + /* Similarly, we accept a case where the memory address is + itself on the stack, and will be reloaded. */ + if (GET_CODE (addr) == MEM) + { + rtx maddr; + + maddr = XEXP (addr, 0); + if (GET_CODE (maddr) == PLUS + && GET_CODE (XEXP (maddr, 0)) == REG + && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM + || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM) + && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT + && ! SMALL_INT (XEXP (maddr, 1))) + || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1))))) + return 1; + } + + /* We also accept the same case when we have a 16 bit signed + offset mixed in as well. The large address will get + reloaded, and the 16 bit offset will be OK. */ + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 0)) == MEM + && GET_CODE (XEXP (addr, 1)) == CONST_INT + && SMALL_INT (XEXP (addr, 1))) + { + addr = XEXP (XEXP (addr, 0), 0); + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 0)) == REG + && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM + || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM) + && ((GET_CODE (XEXP (addr, 1)) == CONST_INT + && ! SMALL_INT (XEXP (addr, 1))) + || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1))))) + return 1; + } + } + + return 0; + } + + if (TARGET_64BIT) + { + /* In this case we can use an instruction like sd. */ + return 1; + } + + /* Make sure that 4 added to the address is a valid memory address. + This essentially just checks for overflow in an added constant. */ + + addr = XEXP (op, 0); + + if (CONSTANT_ADDRESS_P (addr)) + return 1; + + return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT + ? SImode + : SFmode), + plus_constant_for_output (addr, 4)); +} + +/* Return nonzero if the code of this rtx pattern is EQ or NE. */ + +int +equality_op (op, mode) + rtx op; + enum machine_mode mode; +{ + if (mode != GET_MODE (op)) + return 0; + + return GET_CODE (op) == EQ || GET_CODE (op) == NE; +} + +/* Return nonzero if the code is a relational operations (EQ, LE, etc.) */ + +int +cmp_op (op, mode) + rtx op; + enum machine_mode mode; +{ + if (mode != GET_MODE (op)) + return 0; + + return GET_RTX_CLASS (GET_CODE (op)) == '<'; +} + +/* Return nonzero if the operand is either the PC or a label_ref. */ + +int +pc_or_label_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (op == pc_rtx) + return 1; + + if (GET_CODE (op) == LABEL_REF) + return 1; + + return 0; +} + +/* Test for a valid operand for a call instruction. + Don't allow the arg pointer register or virtual regs + since they may change into reg + const, which the patterns + can't handle yet. */ + +int +call_insn_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (CONSTANT_ADDRESS_P (op) + || (GET_CODE (op) == REG && op != arg_pointer_rtx + && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER + && REGNO (op) <= LAST_VIRTUAL_REGISTER))); +} + +/* Return nonzero if OPERAND is valid as a source operand for a move + instruction. */ + +int +move_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + /* Accept any general operand after reload has started; doing so + avoids losing if reload does an in-place replacement of a register + with a SYMBOL_REF or CONST. */ + return (general_operand (op, mode) + && (! (mips_split_addresses && mips_check_split (op, mode)) + || reload_in_progress || reload_completed) + && ! (TARGET_MIPS16 + && GET_CODE (op) == SYMBOL_REF + && ! mips16_constant (op, mode, 1, 0))); +} + +/* Return nonzero if OPERAND is valid as a source operand for movdi. + This accepts not only general_operand, but also sign extended + constants and registers. We need to accept sign extended constants + in case a sign extended register which is used in an expression, + and is equivalent to a constant, is spilled. */ + +int +movdi_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && (GET_MODE (XEXP (op, 0)) == SImode + || (GET_CODE (XEXP (op, 0)) == CONST_INT + && GET_MODE (XEXP (op, 0)) == VOIDmode)) + && (register_operand (XEXP (op, 0), SImode) + || immediate_operand (XEXP (op, 0), SImode))) + return 1; + + return (general_operand (op, mode) + && ! (TARGET_MIPS16 + && GET_CODE (op) == SYMBOL_REF + && ! mips16_constant (op, mode, 1, 0))); +} + +/* Like register_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_register_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return register_operand (op, mode); +} + +/* Like reg_or_0_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_reg_or_0_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return reg_or_0_operand (op, mode); +} + +/* Like uns_arith_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_uns_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return uns_arith_operand (op, mode); +} + +/* Like arith_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return arith_operand (op, mode); +} + +/* Like nonmemory_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_nonmemory_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return nonmemory_operand (op, mode); +} + +/* Like nonimmediate_operand, but when in 64 bit mode also accept a + sign extend of a 32 bit register, since the value is known to be + already sign extended. */ + +int +se_nonimmediate_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return nonimmediate_operand (op, mode); +} + +/* Accept any operand that can appear in a mips16 constant table + instruction. We can't use any of the standard operand functions + because for these instructions we accept values that are not + accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */ + +int +consttable_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return CONSTANT_P (op); +} + +/* Return nonzero if we split the address into high and low parts. */ + +/* ??? We should also handle reg+array somewhere. We get four + instructions currently, lui %hi/addui %lo/addui reg/lw. Better is + lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept + (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken + out of the address, then we have 4 instructions to combine. Perhaps + add a 3->2 define_split for combine. */ + +/* ??? We could also split a CONST_INT here if it is a large_int(). + However, it doesn't seem to be very useful to have %hi(constant). + We would be better off by doing the masking ourselves and then putting + the explicit high part of the constant in the RTL. This will give better + optimization. Also, %hi(constant) needs assembler changes to work. + There is already a define_split that does this. */ + +int +mips_check_split (address, mode) + rtx address; + enum machine_mode mode; +{ + /* ??? This is the same check used in simple_memory_operand. + We use it here because LO_SUM is not offsettable. */ + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return 0; + + if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address)) + || (GET_CODE (address) == CONST + && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF + && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0))) + || GET_CODE (address) == LABEL_REF) + return 1; + + return 0; +} + +/* We need a lot of little routines to check constant values on the + mips16. These are used to figure out how long the instruction will + be. It would be much better to do this using constraints, but + there aren't nearly enough letters available. */ + +static int +m16_check_op (op, low, high, mask) + rtx op; + int low; + int high; + int mask; +{ + return (GET_CODE (op) == CONST_INT + && INTVAL (op) >= low + && INTVAL (op) <= high + && (INTVAL (op) & mask) == 0); +} + +int +m16_uimm3_b (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, 0x1, 0x8, 0); +} + +int +m16_simm4_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x8, 0x7, 0); +} + +int +m16_nsimm4_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x7, 0x8, 0); +} + +int +m16_simm5_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x10, 0xf, 0); +} + +int +m16_nsimm5_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0xf, 0x10, 0); +} + +int +m16_uimm5_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3); +} + +int +m16_nuimm5_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3); +} + +int +m16_simm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x80, 0x7f, 0); +} + +int +m16_nsimm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x7f, 0x80, 0); +} + +int +m16_uimm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, 0x0, 0xff, 0); +} + +int +m16_nuimm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0xff, 0x0, 0); +} + +int +m16_uimm8_m1_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x1, 0xfe, 0); +} + +int +m16_uimm8_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, 0x0, 0xff << 2, 3); +} + +int +m16_nuimm8_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0xff) << 2, 0x0, 3); +} + +int +m16_simm8_8 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7); +} + +int +m16_nsimm8_8 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7); +} + +/* References to the string table on the mips16 only use a small + offset if the function is small. See the comment in the SYMBOL_REF + case in simple_memory_operand. We can't check for LABEL_REF here, + because the offset is always large if the label is before the + referencing instruction. */ + +int +m16_usym8_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) == SYMBOL_REF + && SYMBOL_REF_FLAG (op) + && current_frame_info.insns_len > 0 + && XSTR (op, 0)[0] == '*' + && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) == 0 + && (current_frame_info.insns_len + get_pool_size () + mips_string_length + < 4 * 0x100)) + { + struct string_constant *l; + + /* Make sure this symbol is on thelist of string constants to be + output for this function. It is possible that it has already + been output, in which case this requires a large offset. */ + for (l = string_constants; l != NULL; l = l->next) + if (strcmp (l->label, XSTR (op, 0)) == 0) + return 1; + } + + return 0; +} + +int +m16_usym5_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) == SYMBOL_REF + && SYMBOL_REF_FLAG (op) + && current_frame_info.insns_len > 0 + && XSTR (op, 0)[0] == '*' + && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) == 0 + && (current_frame_info.insns_len + get_pool_size () + mips_string_length + < 4 * 0x20)) + { + struct string_constant *l; + + /* Make sure this symbol is on thelist of string constants to be + output for this function. It is possible that it has already + been output, in which case this requires a large offset. */ + for (l = string_constants; l != NULL; l = l->next) + if (strcmp (l->label, XSTR (op, 0)) == 0) + return 1; + } + + return 0; +} + +/* Returns an operand string for the given instruction's delay slot, + after updating filled delay slot statistics. + + We assume that operands[0] is the target register that is set. + + In order to check the next insn, most of this functionality is moved + to FINAL_PRESCAN_INSN, and we just set the global variables that + it needs. */ + +/* ??? This function no longer does anything useful, because final_prescan_insn + now will never emit a nop. */ + +char * +mips_fill_delay_slot (ret, type, operands, cur_insn) + char *ret; /* normal string to return */ + enum delay_type type; /* type of delay */ + rtx operands[]; /* operands to use */ + rtx cur_insn; /* current insn */ +{ + register rtx set_reg; + register enum machine_mode mode; + register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX; + register int num_nops; + + if (type == DELAY_LOAD || type == DELAY_FCMP) + num_nops = 1; + + else if (type == DELAY_HILO) + num_nops = 2; + + else + num_nops = 0; + + /* Make sure that we don't put nop's after labels. */ + next_insn = NEXT_INSN (cur_insn); + while (next_insn != 0 && GET_CODE (next_insn) == NOTE) + next_insn = NEXT_INSN (next_insn); + + dslots_load_total += num_nops; + if (TARGET_DEBUG_F_MODE + || !optimize + || type == DELAY_NONE + || operands == 0 + || cur_insn == 0 + || next_insn == 0 + || GET_CODE (next_insn) == CODE_LABEL + || (set_reg = operands[0]) == 0) + { + dslots_number_nops = 0; + mips_load_reg = 0; + mips_load_reg2 = 0; + mips_load_reg3 = 0; + mips_load_reg4 = 0; + return ret; + } + + set_reg = operands[0]; + if (set_reg == 0) + return ret; + + while (GET_CODE (set_reg) == SUBREG) + set_reg = SUBREG_REG (set_reg); + + mode = GET_MODE (set_reg); + dslots_number_nops = num_nops; + mips_load_reg = set_reg; + if (GET_MODE_SIZE (mode) + > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD)) + mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1); + else + mips_load_reg2 = 0; + + if (type == DELAY_HILO) + { + mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST); + mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1); + } + else + { + mips_load_reg3 = 0; + mips_load_reg4 = 0; + } + + return ret; +} + + +/* Determine whether a memory reference takes one (based off of the GP + pointer), two (normal), or three (label + reg) instructions, and bump the + appropriate counter for -mstats. */ + +void +mips_count_memory_refs (op, num) + rtx op; + int num; +{ + int additional = 0; + int n_words = 0; + rtx addr, plus0, plus1; + enum rtx_code code0, code1; + int looping; + + if (TARGET_DEBUG_B_MODE) + { + fprintf (stderr, "\n========== mips_count_memory_refs:\n"); + debug_rtx (op); + } + + /* Skip MEM if passed, otherwise handle movsi of address. */ + addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0); + + /* Loop, going through the address RTL. */ + do + { + looping = FALSE; + switch (GET_CODE (addr)) + { + case REG: + case CONST_INT: + case LO_SUM: + break; + + case PLUS: + plus0 = XEXP (addr, 0); + plus1 = XEXP (addr, 1); + code0 = GET_CODE (plus0); + code1 = GET_CODE (plus1); + + if (code0 == REG) + { + additional++; + addr = plus1; + looping = 1; + continue; + } + + if (code0 == CONST_INT) + { + addr = plus1; + looping = 1; + continue; + } + + if (code1 == REG) + { + additional++; + addr = plus0; + looping = 1; + continue; + } + + if (code1 == CONST_INT) + { + addr = plus0; + looping = 1; + continue; + } + + if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST) + { + addr = plus0; + looping = 1; + continue; + } + + if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST) + { + addr = plus1; + looping = 1; + continue; + } + + break; + + case LABEL_REF: + n_words = 2; /* always 2 words */ + break; + + case CONST: + addr = XEXP (addr, 0); + looping = 1; + continue; + + case SYMBOL_REF: + n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2; + break; + + default: + break; + } + } + while (looping); + + if (n_words == 0) + return; + + n_words += additional; + if (n_words > 3) + n_words = 3; + + num_refs[n_words-1] += num; +} + + +/* Return RTL for the offset from the current function to the argument. + + ??? Which argument is this? */ + +rtx +embedded_pic_offset (x) + rtx x; +{ + if (embedded_pic_fnaddr_rtx == NULL) + { + rtx seq; + + embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode); + + /* Output code at function start to initialize the pseudo-reg. */ + /* ??? We used to do this in FINALIZE_PIC, but that does not work for + inline functions, because it is called after RTL for the function + has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however + does not get copied, and ends up not matching the rest of the RTL. + This solution works, but means that we get unnecessary code to + initialize this value every time a function is inlined into another + function. */ + start_sequence (); + emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx, + XEXP (DECL_RTL (current_function_decl), 0))); + seq = gen_sequence (); + end_sequence (); + push_topmost_sequence (); + emit_insn_after (seq, get_insns ()); + pop_topmost_sequence (); + } + + return gen_rtx (CONST, Pmode, + gen_rtx (MINUS, Pmode, x, + XEXP (DECL_RTL (current_function_decl), 0))); +} + +/* Return the appropriate instructions to move one operand to another. */ + +const char * +mips_move_1word (operands, insn, unsignedp) + rtx operands[]; + rtx insn; + int unsignedp; +{ + const char *ret = 0; + rtx op0 = operands[0]; + rtx op1 = operands[1]; + enum rtx_code code0 = GET_CODE (op0); + enum rtx_code code1 = GET_CODE (op1); + enum machine_mode mode = GET_MODE (op0); + int subreg_word0 = 0; + int subreg_word1 = 0; + enum delay_type delay = DELAY_NONE; + + while (code0 == SUBREG) + { + subreg_word0 += SUBREG_WORD (op0); + op0 = SUBREG_REG (op0); + code0 = GET_CODE (op0); + } + + while (code1 == SUBREG) + { + subreg_word1 += SUBREG_WORD (op1); + op1 = SUBREG_REG (op1); + code1 = GET_CODE (op1); + } + + /* For our purposes, a condition code mode is the same as SImode. */ + if (mode == CCmode) + mode = SImode; + + if (code0 == REG) + { + int regno0 = REGNO (op0) + subreg_word0; + + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + /* Just in case, don't do anything for assigning a register + to itself, unless we are filling a delay slot. */ + if (regno0 == regno1 && set_nomacro == 0) + ret = ""; + + else if (GP_REG_P (regno0)) + { + if (GP_REG_P (regno1)) + ret = "move\t%0,%1"; + + else if (MD_REG_P (regno1)) + { + delay = DELAY_HILO; + if (regno1 != HILO_REGNUM) + ret = "mf%1\t%0"; + else + ret = "mflo\t%0"; + } + + else if (ST_REG_P (regno1) && mips_isa >= 4) + ret = "li\t%0,1\n\tmovf\t%0,%.,%1"; + + else + { + delay = DELAY_LOAD; + if (FP_REG_P (regno1)) + ret = "mfc1\t%0,%1"; + + else if (regno1 == FPSW_REGNUM && mips_isa < 4) + ret = "cfc1\t%0,$31"; + } + } + + else if (FP_REG_P (regno0)) + { + if (GP_REG_P (regno1)) + { + delay = DELAY_LOAD; + ret = "mtc1\t%1,%0"; + } + + if (FP_REG_P (regno1)) + ret = "mov.s\t%0,%1"; + } + + else if (MD_REG_P (regno0)) + { + if (GP_REG_P (regno1)) + { + delay = DELAY_HILO; + if (regno0 != HILO_REGNUM && ! TARGET_MIPS16) + ret = "mt%0\t%1"; + } + } + + else if (regno0 == FPSW_REGNUM && mips_isa < 4) + { + if (GP_REG_P (regno1)) + { + delay = DELAY_LOAD; + ret = "ctc1\t%0,$31"; + } + } + } + + else if (code1 == MEM) + { + delay = DELAY_LOAD; + + if (TARGET_STATS) + mips_count_memory_refs (op1, 1); + + if (GP_REG_P (regno0)) + { + /* For loads, use the mode of the memory item, instead of the + target, so zero/sign extend can use this code as well. */ + switch (GET_MODE (op1)) + { + default: + break; + case SFmode: + ret = "lw\t%0,%1"; + break; + case SImode: + case CCmode: + ret = ((unsignedp && TARGET_64BIT) + ? "lwu\t%0,%1" + : "lw\t%0,%1"); + break; + case HImode: + ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1"; + break; + case QImode: + ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1"; + break; + } + } + + else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode)) + ret = "l.s\t%0,%1"; + + if (ret != (char *)0 && MEM_VOLATILE_P (op1)) + { + size_t i = strlen (ret); + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + else if (code1 == CONST_INT + || (code1 == CONST_DOUBLE + && GET_MODE (op1) == VOIDmode)) + { + if (code1 == CONST_DOUBLE) + { + /* This can happen when storing constants into long long + bitfields. Just store the least significant word of + the value. */ + operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); + } + + if (INTVAL (op1) == 0 && ! TARGET_MIPS16) + { + if (GP_REG_P (regno0)) + ret = "move\t%0,%z1"; + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = "mtc1\t%z1,%0"; + } + + else if (MD_REG_P (regno0)) + { + delay = DELAY_HILO; + ret = "mt%0\t%."; + } + } + + else if (GP_REG_P (regno0)) + { + /* Don't use X format, because that will give out of + range numbers for 64 bit host and 32 bit target. */ + if (! TARGET_MIPS16) + ret = "li\t%0,%1\t\t\t# %X1"; + else + { + if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff) + ret = "li\t%0,%1"; + else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff) + ret = "li\t%0,%n1\n\tneg\t%0"; + } + } + } + + else if (code1 == CONST_DOUBLE && mode == SFmode) + { + if (op1 == CONST0_RTX (SFmode)) + { + if (GP_REG_P (regno0)) + ret = "move\t%0,%."; + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = "mtc1\t%.,%0"; + } + } + + else + { + delay = DELAY_LOAD; + ret = "li.s\t%0,%1"; + } + } + + else if (code1 == LABEL_REF) + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 1); + + ret = "la\t%0,%a1"; + } + + else if (code1 == SYMBOL_REF || code1 == CONST) + { + if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1)) + { + rtx offset = const0_rtx; + + if (GET_CODE (op1) == CONST) + op1 = eliminate_constant_term (XEXP (op1, 0), &offset); + + if (GET_CODE (op1) == SYMBOL_REF) + { + operands[2] = HALF_PIC_PTR (op1); + + if (TARGET_STATS) + mips_count_memory_refs (operands[2], 1); + + if (INTVAL (offset) == 0) + { + delay = DELAY_LOAD; + ret = (unsignedp && TARGET_64BIT + ? "lwu\t%0,%2" + : "lw\t%0,%2"); + } + else + { + dslots_load_total++; + operands[3] = offset; + if (unsignedp && TARGET_64BIT) + ret = (SMALL_INT (offset) + ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3" + : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]"); + else + ret = (SMALL_INT (offset) + ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3" + : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]"); + } + } + } + else if (TARGET_MIPS16 + && code1 == CONST + && GET_CODE (XEXP (op1, 0)) == REG + && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28) + { + /* This case arises on the mips16; see + mips16_gp_pseudo_reg. */ + ret = "move\t%0,%+"; + } + else if (TARGET_MIPS16 + && code1 == SYMBOL_REF + && SYMBOL_REF_FLAG (op1) + && (XSTR (op1, 0)[0] != '*' + || strncmp (XSTR (op1, 0) + 1, + LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) != 0)) + { + /* This can occur when reloading the address of a GP + relative symbol on the mips16. */ + ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)"; + } + else + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 1); + + ret = "la\t%0,%a1"; + } + } + + else if (code1 == PLUS) + { + rtx add_op0 = XEXP (op1, 0); + rtx add_op1 = XEXP (op1, 1); + + if (GET_CODE (XEXP (op1, 1)) == REG + && GET_CODE (XEXP (op1, 0)) == CONST_INT) + add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0); + + operands[2] = add_op0; + operands[3] = add_op1; + ret = "add%:\t%0,%2,%3"; + } + + else if (code1 == HIGH) + { + operands[1] = XEXP (op1, 0); + ret = "lui\t%0,%%hi(%1)"; + } + } + + else if (code0 == MEM) + { + if (TARGET_STATS) + mips_count_memory_refs (op0, 1); + + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + if (GP_REG_P (regno1)) + { + switch (mode) + { + case SFmode: ret = "sw\t%1,%0"; break; + case SImode: ret = "sw\t%1,%0"; break; + case HImode: ret = "sh\t%1,%0"; break; + case QImode: ret = "sb\t%1,%0"; break; + default: break; + } + } + + else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode)) + ret = "s.s\t%1,%0"; + } + + else if (code1 == CONST_INT && INTVAL (op1) == 0) + { + switch (mode) + { + case SFmode: ret = "sw\t%z1,%0"; break; + case SImode: ret = "sw\t%z1,%0"; break; + case HImode: ret = "sh\t%z1,%0"; break; + case QImode: ret = "sb\t%z1,%0"; break; + default: break; + } + } + + else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode)) + { + switch (mode) + { + case SFmode: ret = "sw\t%.,%0"; break; + case SImode: ret = "sw\t%.,%0"; break; + case HImode: ret = "sh\t%.,%0"; break; + case QImode: ret = "sb\t%.,%0"; break; + default: break; + } + } + + if (ret != 0 && MEM_VOLATILE_P (op0)) + { + size_t i = strlen (ret); + + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + if (ret == 0) + { + abort_with_insn (insn, "Bad move"); + return 0; + } + + if (delay != DELAY_NONE) + return mips_fill_delay_slot (ret, delay, operands, insn); + + return ret; +} + + +/* Return the appropriate instructions to move 2 words */ + +const char * +mips_move_2words (operands, insn) + rtx operands[]; + rtx insn; +{ + const char *ret = 0; + rtx op0 = operands[0]; + rtx op1 = operands[1]; + enum rtx_code code0 = GET_CODE (operands[0]); + enum rtx_code code1 = GET_CODE (operands[1]); + int subreg_word0 = 0; + int subreg_word1 = 0; + enum delay_type delay = DELAY_NONE; + + while (code0 == SUBREG) + { + subreg_word0 += SUBREG_WORD (op0); + op0 = SUBREG_REG (op0); + code0 = GET_CODE (op0); + } + + if (code1 == SIGN_EXTEND) + { + op1 = XEXP (op1, 0); + code1 = GET_CODE (op1); + } + + while (code1 == SUBREG) + { + subreg_word1 += SUBREG_WORD (op1); + op1 = SUBREG_REG (op1); + code1 = GET_CODE (op1); + } + + /* Sanity check. */ + if (GET_CODE (operands[1]) == SIGN_EXTEND + && code1 != REG + && code1 != CONST_INT + /* The following three can happen as the result of a questionable + cast. */ + && code1 != LABEL_REF + && code1 != SYMBOL_REF + && code1 != CONST) + abort (); + + if (code0 == REG) + { + int regno0 = REGNO (op0) + subreg_word0; + + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + /* Just in case, don't do anything for assigning a register + to itself, unless we are filling a delay slot. */ + if (regno0 == regno1 && set_nomacro == 0) + ret = ""; + + else if (FP_REG_P (regno0)) + { + if (FP_REG_P (regno1)) + ret = "mov.d\t%0,%1"; + + else + { + delay = DELAY_LOAD; + if (TARGET_FLOAT64) + { + if (!TARGET_64BIT) + abort_with_insn (insn, "Bad move"); + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno1)) + ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0"; + else +#endif + ret = "dmtc1\t%1,%0"; + } + else + ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0"; + } + } + + else if (FP_REG_P (regno1)) + { + delay = DELAY_LOAD; + if (TARGET_FLOAT64) + { + if (!TARGET_64BIT) + abort_with_insn (insn, "Bad move"); + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno0)) + ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32"; + else +#endif + ret = "dmfc1\t%0,%1"; + } + else + ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1"; + } + + else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16) + { + delay = DELAY_HILO; + if (TARGET_64BIT) + { + if (regno0 != HILO_REGNUM) + ret = "mt%0\t%1"; + else if (regno1 == 0) + ret = "mtlo\t%.\n\tmthi\t%."; + } + else + ret = "mthi\t%M1\n\tmtlo\t%L1"; + } + + else if (GP_REG_P (regno0) && MD_REG_P (regno1)) + { + delay = DELAY_HILO; + if (TARGET_64BIT) + { + if (regno1 != HILO_REGNUM) + ret = "mf%1\t%0"; + } + else + ret = "mfhi\t%M0\n\tmflo\t%L0"; + } + + else if (TARGET_64BIT) + ret = "move\t%0,%1"; + + else if (regno0 != (regno1+1)) + ret = "move\t%0,%1\n\tmove\t%D0,%D1"; + + else + ret = "move\t%D0,%D1\n\tmove\t%0,%1"; + } + + else if (code1 == CONST_DOUBLE) + { + /* Move zero from $0 unless !TARGET_64BIT and recipient + is 64-bit fp reg, in which case generate a constant. */ + if (op1 != CONST0_RTX (GET_MODE (op1)) + || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0))) + { + if (GET_MODE (op1) == DFmode) + { + delay = DELAY_LOAD; + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno0)) + { + if (TARGET_FLOAT64 && !TARGET_64BIT) + { + split_double (op1, operands + 2, operands + 3); + ret = "li\t%0,%2\n\tli\t%D0,%3"; + } + else + ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32"; + } + else +#endif + ret = "li.d\t%0,%1"; + } + + else if (TARGET_64BIT) + { + if (! TARGET_MIPS16) + ret = "dli\t%0,%1"; + } + + else + { + split_double (op1, operands + 2, operands + 3); + ret = "li\t%0,%2\n\tli\t%D0,%3"; + } + } + + else + { + if (GP_REG_P (regno0)) + ret = (TARGET_64BIT +#ifdef TARGET_FP_CALL_32 + && ! FP_CALL_GP_REG_P (regno0) +#endif + ? "move\t%0,%." + : "move\t%0,%.\n\tmove\t%D0,%."); + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = (TARGET_64BIT + ? "dmtc1\t%.,%0" + : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"); + } + } + } + + else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16) + { + if (GP_REG_P (regno0)) + ret = (TARGET_64BIT + ? "move\t%0,%." + : "move\t%0,%.\n\tmove\t%D0,%."); + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = (TARGET_64BIT + ? "dmtc1\t%.,%0" + : (TARGET_FLOAT64 + ? "li.d\t%0,%1" + : "mtc1\t%.,%0\n\tmtc1\t%.,%D0")); + } + else if (MD_REG_P (regno0)) + { + delay = DELAY_HILO; + ret = (regno0 == HILO_REGNUM + ? "mtlo\t%.\n\tmthi\t%." + : "mt%0\t%.\n"); + } + } + + else if (code1 == CONST_INT && GET_MODE (op0) == DImode + && GP_REG_P (regno0)) + { + if (TARGET_64BIT) + { + if (TARGET_MIPS16) + { + if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff) + ret = "li\t%0,%1"; + else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff) + ret = "li\t%0,%n1\n\tneg\t%0"; + } + else if (GET_CODE (operands[1]) == SIGN_EXTEND) + ret = "li\t%0,%1\t\t# %X1"; + else if (HOST_BITS_PER_WIDE_INT < 64) + /* We can't use 'X' for negative numbers, because then we won't + get the right value for the upper 32 bits. */ + ret = (INTVAL (op1) < 0 + ? "dli\t%0,%1\t\t\t# %X1" + : "dli\t%0,%X1\t\t# %1"); + else + /* We must use 'X', because otherwise LONG_MIN will print as + a number that the assembler won't accept. */ + ret = "dli\t%0,%X1\t\t# %1"; + } + else if (HOST_BITS_PER_WIDE_INT < 64) + { + operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1); + if (TARGET_MIPS16) + { + if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff) + ret = "li\t%M0,%2\n\tli\t%L0,%1"; + else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff) + { + operands[2] = GEN_INT (1); + ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0"; + } + } + else + ret = "li\t%M0,%2\n\tli\t%L0,%1"; + } + else + { + /* We use multiple shifts here, to avoid warnings about out + of range shifts on 32 bit hosts. */ + operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16); + operands[1] + = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16); + ret = "li\t%M0,%2\n\tli\t%L0,%1"; + } + } + + else if (code1 == MEM) + { + delay = DELAY_LOAD; + + if (TARGET_STATS) + mips_count_memory_refs (op1, 2); + + if (FP_REG_P (regno0)) + ret = "l.d\t%0,%1"; + + else if (TARGET_64BIT) + { + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno0)) + ret = (double_memory_operand (op1, GET_MODE (op1)) + ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1" + : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32"); + else +#endif + ret = "ld\t%0,%1"; + } + + else if (double_memory_operand (op1, GET_MODE (op1))) + { + operands[2] = adj_offsettable_operand (op1, 4); + ret = (reg_mentioned_p (op0, op1) + ? "lw\t%D0,%2\n\tlw\t%0,%1" + : "lw\t%0,%1\n\tlw\t%D0,%2"); + } + + if (ret != 0 && MEM_VOLATILE_P (op1)) + { + size_t i = strlen (ret); + + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + else if (code1 == LABEL_REF) + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 2); + + if (GET_CODE (operands[1]) == SIGN_EXTEND) + /* We deliberately remove the 'a' from '%1', so that we don't + have to add SIGN_EXTEND support to print_operand_address. + print_operand will just call print_operand_address in this + case, so there is no problem. */ + ret = "la\t%0,%1"; + else + ret = "dla\t%0,%a1"; + } + else if (code1 == SYMBOL_REF || code1 == CONST) + { + if (TARGET_MIPS16 + && code1 == CONST + && GET_CODE (XEXP (op1, 0)) == REG + && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28) + { + /* This case arises on the mips16; see + mips16_gp_pseudo_reg. */ + ret = "move\t%0,%+"; + } + else if (TARGET_MIPS16 + && code1 == SYMBOL_REF + && SYMBOL_REF_FLAG (op1) + && (XSTR (op1, 0)[0] != '*' + || strncmp (XSTR (op1, 0) + 1, + LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) != 0)) + { + /* This can occur when reloading the address of a GP + relative symbol on the mips16. */ + ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)"; + } + else + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 2); + + if (GET_CODE (operands[1]) == SIGN_EXTEND) + /* We deliberately remove the 'a' from '%1', so that we don't + have to add SIGN_EXTEND support to print_operand_address. + print_operand will just call print_operand_address in this + case, so there is no problem. */ + ret = "la\t%0,%1"; + else + ret = "dla\t%0,%a1"; + } + } + } + + else if (code0 == MEM) + { + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + if (FP_REG_P (regno1)) + ret = "s.d\t%1,%0"; + + else if (TARGET_64BIT) + { + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno1)) + ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0"; + else +#endif + ret = "sd\t%1,%0"; + } + + else if (double_memory_operand (op0, GET_MODE (op0))) + { + operands[2] = adj_offsettable_operand (op0, 4); + ret = "sw\t%1,%0\n\tsw\t%D1,%2"; + } + } + + else if (((code1 == CONST_INT && INTVAL (op1) == 0) + || (code1 == CONST_DOUBLE + && op1 == CONST0_RTX (GET_MODE (op1)))) + && (TARGET_64BIT + || double_memory_operand (op0, GET_MODE (op0)))) + { + if (TARGET_64BIT) + ret = "sd\t%.,%0"; + else + { + operands[2] = adj_offsettable_operand (op0, 4); + ret = "sw\t%.,%0\n\tsw\t%.,%2"; + } + } + + if (TARGET_STATS) + mips_count_memory_refs (op0, 2); + + if (ret != 0 && MEM_VOLATILE_P (op0)) + { + size_t i = strlen (ret); + + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + if (ret == 0) + { + abort_with_insn (insn, "Bad move"); + return 0; + } + + if (delay != DELAY_NONE) + return mips_fill_delay_slot (ret, delay, operands, insn); + + return ret; +} + +/* Provide the costs of an addressing mode that contains ADDR. + If ADDR is not a valid address, its cost is irrelevant. */ + +int +mips_address_cost (addr) + rtx addr; +{ + switch (GET_CODE (addr)) + { + case LO_SUM: + return 1; + + case LABEL_REF: + return 2; + + case CONST: + { + rtx offset = const0_rtx; + addr = eliminate_constant_term (XEXP (addr, 0), &offset); + if (GET_CODE (addr) == LABEL_REF) + return 2; + + if (GET_CODE (addr) != SYMBOL_REF) + return 4; + + if (! SMALL_INT (offset)) + return 2; + } + + /* ... fall through ... */ + + case SYMBOL_REF: + return SYMBOL_REF_FLAG (addr) ? 1 : 2; + + case PLUS: + { + register rtx plus0 = XEXP (addr, 0); + register rtx plus1 = XEXP (addr, 1); + + if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) + plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0); + + if (GET_CODE (plus0) != REG) + break; + + switch (GET_CODE (plus1)) + { + case CONST_INT: + return SMALL_INT (plus1) ? 1 : 2; + + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case HIGH: + case LO_SUM: + return mips_address_cost (plus1) + 1; + + default: + break; + } + } + + default: + break; + } + + return 4; +} + +/* Return nonzero if X is an address which needs a temporary register when + reloaded while generating PIC code. */ + +int +pic_address_needs_scratch (x) + rtx x; +{ + /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) + return 1; + + return 0; +} + +/* Make normal rtx_code into something we can index from an array */ + +static enum internal_test +map_test_to_internal_test (test_code) + enum rtx_code test_code; +{ + enum internal_test test = ITEST_MAX; + + switch (test_code) + { + case EQ: test = ITEST_EQ; break; + case NE: test = ITEST_NE; break; + case GT: test = ITEST_GT; break; + case GE: test = ITEST_GE; break; + case LT: test = ITEST_LT; break; + case LE: test = ITEST_LE; break; + case GTU: test = ITEST_GTU; break; + case GEU: test = ITEST_GEU; break; + case LTU: test = ITEST_LTU; break; + case LEU: test = ITEST_LEU; break; + default: break; + } + + return test; +} + + +/* Generate the code to compare two integer values. The return value is: + (reg:SI xx) The pseudo register the comparison is in + 0 No register, generate a simple branch. + + ??? This is called with result nonzero by the Scond patterns in + mips.md. These patterns are called with a target in the mode of + the Scond instruction pattern. Since this must be a constant, we + must use SImode. This means that if RESULT is non-zero, it will + always be an SImode register, even if TARGET_64BIT is true. We + cope with this by calling convert_move rather than emit_move_insn. + This will sometimes lead to an unnecessary extension of the result; + for example: + + long long + foo (long long i) + { + return i < 5; + } + + */ + +rtx +gen_int_relational (test_code, result, cmp0, cmp1, p_invert) + enum rtx_code test_code; /* relational test (EQ, etc) */ + rtx result; /* result to store comp. or 0 if branch */ + rtx cmp0; /* first operand to compare */ + rtx cmp1; /* second operand to compare */ + int *p_invert; /* NULL or ptr to hold whether branch needs */ + /* to reverse its test */ +{ + struct cmp_info + { + enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */ + int const_low; /* low bound of constant we can accept */ + int const_high; /* high bound of constant we can accept */ + int const_add; /* constant to add (convert LE -> LT) */ + int reverse_regs; /* reverse registers in test */ + int invert_const; /* != 0 if invert value if cmp1 is constant */ + int invert_reg; /* != 0 if invert value if cmp1 is register */ + int unsignedp; /* != 0 for unsigned comparisons. */ + }; + + static struct cmp_info info[ (int)ITEST_MAX ] = { + + { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */ + { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */ + { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */ + { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */ + { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */ + { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */ + { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */ + { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */ + { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */ + { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */ + }; + + enum internal_test test; + enum machine_mode mode; + struct cmp_info *p_info; + int branch_p; + int eqne_p; + int invert; + rtx reg; + rtx reg2; + + test = map_test_to_internal_test (test_code); + if (test == ITEST_MAX) + abort (); + + p_info = &info[(int) test]; + eqne_p = (p_info->test_code == XOR); + + mode = GET_MODE (cmp0); + if (mode == VOIDmode) + mode = GET_MODE (cmp1); + + /* Eliminate simple branches */ + branch_p = (result == 0); + if (branch_p) + { + if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG) + { + /* Comparisons against zero are simple branches */ + if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0 + && (! TARGET_MIPS16 || eqne_p)) + return 0; + + /* Test for beq/bne. */ + if (eqne_p && ! TARGET_MIPS16) + return 0; + } + + /* allocate a pseudo to calculate the value in. */ + result = gen_reg_rtx (mode); + } + + /* Make sure we can handle any constants given to us. */ + if (GET_CODE (cmp0) == CONST_INT) + cmp0 = force_reg (mode, cmp0); + + if (GET_CODE (cmp1) == CONST_INT) + { + HOST_WIDE_INT value = INTVAL (cmp1); + + if (value < p_info->const_low + || value > p_info->const_high + /* ??? Why? And why wasn't the similar code below modified too? */ + || (TARGET_64BIT + && HOST_BITS_PER_WIDE_INT < 64 + && p_info->const_add != 0 + && ((p_info->unsignedp + ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add) + > (unsigned HOST_WIDE_INT) INTVAL (cmp1)) + : (value + p_info->const_add) > INTVAL (cmp1)) + != (p_info->const_add > 0)))) + cmp1 = force_reg (mode, cmp1); + } + + /* See if we need to invert the result. */ + invert = (GET_CODE (cmp1) == CONST_INT + ? p_info->invert_const : p_info->invert_reg); + + if (p_invert != (int *)0) + { + *p_invert = invert; + invert = 0; + } + + /* Comparison to constants, may involve adding 1 to change a LT into LE. + Comparison between two registers, may involve switching operands. */ + if (GET_CODE (cmp1) == CONST_INT) + { + if (p_info->const_add != 0) + { + HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add; + + /* If modification of cmp1 caused overflow, + we would get the wrong answer if we follow the usual path; + thus, x > 0xffffffffU would turn into x > 0U. */ + if ((p_info->unsignedp + ? (unsigned HOST_WIDE_INT) new > + (unsigned HOST_WIDE_INT) INTVAL (cmp1) + : new > INTVAL (cmp1)) + != (p_info->const_add > 0)) + { + /* This test is always true, but if INVERT is true then + the result of the test needs to be inverted so 0 should + be returned instead. */ + emit_move_insn (result, invert ? const0_rtx : const_true_rtx); + return result; + } + else + cmp1 = GEN_INT (new); + } + } + + else if (p_info->reverse_regs) + { + rtx temp = cmp0; + cmp0 = cmp1; + cmp1 = temp; + } + + if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) + reg = cmp0; + else + { + reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result; + convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0); + } + + if (test == ITEST_NE) + { + if (! TARGET_MIPS16) + { + convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0); + invert = 0; + } + else + { + reg2 = invert ? gen_reg_rtx (mode) : result; + convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0); + reg = reg2; + } + } + + else if (test == ITEST_EQ) + { + reg2 = invert ? gen_reg_rtx (mode) : result; + convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0); + reg = reg2; + } + + if (invert) + { + rtx one; + + if (! TARGET_MIPS16) + one = const1_rtx; + else + { + /* The value is in $24. Copy it to another register, so + that reload doesn't think it needs to store the $24 and + the input to the XOR in the same location. */ + reg2 = gen_reg_rtx (mode); + emit_move_insn (reg2, reg); + reg = reg2; + one = force_reg (mode, const1_rtx); + } + convert_move (result, gen_rtx (XOR, mode, reg, one), 0); + } + + return result; +} + +/* Emit the common code for doing conditional branches. + operand[0] is the label to jump to. + The comparison operands are saved away by cmp{si,di,sf,df}. */ + +void +gen_conditional_branch (operands, test_code) + rtx operands[]; + enum rtx_code test_code; +{ + enum cmp_type type = branch_type; + rtx cmp0 = branch_cmp[0]; + rtx cmp1 = branch_cmp[1]; + enum machine_mode mode; + rtx reg; + int invert; + rtx label1, label2; + + switch (type) + { + case CMP_SI: + case CMP_DI: + mode = type == CMP_SI ? SImode : DImode; + invert = 0; + reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert); + + if (reg) + { + cmp0 = reg; + cmp1 = const0_rtx; + test_code = NE; + } + else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0) + /* We don't want to build a comparison against a non-zero + constant. */ + cmp1 = force_reg (mode, cmp1); + + break; + + case CMP_SF: + case CMP_DF: + if (mips_isa < 4) + reg = gen_rtx (REG, CCmode, FPSW_REGNUM); + else + reg = gen_reg_rtx (CCmode); + + /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result == + 0 in the instruction built below. The MIPS FPU handles + inequality testing by testing for equality and looking for a + false result. */ + emit_insn (gen_rtx (SET, VOIDmode, reg, + gen_rtx (test_code == NE ? EQ : test_code, + CCmode, cmp0, cmp1))); + + test_code = test_code == NE ? EQ : NE; + mode = CCmode; + cmp0 = reg; + cmp1 = const0_rtx; + invert = 0; + break; + + default: + abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test"); + } + + /* Generate the branch. */ + + label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]); + label2 = pc_rtx; + + if (invert) + { + label2 = label1; + label1 = pc_rtx; + } + + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, + gen_rtx (IF_THEN_ELSE, VOIDmode, + gen_rtx (test_code, mode, cmp0, cmp1), + label1, label2))); +} + +/* Emit the common code for conditional moves. OPERANDS is the array + of operands passed to the conditional move defined_expand. */ + +void +gen_conditional_move (operands) + rtx *operands; +{ + rtx op0 = branch_cmp[0]; + rtx op1 = branch_cmp[1]; + enum machine_mode mode = GET_MODE (branch_cmp[0]); + enum rtx_code cmp_code = GET_CODE (operands[1]); + enum rtx_code move_code = NE; + enum machine_mode op_mode = GET_MODE (operands[0]); + enum machine_mode cmp_mode; + rtx cmp_reg; + + if (GET_MODE_CLASS (mode) != MODE_FLOAT) + { + switch (cmp_code) + { + case EQ: + cmp_code = XOR; + move_code = EQ; + break; + case NE: + cmp_code = XOR; + break; + case LT: + break; + case GE: + cmp_code = LT; + move_code = EQ; + break; + case GT: + cmp_code = LT; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + break; + case LE: + cmp_code = LT; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + move_code = EQ; + break; + case LTU: + break; + case GEU: + cmp_code = LTU; + move_code = EQ; + break; + case GTU: + cmp_code = LTU; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + break; + case LEU: + cmp_code = LTU; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + move_code = EQ; + break; + default: + abort (); + } + } + else if (cmp_code == NE) + cmp_code = EQ, move_code = EQ; + + if (mode == SImode || mode == DImode) + cmp_mode = mode; + else if (mode == SFmode || mode == DFmode) + cmp_mode = CCmode; + else + abort (); + + cmp_reg = gen_reg_rtx (cmp_mode); + emit_insn (gen_rtx (SET, cmp_mode, cmp_reg, + gen_rtx (cmp_code, cmp_mode, op0, op1))); + + emit_insn (gen_rtx (SET, op_mode, operands[0], + gen_rtx (IF_THEN_ELSE, op_mode, + gen_rtx (move_code, VOIDmode, + cmp_reg, CONST0_RTX (SImode)), + operands[2], operands[3]))); +} + +/* Write a loop to move a constant number of bytes. + Generate load/stores as follows: + + do { + temp1 = src[0]; + temp2 = src[1]; + ... + temp = src[MAX_MOVE_REGS-1]; + dest[0] = temp1; + dest[1] = temp2; + ... + dest[MAX_MOVE_REGS-1] = temp; + src += MAX_MOVE_REGS; + dest += MAX_MOVE_REGS; + } while (src != final); + + This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp + registers are needed. + + Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3 + cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every + (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */ + +#define MAX_MOVE_REGS 4 +#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) + +static void +block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src) + rtx dest_reg; /* register holding destination address */ + rtx src_reg; /* register holding source address */ + int bytes; /* # bytes to move */ + int align; /* alignment */ + rtx orig_dest; /* original dest for change_address */ + rtx orig_src; /* original source for making a reg note */ +{ + rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg); + rtx src_mem = change_address (orig_src, BLKmode, src_reg); + rtx align_rtx = GEN_INT (align); + rtx label; + rtx final_src; + rtx bytes_rtx; + int leftover; + + if (bytes < 2 * MAX_MOVE_BYTES) + abort (); + + leftover = bytes % MAX_MOVE_BYTES; + bytes -= leftover; + + label = gen_label_rtx (); + final_src = gen_reg_rtx (Pmode); + bytes_rtx = GEN_INT (bytes); + + if (bytes > 0x7fff) + { + if (Pmode == DImode) + { + emit_insn (gen_movdi (final_src, bytes_rtx)); + emit_insn (gen_adddi3 (final_src, final_src, src_reg)); + } + else + { + emit_insn (gen_movsi (final_src, bytes_rtx)); + emit_insn (gen_addsi3 (final_src, final_src, src_reg)); + } + } + else + { + if (Pmode == DImode) + emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx)); + else + emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx)); + } + + emit_label (label); + + bytes_rtx = GEN_INT (MAX_MOVE_BYTES); + emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx)); + + if (Pmode == DImode) + { + emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx)); + emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx)); + emit_insn (gen_cmpdi (src_reg, final_src)); + } + else + { + emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx)); + emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx)); + emit_insn (gen_cmpsi (src_reg, final_src)); + } + + emit_jump_insn (gen_bne (label)); + + if (leftover) + emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover), + align_rtx)); +} + +/* Use a library function to move some bytes. */ + +static void +block_move_call (dest_reg, src_reg, bytes_rtx) + rtx dest_reg; + rtx src_reg; + rtx bytes_rtx; +{ + /* We want to pass the size as Pmode, which will normally be SImode + but will be DImode if we are using 64 bit longs and pointers. */ + if (GET_MODE (bytes_rtx) != VOIDmode + && GET_MODE (bytes_rtx) != Pmode) + bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1); + +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0, + VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode, + convert_to_mode (TYPE_MODE (sizetype), bytes_rtx, + TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#else + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0, + VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode, + convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx, + TREE_UNSIGNED (integer_type_node)), + TYPE_MODE (integer_type_node)); +#endif +} + +/* Expand string/block move operations. + + operands[0] is the pointer to the destination. + operands[1] is the pointer to the source. + operands[2] is the number of bytes to move. + operands[3] is the alignment. */ + +void +expand_block_move (operands) + rtx operands[]; +{ + rtx bytes_rtx = operands[2]; + rtx align_rtx = operands[3]; + int constp = GET_CODE (bytes_rtx) == CONST_INT; + HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0; + int align = INTVAL (align_rtx); + rtx orig_src = operands[1]; + rtx orig_dest = operands[0]; + rtx src_reg; + rtx dest_reg; + + if (constp && bytes <= 0) + return; + + if (align > UNITS_PER_WORD) + align = UNITS_PER_WORD; + + /* Move the address into scratch registers. */ + dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); + src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); + + if (TARGET_MEMCPY) + block_move_call (dest_reg, src_reg, bytes_rtx); + + else if (constp && bytes <= 2 * MAX_MOVE_BYTES + && align == UNITS_PER_WORD) + move_by_pieces (orig_dest, orig_src, bytes, align); + + else if (constp && bytes <= 2 * MAX_MOVE_BYTES) + emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode, + dest_reg), + change_address (orig_src, BLKmode, + src_reg), + bytes_rtx, align_rtx)); + + else if (constp && align >= UNITS_PER_WORD && optimize) + block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src); + + else if (constp && optimize) + { + /* If the alignment is not word aligned, generate a test at + runtime, to see whether things wound up aligned, and we + can use the faster lw/sw instead ulw/usw. */ + + rtx temp = gen_reg_rtx (Pmode); + rtx aligned_label = gen_label_rtx (); + rtx join_label = gen_label_rtx (); + int leftover = bytes % MAX_MOVE_BYTES; + + bytes -= leftover; + + if (Pmode == DImode) + { + emit_insn (gen_iordi3 (temp, src_reg, dest_reg)); + emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1))); + emit_insn (gen_cmpdi (temp, const0_rtx)); + } + else + { + emit_insn (gen_iorsi3 (temp, src_reg, dest_reg)); + emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1))); + emit_insn (gen_cmpsi (temp, const0_rtx)); + } + + emit_jump_insn (gen_beq (aligned_label)); + + /* Unaligned loop. */ + block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src); + emit_jump_insn (gen_jump (join_label)); + emit_barrier (); + + /* Aligned loop. */ + emit_label (aligned_label); + block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest, + orig_src); + emit_label (join_label); + + /* Bytes at the end of the loop. */ + if (leftover) + emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode, + dest_reg), + change_address (orig_src, BLKmode, + src_reg), + GEN_INT (leftover), + GEN_INT (align))); + } + + else + block_move_call (dest_reg, src_reg, bytes_rtx); +} + +/* Emit load/stores for a small constant block_move. + + operands[0] is the memory address of the destination. + operands[1] is the memory address of the source. + operands[2] is the number of bytes to move. + operands[3] is the alignment. + operands[4] is a temp register. + operands[5] is a temp register. + ... + operands[3+num_regs] is the last temp register. + + The block move type can be one of the following: + BLOCK_MOVE_NORMAL Do all of the block move. + BLOCK_MOVE_NOT_LAST Do all but the last store. + BLOCK_MOVE_LAST Do just the last store. */ + +const char * +output_block_move (insn, operands, num_regs, move_type) + rtx insn; + rtx operands[]; + int num_regs; + enum block_move_type move_type; +{ + rtx dest_reg = XEXP (operands[0], 0); + rtx src_reg = XEXP (operands[1], 0); + HOST_WIDE_INT bytes = INTVAL (operands[2]); + int align = INTVAL (operands[3]); + int num = 0; + int offset = 0; + int use_lwl_lwr = 0; + int last_operand = num_regs + 4; + int safe_regs = 4; + int i; + rtx xoperands[10]; + + struct { + const char *load; /* load insn without nop */ + const char *load_nop; /* load insn with trailing nop */ + const char *store; /* store insn */ + const char *final; /* if last_store used: NULL or swr */ + const char *last_store; /* last store instruction */ + int offset; /* current offset */ + enum machine_mode mode; /* mode to use on (MEM) */ + } load_store[4]; + + /* ??? Detect a bug in GCC, where it can give us a register + the same as one of the addressing registers and reduce + the number of registers available. */ + for (i = 4; + i < last_operand + && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0])); + i++) + if (! reg_mentioned_p (operands[i], operands[0]) + && ! reg_mentioned_p (operands[i], operands[1])) + xoperands[safe_regs++] = operands[i]; + + if (safe_regs < last_operand) + { + xoperands[0] = operands[0]; + xoperands[1] = operands[1]; + xoperands[2] = operands[2]; + xoperands[3] = operands[3]; + return output_block_move (insn, xoperands, safe_regs - 4, move_type); + } + + /* If we are given global or static addresses, and we would be + emitting a few instructions, try to save time by using a + temporary register for the pointer. */ + /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in + an ldl/ldr instruction pair. We play it safe, and always move + constant addresses into registers when generating N32/N64 code, just + in case we might emit an unaligned load instruction. */ + if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL + || mips_abi == ABI_N32 || mips_abi == ABI_64)) + { + if (CONSTANT_P (src_reg)) + { + if (TARGET_STATS) + mips_count_memory_refs (operands[1], 1); + + src_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[1] = operands[1]; + xoperands[0] = src_reg; + if (Pmode == DImode) + output_asm_insn ("dla\t%0,%1", xoperands); + else + output_asm_insn ("la\t%0,%1", xoperands); + } + } + + if (CONSTANT_P (dest_reg)) + { + if (TARGET_STATS) + mips_count_memory_refs (operands[0], 1); + + dest_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[1] = operands[0]; + xoperands[0] = dest_reg; + if (Pmode == DImode) + output_asm_insn ("dla\t%0,%1", xoperands); + else + output_asm_insn ("la\t%0,%1", xoperands); + } + } + } + + /* ??? We really shouldn't get any LO_SUM addresses here, because they + are not offsettable, however, offsettable_address_p says they are + offsettable. I think this is a bug in offsettable_address_p. + For expediency, we fix this by just loading the address into a register + if we happen to get one. */ + + if (GET_CODE (src_reg) == LO_SUM) + { + src_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[2] = XEXP (XEXP (operands[1], 0), 1); + xoperands[1] = XEXP (XEXP (operands[1], 0), 0); + xoperands[0] = src_reg; + if (Pmode == DImode) + output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands); + else + output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands); + } + } + + if (GET_CODE (dest_reg) == LO_SUM) + { + dest_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[2] = XEXP (XEXP (operands[0], 0), 1); + xoperands[1] = XEXP (XEXP (operands[0], 0), 0); + xoperands[0] = dest_reg; + if (Pmode == DImode) + output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands); + else + output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands); + } + } + + if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0]))) + num_regs = sizeof (load_store) / sizeof (load_store[0]); + + else if (num_regs < 1) + abort_with_insn (insn, + "Cannot do block move, not enough scratch registers"); + + while (bytes > 0) + { + load_store[num].offset = offset; + + if (TARGET_64BIT && bytes >= 8 && align >= 8) + { + load_store[num].load = "ld\t%0,%1"; + load_store[num].load_nop = "ld\t%0,%1%#"; + load_store[num].store = "sd\t%0,%1"; + load_store[num].last_store = "sd\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = DImode; + offset += 8; + bytes -= 8; + } + + /* ??? Fails because of a MIPS assembler bug? */ + else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16) + { + if (BYTES_BIG_ENDIAN) + { + load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2"; + load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#"; + load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2"; + load_store[num].last_store = "sdr\t%0,%2"; + load_store[num].final = "sdl\t%0,%1"; + } + else + { + load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1"; + load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#"; + load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1"; + load_store[num].last_store = "sdr\t%0,%1"; + load_store[num].final = "sdl\t%0,%2"; + } + + load_store[num].mode = DImode; + offset += 8; + bytes -= 8; + use_lwl_lwr = 1; + } + + else if (bytes >= 4 && align >= 4) + { + load_store[num].load = "lw\t%0,%1"; + load_store[num].load_nop = "lw\t%0,%1%#"; + load_store[num].store = "sw\t%0,%1"; + load_store[num].last_store = "sw\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = SImode; + offset += 4; + bytes -= 4; + } + + else if (bytes >= 4 && ! TARGET_MIPS16) + { + if (BYTES_BIG_ENDIAN) + { + load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2"; + load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#"; + load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2"; + load_store[num].last_store = "swr\t%0,%2"; + load_store[num].final = "swl\t%0,%1"; + } + else + { + load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1"; + load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#"; + load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1"; + load_store[num].last_store = "swr\t%0,%1"; + load_store[num].final = "swl\t%0,%2"; + } + + load_store[num].mode = SImode; + offset += 4; + bytes -= 4; + use_lwl_lwr = 1; + } + + else if (bytes >= 2 && align >= 2) + { + load_store[num].load = "lh\t%0,%1"; + load_store[num].load_nop = "lh\t%0,%1%#"; + load_store[num].store = "sh\t%0,%1"; + load_store[num].last_store = "sh\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = HImode; + offset += 2; + bytes -= 2; + } + else + { + load_store[num].load = "lb\t%0,%1"; + load_store[num].load_nop = "lb\t%0,%1%#"; + load_store[num].store = "sb\t%0,%1"; + load_store[num].last_store = "sb\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = QImode; + offset++; + bytes--; + } + + if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) + { + dslots_load_total++; + dslots_load_filled++; + + if (CONSTANT_P (src_reg)) + mips_count_memory_refs (src_reg, 1); + + if (CONSTANT_P (dest_reg)) + mips_count_memory_refs (dest_reg, 1); + } + + /* Emit load/stores now if we have run out of registers or are + at the end of the move. */ + + if (++num == num_regs || bytes == 0) + { + /* If only load/store, we need a NOP after the load. */ + if (num == 1) + { + load_store[0].load = load_store[0].load_nop; + if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) + dslots_load_filled--; + } + + if (move_type != BLOCK_MOVE_LAST) + { + for (i = 0; i < num; i++) + { + int offset; + + if (!operands[i + 4]) + abort (); + + if (GET_MODE (operands[i + 4]) != load_store[i].mode) + operands[i + 4] = gen_rtx (REG, load_store[i].mode, + REGNO (operands[i + 4])); + + offset = load_store[i].offset; + xoperands[0] = operands[i + 4]; + xoperands[1] = gen_rtx (MEM, load_store[i].mode, + plus_constant (src_reg, offset)); + + if (use_lwl_lwr) + { + int extra_offset + = GET_MODE_SIZE (load_store[i].mode) - 1; + + xoperands[2] = gen_rtx (MEM, load_store[i].mode, + plus_constant (src_reg, + extra_offset + + offset)); + } + + output_asm_insn (load_store[i].load, xoperands); + } + } + + for (i = 0; i < num; i++) + { + int last_p = (i == num-1 && bytes == 0); + int offset = load_store[i].offset; + + xoperands[0] = operands[i + 4]; + xoperands[1] = gen_rtx (MEM, load_store[i].mode, + plus_constant (dest_reg, offset)); + + + if (use_lwl_lwr) + { + int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1; + xoperands[2] = gen_rtx (MEM, load_store[i].mode, + plus_constant (dest_reg, + extra_offset + + offset)); + } + + if (move_type == BLOCK_MOVE_NORMAL) + output_asm_insn (load_store[i].store, xoperands); + + else if (move_type == BLOCK_MOVE_NOT_LAST) + { + if (!last_p) + output_asm_insn (load_store[i].store, xoperands); + + else if (load_store[i].final != 0) + output_asm_insn (load_store[i].final, xoperands); + } + + else if (last_p) + output_asm_insn (load_store[i].last_store, xoperands); + } + + num = 0; /* reset load_store */ + use_lwl_lwr = 0; + } + } + + return ""; +} + +/* Argument support functions. */ + +/* Initialize CUMULATIVE_ARGS for a function. */ + +void +init_cumulative_args (cum, fntype, libname) + CUMULATIVE_ARGS *cum; /* argument info to initialize */ + tree fntype; /* tree ptr for function decl */ + rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */ +{ + static CUMULATIVE_ARGS zero_cum; + tree param, next_param; + + if (TARGET_DEBUG_E_MODE) + { + fprintf (stderr, + "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype); + + if (!fntype) + fputc ('\n', stderr); + + else + { + tree ret_type = TREE_TYPE (fntype); + fprintf (stderr, ", fntype code = %s, ret code = %s\n", + tree_code_name[(int)TREE_CODE (fntype)], + tree_code_name[(int)TREE_CODE (ret_type)]); + } + } + + *cum = zero_cum; + + /* Determine if this function has variable arguments. This is + indicated by the last argument being 'void_type_mode' if there + are no variable arguments. The standard MIPS calling sequence + passes all arguments in the general purpose registers in this case. */ + + for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0; + param != 0; param = next_param) + { + next_param = TREE_CHAIN (param); + if (next_param == 0 && TREE_VALUE (param) != void_type_node) + cum->gp_reg_found = 1; + } +} + +/* Advance the argument to the next argument position. */ + +void +function_arg_advance (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named; /* whether or not the argument was named */ +{ + if (TARGET_DEBUG_E_MODE) + { + fprintf (stderr, + "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ", + cum->gp_reg_found, cum->arg_number, cum->arg_words, + GET_MODE_NAME (mode)); + fprintf (stderr, HOST_PTR_PRINTF, type); + fprintf (stderr, ", %d )\n\n", named); + } + + cum->arg_number++; + switch (mode) + { + case VOIDmode: + break; + + default: + if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT + && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + abort (); + + cum->gp_reg_found = 1; + cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + break; + + case BLKmode: + cum->gp_reg_found = 1; + cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + break; + + case SFmode: + if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT) + cum->fp_arg_words++; + else + cum->arg_words++; + if (! cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 1 << ((cum->arg_number - 1) * 2); + break; + + case DFmode: + if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT) + cum->fp_arg_words += (TARGET_64BIT ? 1 : 2); + else + cum->arg_words += (TARGET_64BIT ? 1 : 2); + if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2) + cum->fp_code += 2 << ((cum->arg_number - 1) * 2); + break; + + case DImode: + cum->gp_reg_found = 1; + cum->arg_words += (TARGET_64BIT ? 1 : 2); + break; + + case QImode: + case HImode: + case SImode: + cum->gp_reg_found = 1; + cum->arg_words++; + break; + } +} + +/* Return an RTL expression containing the register for the given mode, + or 0 if the argument is to be passed on the stack. */ + +struct rtx_def * +function_arg (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named; /* != 0 for normal args, == 0 for ... args */ +{ + rtx ret; + int regbase = -1; + int bias = 0; + int *arg_words = &cum->arg_words; + int struct_p = (type != 0 + && (TREE_CODE (type) == RECORD_TYPE + || TREE_CODE (type) == UNION_TYPE + || TREE_CODE (type) == QUAL_UNION_TYPE)); + + if (TARGET_DEBUG_E_MODE) + { + fprintf (stderr, + "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ", + cum->gp_reg_found, cum->arg_number, cum->arg_words, + GET_MODE_NAME (mode)); + fprintf (stderr, HOST_PTR_PRINTF, type); + fprintf (stderr, ", %d ) = ", named); + } + + + cum->last_arg_fp = 0; + switch (mode) + { + case SFmode: + if (mips_abi == ABI_32 || mips_abi == ABI_O64) + { + if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT) + regbase = GP_ARG_FIRST; + else + { + regbase = FP_ARG_FIRST; + + /* If the first arg was a float in a floating point register, + then set bias to align this float arg properly. */ + if (cum->arg_words == 1) + bias = 1; + } + } + else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT) + { + if (! TARGET_64BIT) + cum->fp_arg_words += cum->fp_arg_words & 1; + cum->last_arg_fp = 1; + arg_words = &cum->fp_arg_words; + regbase = FP_ARG_FIRST; + } + else + regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST); + break; + + case DFmode: + if (! TARGET_64BIT) + { + if (mips_abi == ABI_EABI + && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT) + cum->fp_arg_words += cum->fp_arg_words & 1; + else + cum->arg_words += cum->arg_words & 1; + } + + if (mips_abi == ABI_32 || mips_abi == ABI_O64) + regbase = ((cum->gp_reg_found + || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT + || cum->arg_number >= 2) + ? GP_ARG_FIRST : FP_ARG_FIRST); + else if (mips_abi == ABI_EABI + && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT) + { + cum->last_arg_fp = 1; + arg_words = &cum->fp_arg_words; + regbase = FP_ARG_FIRST; + } + else + regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named + ? GP_ARG_FIRST : FP_ARG_FIRST); + break; + + default: + if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT + && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + abort (); + + /* Drops through. */ + case BLKmode: + if (type != (tree)0 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD + && ! TARGET_64BIT && mips_abi != ABI_EABI) + cum->arg_words += (cum->arg_words & 1); + regbase = GP_ARG_FIRST; + break; + + case VOIDmode: + case QImode: + case HImode: + case SImode: + regbase = GP_ARG_FIRST; + break; + + case DImode: + if (! TARGET_64BIT) + cum->arg_words += (cum->arg_words & 1); + regbase = GP_ARG_FIRST; + } + + if (*arg_words >= MAX_ARGS_IN_REGISTERS) + { + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "%s\n", struct_p ? ", [struct]" : ""); + + ret = 0; + } + else + { + if (regbase == -1) + abort (); + + if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32 + || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named) + ret = gen_rtx (REG, mode, regbase + *arg_words + bias); + else + { + /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the + structure contains a double in its entirety, then that 64 bit + chunk is passed in a floating point register. */ + tree field; + + /* First check to see if there is any such field. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + if (TREE_CODE (field) == FIELD_DECL + && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE + && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD + && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) + % BITS_PER_WORD == 0)) + break; + + /* If the whole struct fits a DFmode register, + we don't need the PARALLEL. */ + if (! field || mode == DFmode) + ret = gen_rtx (REG, mode, regbase + *arg_words + bias); + else + { + /* Now handle the special case by returning a PARALLEL + indicating where each 64 bit chunk goes. */ + int chunks; + int bitpos; + int regno; + int i; + + /* ??? If this is a packed structure, then the last hunk won't + be 64 bits. */ + + chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD; + if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS) + chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias; + + /* assign_parms checks the mode of ENTRY_PARM, so we must + use the actual mode here. */ + ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks)); + + bitpos = 0; + regno = regbase + *arg_words + bias; + field = TYPE_FIELDS (type); + for (i = 0; i < chunks; i++) + { + rtx reg; + + for (; field; field = TREE_CHAIN (field)) + if (TREE_CODE (field) == FIELD_DECL + && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) + >= bitpos)) + break; + + if (field + && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos + && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE + && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) + reg = gen_rtx (REG, DFmode, + regno + FP_ARG_FIRST - GP_ARG_FIRST); + else + reg = gen_rtx (REG, word_mode, regno); + + XVECEXP (ret, 0, i) + = gen_rtx (EXPR_LIST, VOIDmode, reg, + GEN_INT (bitpos / BITS_PER_UNIT)); + + bitpos += 64; + regno++; + } + } + } + + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias], + struct_p ? ", [struct]" : ""); + + /* The following is a hack in order to pass 1 byte structures + the same way that the MIPS compiler does (namely by passing + the structure in the high byte or half word of the register). + This also makes varargs work. If we have such a structure, + we save the adjustment RTL, and the call define expands will + emit them. For the VOIDmode argument (argument after the + last real argument), pass back a parallel vector holding each + of the adjustments. */ + + /* ??? function_arg can be called more than once for each argument. + As a result, we compute more adjustments than we need here. + See the CUMULATIVE_ARGS definition in mips.h. */ + + /* ??? This scheme requires everything smaller than the word size to + shifted to the left, but when TARGET_64BIT and ! TARGET_INT64, + that would mean every int needs to be shifted left, which is very + inefficient. Let's not carry this compatibility to the 64 bit + calling convention for now. */ + + if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD + && ! TARGET_64BIT && mips_abi != ABI_EABI) + { + rtx amount = GEN_INT (BITS_PER_WORD + - int_size_in_bytes (type) * BITS_PER_UNIT); + rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias); + + if (TARGET_64BIT) + cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount); + else + cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount); + } + } + + /* We will be called with a mode of VOIDmode after the last argument + has been seen. Whatever we return will be passed to the call + insn. If we need any shifts for small structures, return them in + a PARALLEL; in that case, stuff the mips16 fp_code in as the + mode. Otherwise, if we have need a mips16 fp_code, return a REG + with the code stored as the mode. */ + if (mode == VOIDmode) + { + if (cum->num_adjusts > 0) + ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code, + gen_rtvec_v (cum->num_adjusts, cum->adjust)); + else if (TARGET_MIPS16 && cum->fp_code != 0) + ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0); + } + + return ret; +} + +int +function_arg_partial_nregs (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */ +{ + if ((mode == BLKmode + || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT + || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + && cum->arg_words < MAX_ARGS_IN_REGISTERS + && mips_abi != ABI_EABI) + { + int words; + if (mode == BLKmode) + words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + else + words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + + if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS) + return 0; /* structure fits in registers */ + + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "function_arg_partial_nregs = %d\n", + MAX_ARGS_IN_REGISTERS - cum->arg_words); + + return MAX_ARGS_IN_REGISTERS - cum->arg_words; + } + + else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1 + && ! TARGET_64BIT && mips_abi != ABI_EABI) + { + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "function_arg_partial_nregs = 1\n"); + + return 1; + } + + return 0; +} + +/* Abort after printing out a specific insn. */ + +static void +abort_with_insn (insn, reason) + rtx insn; + const char *reason; +{ + error (reason); + debug_rtx (insn); + abort (); +} + +/* Write a message to stderr (for use in macros expanded in files that do not + include stdio.h). */ + +void +trace (s, s1, s2) + char *s, *s1, *s2; +{ + fprintf (stderr, s, s1, s2); +} + +/* Set up the threshold for data to go into the small data area, instead + of the normal data area, and detect any conflicts in the switches. */ + +void +override_options () +{ + register int i, start; + register int regno; + register enum machine_mode mode; + + mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE; + + if (mips_section_threshold <= 0) + target_flags &= ~MASK_GPOPT; + else if (optimize) + target_flags |= MASK_GPOPT; + +#ifndef MIPS_ISA_DEFAULT +#define MIPS_ISA_DEFAULT 1 +#endif + + /* If both single-float and soft-float are set, then clear the one that + was set by TARGET_DEFAULT, leaving the one that was set by the + user. We assume here that the specs prevent both being set by the + user. */ +#ifdef TARGET_DEFAULT + if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT) + target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT)); +#endif + + /* Get the architectural level. */ + if (mips_isa_string == 0) + mips_isa = MIPS_ISA_DEFAULT; + + else if (ISDIGIT (*mips_isa_string)) + { + mips_isa = atoi (mips_isa_string); + if (mips_isa == 16) + { + /* -mno-mips16 overrides -mips16. */ + if (mips_no_mips16_string == NULL) + { + target_flags |= MASK_MIPS16; + if (TARGET_64BIT) + mips_isa = 3; + else + mips_isa = MIPS_ISA_DEFAULT; + } + else + { + mips_isa = MIPS_ISA_DEFAULT; + } + } + else if (mips_isa < 1 || mips_isa > 4) + { + error ("-mips%d not supported", mips_isa); + mips_isa = 1; + } + } + + else + { + error ("bad value (%s) for -mips switch", mips_isa_string); + mips_isa = 1; + } + +#ifdef MIPS_ABI_DEFAULT + /* Get the ABI to use. */ + if (mips_abi_string == (char *) 0) + mips_abi = MIPS_ABI_DEFAULT; + else if (! strcmp (mips_abi_string, "32")) + mips_abi = ABI_32; + else if (! strcmp (mips_abi_string, "o64")) + mips_abi = ABI_O64; + else if (! strcmp (mips_abi_string, "n32")) + mips_abi = ABI_N32; + else if (! strcmp (mips_abi_string, "64")) + mips_abi = ABI_64; + else if (! strcmp (mips_abi_string, "eabi")) + mips_abi = ABI_EABI; + else + error ("bad value (%s) for -mabi= switch", mips_abi_string); + + /* A specified ISA defaults the ABI if it was not specified. */ + if (mips_abi_string == 0 && mips_isa_string + && mips_abi != ABI_EABI && mips_abi != ABI_O64) + { + if (mips_isa <= 2) + mips_abi = ABI_32; + else + mips_abi = ABI_64; + } + + /* A specified ABI defaults the ISA if it was not specified. */ + else if (mips_isa_string == 0 && mips_abi_string + && mips_abi != ABI_EABI && mips_abi != ABI_O64) + { + if (mips_abi == ABI_32) + mips_isa = 1; + else if (mips_abi == ABI_N32) + mips_isa = 3; + else + mips_isa = 4; + } + + /* If both ABI and ISA were specified, check for conflicts. */ + else if (mips_isa_string && mips_abi_string) + { + if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64 + || mips_abi == ABI_O64)) + || (mips_isa >= 3 && mips_abi == ABI_32)) + error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa); + } + + /* Override TARGET_DEFAULT if necessary. */ + if (mips_abi == ABI_32) + target_flags &= ~ (MASK_FLOAT64|MASK_64BIT); + + /* If no type size setting options (-mlong64,-mint64,-mlong32) were used + then set the type sizes. In the EABI in 64 bit mode, longs and + pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */ + if (mips_explicit_type_size_string == NULL + && ((mips_abi == ABI_EABI && TARGET_64BIT) + || mips_abi == ABI_64)) + target_flags |= MASK_LONG64; + + /* ??? This doesn't work yet, so don't let people try to use it. */ + if (mips_abi == ABI_32) + error ("The -mabi=32 support does not work yet."); + +#else + if (mips_abi_string) + error ("This target does not support the -mabi switch."); +#endif + +#ifdef MIPS_CPU_STRING_DEFAULT + /* ??? There is a minor inconsistency here. If the user specifies an ISA + greater than that supported by the default processor, then the user gets + an error. Normally, the compiler will just default to the base level cpu + for the indicated isa. */ + if (mips_cpu_string == 0) + mips_cpu_string = MIPS_CPU_STRING_DEFAULT; +#endif + + /* Identify the processor type */ + if (mips_cpu_string == 0 + || !strcmp (mips_cpu_string, "default") + || !strcmp (mips_cpu_string, "DEFAULT")) + { + switch (mips_isa) + { + default: + mips_cpu_string = "3000"; + mips_cpu = PROCESSOR_R3000; + break; + case 2: + mips_cpu_string = "6000"; + mips_cpu = PROCESSOR_R6000; + break; + case 3: + mips_cpu_string = "4000"; + mips_cpu = PROCESSOR_R4000; + break; + case 4: + mips_cpu_string = "8000"; + mips_cpu = PROCESSOR_R8000; + break; + } + } + + else + { + const char *p = mips_cpu_string; + int seen_v = 0; + + /* We need to cope with the various "vr" prefixes for the NEC 4300 + and 4100 processors. */ + if (*p == 'v' || *p == 'V') + seen_v = 1, p++; + + if (*p == 'r' || *p == 'R') + p++; + + /* Since there is no difference between a R2000 and R3000 in + terms of the scheduler, we collapse them into just an R3000. */ + + mips_cpu = PROCESSOR_DEFAULT; + switch (*p) + { + case '2': + if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K")) + mips_cpu = PROCESSOR_R3000; + break; + + case '3': + if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K")) + mips_cpu = PROCESSOR_R3000; + else if (!strcmp (p, "3900")) + mips_cpu = PROCESSOR_R3900; + break; + + case '4': + if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K")) + mips_cpu = PROCESSOR_R4000; + /* The vr4100 is a non-FP ISA III processor with some extra + instructions. */ + else if (!strcmp (p, "4100")) + { + mips_cpu = PROCESSOR_R4100; + target_flags |= MASK_SOFT_FLOAT ; + } + /* The vr4300 is a standard ISA III processor, but with a different + pipeline. */ + else if (!strcmp (p, "4300")) + mips_cpu = PROCESSOR_R4300; + /* The r4400 is exactly the same as the r4000 from the compiler's + viewpoint. */ + else if (!strcmp (p, "4400")) + mips_cpu = PROCESSOR_R4000; + else if (!strcmp (p, "4600")) + mips_cpu = PROCESSOR_R4600; + else if (!strcmp (p, "4650")) + mips_cpu = PROCESSOR_R4650; + break; + + case '5': + if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K")) + mips_cpu = PROCESSOR_R5000; + break; + + case '6': + if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K")) + mips_cpu = PROCESSOR_R6000; + break; + + case '8': + if (!strcmp (p, "8000")) + mips_cpu = PROCESSOR_R8000; + break; + + case 'o': + if (!strcmp (p, "orion")) + mips_cpu = PROCESSOR_R4600; + break; + } + + if (seen_v + && mips_cpu != PROCESSOR_R4300 + && mips_cpu != PROCESSOR_R4100 + && mips_cpu != PROCESSOR_R5000) + mips_cpu = PROCESSOR_DEFAULT; + + if (mips_cpu == PROCESSOR_DEFAULT) + { + error ("bad value (%s) for -mcpu= switch", mips_cpu_string); + mips_cpu_string = "default"; + } + } + + if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1) + || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2) + || ((mips_cpu == PROCESSOR_R4000 + || mips_cpu == PROCESSOR_R4100 + || mips_cpu == PROCESSOR_R4300 + || mips_cpu == PROCESSOR_R4600 + || mips_cpu == PROCESSOR_R4650) + && mips_isa > 3)) + error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa); + + /* make sure sizes of ints/longs/etc. are ok */ + if (mips_isa < 3) + { + if (TARGET_FLOAT64) + fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers"); + + else if (TARGET_64BIT) + fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers"); + } + + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + flag_pcc_struct_return = 0; + + /* Tell halfpic.c that we have half-pic code if we do. */ + if (TARGET_HALF_PIC) + HALF_PIC_INIT (); + + /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need + to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */ + /* ??? -non_shared turns off pic code generation, but this is not + implemented. */ + if (TARGET_ABICALLS) + { + mips_abicalls = MIPS_ABICALLS_YES; + flag_pic = 1; + if (mips_section_threshold > 0) + warning ("-G is incompatible with PIC code which is the default"); + } + else + mips_abicalls = MIPS_ABICALLS_NO; + + /* -membedded-pic is a form of PIC code suitable for embedded + systems. All calls are made using PC relative addressing, and + all data is addressed using the $gp register. This requires gas, + which does most of the work, and GNU ld, which automatically + expands PC relative calls which are out of range into a longer + instruction sequence. All gcc really does differently is + generate a different sequence for a switch. */ + if (TARGET_EMBEDDED_PIC) + { + flag_pic = 1; + if (TARGET_ABICALLS) + warning ("-membedded-pic and -mabicalls are incompatible"); + + if (g_switch_set) + warning ("-G and -membedded-pic are incompatible"); + + /* Setting mips_section_threshold is not required, because gas + will force everything to be GP addressable anyhow, but + setting it will cause gcc to make better estimates of the + number of instructions required to access a particular data + item. */ + mips_section_threshold = 0x7fffffff; + } + + /* This optimization requires a linker that can support a R_MIPS_LO16 + relocation which is not immediately preceded by a R_MIPS_HI16 relocation. + GNU ld has this support, but not all other MIPS linkers do, so we enable + this optimization only if the user requests it, or if GNU ld is the + standard linker for this configuration. */ + /* ??? This does not work when target addresses are DImode. + This is because we are missing DImode high/lo_sum patterns. */ + if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic + && Pmode == SImode) + mips_split_addresses = 1; + else + mips_split_addresses = 0; + + /* -mrnames says to use the MIPS software convention for register + names instead of the hardware names (ie, $a0 instead of $4). + We do this by switching the names in mips_reg_names, which the + reg_names points into via the REGISTER_NAMES macro. */ + + if (TARGET_NAME_REGS) + bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, + sizeof (mips_reg_names)); + + /* When compiling for the mips16, we can not use floating point. We + record the original hard float value in mips16_hard_float. */ + if (TARGET_MIPS16) + { + if (TARGET_SOFT_FLOAT) + mips16_hard_float = 0; + else + mips16_hard_float = 1; + target_flags |= MASK_SOFT_FLOAT; + + /* Don't run the scheduler before reload, since it tends to + increase register pressure. */ + flag_schedule_insns = 0; + } + + /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only + to avoid using up another bit in target_flags. */ + if (mips_entry_string != NULL) + { + if (*mips_entry_string != '\0') + error ("Invalid option `entry%s'", mips_entry_string); + + if (! TARGET_MIPS16) + warning ("-mentry is only meaningful with -mips-16"); + else + mips_entry = 1; + } + + /* We copy TARGET_MIPS16 into the mips16 global variable, so that + attributes can access it. */ + if (TARGET_MIPS16) + mips16 = 1; + else + mips16 = 0; + + /* Initialize the high and low values for legitimate floating point + constants. Rather than trying to get the accuracy down to the + last bit, just use approximate ranges. */ + dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode); + dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode); + sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode); + sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode); + + mips_print_operand_punct['?'] = 1; + mips_print_operand_punct['#'] = 1; + mips_print_operand_punct['&'] = 1; + mips_print_operand_punct['!'] = 1; + mips_print_operand_punct['*'] = 1; + mips_print_operand_punct['@'] = 1; + mips_print_operand_punct['.'] = 1; + mips_print_operand_punct['('] = 1; + mips_print_operand_punct[')'] = 1; + mips_print_operand_punct['['] = 1; + mips_print_operand_punct[']'] = 1; + mips_print_operand_punct['<'] = 1; + mips_print_operand_punct['>'] = 1; + mips_print_operand_punct['{'] = 1; + mips_print_operand_punct['}'] = 1; + mips_print_operand_punct['^'] = 1; + mips_print_operand_punct['$'] = 1; + mips_print_operand_punct['+'] = 1; + + mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS; + mips_char_to_class['e'] = M16_NA_REGS; + mips_char_to_class['t'] = T_REG; + mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS); + mips_char_to_class['h'] = HI_REG; + mips_char_to_class['l'] = LO_REG; + mips_char_to_class['a'] = HILO_REG; + mips_char_to_class['x'] = MD_REGS; + mips_char_to_class['b'] = ALL_REGS; + mips_char_to_class['y'] = GR_REGS; + mips_char_to_class['z'] = ST_REGS; + + /* Set up array to map GCC register number to debug register number. + Ignore the special purpose register numbers. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + mips_dbx_regno[i] = -1; + + start = GP_DBX_FIRST - GP_REG_FIRST; + for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) + mips_dbx_regno[i] = i + start; + + start = FP_DBX_FIRST - FP_REG_FIRST; + for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) + mips_dbx_regno[i] = i + start; + + /* Set up array giving whether a given register can hold a given mode. + At present, restrict ints from being in FP registers, because reload + is a little enthusiastic about storing extra values in FP registers, + and this is not good for things like OS kernels. Also, due to the + mandatory delay, it is as fast to load from cached memory as to move + from the FP register. */ + + for (mode = VOIDmode; + mode != MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int)mode + 1)) + { + register int size = GET_MODE_SIZE (mode); + register enum mode_class class = GET_MODE_CLASS (mode); + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + { + register int temp; + + if (mode == CCmode) + { + if (mips_isa < 4) + temp = (regno == FPSW_REGNUM); + else + temp = (ST_REG_P (regno) || GP_REG_P (regno) + || FP_REG_P (regno)); + } + + else if (GP_REG_P (regno)) + temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD); + + else if (FP_REG_P (regno)) + temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)) + && (class == MODE_FLOAT + || class == MODE_COMPLEX_FLOAT + || (TARGET_DEBUG_H_MODE && class == MODE_INT)) + && (! TARGET_SINGLE_FLOAT || size <= 4)); + + else if (MD_REG_P (regno)) + temp = (class == MODE_INT + && (size <= UNITS_PER_WORD + || (regno == MD_REG_FIRST + && size == 2 * UNITS_PER_WORD))); + + else + temp = 0; + + mips_hard_regno_mode_ok[(int)mode][regno] = temp; + } + } + + /* Save GPR registers in word_mode sized hunks. word_mode hasn't been + initialized yet, so we can't use that here. */ + gpr_mode = TARGET_64BIT ? DImode : SImode; +} + +/* On the mips16, we want to allocate $24 (T_REG) before other + registers for instructions for which it is possible. This helps + avoid shuffling registers around in order to set up for an xor, + encouraging the compiler to use a cmp instead. */ + +void +mips_order_regs_for_local_alloc () +{ + register int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_alloc_order[i] = i; + + if (TARGET_MIPS16) + { + /* It really doesn't matter where we put register 0, since it is + a fixed register anyhow. */ + reg_alloc_order[0] = 24; + reg_alloc_order[24] = 0; + } +} + + +/* The MIPS debug format wants all automatic variables and arguments + to be in terms of the virtual frame pointer (stack pointer before + any adjustment in the function), while the MIPS 3.0 linker wants + the frame pointer to be the stack pointer after the initial + adjustment. So, we do the adjustment here. The arg pointer (which + is eliminated) points to the virtual frame pointer, while the frame + pointer (which may be eliminated) points to the stack pointer after + the initial adjustments. */ + +HOST_WIDE_INT +mips_debugger_offset (addr, offset) + rtx addr; + HOST_WIDE_INT offset; +{ + rtx offset2 = const0_rtx; + rtx reg = eliminate_constant_term (addr, &offset2); + + if (offset == 0) + offset = INTVAL (offset2); + + if (reg == stack_pointer_rtx || reg == frame_pointer_rtx + || reg == hard_frame_pointer_rtx) + { + HOST_WIDE_INT frame_size = (!current_frame_info.initialized) + ? compute_frame_size (get_frame_size ()) + : current_frame_info.total_size; + + /* MIPS16 frame is smaller */ + if (frame_pointer_needed && TARGET_MIPS16) + frame_size -= current_function_outgoing_args_size; + + offset = offset - frame_size; + } + + /* sdbout_parms does not want this to crash for unrecognized cases. */ +#if 0 + else if (reg != arg_pointer_rtx) + abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer."); +#endif + + return offset; +} + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand X. X is an RTL + expression. + + CODE is a value that can be used to specify one of several ways + of printing the operand. It is used when identical operands + must be printed differently depending on the context. CODE + comes from the `%' specification that was used to request + printing of the operand. If the specification was just `%DIGIT' + then CODE is 0; if the specification was `%LTR DIGIT' then CODE + is the ASCII code for LTR. + + If X is a register, this macro should print the register's name. + The names can be found in an array `reg_names' whose type is + `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. + + When the machine description has a specification `%PUNCT' (a `%' + followed by a punctuation character), this macro is called with + a null pointer for X and the punctuation character for CODE. + + The MIPS specific codes are: + + 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x", + 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x", + 'd' output integer constant in decimal, + 'z' if the operand is 0, use $0 instead of normal operand. + 'D' print second register of double-word register operand. + 'L' print low-order register of double-word register operand. + 'M' print high-order register of double-word register operand. + 'C' print part of opcode for a branch condition. + 'N' print part of opcode for a branch condition, inverted. + 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch). + 'B' print 'z' for EQ, 'n' for NE + 'b' print 'n' for EQ, 'z' for NE + 'T' print 'f' for EQ, 't' for NE + 't' print 't' for EQ, 'f' for NE + 'Z' print register and a comma, but print nothing for $fcc0 + '(' Turn on .set noreorder + ')' Turn on .set reorder + '[' Turn on .set noat + ']' Turn on .set at + '<' Turn on .set nomacro + '>' Turn on .set macro + '{' Turn on .set volatile (not GAS) + '}' Turn on .set novolatile (not GAS) + '&' Turn on .set noreorder if filling delay slots + '*' Turn on both .set noreorder and .set nomacro if filling delay slots + '!' Turn on .set nomacro if filling delay slots + '#' Print nop if in a .set noreorder section. + '?' Print 'l' if we are to use a branch likely instead of normal branch. + '@' Print the name of the assembler temporary register (at or $1). + '.' Print the name of the register with a hard-wired zero (zero or $0). + '^' Print the name of the pic call-through register (t9 or $25). + '$' Print the name of the stack pointer register (sp or $29). + '+' Print the name of the gp register (gp or $28). */ + +void +print_operand (file, op, letter) + FILE *file; /* file to write to */ + rtx op; /* operand to print */ + int letter; /* % or 0 */ +{ + register enum rtx_code code; + + if (PRINT_OPERAND_PUNCT_VALID_P (letter)) + { + switch (letter) + { + case '?': + if (mips_branch_likely) + putc ('l', file); + break; + + case '@': + fputs (reg_names [GP_REG_FIRST + 1], file); + break; + + case '^': + fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file); + break; + + case '.': + fputs (reg_names [GP_REG_FIRST + 0], file); + break; + + case '$': + fputs (reg_names[STACK_POINTER_REGNUM], file); + break; + + case '+': + fputs (reg_names[GP_REG_FIRST + 28], file); + break; + + case '&': + if (final_sequence != 0 && set_noreorder++ == 0) + fputs (".set\tnoreorder\n\t", file); + break; + + case '*': + if (final_sequence != 0) + { + if (set_noreorder++ == 0) + fputs (".set\tnoreorder\n\t", file); + + if (set_nomacro++ == 0) + fputs (".set\tnomacro\n\t", file); + } + break; + + case '!': + if (final_sequence != 0 && set_nomacro++ == 0) + fputs ("\n\t.set\tnomacro", file); + break; + + case '#': + if (set_noreorder != 0) + fputs ("\n\tnop", file); + else if (TARGET_STATS) + fputs ("\n\t#nop", file); + + break; + + case '(': + if (set_noreorder++ == 0) + fputs (".set\tnoreorder\n\t", file); + break; + + case ')': + if (set_noreorder == 0) + error ("internal error: %%) found without a %%( in assembler pattern"); + + else if (--set_noreorder == 0) + fputs ("\n\t.set\treorder", file); + + break; + + case '[': + if (set_noat++ == 0) + fputs (".set\tnoat\n\t", file); + break; + + case ']': + if (set_noat == 0) + error ("internal error: %%] found without a %%[ in assembler pattern"); + else if (--set_noat == 0) + fputs ("\n\t.set\tat", file); + + break; + + case '<': + if (set_nomacro++ == 0) + fputs (".set\tnomacro\n\t", file); + break; + + case '>': + if (set_nomacro == 0) + error ("internal error: %%> found without a %%< in assembler pattern"); + else if (--set_nomacro == 0) + fputs ("\n\t.set\tmacro", file); + + break; + + case '{': + if (set_volatile++ == 0) + fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#"); + break; + + case '}': + if (set_volatile == 0) + error ("internal error: %%} found without a %%{ in assembler pattern"); + else if (--set_volatile == 0) + fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#"); + + break; + + default: + error ("PRINT_OPERAND: Unknown punctuation '%c'", letter); + break; + } + + return; + } + + if (! op) + { + error ("PRINT_OPERAND null pointer"); + return; + } + + code = GET_CODE (op); + + if (code == SIGN_EXTEND) + op = XEXP (op, 0), code = GET_CODE (op); + + if (letter == 'C') + switch (code) + { + case EQ: fputs ("eq", file); break; + case NE: fputs ("ne", file); break; + case GT: fputs ("gt", file); break; + case GE: fputs ("ge", file); break; + case LT: fputs ("lt", file); break; + case LE: fputs ("le", file); break; + case GTU: fputs ("gtu", file); break; + case GEU: fputs ("geu", file); break; + case LTU: fputs ("ltu", file); break; + case LEU: fputs ("leu", file); break; + default: + abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C"); + } + + else if (letter == 'N') + switch (code) + { + case EQ: fputs ("ne", file); break; + case NE: fputs ("eq", file); break; + case GT: fputs ("le", file); break; + case GE: fputs ("lt", file); break; + case LT: fputs ("ge", file); break; + case LE: fputs ("gt", file); break; + case GTU: fputs ("leu", file); break; + case GEU: fputs ("ltu", file); break; + case LTU: fputs ("geu", file); break; + case LEU: fputs ("gtu", file); break; + default: + abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N"); + } + + else if (letter == 'S') + { + char buffer[100]; + + ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op)); + assemble_name (file, buffer); + } + + else if (letter == 'Z') + { + register int regnum; + + if (code != REG) + abort (); + + regnum = REGNO (op); + if (! ST_REG_P (regnum)) + abort (); + + if (regnum != ST_REG_FIRST) + fprintf (file, "%s,", reg_names[regnum]); + } + + else if (code == REG || code == SUBREG) + { + register int regnum; + + if (code == REG) + regnum = REGNO (op); + else + regnum = true_regnum (op); + + if ((letter == 'M' && ! WORDS_BIG_ENDIAN) + || (letter == 'L' && WORDS_BIG_ENDIAN) + || letter == 'D') + regnum++; + + fprintf (file, "%s", reg_names[regnum]); + } + + else if (code == MEM) + output_address (XEXP (op, 0)); + + else if (code == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT) + { + REAL_VALUE_TYPE d; + char s[30]; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + REAL_VALUE_TO_DECIMAL (d, "%.20e", s); + fprintf (file, s); + } + + else if (letter == 'x' && GET_CODE (op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op)); + + else if (letter == 'X' && GET_CODE(op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); + + else if (letter == 'd' && GET_CODE(op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op))); + + else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0) + fputs (reg_names[GP_REG_FIRST], file); + + else if (letter == 'd' || letter == 'x' || letter == 'X') + fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", + letter); + + else if (letter == 'B') + fputs (code == EQ ? "z" : "n", file); + else if (letter == 'b') + fputs (code == EQ ? "n" : "z", file); + else if (letter == 'T') + fputs (code == EQ ? "f" : "t", file); + else if (letter == 't') + fputs (code == EQ ? "t" : "f", file); + + else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG) + { + /* This case arises on the mips16; see mips16_gp_pseudo_reg. */ + print_operand (file, XEXP (op, 0), letter); + } + + else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op)) + { + fputs ("%gprel(", file); + mips16_output_gp_offset (file, op); + fputs (")", file); + } + + else + output_addr_const (file, op); +} + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand that is a memory + reference whose address is ADDR. ADDR is an RTL expression. + + On some machines, the syntax for a symbolic address depends on + the section that the address refers to. On these machines, + define the macro `ENCODE_SECTION_INFO' to store the information + into the `symbol_ref', and then check for it here. */ + +void +print_operand_address (file, addr) + FILE *file; + rtx addr; +{ + if (!addr) + error ("PRINT_OPERAND_ADDRESS, null pointer"); + + else + switch (GET_CODE (addr)) + { + case REG: + if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM) + abort_with_insn (addr, "Arg pointer not eliminated."); + + fprintf (file, "0(%s)", reg_names [REGNO (addr)]); + break; + + case LO_SUM: + { + register rtx arg0 = XEXP (addr, 0); + register rtx arg1 = XEXP (addr, 1); + + if (! mips_split_addresses) + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM."); + + if (GET_CODE (arg0) != REG) + abort_with_insn (addr, + "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."); + + fprintf (file, "%%lo("); + print_operand_address (file, arg1); + fprintf (file, ")(%s)", reg_names [REGNO (arg0)]); + } + break; + + case PLUS: + { + register rtx reg = 0; + register rtx offset = 0; + register rtx arg0 = XEXP (addr, 0); + register rtx arg1 = XEXP (addr, 1); + + if (GET_CODE (arg0) == REG) + { + reg = arg0; + offset = arg1; + if (GET_CODE (offset) == REG) + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs"); + } + + else if (GET_CODE (arg1) == REG) + reg = arg1, offset = arg0; + else if (CONSTANT_P (arg0) && CONSTANT_P (arg1)) + { + output_addr_const (file, addr); + break; + } + else + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs"); + + if (! CONSTANT_P (offset)) + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2"); + + if (REGNO (reg) == ARG_POINTER_REGNUM) + abort_with_insn (addr, "Arg pointer not eliminated."); + + if (TARGET_MIPS16 + && GET_CODE (offset) == CONST + && mips16_gp_offset_p (offset)) + { + fputs ("%gprel(", file); + mips16_output_gp_offset (file, offset); + fputs (")", file); + } + else + output_addr_const (file, offset); + fprintf (file, "(%s)", reg_names [REGNO (reg)]); + } + break; + + case LABEL_REF: + case SYMBOL_REF: + case CONST_INT: + case CONST: + output_addr_const (file, addr); + break; + + default: + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1"); + break; + } +} + + +/* If optimizing for the global pointer, keep track of all of the externs, so + that at the end of the file, we can emit the appropriate .extern + declaration for them, before writing out the text section. We assume all + names passed to us are in the permanent obstack, so they will be valid at + the end of the compilation. + + If we have -G 0, or the extern size is unknown, or the object is in a user + specified section that is not .sbss/.sdata, don't bother emitting the + .externs. In the case of user specified sections this behaviour is + required as otherwise GAS will think the object lives in .sbss/.sdata. */ + +int +mips_output_external (file, decl, name) + FILE *file ATTRIBUTE_UNUSED; + tree decl; + char *name; +{ + register struct extern_list *p; + int len; + tree section_name; + + if (TARGET_GP_OPT + && TREE_CODE (decl) != FUNCTION_DECL + && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0 + && ((section_name = DECL_SECTION_NAME (decl)) == NULL + || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0 + || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0)) + { + p = (struct extern_list *) permalloc (sizeof (struct extern_list)); + p->next = extern_head; + p->name = name; + p->size = len; + extern_head = p; + } + +#ifdef ASM_OUTPUT_UNDEF_FUNCTION + if (TREE_CODE (decl) == FUNCTION_DECL + /* ??? Don't include alloca, since gcc will always expand it + inline. If we don't do this, the C++ library fails to build. */ + && strcmp (name, "alloca") + /* ??? Don't include __builtin_next_arg, because then gcc will not + bootstrap under Irix 5.1. */ + && strcmp (name, "__builtin_next_arg")) + { + p = (struct extern_list *) permalloc (sizeof (struct extern_list)); + p->next = extern_head; + p->name = name; + p->size = -1; + extern_head = p; + } +#endif + + return 0; +} + +#ifdef ASM_OUTPUT_UNDEF_FUNCTION +int +mips_output_external_libcall (file, name) + FILE *file; + char *name; +{ + register struct extern_list *p; + + p = (struct extern_list *) permalloc (sizeof (struct extern_list)); + p->next = extern_head; + p->name = name; + p->size = -1; + extern_head = p; + + return 0; +} +#endif + +/* Compute a string to use as a temporary file name. */ + +/* On MSDOS, write temp files in current dir + because there's no place else we can expect to use. */ +#if __MSDOS__ +#ifndef P_tmpdir +#define P_tmpdir "./" +#endif +#endif + +static FILE * +make_temp_file () +{ + FILE *stream; + const char *base = getenv ("TMPDIR"); + int len; + + if (base == 0) + { +#ifdef P_tmpdir + if (access (P_tmpdir, R_OK | W_OK) == 0) + base = P_tmpdir; + else +#endif + if (access ("/usr/tmp", R_OK | W_OK) == 0) + base = "/usr/tmp/"; + else + base = "/tmp/"; + } + + len = strlen (base); + /* temp_filename is global, so we must use malloc, not alloca. */ + temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX")); + strcpy (temp_filename, base); + if (len > 0 && temp_filename[len-1] != '/') + temp_filename[len++] = '/'; + + strcpy (temp_filename + len, "ctXXXXXX"); + mktemp (temp_filename); + + stream = fopen (temp_filename, "w+"); + if (!stream) + pfatal_with_name (temp_filename); + +#ifndef __MSDOS__ + /* In MSDOS, we cannot unlink the temporary file until we are finished using + it. Otherwise, we delete it now, so that it will be gone even if the + compiler happens to crash. */ + unlink (temp_filename); +#endif + return stream; +} + +/* Emit a new filename to a stream. If this is MIPS ECOFF, watch out + for .file's that start within a function. If we are smuggling stabs, try to + put out a MIPS ECOFF file and a stab. */ + +void +mips_output_filename (stream, name) + FILE *stream; + char *name; +{ + static int first_time = 1; + char ltext_label_name[100]; + + if (first_time) + { + first_time = 0; + SET_FILE_NUMBER (); + current_function_file = name; + ASM_OUTPUT_FILENAME (stream, num_source_filenames, name); + /* This tells mips-tfile that stabs will follow. */ + if (!TARGET_GAS && write_symbols == DBX_DEBUG) + fprintf (stream, "\t#@stabs\n"); + } + + else if (write_symbols == DBX_DEBUG) + { + ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); + fprintf (stream, "%s ", ASM_STABS_OP); + output_quoted_string (stream, name); + fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]); + } + + else if (name != current_function_file + && strcmp (name, current_function_file) != 0) + { + if (inside_function && !TARGET_GAS) + { + if (!file_in_function_warning) + { + file_in_function_warning = 1; + ignore_line_number = 1; + warning ("MIPS ECOFF format does not allow changing filenames within functions with #line"); + } + } + else + { + SET_FILE_NUMBER (); + current_function_file = name; + ASM_OUTPUT_FILENAME (stream, num_source_filenames, name); + } + } +} + +/* Emit a linenumber. For encapsulated stabs, we need to put out a stab + as well as a .loc, since it is possible that MIPS ECOFF might not be + able to represent the location for inlines that come from a different + file. */ + +void +mips_output_lineno (stream, line) + FILE *stream; + int line; +{ + if (write_symbols == DBX_DEBUG) + { + ++sym_lineno; + fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n", + LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line, + LOCAL_LABEL_PREFIX, sym_lineno); + } + + else + { + fprintf (stream, "\n\t%s.loc\t%d %d\n", + (ignore_line_number) ? "#" : "", + num_source_filenames, line); + + LABEL_AFTER_LOC (stream); + } +} + +/* If defined, a C statement to be executed just prior to the output of + assembler code for INSN, to modify the extracted operands so they will be + output differently. + + Here the argument OPVEC is the vector containing the operands extracted + from INSN, and NOPERANDS is the number of elements of the vector which + contain meaningful data for this insn. The contents of this vector are + what will be used to convert the insn template into assembler code, so you + can change the assembler output by changing the contents of the vector. + + We use it to check if the current insn needs a nop in front of it because + of load delays, and also to update the delay slot statistics. */ + +/* ??? There is no real need for this function, because it never actually + emits a NOP anymore. */ + +void +final_prescan_insn (insn, opvec, noperands) + rtx insn; + rtx opvec[] ATTRIBUTE_UNUSED; + int noperands ATTRIBUTE_UNUSED; +{ + if (dslots_number_nops > 0) + { + rtx pattern = PATTERN (insn); + int length = get_attr_length (insn); + + /* Do we need to emit a NOP? */ + if (length == 0 + || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern)) + || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern)) + || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern)) + || (mips_load_reg4 != 0 + && reg_mentioned_p (mips_load_reg4, pattern))) + fputs ("\t#nop\n", asm_out_file); + + else + dslots_load_filled++; + + while (--dslots_number_nops > 0) + fputs ("\t#nop\n", asm_out_file); + + mips_load_reg = 0; + mips_load_reg2 = 0; + mips_load_reg3 = 0; + mips_load_reg4 = 0; + } + + if (TARGET_STATS + && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)) + dslots_jump_total++; +} + +/* Output at beginning of assembler file. + + If we are optimizing to use the global pointer, create a temporary file to + hold all of the text stuff, and write it out to the end. This is needed + because the MIPS assembler is evidently one pass, and if it hasn't seen the + relevant .comm/.lcomm/.extern/.sdata declaration when the code is + processed, it generates a two instruction sequence. */ + +void +mips_asm_file_start (stream) + FILE *stream; +{ + ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename); + + /* Versions of the MIPS assembler before 2.20 generate errors if a branch + inside of a .set noreorder section jumps to a label outside of the .set + noreorder section. Revision 2.20 just set nobopt silently rather than + fixing the bug. */ + + if (TARGET_MIPS_AS && optimize && flag_delayed_branch) + fprintf (stream, "\t.set\tnobopt\n"); + + /* Generate the pseudo ops that System V.4 wants. */ +#ifndef ABICALLS_ASM_OP +#define ABICALLS_ASM_OP ".abicalls" +#endif + if (TARGET_ABICALLS) + /* ??? but do not want this (or want pic0) if -non-shared? */ + fprintf (stream, "\t%s\n", ABICALLS_ASM_OP); + + if (TARGET_MIPS16) + fprintf (stream, "\t.set\tmips16\n"); + + /* Start a section, so that the first .popsection directive is guaranteed + to have a previously defined section to pop back to. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI) + fprintf (stream, "\t.section\t.text\n"); + + /* This code exists so that we can put all externs before all symbol + references. This is necessary for the MIPS assembler's global pointer + optimizations to work. */ + if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16) + { + asm_out_data_file = stream; + asm_out_text_file = make_temp_file (); + } + + else + asm_out_data_file = asm_out_text_file = stream; + + if (flag_verbose_asm) + fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n", + ASM_COMMENT_START, + mips_section_threshold, mips_cpu_string, mips_isa); +} + +/* If we are optimizing the global pointer, emit the text section now and any + small externs which did not have .comm, etc that are needed. Also, give a + warning if the data area is more than 32K and -pic because 3 instructions + are needed to reference the data pointers. */ + +void +mips_asm_file_end (file) + FILE *file; +{ + char buffer[8192]; + tree name_tree; + struct extern_list *p; + int len; + + if (HALF_PIC_P ()) + { + HALF_PIC_FINISH (file); + } + + if (extern_head) + { + fputs ("\n", file); + + for (p = extern_head; p != 0; p = p->next) + { + name_tree = get_identifier (p->name); + + /* Positively ensure only one .extern for any given symbol. */ + if (! TREE_ASM_WRITTEN (name_tree)) + { + TREE_ASM_WRITTEN (name_tree) = 1; +#ifdef ASM_OUTPUT_UNDEF_FUNCTION + if (p->size == -1) + ASM_OUTPUT_UNDEF_FUNCTION (file, p->name); + else +#endif + { + fputs ("\t.extern\t", file); + assemble_name (file, p->name); + fprintf (file, ", %d\n", p->size); + } + } + } + } + + if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16) + { + fprintf (file, "\n\t.text\n"); + rewind (asm_out_text_file); + if (ferror (asm_out_text_file)) + fatal_io_error (temp_filename); + + while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0) + if ((int) fwrite (buffer, 1, len, file) != len) + pfatal_with_name (asm_file_name); + + if (len < 0) + pfatal_with_name (temp_filename); + + if (fclose (asm_out_text_file) != 0) + pfatal_with_name (temp_filename); + +#ifdef __MSDOS__ + unlink (temp_filename); +#endif + } +} + +/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol + is used, so that we don't emit an .extern for it in mips_asm_file_end. */ + +void +mips_declare_object (stream, name, init_string, final_string, size) + FILE *stream; + char *name; + char *init_string; + char *final_string; + int size; +{ + fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */ + assemble_name (stream, name); + fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */ + + if (TARGET_GP_OPT) + { + tree name_tree = get_identifier (name); + TREE_ASM_WRITTEN (name_tree) = 1; + } +} + +/* Output a double precision value to the assembler. If both the + host and target are IEEE, emit the values in hex. */ + +void +mips_output_double (stream, value) + FILE *stream; + REAL_VALUE_TYPE value; +{ +#ifdef REAL_VALUE_TO_TARGET_DOUBLE + long value_long[2]; + REAL_VALUE_TO_TARGET_DOUBLE (value, value_long); + + fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n", + value_long[0], value, value_long[1]); +#else + fprintf (stream, "\t.double\t%.20g\n", value); +#endif +} + +/* Output a single precision value to the assembler. If both the + host and target are IEEE, emit the values in hex. */ + +void +mips_output_float (stream, value) + FILE *stream; + REAL_VALUE_TYPE value; +{ +#ifdef REAL_VALUE_TO_TARGET_SINGLE + long value_long; + REAL_VALUE_TO_TARGET_SINGLE (value, value_long); + + fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value); +#else + fprintf (stream, "\t.float\t%.12g\n", value); +#endif +} + +/* Return the bytes needed to compute the frame pointer from the current + stack pointer. + + Mips stack frames look like: + + Before call After call + +-----------------------+ +-----------------------+ + high | | | | + mem. | | | | + | caller's temps. | | caller's temps. | + | | | | + +-----------------------+ +-----------------------+ + | | | | + | arguments on stack. | | arguments on stack. | + | | | | + +-----------------------+ +-----------------------+ + | 4 words to save | | 4 words to save | + | arguments passed | | arguments passed | + | in registers, even | | in registers, even | + SP->| if not passed. | VFP->| if not passed. | + +-----------------------+ +-----------------------+ + | | + | fp register save | + | | + +-----------------------+ + | | + | gp register save | + | | + +-----------------------+ + | | + | local variables | + | | + +-----------------------+ + | | + | alloca allocations | + | | + +-----------------------+ + | | + | GP save for V.4 abi | + | | + +-----------------------+ + | | + | arguments on stack | + | | + +-----------------------+ + | 4 words to save | + | arguments passed | + | in registers, even | + low SP->| if not passed. | + memory +-----------------------+ + +*/ + +HOST_WIDE_INT +compute_frame_size (size) + HOST_WIDE_INT size; /* # of var. bytes allocated */ +{ + int regno; + HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */ + HOST_WIDE_INT var_size; /* # bytes that variables take up */ + HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */ + HOST_WIDE_INT extra_size; /* # extra bytes */ + HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */ + HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */ + HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */ + long mask; /* mask of saved gp registers */ + long fmask; /* mask of saved fp registers */ + int fp_inc; /* 1 or 2 depending on the size of fp regs */ + long fp_bits; /* bitmask to use for each fp register */ + + gp_reg_size = 0; + fp_reg_size = 0; + mask = 0; + fmask = 0; + extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0)); + var_size = MIPS_STACK_ALIGN (size); + args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size); + + /* The MIPS 3.0 linker does not like functions that dynamically + allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it + looks like we are trying to create a second frame pointer to the + function, so allocate some stack space to make it happy. */ + + if (args_size == 0 && current_function_calls_alloca) + args_size = 4 * UNITS_PER_WORD; + + total_size = var_size + args_size + extra_size; + + /* Calculate space needed for gp registers. */ + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + { + /* $18 is a special case on the mips16. It may be used to call + a function which returns a floating point value, but it is + marked in call_used_regs. $31 is also a special case. When + not using -mentry, it will be used to copy a return value + into the floating point registers if the return value is + floating point. */ + if (MUST_SAVE_REGISTER (regno) + || (TARGET_MIPS16 + && regno == GP_REG_FIRST + 18 + && regs_ever_live[regno]) + || (TARGET_MIPS16 + && regno == GP_REG_FIRST + 31 + && mips16_hard_float + && ! mips_entry + && ! aggregate_value_p (DECL_RESULT (current_function_decl)) + && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl))) + == MODE_FLOAT) + && (! TARGET_SINGLE_FLOAT + || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl))) + <= 4)))) + { + gp_reg_size += GET_MODE_SIZE (gpr_mode); + mask |= 1L << (regno - GP_REG_FIRST); + + /* The entry and exit pseudo instructions can not save $17 + without also saving $16. */ + if (mips_entry + && regno == GP_REG_FIRST + 17 + && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16)) + { + gp_reg_size += UNITS_PER_WORD; + mask |= 1L << 16; + } + } + } + + /* Calculate space needed for fp registers. */ + if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) + { + fp_inc = 1; + fp_bits = 1; + } + else + { + fp_inc = 2; + fp_bits = 3; + } + + /* This loop must iterate over the same space as its companion in + save_restore_regs. */ + for (regno = (FP_REG_LAST - fp_inc + 1); + regno >= FP_REG_FIRST; + regno -= fp_inc) + { + if (regs_ever_live[regno] && !call_used_regs[regno]) + { + fp_reg_size += fp_inc * UNITS_PER_FPREG; + fmask |= fp_bits << (regno - FP_REG_FIRST); + } + } + + gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); + total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size); + + /* The gp reg is caller saved in the 32 bit ABI, so there is no need + for leaf routines (total_size == extra_size) to save the gp reg. + The gp reg is callee saved in the 64 bit ABI, so all routines must + save the gp reg. This is not a leaf routine if -p, because of the + call to mcount. */ + if (total_size == extra_size + && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) + && ! profile_flag) + total_size = extra_size = 0; + else if (TARGET_ABICALLS) + { + /* Add the context-pointer to the saved registers. */ + gp_reg_size += UNITS_PER_WORD; + mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST); + total_size -= gp_reg_rounded; + gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); + total_size += gp_reg_rounded; + } + + /* Add in space reserved on the stack by the callee for storing arguments + passed in registers. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size); + + /* The entry pseudo instruction will allocate 32 bytes on the stack. */ + if (mips_entry && total_size > 0 && total_size < 32) + total_size = 32; + + /* Save other computed information. */ + current_frame_info.total_size = total_size; + current_frame_info.var_size = var_size; + current_frame_info.args_size = args_size; + current_frame_info.extra_size = extra_size; + current_frame_info.gp_reg_size = gp_reg_size; + current_frame_info.fp_reg_size = fp_reg_size; + current_frame_info.mask = mask; + current_frame_info.fmask = fmask; + current_frame_info.initialized = reload_completed; + current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD; + current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG); + + if (mask) + { + unsigned long offset; + + /* When using mips_entry, the registers are always saved at the + top of the stack. */ + if (! mips_entry) + offset = (args_size + extra_size + var_size + + gp_reg_size - GET_MODE_SIZE (gpr_mode)); + else + offset = total_size - GET_MODE_SIZE (gpr_mode); + + current_frame_info.gp_sp_offset = offset; + current_frame_info.gp_save_offset = offset - total_size; + } + else + { + current_frame_info.gp_sp_offset = 0; + current_frame_info.gp_save_offset = 0; + } + + if (fmask) + { + unsigned long offset = (args_size + extra_size + var_size + + gp_reg_rounded + fp_reg_size + - fp_inc * UNITS_PER_FPREG); + current_frame_info.fp_sp_offset = offset; + current_frame_info.fp_save_offset = offset - total_size; + } + else + { + current_frame_info.fp_sp_offset = 0; + current_frame_info.fp_save_offset = 0; + } + + /* Ok, we're done. */ + return total_size; +} + +/* Common code to emit the insns (or to write the instructions to a file) + to save/restore registers. + + Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg) + is not modified within save_restore_insns. */ + +#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0) + +static void +save_restore_insns (store_p, large_reg, large_offset, file) + int store_p; /* true if this is prologue */ + rtx large_reg; /* register holding large offset constant or NULL */ + long large_offset; /* large constant offset value */ + FILE *file; /* file to write instructions instead of making RTL */ +{ + long mask = current_frame_info.mask; + long fmask = current_frame_info.fmask; + int regno; + rtx base_reg_rtx; + HOST_WIDE_INT base_offset; + HOST_WIDE_INT gp_offset; + HOST_WIDE_INT fp_offset; + HOST_WIDE_INT end_offset; + rtx insn; + + if (frame_pointer_needed + && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST)) + abort (); + + if (mask == 0 && fmask == 0) + return; + + /* Save registers starting from high to low. The debuggers prefer at least + the return register be stored at func+4, and also it allows us not to + need a nop in the epilog if at least one register is reloaded in + addition to return address. */ + + /* Save GP registers if needed. */ + if (mask) + { + /* Pick which pointer to use as a base register. For small frames, just + use the stack pointer. Otherwise, use a temporary register. Save 2 + cycles if the save area is near the end of a large frame, by reusing + the constant created in the prologue/epilogue to adjust the stack + frame. */ + + gp_offset = current_frame_info.gp_sp_offset; + end_offset + = gp_offset - (current_frame_info.gp_reg_size + - GET_MODE_SIZE (gpr_mode)); + + if (gp_offset < 0 || end_offset < 0) + fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.", + (long) gp_offset, (long) end_offset); + + /* If we see a large frame in mips16 mode, we save the registers + before adjusting the stack pointer, and load them afterward. */ + else if (TARGET_MIPS16 && large_offset > 32767) + base_reg_rtx = stack_pointer_rtx, base_offset = large_offset; + + else if (gp_offset < 32768) + base_reg_rtx = stack_pointer_rtx, base_offset = 0; + + else if (large_reg != 0 + && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768 + && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768) + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = large_offset; + if (file == 0) + { + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + fprintf (file, "\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[REGNO (large_reg)], + reg_names[STACK_POINTER_REGNUM]); + } + + else + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = gp_offset; + if (file == 0) + { + rtx gp_offset_rtx = GEN_INT (gp_offset); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (gp_offset_rtx) + && GET_MODE (base_reg_rtx) == SImode) + { + insn = emit_move_insn (base_reg_rtx, + GEN_INT (gp_offset & 0xffff0000)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + insn + = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, + GEN_INT (gp_offset & 0x0000ffff))); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (base_reg_rtx, gp_offset_rtx); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + fprintf (file, "\tli\t%s,0x%.08lx\t# ", + reg_names[MIPS_TEMP2_REGNUM], (long) base_offset); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset); + fprintf (file, "\n\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[MIPS_TEMP2_REGNUM], + reg_names[STACK_POINTER_REGNUM]); + } + } + + /* When we restore the registers in MIPS16 mode, then if we are + using a frame pointer, and this is not a large frame, the + current stack pointer will be offset by + current_function_outgoing_args_size. Doing it this way lets + us avoid offsetting the frame pointer before copying it into + the stack pointer; there is no instruction to set the stack + pointer to the sum of a register and a constant. */ + if (TARGET_MIPS16 + && ! store_p + && frame_pointer_needed + && large_offset <= 32767) + base_offset += current_function_outgoing_args_size; + + for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) + if (BITSET_P (mask, regno - GP_REG_FIRST)) + { + if (file == 0) + { + rtx reg_rtx; + rtx mem_rtx + = gen_rtx (MEM, gpr_mode, + gen_rtx (PLUS, Pmode, base_reg_rtx, + GEN_INT (gp_offset - base_offset))); + + RTX_UNCHANGING_P (mem_rtx) = 1; + + /* The mips16 does not have an instruction to load + $31, so we load $7 instead, and work things out + in the caller. */ + if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31) + reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7); + /* The mips16 sometimes needs to save $18. */ + else if (TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + { + if (! store_p) + reg_rtx = gen_rtx (REG, gpr_mode, 6); + else + { + reg_rtx = gen_rtx (REG, gpr_mode, 3); + emit_move_insn (reg_rtx, + gen_rtx (REG, gpr_mode, regno)); + } + } + else + reg_rtx = gen_rtx (REG, gpr_mode, regno); + + if (store_p) + { + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + else if (!TARGET_ABICALLS + || (mips_abi != ABI_32 && mips_abi != ABI_O64) + || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) + { + emit_move_insn (reg_rtx, mem_rtx); + if (TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + emit_move_insn (gen_rtx (REG, gpr_mode, regno), + reg_rtx); + } + } + else + { + if (store_p || !TARGET_ABICALLS + || (mips_abi != ABI_32 && mips_abi != ABI_O64) + || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) + { + int r = regno; + + /* The mips16 does not have an instruction to + load $31, so we load $7 instead, and work + things out in the caller. */ + if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31) + r = GP_REG_FIRST + 7; + /* The mips16 sometimes needs to save $18. */ + if (TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + { + if (! store_p) + r = GP_REG_FIRST + 6; + else + { + r = GP_REG_FIRST + 3; + fprintf (file, "\tmove\t%s,%s\n", + reg_names[r], reg_names[regno]); + } + } + fprintf (file, "\t%s\t%s,", + (TARGET_64BIT + ? (store_p) ? "sd" : "ld" + : (store_p) ? "sw" : "lw"), + reg_names[r]); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, + gp_offset - base_offset); + fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]); + if (! store_p + && TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + fprintf (file, "\tmove\t%s,%s\n", + reg_names[regno], reg_names[r]); + } + + } + gp_offset -= GET_MODE_SIZE (gpr_mode); + } + } + else + base_reg_rtx = 0, base_offset = 0; + + /* Save floating point registers if needed. */ + if (fmask) + { + int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2; + int fp_size = fp_inc * UNITS_PER_FPREG; + + /* Pick which pointer to use as a base register. */ + fp_offset = current_frame_info.fp_sp_offset; + end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size); + + if (fp_offset < 0 || end_offset < 0) + fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.", + (long) fp_offset, (long) end_offset); + + else if (fp_offset < 32768) + base_reg_rtx = stack_pointer_rtx, base_offset = 0; + + else if (base_reg_rtx != 0 + && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768 + && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768) + ; /* already set up for gp registers above */ + + else if (large_reg != 0 + && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768 + && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768) + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = large_offset; + if (file == 0) + { + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + + else + fprintf (file, "\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[REGNO (large_reg)], + reg_names[STACK_POINTER_REGNUM]); + } + + else + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = fp_offset; + if (file == 0) + { + rtx fp_offset_rtx = GEN_INT (fp_offset); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (fp_offset_rtx) + && GET_MODE (base_reg_rtx) == SImode) + { + insn = emit_move_insn (base_reg_rtx, + GEN_INT (fp_offset & 0xffff0000)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, + GEN_INT (fp_offset & 0x0000ffff))); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (base_reg_rtx, fp_offset_rtx); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + fprintf (file, "\tli\t%s,0x%.08lx\t# ", + reg_names[MIPS_TEMP2_REGNUM], (long) base_offset); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset); + fprintf (file, "\n\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[MIPS_TEMP2_REGNUM], + reg_names[STACK_POINTER_REGNUM]); + } + } + + /* This loop must iterate over the same space as its companion in + compute_frame_size. */ + for (regno = (FP_REG_LAST - fp_inc + 1); + regno >= FP_REG_FIRST; + regno -= fp_inc) + if (BITSET_P (fmask, regno - FP_REG_FIRST)) + { + if (file == 0) + { + enum machine_mode sz + = TARGET_SINGLE_FLOAT ? SFmode : DFmode; + rtx reg_rtx = gen_rtx (REG, sz, regno); + rtx mem_rtx = gen_rtx (MEM, sz, + gen_rtx (PLUS, Pmode, base_reg_rtx, + GEN_INT (fp_offset + - base_offset))); + RTX_UNCHANGING_P (mem_rtx) = 1; + + if (store_p) + { + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + else + emit_move_insn (reg_rtx, mem_rtx); + } + else + { + fprintf (file, "\t%s\t%s,", + (TARGET_SINGLE_FLOAT + ? (store_p ? "s.s" : "l.s") + : (store_p ? "s.d" : "l.d")), + reg_names[regno]); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, + fp_offset - base_offset); + fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]); + } + + fp_offset -= fp_size; + } + } +} + +/* Set up the stack and frame (if desired) for the function. */ + +void +function_prologue (file, size) + FILE *file; + int size ATTRIBUTE_UNUSED; +{ +#ifndef FUNCTION_NAME_ALREADY_DECLARED + char *fnname; +#endif + long tsize = current_frame_info.total_size; + + ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl)); + +#ifdef SDB_DEBUGGING_INFO + if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG) + ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); +#endif + + /* In mips16 mode, we may need to generate a 32 bit to handle + floating point arguments. The linker will arrange for any 32 bit + functions to call this stub, which will then jump to the 16 bit + function proper. */ + if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT + && current_function_args_info.fp_code != 0) + build_mips16_function_stub (file); + + inside_function = 1; + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + /* Get the function name the same way that toplev.c does before calling + assemble_start_function. This is needed so that the name used here + exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + + if (!flag_inhibit_size_directive) + { + fputs ("\t.ent\t", file); + assemble_name (file, fnname); + fputs ("\n", file); + } + + assemble_name (file, fnname); + fputs (":\n", file); +#endif + + if (!flag_inhibit_size_directive) + { + /* .frame FRAMEREG, FRAMESIZE, RETREG */ + fprintf (file, + "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", + (reg_names[(frame_pointer_needed) + ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]), + ((frame_pointer_needed && TARGET_MIPS16) + ? (tsize - current_function_outgoing_args_size) + : tsize), + reg_names[31 + GP_REG_FIRST], + current_frame_info.var_size, + current_frame_info.num_gp, + current_frame_info.num_fp, + current_function_outgoing_args_size, + current_frame_info.extra_size); + + /* .mask MASK, GPOFFSET; .fmask FPOFFSET */ + fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n", + current_frame_info.mask, + current_frame_info.gp_save_offset, + current_frame_info.fmask, + current_frame_info.fp_save_offset); + + /* Require: + OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg. + HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */ + } + + if (mips_entry && ! mips_can_use_return_insn ()) + { + int save16 = BITSET_P (current_frame_info.mask, 16); + int save17 = BITSET_P (current_frame_info.mask, 17); + int save31 = BITSET_P (current_frame_info.mask, 31); + int savearg = 0; + rtx insn; + + /* Look through the initial insns to see if any of them store + the function parameters into the incoming parameter storage + area. If they do, we delete the insn, and save the register + using the entry pseudo-instruction instead. We don't try to + look past a label, jump, or call. */ + for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) + { + rtx note, set, src, dest, base, offset; + int hireg; + + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + break; + if (GET_CODE (insn) != INSN) + continue; + set = PATTERN (insn); + if (GET_CODE (set) != SET) + continue; + + /* An insn storing a function parameter will still have a + REG_EQUIV note on it mentioning the argument pointer. */ + note = find_reg_note (insn, REG_EQUIV, NULL_RTX); + if (note == NULL_RTX) + continue; + if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0))) + continue; + + src = SET_SRC (set); + if (GET_CODE (src) != REG + || REGNO (src) < GP_REG_FIRST + 4 + || REGNO (src) > GP_REG_FIRST + 7) + continue; + + dest = SET_DEST (set); + if (GET_CODE (dest) != MEM) + continue; + if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD) + ; + else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD + && REGNO (src) < GP_REG_FIRST + 7) + ; + else + continue; + offset = const0_rtx; + base = eliminate_constant_term (XEXP (dest, 0), &offset); + if (GET_CODE (base) != REG + || GET_CODE (offset) != CONST_INT) + continue; + if (REGNO (base) == STACK_POINTER_REGNUM + && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD) + ; + else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM + && (INTVAL (offset) + == (tsize + + (REGNO (src) - 4) * UNITS_PER_WORD + - current_function_outgoing_args_size))) + ; + else + continue; + + /* This insn stores a parameter onto the stack, in the same + location where the entry pseudo-instruction will put it. + Delete the insn, and arrange to tell the entry + instruction to save the register. */ + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + + hireg = (REGNO (src) + + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest)) + - 1); + if (hireg > savearg) + savearg = hireg; + } + + /* If this is a varargs function, we need to save all the + registers onto the stack anyhow. */ + if (current_function_stdarg || current_function_varargs) + savearg = GP_REG_FIRST + 7; + + fprintf (file, "\tentry\t"); + if (savearg > 0) + { + if (savearg == GP_REG_FIRST + 4) + fprintf (file, "%s", reg_names[savearg]); + else + fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4], + reg_names[savearg]); + } + if (save16 || save17) + { + if (savearg > 0) + fprintf (file, ","); + fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]); + if (save17) + fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]); + } + if (save31) + { + if (savearg > 0 || save16 || save17) + fprintf (file, ","); + fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]); + } + fprintf (file, "\n"); + } + + if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)) + { + char *sp_str = reg_names[STACK_POINTER_REGNUM]; + + fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n", + reg_names[PIC_FUNCTION_ADDR_REGNUM]); + if (tsize > 0) + { + fprintf (file, "\t%s\t%s,%s,%ld\n", + (Pmode == DImode ? "dsubu" : "subu"), + sp_str, sp_str, tsize); + fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size); + } + + if (dwarf2out_do_frame ()) + dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize); + } +} + +/* Expand the prologue into a bunch of separate insns. */ + +void +mips_expand_prologue () +{ + int regno; + HOST_WIDE_INT tsize; + rtx tmp_rtx = 0; + char *arg_name = 0; + tree fndecl = current_function_decl; + tree fntype = TREE_TYPE (fndecl); + tree fnargs = DECL_ARGUMENTS (fndecl); + rtx next_arg_reg; + int i; + tree next_arg; + tree cur_arg; + CUMULATIVE_ARGS args_so_far; + rtx reg_18_save = NULL_RTX; + + /* If struct value address is treated as the first argument, make it so. */ + if (aggregate_value_p (DECL_RESULT (fndecl)) + && ! current_function_returns_pcc_struct + && struct_value_incoming_rtx == 0) + { + tree type = build_pointer_type (fntype); + tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type); + + DECL_ARG_TYPE (function_result_decl) = type; + TREE_CHAIN (function_result_decl) = fnargs; + fnargs = function_result_decl; + } + + /* Determine the last argument, and get its name. */ + + INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0); + regno = GP_ARG_FIRST; + + for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg) + { + tree passed_type = DECL_ARG_TYPE (cur_arg); + enum machine_mode passed_mode = TYPE_MODE (passed_type); + rtx entry_parm; + + if (TREE_ADDRESSABLE (passed_type)) + { + passed_type = build_pointer_type (passed_type); + passed_mode = Pmode; + } + + entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1); + + if (entry_parm) + { + int words; + + /* passed in a register, so will get homed automatically */ + if (GET_MODE (entry_parm) == BLKmode) + words = (int_size_in_bytes (passed_type) + 3) / 4; + else + words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4; + + regno = REGNO (entry_parm) + words - 1; + } + else + { + regno = GP_ARG_LAST+1; + break; + } + + FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1); + + next_arg = TREE_CHAIN (cur_arg); + if (next_arg == 0) + { + if (DECL_NAME (cur_arg)) + arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg)); + + break; + } + } + + /* In order to pass small structures by value in registers compatibly with + the MIPS compiler, we need to shift the value into the high part of the + register. Function_arg has encoded a PARALLEL rtx, holding a vector of + adjustments to be made as the next_arg_reg variable, so we split up the + insns, and emit them separately. */ + + next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1); + if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL) + { + rtvec adjust = XVEC (next_arg_reg, 0); + int num = GET_NUM_ELEM (adjust); + + for (i = 0; i < num; i++) + { + rtx pattern = RTVEC_ELT (adjust, i); + if (GET_CODE (pattern) != SET + || GET_CODE (SET_SRC (pattern)) != ASHIFT) + abort_with_insn (pattern, "Insn is not a shift"); + + PUT_CODE (SET_SRC (pattern), ASHIFTRT); + emit_insn (pattern); + } + } + + tsize = compute_frame_size (get_frame_size ()); + + /* If this function is a varargs function, store any registers that + would normally hold arguments ($4 - $7) on the stack. */ + if ((mips_abi == ABI_32 || mips_abi == ABI_O64) + && (! mips_entry || mips_can_use_return_insn ()) + && ((TYPE_ARG_TYPES (fntype) != 0 + && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) + != void_type_node)) + || (arg_name != 0 + && ((arg_name[0] == '_' + && strcmp (arg_name, "__builtin_va_alist") == 0) + || (arg_name[0] == 'v' + && strcmp (arg_name, "va_alist") == 0))))) + { + int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD; + rtx ptr = stack_pointer_rtx; + + /* If we are doing svr4-abi, sp has already been decremented by tsize. */ + if (TARGET_ABICALLS) + offset += tsize; + + for (; regno <= GP_ARG_LAST; regno++) + { + if (offset != 0) + ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset)); + emit_move_insn (gen_rtx (MEM, gpr_mode, ptr), + gen_rtx (REG, gpr_mode, regno)); + + offset += GET_MODE_SIZE (gpr_mode); + } + } + + /* If we are using the entry pseudo instruction, it will + automatically subtract 32 from the stack pointer, so we don't + need to. The entry pseudo instruction is emitted by + function_prologue. */ + if (mips_entry && ! mips_can_use_return_insn ()) + { + if (tsize > 0 && tsize <= 32 && frame_pointer_needed) + { + rtx insn; + + /* If we are using a frame pointer with a small stack frame, + we need to initialize it here since it won't be done + below. */ + if (TARGET_MIPS16 && current_function_outgoing_args_size != 0) + { + rtx incr = GEN_INT (current_function_outgoing_args_size); + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + else + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + } + else if (Pmode == DImode) + insn = emit_insn (gen_movdi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + + RTX_FRAME_RELATED_P (insn) = 1; + } + + /* We may need to save $18, if it is used to call a function + which may return a floating point value. Set up a sequence + of instructions to do so. Later on we emit them at the right + moment. */ + if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18)) + { + rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3); + long gp_offset, base_offset; + + gp_offset = current_frame_info.gp_sp_offset; + if (BITSET_P (current_frame_info.mask, 16)) + gp_offset -= UNITS_PER_WORD; + if (BITSET_P (current_frame_info.mask, 17)) + gp_offset -= UNITS_PER_WORD; + if (BITSET_P (current_frame_info.mask, 31)) + gp_offset -= UNITS_PER_WORD; + if (tsize > 32767) + base_offset = tsize; + else + base_offset = 0; + start_sequence (); + emit_move_insn (reg_rtx, + gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18)); + emit_move_insn (gen_rtx (MEM, gpr_mode, + gen_rtx (PLUS, Pmode, stack_pointer_rtx, + GEN_INT (gp_offset + - base_offset))), + reg_rtx); + reg_18_save = gen_sequence (); + end_sequence (); + } + + if (tsize > 32) + tsize -= 32; + else + { + tsize = 0; + if (reg_18_save != NULL_RTX) + emit_insn (reg_18_save); + } + } + + if (tsize > 0) + { + rtx tsize_rtx = GEN_INT (tsize); + + /* If we are doing svr4-abi, sp move is done by + function_prologue. In mips16 mode with a large frame, we + save the registers before adjusting the stack. */ + if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64)) + && (!TARGET_MIPS16 || tsize <= 32767)) + { + rtx insn; + + if (tsize > 32767) + { + tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode) + { + insn = emit_move_insn (tmp_rtx, + GEN_INT (tsize & 0xffff0000)); + RTX_FRAME_RELATED_P (insn) = 1; + insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx, + GEN_INT (tsize & 0x0000ffff))); + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (tmp_rtx, tsize_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + + tsize_rtx = tmp_rtx; + } + + if (Pmode == DImode) + insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + else + insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (! mips_entry) + save_restore_insns (1, tmp_rtx, tsize, (FILE *)0); + else if (reg_18_save != NULL_RTX) + emit_insn (reg_18_save); + + if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64)) + && TARGET_MIPS16 + && tsize > 32767) + { + rtx reg_rtx; + + if (!frame_pointer_needed) + abort (); + + reg_rtx = gen_rtx (REG, Pmode, 3); + emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); + emit_move_insn (reg_rtx, tsize_rtx); + if (Pmode == DImode) + emit_insn (gen_subdi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + reg_rtx)); + else + emit_insn (gen_subsi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + reg_rtx)); + emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); + } + + if (frame_pointer_needed) + { + rtx insn = 0; + + /* On the mips16, we encourage the use of unextended + instructions when using the frame pointer by pointing the + frame pointer ahead of the argument space allocated on + the stack. */ + if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64)) + && TARGET_MIPS16 + && tsize > 32767) + { + /* In this case, we have already copied the stack + pointer into the frame pointer, above. We need only + adjust for the outgoing argument size. */ + if (current_function_outgoing_args_size != 0) + { + rtx incr = GEN_INT (current_function_outgoing_args_size); + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + incr)); + else + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + incr)); + } + } + else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0) + { + rtx incr = GEN_INT (current_function_outgoing_args_size); + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + else + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + } + else if (Pmode == DImode) + insn = emit_insn (gen_movdi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64)) + emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0), + gen_rtx (REG, DImode, 25))); + } + + /* If we are profiling, make sure no instructions are scheduled before + the call to mcount. */ + + if (profile_flag || profile_block_flag) + emit_insn (gen_blockage ()); +} + +/* Do any necessary cleanup after a function to restore stack, frame, + and regs. */ + +#define RA_MASK ((long) 0x80000000) /* 1 << 31 */ +#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) + +void +function_epilogue (file, size) + FILE *file ATTRIBUTE_UNUSED; + HOST_WIDE_INT size ATTRIBUTE_UNUSED; +{ + char *fnname; + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + /* Get the function name the same way that toplev.c does before calling + assemble_start_function. This is needed so that the name used here + exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + + if (!flag_inhibit_size_directive) + { + fputs ("\t.end\t", file); + assemble_name (file, fnname); + fputs ("\n", file); + } +#endif + + if (TARGET_STATS) + { + int num_gp_regs = current_frame_info.gp_reg_size / 4; + int num_fp_regs = current_frame_info.fp_reg_size / 8; + int num_regs = num_gp_regs + num_fp_regs; + char *name = fnname; + + if (name[0] == '*') + name++; + + dslots_load_total += num_regs; + + fprintf (stderr, + "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d", + name, frame_pointer_needed ? 'y' : 'n', + (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y', + current_function_calls_alloca ? 'y' : 'n', + current_function_calls_setjmp ? 'y' : 'n', + current_frame_info.total_size, + current_function_outgoing_args_size, num_gp_regs, num_fp_regs, + dslots_load_total, dslots_load_filled, + dslots_jump_total, dslots_jump_filled, + num_refs[0], num_refs[1], num_refs[2]); + + if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs) + { + fprintf (stderr, + " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs); + prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS; + } + + if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs) + { + fprintf (stderr, + " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs); + prev_half_pic_refs = HALF_PIC_NUMBER_REFS; + } + + fputc ('\n', stderr); + } + + /* Reset state info for each function. */ + inside_function = 0; + ignore_line_number = 0; + dslots_load_total = 0; + dslots_jump_total = 0; + dslots_load_filled = 0; + dslots_jump_filled = 0; + num_refs[0] = 0; + num_refs[1] = 0; + num_refs[2] = 0; + mips_load_reg = 0; + mips_load_reg2 = 0; + current_frame_info = zero_frame_info; + + while (string_constants != NULL) + { + struct string_constant *next; + + next = string_constants->next; + free (string_constants); + string_constants = next; + } + + /* Restore the output file if optimizing the GP (optimizing the GP causes + the text to be diverted to a tempfile, so that data decls come before + references to the data). */ + + if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS) + asm_out_file = asm_out_data_file; +} + +/* Expand the epilogue into a bunch of separate insns. */ + +void +mips_expand_epilogue () +{ + HOST_WIDE_INT tsize = current_frame_info.total_size; + rtx tsize_rtx = GEN_INT (tsize); + rtx tmp_rtx = (rtx)0; + + if (mips_can_use_return_insn ()) + { + emit_insn (gen_return ()); + return; + } + + if (mips_entry && ! mips_can_use_return_insn ()) + tsize -= 32; + + if (tsize > 32767 && ! TARGET_MIPS16) + { + tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM); + emit_move_insn (tmp_rtx, tsize_rtx); + tsize_rtx = tmp_rtx; + } + + if (tsize > 0) + { + long orig_tsize = tsize; + + if (frame_pointer_needed) + { + emit_insn (gen_blockage ()); + + /* On the mips16, the frame pointer is offset from the stack + pointer by current_function_outgoing_args_size. We + account for that by changing tsize. Note that this can + actually make tsize negative. */ + if (TARGET_MIPS16) + { + tsize -= current_function_outgoing_args_size; + + /* If we have a large frame, it's easier to add to $17 + than to $sp, since the mips16 has no instruction to + add a register to $sp. */ + if (orig_tsize > 32767) + { + rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6); + + emit_move_insn (g6_rtx, GEN_INT (tsize)); + if (Pmode == DImode) + emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + g6_rtx)); + else + emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + g6_rtx)); + tsize = 0; + } + + if (tsize && tsize != orig_tsize) + tsize_rtx = GEN_INT (tsize); + } + + if (Pmode == DImode) + emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx)); + else + emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); + } + + /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we + are going to restore it, then we must emit a blockage insn to + prevent the scheduler from moving the restore out of the epilogue. */ + else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64 + && (current_frame_info.mask + & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)))) + emit_insn (gen_blockage ()); + + save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0); + + /* In mips16 mode with a large frame, we adjust the stack + pointer before restoring the registers. In this case, we + should always be using a frame pointer, so everything should + have been handled above. */ + if (tsize > 32767 && TARGET_MIPS16) + abort (); + + emit_insn (gen_blockage ()); + if (Pmode == DImode && tsize != 0) + emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + else if (tsize != 0) + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + } + + /* The mips16 loads the return address into $7, not $31. */ + if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0) + emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, + GP_REG_FIRST + 7))); + else + emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, + GP_REG_FIRST + 31))); +} + +/* Return nonzero if this function is known to have a null epilogue. + This allows the optimizer to omit jumps to jumps if no stack + was created. */ + +int +mips_can_use_return_insn () +{ + if (! reload_completed) + return 0; + + if (regs_ever_live[31] || profile_flag) + return 0; + + /* In mips16 mode, a function which returns a floating point value + needs to arrange to copy the return value into the floating point + registers. */ + if (TARGET_MIPS16 + && mips16_hard_float + && ! aggregate_value_p (DECL_RESULT (current_function_decl)) + && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl))) + == MODE_FLOAT) + && (! TARGET_SINGLE_FLOAT + || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl))) + <= 4))) + return 0; + + if (current_frame_info.initialized) + return current_frame_info.total_size == 0; + + return compute_frame_size (get_frame_size ()) == 0; +} + +/* Choose the section to use for the constant rtx expression X that has + mode MODE. */ + +void +mips_select_rtx_section (mode, x) + enum machine_mode mode; + rtx x ATTRIBUTE_UNUSED; +{ + if (TARGET_MIPS16) + { + /* In mips16 mode, the constant table always goes in the same section + as the function, so that constants can be loaded using PC relative + addressing. */ + function_section (current_function_decl); + } + else if (TARGET_EMBEDDED_DATA) + { + /* For embedded applications, always put constants in read-only data, + in order to reduce RAM usage. */ + READONLY_DATA_SECTION (); + } + else + { + /* For hosted applications, always put constants in small data if + possible, as this gives the best performance. */ + + if (GET_MODE_SIZE (mode) <= mips_section_threshold + && mips_section_threshold > 0) + SMALL_DATA_SECTION (); + else + READONLY_DATA_SECTION (); + } +} + +/* Choose the section to use for DECL. RELOC is true if its value contains + any relocatable expression. + + Some of the logic used here needs to be replicated in + ENCODE_SECTION_INFO in mips.h so that references to these symbols + are done correctly. Specifically, at least all symbols assigned + here to rom (.text and/or .rodata) must not be referenced via + ENCODE_SECTION_INFO with %gprel, as the rom might be too far away. + + If you need to make a change here, you probably should check + ENCODE_SECTION_INFO to see if it needs a similar change. */ + +void +mips_select_section (decl, reloc) + tree decl; + int reloc; +{ + int size = int_size_in_bytes (TREE_TYPE (decl)); + + if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16) + && TREE_CODE (decl) == STRING_CST + && !flag_writable_strings) + /* For embedded position independent code, put constant strings in the + text section, because the data section is limited to 64K in size. + For mips16 code, put strings in the text section so that a PC + relative load instruction can be used to get their address. */ + text_section (); + else if (TARGET_EMBEDDED_DATA) + { + /* For embedded applications, always put an object in read-only data + if possible, in order to reduce RAM usage. */ + + if (((TREE_CODE (decl) == VAR_DECL + && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl) + && DECL_INITIAL (decl) + && (DECL_INITIAL (decl) == error_mark_node + || TREE_CONSTANT (DECL_INITIAL (decl)))) + /* Deal with calls from output_constant_def_contents. */ + || (TREE_CODE (decl) != VAR_DECL + && (TREE_CODE (decl) != STRING_CST + || !flag_writable_strings))) + && ! (flag_pic && reloc)) + READONLY_DATA_SECTION (); + else if (size > 0 && size <= mips_section_threshold) + SMALL_DATA_SECTION (); + else + data_section (); + } + else + { + /* For hosted applications, always put an object in small data if + possible, as this gives the best performance. */ + + if (size > 0 && size <= mips_section_threshold) + SMALL_DATA_SECTION (); + else if (((TREE_CODE (decl) == VAR_DECL + && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl) + && DECL_INITIAL (decl) + && (DECL_INITIAL (decl) == error_mark_node + || TREE_CONSTANT (DECL_INITIAL (decl)))) + /* Deal with calls from output_constant_def_contents. */ + || (TREE_CODE (decl) != VAR_DECL + && (TREE_CODE (decl) != STRING_CST + || !flag_writable_strings))) + && ! (flag_pic && reloc)) + READONLY_DATA_SECTION (); + else + data_section (); + } +} + +#ifdef MIPS_ABI_DEFAULT + +/* Support functions for the 64 bit ABI. */ + +/* Return register to use for a function return value with VALTYPE for function + FUNC. */ + +rtx +mips_function_value (valtype, func) + tree valtype; + tree func ATTRIBUTE_UNUSED; +{ + int reg = GP_RETURN; + enum machine_mode mode = TYPE_MODE (valtype); + enum mode_class mclass = GET_MODE_CLASS (mode); + int unsignedp = TREE_UNSIGNED (valtype); + + /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode + just as PROMOTE_MODE does. */ + mode = promote_mode (valtype, mode, &unsignedp, 1); + + /* ??? How should we return complex float? */ + if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) + { + if (TARGET_SINGLE_FLOAT + && (mclass == MODE_FLOAT + ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4)) + reg = GP_RETURN; + else + reg = FP_RETURN; + } + + else if (TREE_CODE (valtype) == RECORD_TYPE + && mips_abi != ABI_32 + && mips_abi != ABI_O64 + && mips_abi != ABI_EABI) + { + /* A struct with only one or two floating point fields is returned in + the floating point registers. */ + tree field, fields[2]; + int i; + + for (i = 0, field = TYPE_FIELDS (valtype); field; + field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) != FIELD_DECL) + continue; + + if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2) + break; + + fields[i++] = field; + } + + /* Must check i, so that we reject structures with no elements. */ + if (! field) + { + if (i == 1) + { + /* The structure has DImode, but we don't allow DImode values + in FP registers, so we use a PARALLEL even though it isn't + strictly necessary. */ + enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0])); + + return gen_rtx (PARALLEL, mode, + gen_rtvec (1, + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (REG, field_mode, + FP_RETURN), + const0_rtx))); + } + + else if (i == 2) + { + enum machine_mode first_mode + = TYPE_MODE (TREE_TYPE (fields[0])); + enum machine_mode second_mode + = TYPE_MODE (TREE_TYPE (fields[1])); + int first_offset + = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0])); + int second_offset + = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1])); + + return gen_rtx (PARALLEL, mode, + gen_rtvec (2, + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (REG, first_mode, + FP_RETURN), + GEN_INT (first_offset + / BITS_PER_UNIT)), + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (REG, second_mode, + FP_RETURN + 2), + GEN_INT (second_offset + / BITS_PER_UNIT)))); + } + } + } + + return gen_rtx (REG, mode, reg); +} + +/* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return + nonzero when an argument must be passed by reference. */ + +int +function_arg_pass_by_reference (cum, mode, type, named) + CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; + enum machine_mode mode; + tree type; + int named ATTRIBUTE_UNUSED; +{ + int size; + + if (mips_abi != ABI_EABI) + return 0; + + /* ??? How should SCmode be handled? */ + if (type == NULL_TREE || mode == DImode || mode == DFmode) + return 0; + + size = int_size_in_bytes (type); + return size == -1 || size > UNITS_PER_WORD; +} +#endif + +/* This function returns the register class required for a secondary + register when copying between one of the registers in CLASS, and X, + using MODE. If IN_P is nonzero, the copy is going from X to the + register, otherwise the register is the source. A return value of + NO_REGS means that no secondary register is required. */ + +enum reg_class +mips_secondary_reload_class (class, mode, x, in_p) + enum reg_class class; + enum machine_mode mode; + rtx x; + int in_p; +{ + enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS; + int regno = -1; + int gp_reg_p; + + if (GET_CODE (x) == SIGN_EXTEND) + { + int off = 0; + + x = XEXP (x, 0); + + /* We may be called with reg_renumber NULL from regclass. + ??? This is probably a bug. */ + if (reg_renumber) + regno = true_regnum (x); + else + { + while (GET_CODE (x) == SUBREG) + { + off += SUBREG_WORD (x); + x = SUBREG_REG (x); + } + + if (GET_CODE (x) == REG) + regno = REGNO (x) + off; + } + } + + else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) + regno = true_regnum (x); + + gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); + + /* We always require a general register when copying anything to + HILO_REGNUM, except when copying an SImode value from HILO_REGNUM + to a general register, or when copying from register 0. */ + if (class == HILO_REG && regno != GP_REG_FIRST + 0) + return ((! in_p + && gp_reg_p + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) + ? NO_REGS : gr_regs); + else if (regno == HILO_REGNUM) + return ((in_p + && class == gr_regs + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) + ? NO_REGS : gr_regs); + + /* Copying from HI or LO to anywhere other than a general register + requires a general register. */ + if (class == HI_REG || class == LO_REG || class == MD_REGS) + { + if (TARGET_MIPS16 && in_p) + { + /* We can't really copy to HI or LO at all in mips16 mode. */ + return M16_REGS; + } + return gp_reg_p ? NO_REGS : gr_regs; + } + if (MD_REG_P (regno)) + { + if (TARGET_MIPS16 && ! in_p) + { + /* We can't really copy to HI or LO at all in mips16 mode. */ + return M16_REGS; + } + return class == gr_regs ? NO_REGS : gr_regs; + } + + /* We can only copy a value to a condition code register from a + floating point register, and even then we require a scratch + floating point register. We can only copy a value out of a + condition code register into a general register. */ + if (class == ST_REGS) + { + if (in_p) + return FP_REGS; + return GP_REG_P (regno) ? NO_REGS : GR_REGS; + } + if (ST_REG_P (regno)) + { + if (! in_p) + return FP_REGS; + return class == GR_REGS ? NO_REGS : GR_REGS; + } + + /* In mips16 mode, going between memory and anything but M16_REGS + requires an M16_REG. */ + if (TARGET_MIPS16) + { + if (class != M16_REGS && class != M16_NA_REGS) + { + if (gp_reg_p) + return NO_REGS; + return M16_REGS; + } + if (! gp_reg_p) + { + if (class == M16_REGS || class == M16_NA_REGS) + return NO_REGS; + return M16_REGS; + } + } + + return NO_REGS; +} + +/* For each mips16 function which refers to GP relative symbols, we + use a pseudo register, initialized at the start of the function, to + hold the $gp value. */ + +rtx +mips16_gp_pseudo_reg () +{ + if (mips16_gp_pseudo_rtx == NULL_RTX) + { + rtx const_gp; + rtx insn, scan; + + mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); + RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1; + + /* We want to initialize this to a value which gcc will believe + is constant. */ + const_gp = gen_rtx (CONST, Pmode, + gen_rtx (REG, Pmode, GP_REG_FIRST + 28)); + + start_sequence (); + emit_move_insn (mips16_gp_pseudo_rtx, const_gp); + insn = gen_sequence (); + end_sequence (); + + push_topmost_sequence (); + /* We need to emit the initialization after the FUNCTION_BEG + note, so that it will be integrated. */ + for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan)) + if (GET_CODE (scan) == NOTE + && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG) + break; + if (scan == NULL_RTX) + scan = get_insns (); + insn = emit_insn_after (insn, scan); + pop_topmost_sequence (); + } + + return mips16_gp_pseudo_rtx; +} + +/* Return an RTX which represents the signed 16 bit offset from the + $gp register for the given symbol. This is only used on the + mips16. */ + +rtx +mips16_gp_offset (sym) + rtx sym; +{ + tree gp; + + if (GET_CODE (sym) != SYMBOL_REF + || ! SYMBOL_REF_FLAG (sym)) + abort (); + + /* We use a special identifier to represent the value of the gp + register. */ + gp = get_identifier ("__mips16_gp_value"); + + return gen_rtx (CONST, Pmode, + gen_rtx (MINUS, Pmode, sym, + gen_rtx (SYMBOL_REF, Pmode, + IDENTIFIER_POINTER (gp)))); +} + +/* Return nonzero if the given RTX represents a signed 16 bit offset + from the $gp register. */ + +int +mips16_gp_offset_p (x) + rtx x; +{ + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + /* It's OK to add a small integer value to a gp offset. */ + if (GET_CODE (x) == PLUS) + { + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && SMALL_INT (XEXP (x, 1))) + return mips16_gp_offset_p (XEXP (x, 0)); + if (GET_CODE (XEXP (x, 0)) == CONST_INT + && SMALL_INT (XEXP (x, 0))) + return mips16_gp_offset_p (XEXP (x, 1)); + return 0; + } + + /* Make sure it is in the form SYM - __mips16_gp_value. */ + return (GET_CODE (x) == MINUS + && GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && SYMBOL_REF_FLAG (XEXP (x, 0)) + && GET_CODE (XEXP (x, 1)) == SYMBOL_REF + && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0); +} + +/* Output a GP offset. We don't want to print the subtraction of + __mips16_gp_value; it is implicitly represented by the %gprel which + should have been printed by the caller. */ + +static void +mips16_output_gp_offset (file, x) + FILE *file; + rtx x; +{ + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + if (GET_CODE (x) == PLUS) + { + mips16_output_gp_offset (file, XEXP (x, 0)); + fputs ("+", file); + mips16_output_gp_offset (file, XEXP (x, 1)); + return; + } + + if (GET_CODE (x) == MINUS + && GET_CODE (XEXP (x, 1)) == SYMBOL_REF + && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0) + { + mips16_output_gp_offset (file, XEXP (x, 0)); + return; + } + + output_addr_const (file, x); +} + +/* Return nonzero if a constant should not be output until after the + function. This is true of most string constants, so that we can + use a more efficient PC relative reference. However, a static + inline function may never call assemble_function_end to write out + the constant pool, so don't try to postpone the constant in that + case. + + ??? It's really a bug that a static inline function can put stuff + in the constant pool even if the function itself is not output. + + We record which string constants we've seen, so that we know which + ones might use the more efficient reference. */ + +int +mips16_constant_after_function_p (x) + tree x; +{ + if (TREE_CODE (x) == STRING_CST + && ! flag_writable_strings + && current_function_decl != 0 + && ! DECL_DEFER_OUTPUT (current_function_decl) + && ! (DECL_INLINE (current_function_decl) + && ((! TREE_PUBLIC (current_function_decl) + && ! TREE_ADDRESSABLE (current_function_decl) + && ! flag_keep_inline_functions) + || DECL_EXTERNAL (current_function_decl)))) + { + struct string_constant *n; + + n = (struct string_constant *) xmalloc (sizeof *n); + n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0); + n->next = string_constants; + string_constants = n; + + return 1; + } + + return 0; +} + +/* Validate a constant for the mips16. This rejects general symbolic + addresses, which must be loaded from memory. If ADDR is nonzero, + this should reject anything which is not a legal address. If + ADDEND is nonzero, this is being added to something else. */ + +int +mips16_constant (x, mode, addr, addend) + rtx x; + enum machine_mode mode; + int addr; + int addend; +{ + while (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + switch (GET_CODE (x)) + { + default: + return 0; + + case PLUS: + return (mips16_constant (XEXP (x, 0), mode, addr, 1) + && mips16_constant (XEXP (x, 1), mode, addr, 1)); + + case SYMBOL_REF: + if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8) + return 0; + if (CONSTANT_POOL_ADDRESS_P (x)) + return 1; + + /* If we aren't looking for a memory address, we can accept a GP + relative symbol, which will have SYMBOL_REF_FLAG set; movsi + knows how to handle this. We can always accept a string + constant, which is the other case in which SYMBOL_REF_FLAG + will be set. */ + if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode) + return 1; + + /* We can accept a string constant, which will have + SYMBOL_REF_FLAG set but must be recognized by name to + distinguish from a GP accessible symbol. The name of a + string constant will have been generated by + ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */ + if (SYMBOL_REF_FLAG (x)) + { + char *name = XSTR (x, 0); + + return (name[0] == '*' + && strncmp (name + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) == 0); + } + + return 0; + + case LABEL_REF: + if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8) + return 0; + return 1; + + case CONST_INT: + if (addr && ! addend) + return 0; + return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff; + + case REG: + /* We need to treat $gp as a legitimate constant, because + mips16_gp_pseudo_reg assumes that. */ + return REGNO (x) == GP_REG_FIRST + 28; + } +} + +/* Write out code to move floating point arguments in or out of + general registers. Output the instructions to FILE. FP_CODE is + the code describing which arguments are present (see the comment at + the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if + we are copying from the floating point registers. */ + +static void +mips16_fp_args (file, fp_code, from_fp_p) + FILE *file; + int fp_code; + int from_fp_p; +{ + const char *s; + int gparg, fparg; + unsigned int f; + + /* This code only works for the original 32 bit ABI and the O64 ABI. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + abort (); + + if (from_fp_p) + s = "mfc1"; + else + s = "mtc1"; + gparg = GP_ARG_FIRST; + fparg = FP_ARG_FIRST; + for (f = (unsigned int) fp_code; f != 0; f >>= 2) + { + if ((f & 3) == 1) + { + if ((fparg & 1) != 0) + ++fparg; + fprintf (file, "\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg]); + } + else if ((f & 3) == 2) + { + if (TARGET_64BIT) + fprintf (file, "\td%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg]); + else + { + if ((fparg & 1) != 0) + ++fparg; + if (TARGET_BIG_ENDIAN) + fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg + 1], s, + reg_names[gparg + 1], reg_names[fparg]); + else + fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg], s, + reg_names[gparg + 1], reg_names[fparg + 1]); + ++gparg; + ++fparg; + } + } + else + abort (); + + ++gparg; + ++fparg; + } +} + +/* Build a mips16 function stub. This is used for functions which + take aruments in the floating point registers. It is 32 bit code + that moves the floating point args into the general registers, and + then jumps to the 16 bit code. */ + +static void +build_mips16_function_stub (file) + FILE *file; +{ + char *fnname; + char *secname, *stubname; + tree stubid, stubdecl; + int need_comma; + unsigned int f; + + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + secname = (char *) alloca (strlen (fnname) + 20); + sprintf (secname, ".mips16.fn.%s", fnname); + stubname = (char *) alloca (strlen (fnname) + 20); + sprintf (stubname, "__fn_stub_%s", fnname); + stubid = get_identifier (stubname); + stubdecl = build_decl (FUNCTION_DECL, stubid, + build_function_type (void_type_node, NULL_TREE)); + DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); + + fprintf (file, "\t# Stub function for %s (", current_function_name); + need_comma = 0; + for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2) + { + fprintf (file, "%s%s", + need_comma ? ", " : "", + (f & 3) == 1 ? "float" : "double"); + need_comma = 1; + } + fprintf (file, ")\n"); + + fprintf (file, "\t.set\tnomips16\n"); + function_section (stubdecl); + ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT)); + + /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are + within a .ent, and we can not emit another .ent. */ +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.ent\t", file); + assemble_name (file, stubname); + fputs ("\n", file); +#endif + + assemble_name (file, stubname); + fputs (":\n", file); + + /* We don't want the assembler to insert any nops here. */ + fprintf (file, "\t.set\tnoreorder\n"); + + mips16_fp_args (file, current_function_args_info.fp_code, 1); + + fprintf (asm_out_file, "\t.set\tnoat\n"); + fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]); + assemble_name (file, fnname); + fprintf (file, "\n"); + fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]); + fprintf (asm_out_file, "\t.set\tat\n"); + + /* Unfortunately, we can't fill the jump delay slot. We can't fill + with one of the mfc1 instructions, because the result is not + available for one instruction, so if the very first instruction + in the function refers to the register, it will see the wrong + value. */ + fprintf (file, "\tnop\n"); + + fprintf (file, "\t.set\treorder\n"); + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.end\t", file); + assemble_name (file, stubname); + fputs ("\n", file); +#endif + + fprintf (file, "\t.set\tmips16\n"); + + function_section (current_function_decl); +} + +/* We keep a list of functions for which we have already built stubs + in build_mips16_call_stub. */ + +struct mips16_stub +{ + struct mips16_stub *next; + char *name; + int fpret; +}; + +static struct mips16_stub *mips16_stubs; + +/* Build a call stub for a mips16 call. A stub is needed if we are + passing any floating point values which should go into the floating + point registers. If we are, and the call turns out to be to a 32 + bit function, the stub will be used to move the values into the + floating point registers before calling the 32 bit function. The + linker will magically adjust the function call to either the 16 bit + function or the 32 bit stub, depending upon where the function call + is actually defined. + + Similarly, we need a stub if the return value might come back in a + floating point register. + + RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn + (RETVAL is NULL if this is call rather than call_value). FP_CODE + is the code built by function_arg. This function returns a nonzero + value if it builds the call instruction itself. */ + +int +build_mips16_call_stub (retval, fnmem, arg_size, fp_code) + rtx retval; + rtx fnmem; + rtx arg_size; + int fp_code; +{ + int fpret; + rtx fn; + char *fnname, *secname, *stubname; + struct mips16_stub *l; + tree stubid, stubdecl; + int need_comma; + unsigned int f; + + /* We don't need to do anything if we aren't in mips16 mode, or if + we were invoked with the -msoft-float option. */ + if (! TARGET_MIPS16 || ! mips16_hard_float) + return 0; + + /* Figure out whether the value might come back in a floating point + register. */ + fpret = (retval != 0 + && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT + && (! TARGET_SINGLE_FLOAT + || GET_MODE_SIZE (GET_MODE (retval)) <= 4)); + + /* We don't need to do anything if there were no floating point + arguments and the value will not be returned in a floating point + register. */ + if (fp_code == 0 && ! fpret) + return 0; + + if (GET_CODE (fnmem) != MEM) + abort (); + fn = XEXP (fnmem, 0); + + /* We don't need to do anything if this is a call to a special + mips16 support function. */ + if (GET_CODE (fn) == SYMBOL_REF + && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0) + return 0; + + /* This code will only work for o32 and o64 abis. The other ABI's + require more sophisticated support. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + abort (); + + /* We can only handle SFmode and DFmode floating point return + values. */ + if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode) + abort (); + + /* If we're calling via a function pointer, then we must always call + via a stub. There are magic stubs provided in libgcc.a for each + of the required cases. Each of them expects the function address + to arrive in register $2. */ + + if (GET_CODE (fn) != SYMBOL_REF) + { + char buf[30]; + tree id; + rtx stub_fn, stub_mem, insn; + + /* ??? If this code is modified to support other ABI's, we need + to handle PARALLEL return values here. */ + + sprintf (buf, "__mips16_call_stub_%s%d", + (fpret + ? (GET_MODE (retval) == SFmode ? "sf_" : "df_") + : ""), + fp_code); + id = get_identifier (buf); + stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id)); + stub_mem = gen_rtx (MEM, Pmode, stub_fn); + + emit_move_insn (gen_rtx (REG, Pmode, 2), fn); + + if (retval == NULL_RTX) + insn = gen_call_internal0 (stub_mem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + else + insn = gen_call_value_internal0 (retval, stub_mem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + insn = emit_call_insn (insn); + + /* Put the register usage information on the CALL. */ + if (GET_CODE (insn) != CALL_INSN) + abort (); + CALL_INSN_FUNCTION_USAGE (insn) = + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)), + CALL_INSN_FUNCTION_USAGE (insn)); + + /* If we are handling a floating point return value, we need to + save $18 in the function prologue. Putting a note on the + call will mean that regs_ever_live[$18] will be true if the + call is not eliminated, and we can check that in the prologue + code. */ + if (fpret) + CALL_INSN_FUNCTION_USAGE (insn) = + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)), + CALL_INSN_FUNCTION_USAGE (insn)); + + /* Return 1 to tell the caller that we've generated the call + insn. */ + return 1; + } + + /* We know the function we are going to call. If we have already + built a stub, we don't need to do anything further. */ + + fnname = XSTR (fn, 0); + for (l = mips16_stubs; l != NULL; l = l->next) + if (strcmp (l->name, fnname) == 0) + break; + + if (l == NULL) + { + /* Build a special purpose stub. When the linker sees a + function call in mips16 code, it will check where the target + is defined. If the target is a 32 bit call, the linker will + search for the section defined here. It can tell which + symbol this section is associated with by looking at the + relocation information (the name is unreliable, since this + might be a static function). If such a section is found, the + linker will redirect the call to the start of the magic + section. + + If the function does not return a floating point value, the + special stub section is named + .mips16.call.FNNAME + + If the function does return a floating point value, the stub + section is named + .mips16.call.fp.FNNAME + */ + + secname = (char *) alloca (strlen (fnname) + 40); + sprintf (secname, ".mips16.call.%s%s", + fpret ? "fp." : "", + fnname); + stubname = (char *) alloca (strlen (fnname) + 20); + sprintf (stubname, "__call_stub_%s%s", + fpret ? "fp_" : "", + fnname); + stubid = get_identifier (stubname); + stubdecl = build_decl (FUNCTION_DECL, stubid, + build_function_type (void_type_node, NULL_TREE)); + DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); + + fprintf (asm_out_file, "\t# Stub function to call %s%s (", + (fpret + ? (GET_MODE (retval) == SFmode ? "float " : "double ") + : ""), + fnname); + need_comma = 0; + for (f = (unsigned int) fp_code; f != 0; f >>= 2) + { + fprintf (asm_out_file, "%s%s", + need_comma ? ", " : "", + (f & 3) == 1 ? "float" : "double"); + need_comma = 1; + } + fprintf (asm_out_file, ")\n"); + + fprintf (asm_out_file, "\t.set\tnomips16\n"); + assemble_start_function (stubdecl, stubname); + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.ent\t", asm_out_file); + assemble_name (asm_out_file, stubname); + fputs ("\n", asm_out_file); + + assemble_name (asm_out_file, stubname); + fputs (":\n", asm_out_file); +#endif + + /* We build the stub code by hand. That's the only way we can + do it, since we can't generate 32 bit code during a 16 bit + compilation. */ + + /* We don't want the assembler to insert any nops here. */ + fprintf (asm_out_file, "\t.set\tnoreorder\n"); + + mips16_fp_args (asm_out_file, fp_code, 0); + + if (! fpret) + { + fprintf (asm_out_file, "\t.set\tnoat\n"); + fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1], + fnname); + fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]); + fprintf (asm_out_file, "\t.set\tat\n"); + /* Unfortunately, we can't fill the jump delay slot. We + can't fill with one of the mtc1 instructions, because the + result is not available for one instruction, so if the + very first instruction in the function refers to the + register, it will see the wrong value. */ + fprintf (asm_out_file, "\tnop\n"); + } + else + { + fprintf (asm_out_file, "\tmove\t%s,%s\n", + reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]); + fprintf (asm_out_file, "\tjal\t%s\n", fnname); + /* As above, we can't fill the delay slot. */ + fprintf (asm_out_file, "\tnop\n"); + if (GET_MODE (retval) == SFmode) + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]); + else + { + if (TARGET_BIG_ENDIAN) + { + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[FP_REG_FIRST + 1]); + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 3], + reg_names[FP_REG_FIRST + 0]); + } + else + { + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[FP_REG_FIRST + 0]); + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 3], + reg_names[FP_REG_FIRST + 1]); + } + } + fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]); + /* As above, we can't fill the delay slot. */ + fprintf (asm_out_file, "\tnop\n"); + } + + fprintf (asm_out_file, "\t.set\treorder\n"); + +#ifdef ASM_DECLARE_FUNCTION_SIZE + ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); +#endif + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.end\t", asm_out_file); + assemble_name (asm_out_file, stubname); + fputs ("\n", asm_out_file); +#endif + + fprintf (asm_out_file, "\t.set\tmips16\n"); + + /* Record this stub. */ + l = (struct mips16_stub *) xmalloc (sizeof *l); + l->name = (char *) xmalloc (strlen (fnname) + 1); + strcpy (l->name, fnname); + l->fpret = fpret; + l->next = mips16_stubs; + mips16_stubs = l; + } + + /* If we expect a floating point return value, but we've built a + stub which does not expect one, then we're in trouble. We can't + use the existing stub, because it won't handle the floating point + value. We can't build a new stub, because the linker won't know + which stub to use for the various calls in this object file. + Fortunately, this case is illegal, since it means that a function + was declared in two different ways in a single compilation. */ + if (fpret && ! l->fpret) + error ("can not handle inconsistent calls to `%s'", fnname); + + /* If we are calling a stub which handles a floating point return + value, we need to arrange to save $18 in the prologue. We do + this by marking the function call as using the register. The + prologue will later see that it is used, and emit code to save + it. */ + + if (l->fpret) + { + rtx insn; + + if (retval == NULL_RTX) + insn = gen_call_internal0 (fnmem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + else + insn = gen_call_value_internal0 (retval, fnmem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + insn = emit_call_insn (insn); + + if (GET_CODE (insn) != CALL_INSN) + abort (); + + CALL_INSN_FUNCTION_USAGE (insn) = + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)), + CALL_INSN_FUNCTION_USAGE (insn)); + + /* Return 1 to tell the caller that we've generated the call + insn. */ + return 1; + } + + /* Return 0 to let the caller generate the call insn. */ + return 0; +} + +/* This function looks through the code for a function, and tries to + optimize the usage of the $gp register. We arrange to copy $gp + into a pseudo-register, and then let gcc's normal reload handling + deal with the pseudo-register. Unfortunately, if reload choose to + put the pseudo-register into a call-clobbered register, it will + emit saves and restores for that register around any function + calls. We don't need the saves, and it's faster to copy $gp than + to do an actual restore. ??? This still means that we waste a + stack slot. + + This is an optimization, and the code which gcc has actually + generated is correct, so we do not need to catch all cases. */ + +static void +mips16_optimize_gp (first) + rtx first; +{ + rtx gpcopy, slot, insn; + + /* Look through the instructions. Set GPCOPY to the register which + holds a copy of $gp. Set SLOT to the stack slot where it is + saved. If we find an instruction which sets GPCOPY to anything + other than $gp or SLOT, then we can't use it. If we find an + instruction which sets SLOT to anything other than GPCOPY, we + can't use it. */ + + gpcopy = NULL_RTX; + slot = NULL_RTX; + for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn)) + { + rtx set; + + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + set = PATTERN (insn); + + /* We know that all references to memory will be inside a SET, + because there is no other way to access memory on the mips16. + We don't have to worry about a PARALLEL here, because the + mips.md file will never generate them for memory references. */ + if (GET_CODE (set) != SET) + continue; + + if (gpcopy == NULL_RTX + && GET_CODE (SET_SRC (set)) == CONST + && GET_CODE (XEXP (SET_SRC (set), 0)) == REG + && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28 + && GET_CODE (SET_DEST (set)) == REG + && GET_MODE (SET_DEST (set)) == Pmode) + gpcopy = SET_DEST (set); + else if (slot == NULL_RTX + && gpcopy != NULL_RTX + && GET_CODE (SET_DEST (set)) == MEM + && GET_CODE (SET_SRC (set)) == REG + && REGNO (SET_SRC (set)) == REGNO (gpcopy) + && GET_MODE (SET_DEST (set)) == Pmode) + { + rtx base, offset; + + offset = const0_rtx; + base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); + if (GET_CODE (base) == REG + && (REGNO (base) == STACK_POINTER_REGNUM + || REGNO (base) == FRAME_POINTER_REGNUM)) + slot = SET_DEST (set); + } + else if (gpcopy != NULL_RTX + && (GET_CODE (SET_DEST (set)) == REG + || GET_CODE (SET_DEST (set)) == SUBREG) + && reg_overlap_mentioned_p (SET_DEST (set), gpcopy) + && (GET_CODE (SET_DEST (set)) != REG + || REGNO (SET_DEST (set)) != REGNO (gpcopy) + || GET_MODE (SET_DEST (set)) != Pmode + || ((GET_CODE (SET_SRC (set)) != CONST + || GET_CODE (XEXP (SET_SRC (set), 0)) != REG + || (REGNO (XEXP (SET_SRC (set), 0)) + != GP_REG_FIRST + 28)) + && ! rtx_equal_p (SET_SRC (set), slot)))) + break; + else if (slot != NULL_RTX + && GET_CODE (SET_DEST (set)) == MEM + && rtx_equal_p (SET_DEST (set), slot) + && (GET_CODE (SET_SRC (set)) != REG + || REGNO (SET_SRC (set)) != REGNO (gpcopy))) + break; + } + + /* If we couldn't find a unique value for GPCOPY or SLOT, then try a + different optimization. Any time we find a copy of $28 into a + register, followed by an add of a symbol_ref to that register, we + convert it to load the value from the constant table instead. + The copy and add will take six bytes, just as the load and + constant table entry will take six bytes. However, it is + possible that the constant table entry will be shared. + + This could be a peephole optimization, but I don't know if the + peephole code can call force_const_mem. + + Using the same register for the copy of $28 and the add of the + symbol_ref is actually pretty likely, since the add instruction + requires the destination and the first addend to be the same + register. */ + + if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX) + { + rtx next; + + /* This optimization is only reasonable if the constant table + entries are only 4 bytes. */ + if (Pmode != SImode) + return; + + for (insn = first; insn != NULL_RTX; insn = next) + { + rtx set1, set2; + + next = insn; + do + { + next = NEXT_INSN (next); + } + while (next != NULL_RTX + && (GET_CODE (next) == NOTE + || (GET_CODE (next) == INSN + && (GET_CODE (PATTERN (next)) == USE + || GET_CODE (PATTERN (next)) == CLOBBER)))); + + if (next == NULL_RTX) + break; + + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + if (GET_RTX_CLASS (GET_CODE (next)) != 'i') + continue; + + set1 = PATTERN (insn); + if (GET_CODE (set1) != SET) + continue; + set2 = PATTERN (next); + if (GET_CODE (set2) != SET) + continue; + + if (GET_CODE (SET_DEST (set1)) == REG + && GET_CODE (SET_SRC (set1)) == CONST + && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG + && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28 + && rtx_equal_p (SET_DEST (set1), SET_DEST (set2)) + && GET_CODE (SET_SRC (set2)) == PLUS + && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0)) + && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1)) + && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS) + { + rtx sym; + + /* We've found a case we can change to load from the + constant table. */ + + sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0); + if (GET_CODE (sym) != SYMBOL_REF) + abort (); + emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1), + force_const_mem (Pmode, sym)), + next); + + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + + PUT_CODE (next, NOTE); + NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (next) = 0; + } + } + + return; + } + + /* We can safely remove all assignments to SLOT from GPCOPY, and + replace all assignments from SLOT to GPCOPY with assignments from + $28. */ + + for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn)) + { + rtx set; + + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + set = PATTERN (insn); + if (GET_CODE (set) != SET + || GET_MODE (SET_DEST (set)) != Pmode) + continue; + + if (GET_CODE (SET_DEST (set)) == MEM + && rtx_equal_p (SET_DEST (set), slot) + && GET_CODE (SET_SRC (set)) == REG + && REGNO (SET_SRC (set)) == REGNO (gpcopy)) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + else if (GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) == REGNO (gpcopy) + && GET_CODE (SET_SRC (set)) == MEM + && rtx_equal_p (SET_SRC (set), slot)) + { + emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set), + gen_rtx (CONST, Pmode, + gen_rtx (REG, Pmode, + GP_REG_FIRST + 28))), + insn); + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + } +} + +/* We keep a list of constants we which we have to add to internal + constant tables in the middle of large functions. */ + +struct constant +{ + struct constant *next; + rtx value; + rtx label; + enum machine_mode mode; +}; + +/* Add a constant to the list in *PCONSTANTS. */ + +static rtx +add_constant (pconstants, val, mode) + struct constant **pconstants; + rtx val; + enum machine_mode mode; +{ + struct constant *c; + + for (c = *pconstants; c != NULL; c = c->next) + if (mode == c->mode && rtx_equal_p (val, c->value)) + return c->label; + + c = (struct constant *) xmalloc (sizeof *c); + c->value = val; + c->mode = mode; + c->label = gen_label_rtx (); + c->next = *pconstants; + *pconstants = c; + return c->label; +} + +/* Dump out the constants in CONSTANTS after INSN. */ + +static void +dump_constants (constants, insn) + struct constant *constants; + rtx insn; +{ + struct constant *c; + int align; + + c = constants; + align = 0; + while (c != NULL) + { + rtx r; + struct constant *next; + + switch (GET_MODE_SIZE (c->mode)) + { + case 1: + align = 0; + break; + case 2: + if (align < 1) + insn = emit_insn_after (gen_align_2 (), insn); + align = 1; + break; + case 4: + if (align < 2) + insn = emit_insn_after (gen_align_4 (), insn); + align = 2; + break; + default: + if (align < 3) + insn = emit_insn_after (gen_align_8 (), insn); + align = 3; + break; + } + + insn = emit_label_after (c->label, insn); + + switch (c->mode) + { + case QImode: + r = gen_consttable_qi (c->value); + break; + case HImode: + r = gen_consttable_hi (c->value); + break; + case SImode: + r = gen_consttable_si (c->value); + break; + case SFmode: + r = gen_consttable_sf (c->value); + break; + case DImode: + r = gen_consttable_di (c->value); + break; + case DFmode: + r = gen_consttable_df (c->value); + break; + default: + abort (); + } + + insn = emit_insn_after (r, insn); + + next = c->next; + free (c); + c = next; + } + + emit_barrier_after (insn); +} + +/* Find the symbol in an address expression. */ + +static rtx +mips_find_symbol (addr) + rtx addr; +{ + if (GET_CODE (addr) == MEM) + addr = XEXP (addr, 0); + while (GET_CODE (addr) == CONST) + addr = XEXP (addr, 0); + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + return addr; + if (GET_CODE (addr) == PLUS) + { + rtx l1, l2; + + l1 = mips_find_symbol (XEXP (addr, 0)); + l2 = mips_find_symbol (XEXP (addr, 1)); + if (l1 != NULL_RTX && l2 == NULL_RTX) + return l1; + else if (l1 == NULL_RTX && l2 != NULL_RTX) + return l2; + } + return NULL_RTX; +} + +/* Exported to toplev.c. + + Do a final pass over the function, just before delayed branch + scheduling. */ + +void +machine_dependent_reorg (first) + rtx first; +{ + int insns_len, max_internal_pool_size, pool_size, addr; + rtx insn; + struct constant *constants; + + if (! TARGET_MIPS16) + return; + + /* If $gp is used, try to remove stores, and replace loads with + copies from $gp. */ + if (optimize) + mips16_optimize_gp (first); + + /* Scan the function looking for PC relative loads which may be out + of range. All such loads will either be from the constant table, + or be getting the address of a constant string. If the size of + the function plus the size of the constant table is less than + 0x8000, then all loads are in range. */ + + insns_len = 0; + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + insns_len += get_attr_length (insn) * 2; + + /* ??? We put switch tables in .text, but we don't define + JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not + compute their lengths correctly. */ + if (GET_CODE (insn) == JUMP_INSN) + { + rtx body; + + body = PATTERN (insn); + if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) + insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC) + * GET_MODE_SIZE (GET_MODE (body))); + insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1; + } + } + + /* Store the original value of insns_len in current_frame_info, so + that simple_memory_operand can look at it. */ + current_frame_info.insns_len = insns_len; + + pool_size = get_pool_size (); + if (insns_len + pool_size + mips_string_length < 0x8000) + return; + + /* Loop over the insns and figure out what the maximum internal pool + size could be. */ + max_internal_pool_size = 0; + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SET) + { + rtx src; + + src = mips_find_symbol (SET_SRC (PATTERN (insn))); + if (src == NULL_RTX) + continue; + if (CONSTANT_POOL_ADDRESS_P (src)) + max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src)); + else if (SYMBOL_REF_FLAG (src)) + max_internal_pool_size += GET_MODE_SIZE (Pmode); + } + } + + constants = NULL; + addr = 0; + + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SET) + { + rtx val, src; + enum machine_mode mode; + + val = NULL_RTX; + src = mips_find_symbol (SET_SRC (PATTERN (insn))); + if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src)) + { + /* ??? This is very conservative, which means that we + will generate too many copies of the constant table. + The only solution would seem to be some form of + relaxing. */ + if (((insns_len - addr) + + max_internal_pool_size + + get_pool_offset (src)) + >= 0x8000) + { + val = get_pool_constant (src); + mode = get_pool_mode (src); + } + max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src)); + } + else if (src != NULL_RTX && SYMBOL_REF_FLAG (src)) + { + /* Including all of mips_string_length is conservative, + and so is including all of max_internal_pool_size. */ + if (((insns_len - addr) + + max_internal_pool_size + + pool_size + + mips_string_length) + >= 0x8000) + val = src; + mode = Pmode; + max_internal_pool_size -= Pmode; + } + + if (val != NULL_RTX) + { + rtx lab, newsrc; + + /* This PC relative load is out of range. ??? In the + case of a string constant, we are only guessing that + it is range, since we don't know the offset of a + particular string constant. */ + + lab = add_constant (&constants, val, mode); + newsrc = gen_rtx (MEM, mode, + gen_rtx (LABEL_REF, VOIDmode, lab)); + RTX_UNCHANGING_P (newsrc) = 1; + PATTERN (insn) = gen_rtx (SET, VOIDmode, + SET_DEST (PATTERN (insn)), + newsrc); + INSN_CODE (insn) = -1; + } + } + + addr += get_attr_length (insn) * 2; + + /* ??? We put switch tables in .text, but we don't define + JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not + compute their lengths correctly. */ + if (GET_CODE (insn) == JUMP_INSN) + { + rtx body; + + body = PATTERN (insn); + if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) + addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC) + * GET_MODE_SIZE (GET_MODE (body))); + addr += GET_MODE_SIZE (GET_MODE (body)) - 1; + } + + if (GET_CODE (insn) == BARRIER) + { + /* Output any constants we have accumulated. Note that we + don't need to change ADDR, since its only use is + subtraction from INSNS_LEN, and both would be changed by + the same amount. + ??? If the instructions up to the next barrier reuse a + constant, it would often be better to continue + accumulating. */ + if (constants != NULL) + dump_constants (constants, insn); + constants = NULL; + } + + /* ??? If we don't find a barrier within 0x8000 bytes of + instructions and constants in CONSTANTS, we need to invent + one. This seems sufficiently unlikely that I am not going to + worry about it. */ + } + + if (constants != NULL) + { + rtx label, jump, barrier; + + label = gen_label_rtx (); + jump = emit_jump_insn_after (gen_jump (label), get_last_insn ()); + JUMP_LABEL (jump) = label; + LABEL_NUSES (label) = 1; + barrier = emit_barrier_after (jump); + emit_label_after (label, barrier); + dump_constants (constants, barrier); + constants = NULL; + } + + /* ??? If we output all references to a constant in internal + constants table, we don't need to output the constant in the real + constant table, but we have no way to prevent that. */ +} + +/* Return nonzero if X is a SIGN or ZERO extend operator. */ +int +extend_operator (x, mode) + rtx x; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (x); + return code == SIGN_EXTEND || code == ZERO_EXTEND; +} + +/* Accept any operator that can be used to shift the high half of the + input value to the lower half, suitable for truncation. The + remainder (the lower half of the input, and the upper half of the + output) will be discarded. */ +int +highpart_shift_operator (x, mode) + rtx x; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (x); + return (code == LSHIFTRT + || code == ASHIFTRT + || code == ROTATERT + || code == ROTATE); +} diff --git a/contrib/gcc/config/mips/mips.h b/contrib/gcc/config/mips/mips.h new file mode 100644 index 0000000000000..7360e1b5d64a3 --- /dev/null +++ b/contrib/gcc/config/mips/mips.h @@ -0,0 +1,4720 @@ +/* Definitions of target machine for GNU compiler. MIPS version. + Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc. + Contributed by A. Lichnewsky (lich@inria.inria.fr). + Changed by Michael Meissner (meissner@osf.org). + 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and + Brendan Eich (brendan@microunity.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Standard GCC variables that we reference. */ + +extern char *asm_file_name; +extern char call_used_regs[]; +extern int current_function_calls_alloca; +extern char *language_string; +extern int may_call_alloca; +extern char **save_argv; +extern int target_flags; +extern char *version_string; + +/* MIPS external variables defined in mips.c. */ + +/* comparison type */ +enum cmp_type { + CMP_SI, /* compare four byte integers */ + CMP_DI, /* compare eight byte integers */ + CMP_SF, /* compare single precision floats */ + CMP_DF, /* compare double precision floats */ + CMP_MAX /* max comparison type */ +}; + +/* types of delay slot */ +enum delay_type { + DELAY_NONE, /* no delay slot */ + DELAY_LOAD, /* load from memory delay */ + DELAY_HILO, /* move from/to hi/lo registers */ + DELAY_FCMP /* delay after doing c..{d,s} */ +}; + +/* Which processor to schedule for. Since there is no difference between + a R2000 and R3000 in terms of the scheduler, we collapse them into + just an R3000. The elements of the enumeration must match exactly + the cpu attribute in the mips.md machine description. */ + +enum processor_type { + PROCESSOR_DEFAULT, + PROCESSOR_R3000, + PROCESSOR_R3900, + PROCESSOR_R6000, + PROCESSOR_R4000, + PROCESSOR_R4100, + PROCESSOR_R4300, + PROCESSOR_R4600, + PROCESSOR_R4650, + PROCESSOR_R5000, + PROCESSOR_R8000 +}; + +/* Recast the cpu class to be the cpu attribute. */ +#define mips_cpu_attr ((enum attr_cpu)mips_cpu) + +/* Which ABI to use. These are constants because abi64.h must check their + value at preprocessing time. + + ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all + defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */ + +#define ABI_32 0 +#define ABI_N32 1 +#define ABI_64 2 +#define ABI_EABI 3 +#define ABI_O64 4 + +#ifndef MIPS_ABI_DEFAULT +/* We define this away so that there is no extra runtime cost if the target + doesn't support multiple ABIs. */ +#define mips_abi ABI_32 +#else +extern int mips_abi; +#endif + +/* Whether to emit abicalls code sequences or not. */ + +enum mips_abicalls_type { + MIPS_ABICALLS_NO, + MIPS_ABICALLS_YES +}; + +/* Recast the abicalls class to be the abicalls attribute. */ +#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls) + +/* Which type of block move to do (whether or not the last store is + split out so it can fill a branch delay slot). */ + +enum block_move_type { + BLOCK_MOVE_NORMAL, /* generate complete block move */ + BLOCK_MOVE_NOT_LAST, /* generate all but last store */ + BLOCK_MOVE_LAST /* generate just the last store */ +}; + +extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */ +extern char mips_print_operand_punct[]; /* print_operand punctuation chars */ +extern const char *current_function_file; /* filename current function is in */ +extern int num_source_filenames; /* current .file # */ +extern int inside_function; /* != 0 if inside of a function */ +extern int ignore_line_number; /* != 0 if we are to ignore next .loc */ +extern int file_in_function_warning; /* warning given about .file in func */ +extern int sdb_label_count; /* block start/end next label # */ +extern int sdb_begin_function_line; /* Starting Line of current function */ +extern int mips_section_threshold; /* # bytes of data/sdata cutoff */ +extern int g_switch_value; /* value of the -G xx switch */ +extern int g_switch_set; /* whether -G xx was passed. */ +extern int sym_lineno; /* sgi next label # for each stmt */ +extern int set_noreorder; /* # of nested .set noreorder's */ +extern int set_nomacro; /* # of nested .set nomacro's */ +extern int set_noat; /* # of nested .set noat's */ +extern int set_volatile; /* # of nested .set volatile's */ +extern int mips_branch_likely; /* emit 'l' after br (branch likely) */ +extern int mips_dbx_regno[]; /* Map register # to debug register # */ +extern struct rtx_def *branch_cmp[2]; /* operands for compare */ +extern enum cmp_type branch_type; /* what type of branch to use */ +extern enum processor_type mips_cpu; /* which cpu are we scheduling for */ +extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */ +extern int mips_isa; /* architectural level */ +extern int mips16; /* whether generating mips16 code */ +extern int mips16_hard_float; /* mips16 without -msoft-float */ +extern int mips_entry; /* generate entry/exit for mips16 */ +extern const char *mips_cpu_string; /* for -mcpu= */ +extern const char *mips_isa_string; /* for -mips{1,2,3,4} */ +extern const char *mips_abi_string; /* for -mabi={32,n32,64} */ +extern const char *mips_entry_string; /* for -mentry */ +extern const char *mips_no_mips16_string;/* for -mno-mips16 */ +extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */ +extern int mips_split_addresses; /* perform high/lo_sum support */ +extern int dslots_load_total; /* total # load related delay slots */ +extern int dslots_load_filled; /* # filled load delay slots */ +extern int dslots_jump_total; /* total # jump related delay slots */ +extern int dslots_jump_filled; /* # filled jump delay slots */ +extern int dslots_number_nops; /* # of nops needed by previous insn */ +extern int num_refs[3]; /* # 1/2/3 word references */ +extern struct rtx_def *mips_load_reg; /* register to check for load delay */ +extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */ +extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */ +extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */ +extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */ +extern int mips_string_length; /* length of strings for mips16 */ +extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */ + +/* Functions within mips.c that we reference. Some of these return + type HOST_WIDE_INT, so define that here. */ + +#include "hwint.h" + +extern int arith32_operand (); +extern int arith_operand (); +extern int cmp_op (); +#ifdef HOST_WIDE_INT +extern HOST_WIDE_INT compute_frame_size (); +#endif +extern int const_float_1_operand (); +extern void expand_block_move (); +extern int equality_op (); +extern void final_prescan_insn (); +extern struct rtx_def * function_arg (); +extern void function_arg_advance (); +extern int function_arg_partial_nregs (); +extern int function_arg_pass_by_reference (); +extern void function_epilogue (); +extern void function_prologue (); +extern void gen_conditional_branch (); +extern void gen_conditional_move (); +extern struct rtx_def * gen_int_relational (); +extern void init_cumulative_args (); +extern int large_int (); +extern void machine_dependent_reorg (); +extern int mips_address_cost (); +extern void mips_asm_file_end (); +extern void mips_asm_file_start (); +extern int mips_can_use_return_insn (); +extern int mips_const_double_ok (); +extern void mips_count_memory_refs (); +#ifdef HOST_WIDE_INT +extern HOST_WIDE_INT mips_debugger_offset (); +#endif +extern void mips_declare_object (); +extern int mips_epilogue_delay_slots (); +extern void mips_expand_epilogue (); +extern void mips_expand_prologue (); +extern int mips_check_split (); +extern char *mips_fill_delay_slot (); +extern const char *mips_move_1word (); +extern const char *mips_move_2words (); +extern void mips_output_double (); +extern int mips_output_external (); +extern void mips_output_float (); +extern void mips_output_filename (); +extern void mips_output_lineno (); +extern const char *output_block_move (); +extern void override_options (); +extern int pc_or_label_operand (); +extern void print_operand_address (); +extern void print_operand (); +extern void print_options (); +extern int reg_or_0_operand (); +extern int true_reg_or_0_operand (); +extern int simple_epilogue_p (); +extern int simple_memory_operand (); +extern int double_memory_operand (); +extern int small_int (); +extern void trace (); +extern int uns_arith_operand (); +extern struct rtx_def * embedded_pic_offset (); +extern void mips_order_regs_for_local_alloc (); +extern struct rtx_def * mips16_gp_pseudo_reg (); +extern struct rtx_def * mips16_gp_offset (); +extern int mips16_gp_offset_p (); +extern int mips16_constant (); +extern int mips16_constant_after_function_p (); +extern int build_mips16_call_stub (); + +/* Recognition functions that return if a condition is true. */ +extern int address_operand (); +extern int call_insn_operand (); +extern int const_double_operand (); +extern int const_int_operand (); +extern int consttable_operand (); +extern int general_operand (); +extern int immediate_operand (); +extern int memory_address_p (); +extern int memory_operand (); +extern int nonimmediate_operand (); +extern int nonmemory_operand (); +extern int pic_address_needs_scratch (); +extern int register_operand (); +extern int scratch_operand (); +extern int move_operand (); +extern int movdi_operand (); +extern int se_register_operand (); +extern int se_reg_or_0_operand (); +extern int se_uns_arith_operand (); +extern int se_arith_operand (); +extern int se_nonmemory_operand (); +extern int se_nonimmediate_operand (); +extern int extend_operator (); +extern int highpart_shift_operator (); +extern int m16_uimm3_b (); +extern int m16_simm4_1 (); +extern int m16_nsimm4_1 (); +extern int m16_simm5_1 (); +extern int m16_nsimm5_1 (); +extern int m16_uimm5_4 (); +extern int m16_nuimm5_4 (); +extern int m16_simm8_1 (); +extern int m16_nsimm8_1 (); +extern int m16_uimm8_1 (); +extern int m16_nuimm8_1 (); +extern int m16_uimm8_m1_1 (); +extern int m16_uimm8_4 (); +extern int m16_nuimm8_4 (); +extern int m16_simm8_8 (); +extern int m16_nsimm8_8 (); +extern int m16_usym8_4 (); +extern int m16_usym5_4 (); + +/* Functions to change what output section we are using. */ +extern void data_section (); +extern void rdata_section (); +extern void readonly_data_section (); +extern void sdata_section (); +extern void text_section (); +extern void mips_select_rtx_section (); +extern void mips_select_section (); + +/* Stubs for half-pic support if not OSF/1 reference platform. */ + +#ifndef HALF_PIC_P +#define HALF_PIC_P() 0 +#define HALF_PIC_NUMBER_PTRS 0 +#define HALF_PIC_NUMBER_REFS 0 +#define HALF_PIC_ENCODE(DECL) +#define HALF_PIC_DECLARE(NAME) +#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") +#define HALF_PIC_ADDRESS_P(X) 0 +#define HALF_PIC_PTR(X) X +#define HALF_PIC_FINISH(STREAM) +#endif + + +/* Run-time compilation parameters selecting different hardware subsets. */ + +/* Macros used in the machine description to test the flags. */ + + /* Bits for real switches */ +#define MASK_INT64 0x00000001 /* ints are 64 bits */ +#define MASK_LONG64 0x00000002 /* longs are 64 bits */ +#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */ +#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */ +#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */ +#define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */ +#define MASK_STATS 0x00000040 /* print statistics to stderr */ +#define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/ +#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */ +#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */ +#define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */ +#define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/ +#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */ +#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */ +#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */ +#define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */ +#define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */ +#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */ +#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */ +#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */ +#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */ +#define MASK_MIPS16 0x01000000 /* Generate mips16 code */ +#define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */ +#define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */ + + /* Dummy switches used only in spec's*/ +#define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */ + + /* Debug switches, not documented */ +#define MASK_DEBUG 0 /* Eliminate version # in .s file */ +#define MASK_DEBUG_A 0x40000000 /* don't allow