From c46e6a5940c50058e00c0c5f9123fd82e338d29a Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 8 May 2017 17:12:57 +0000 Subject: Vendor import of llvm trunk r302418: https://llvm.org/svn/llvm-project/llvm/trunk@302418 --- lib/Target/AMDGPU/SIISelLowering.cpp | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'lib/Target/AMDGPU/SIISelLowering.cpp') diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 853c8737b464a..cc93c27731ffc 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1042,6 +1042,7 @@ static void allocateHSAUserSGPRs(CCState &CCInfo, static void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, + CallingConv::ID CallConv, bool IsShader) { if (Info.hasWorkGroupIDX()) { unsigned Reg = Info.addWorkGroupIDX(); @@ -1072,8 +1073,15 @@ static void allocateSystemSGPRs(CCState &CCInfo, unsigned PrivateSegmentWaveByteOffsetReg; if (IsShader) { - PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo); - Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg); + PrivateSegmentWaveByteOffsetReg = + Info.getPrivateSegmentWaveByteOffsetSystemSGPR(); + + // This is true if the scratch wave byte offset doesn't have a fixed + // location. + if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) { + PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo); + Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg); + } } else PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset(); @@ -1310,7 +1318,7 @@ SDValue SITargetLowering::LowerFormalArguments( // Start adding system SGPRs. if (IsEntryFunc) - allocateSystemSGPRs(CCInfo, MF, *Info, IsShader); + allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsShader); reservePrivateMemoryRegs(getTargetMachine(), MF, *TRI, *Info); -- cgit v1.2.3