From 6421cca32f69ac849537a3cff78c352195e99f1b Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sat, 10 Dec 2016 15:02:05 +0000 Subject: Vendor import of llvm release_39 branch r288847: https://llvm.org/svn/llvm-project/llvm/branches/release_39@288847 --- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp') diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 56f5728ecfb89..a7b299677c1cc 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -932,13 +932,10 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, .addReg(DestLo, getKillRegState(Dest.isDead())) .addReg(DesiredLo, getKillRegState(Desired.isDead()))); - unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr; - MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr)) - .addReg(StatusReg, RegState::Define | RegState::Dead) - .addReg(DestHi, getKillRegState(Dest.isDead())) - .addReg(DesiredHi, getKillRegState(Desired.isDead())); - AddDefaultPred(MIB); - MIB.addReg(ARM::CPSR, RegState::Kill); + BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) + .addReg(DestHi, getKillRegState(Dest.isDead())) + .addReg(DesiredHi, getKillRegState(Desired.isDead())) + .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; BuildMI(LoadCmpBB, DL, TII->get(Bcc)) -- cgit v1.2.3