From cfca06d7963fa0909f90483b42a6d7d194d01e08 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sun, 26 Jul 2020 19:36:28 +0000 Subject: Vendor import of llvm-project master 2e10b7a39b9, the last commit before the llvmorg-12-init tag, from which release/11.x was branched. --- llvm/lib/Target/Mips/MipsBranchExpansion.cpp | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'llvm/lib/Target/Mips/MipsBranchExpansion.cpp') diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp index 1523a6c020aad..aa8e298fa7593 100644 --- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp +++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp @@ -342,16 +342,25 @@ void MipsBranchExpansion::replaceBranch(MachineBasicBlock &MBB, Iter Br, for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) { MachineOperand &MO = Br->getOperand(I); - if (!MO.isReg()) { - assert(MO.isMBB() && "MBB operand expected."); + switch (MO.getType()) { + case MachineOperand::MO_Register: + MIB.addReg(MO.getReg()); break; + case MachineOperand::MO_Immediate: + // Octeon BBIT family of branch has an immediate operand + // (e.g. BBIT0 $v0, 3, %bb.1). + if (!TII->isBranchWithImm(Br->getOpcode())) + llvm_unreachable("Unexpected immediate in branch instruction"); + MIB.addImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + MIB.addMBB(MBBOpnd); + break; + default: + llvm_unreachable("Unexpected operand type in branch instruction"); } - - MIB.addReg(MO.getReg()); } - MIB.addMBB(MBBOpnd); - if (Br->hasDelaySlot()) { // Bundle the instruction in the delay slot to the newly created branch // and erase the original branch. -- cgit v1.2.3