From 59d6cff90eecf31cb3dd860c4e786674cfdd42eb Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 10 Jun 2013 20:36:52 +0000 Subject: Vendor import of llvm tags/RELEASE_33/final r183502 (effectively, 3.3 release): http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_33/final@183502 --- test/CodeGen/SystemZ/asm-06.ll | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 test/CodeGen/SystemZ/asm-06.ll (limited to 'test/CodeGen/SystemZ/asm-06.ll') diff --git a/test/CodeGen/SystemZ/asm-06.ll b/test/CodeGen/SystemZ/asm-06.ll new file mode 100644 index 0000000000000..c0e24a3664868 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-06.ll @@ -0,0 +1,39 @@ +; Test the GPR constraint "a", which forbids %r0. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define i64 @f1() { +; CHECK: f1: +; CHECK: lhi %r1, 1 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i8 1) + ret i64 %val +} + +define i64 @f2() { +; CHECK: f2: +; CHECK: lhi %r1, 2 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i16 2) + ret i64 %val +} + +define i64 @f3() { +; CHECK: f3: +; CHECK: lhi %r1, 3 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i32 3) + ret i64 %val +} + +define i64 @f4() { +; CHECK: f4: +; CHECK: lghi %r1, 4 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i64 4) + ret i64 %val +} -- cgit v1.3