From 59d6cff90eecf31cb3dd860c4e786674cfdd42eb Mon Sep 17 00:00:00 2001
From: Dimitry Andric <dim@FreeBSD.org>
Date: Mon, 10 Jun 2013 20:36:52 +0000
Subject: Vendor import of llvm tags/RELEASE_33/final r183502 (effectively, 3.3
 release): http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_33/final@183502

---
 test/CodeGen/XCore/global_negative_offset.ll | 25 -----------------
 test/CodeGen/XCore/offset_folding.ll         | 42 ++++++++++++++++++++++++++++
 test/CodeGen/XCore/unaligned_load.ll         | 25 +++++++++--------
 test/CodeGen/XCore/unaligned_store.ll        | 14 ++++++----
 4 files changed, 64 insertions(+), 42 deletions(-)
 delete mode 100644 test/CodeGen/XCore/global_negative_offset.ll
 create mode 100644 test/CodeGen/XCore/offset_folding.ll

(limited to 'test/CodeGen/XCore')

diff --git a/test/CodeGen/XCore/global_negative_offset.ll b/test/CodeGen/XCore/global_negative_offset.ll
deleted file mode 100644
index 0328fb0460f3f..0000000000000
--- a/test/CodeGen/XCore/global_negative_offset.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: llc < %s -march=xcore | FileCheck %s
-
-; Don't fold negative offsets into cp / dp accesses to avoid a relocation
-; error if the address + addend is less than the start of the cp / dp.
-
-@a = external constant [0 x i32], section ".cp.rodata"
-@b = external global [0 x i32]
-
-define i32 *@f() nounwind {
-entry:
-; CHECK: f:
-; CHECK: ldaw r11, cp[a]
-; CHECK: sub r0, r11, 4
-	%0 = getelementptr [0 x i32]* @a, i32 0, i32 -1
-	ret i32* %0
-}
-
-define i32 *@g() nounwind {
-entry:
-; CHECK: g:
-; CHECK: ldaw [[REG:r[0-9]+]], dp[b]
-; CHECK: sub r0, [[REG]], 4
-	%0 = getelementptr [0 x i32]* @b, i32 0, i32 -1
-	ret i32* %0
-}
diff --git a/test/CodeGen/XCore/offset_folding.ll b/test/CodeGen/XCore/offset_folding.ll
new file mode 100644
index 0000000000000..30edfe695c3f7
--- /dev/null
+++ b/test/CodeGen/XCore/offset_folding.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+@a = external constant [0 x i32], section ".cp.rodata"
+@b = external global [0 x i32]
+
+define i32 *@f1() nounwind {
+entry:
+; CHECK: f1:
+; CHECK: ldaw r11, cp[a+4]
+; CHECK: mov r0, r11
+	%0 = getelementptr [0 x i32]* @a, i32 0, i32 1
+	ret i32* %0
+}
+
+define i32 *@f2() nounwind {
+entry:
+; CHECK: f2:
+; CHECK: ldaw r0, dp[b+4]
+	%0 = getelementptr [0 x i32]* @b, i32 0, i32 1
+	ret i32* %0
+}
+
+; Don't fold negative offsets into cp / dp accesses to avoid a relocation
+; error if the address + addend is less than the start of the cp / dp.
+
+define i32 *@f3() nounwind {
+entry:
+; CHECK: f3:
+; CHECK: ldaw r11, cp[a]
+; CHECK: sub r0, r11, 4
+	%0 = getelementptr [0 x i32]* @a, i32 0, i32 -1
+	ret i32* %0
+}
+
+define i32 *@f4() nounwind {
+entry:
+; CHECK: f4:
+; CHECK: ldaw [[REG:r[0-9]+]], dp[b]
+; CHECK: sub r0, [[REG]], 4
+	%0 = getelementptr [0 x i32]* @b, i32 0, i32 -1
+	ret i32* %0
+}
diff --git a/test/CodeGen/XCore/unaligned_load.ll b/test/CodeGen/XCore/unaligned_load.ll
index 0ee8e1c32667b..772a847bd220b 100644
--- a/test/CodeGen/XCore/unaligned_load.ll
+++ b/test/CodeGen/XCore/unaligned_load.ll
@@ -1,20 +1,19 @@
-; RUN: llc < %s -march=xcore > %t1.s
-; RUN: grep "bl __misaligned_load" %t1.s | count 1
-; RUN: grep ld16s %t1.s | count 2
-; RUN: grep ldw %t1.s | count 2
-; RUN: grep shl %t1.s | count 2
-; RUN: grep shr %t1.s | count 1
-; RUN: grep zext %t1.s | count 1
-; RUN: grep "or " %t1.s | count 2
+; RUN: llc < %s -march=xcore | FileCheck %s
 
-; Byte aligned load. Expands to call to __misaligned_load.
+; Byte aligned load.
+; CHECK: align1
+; CHECK: bl __misaligned_load
 define i32 @align1(i32* %p) nounwind {
 entry:
 	%0 = load i32* %p, align 1		; <i32> [#uses=1]
 	ret i32 %0
 }
 
-; Half word aligned load. Expands to two 16bit loads.
+; Half word aligned load.
+; CHECK: align2:
+; CHECK: ld16s
+; CHECK: ld16s
+; CHECK: or
 define i32 @align2(i32* %p) nounwind {
 entry:
 	%0 = load i32* %p, align 2		; <i32> [#uses=1]
@@ -23,7 +22,11 @@ entry:
 
 @a = global [5 x i8] zeroinitializer, align 4
 
-; Constant offset from word aligned base. Expands to two 32bit loads.
+; Constant offset from word aligned base.
+; CHECK: align3:
+; CHECK: ldw {{r[0-9]+}}, dp
+; CHECK: ldw {{r[0-9]+}}, dp
+; CHECK: or
 define i32 @align3() nounwind {
 entry:
 	%0 = load i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1
diff --git a/test/CodeGen/XCore/unaligned_store.ll b/test/CodeGen/XCore/unaligned_store.ll
index 62078e6f60778..94e1852faea74 100644
--- a/test/CodeGen/XCore/unaligned_store.ll
+++ b/test/CodeGen/XCore/unaligned_store.ll
@@ -1,16 +1,18 @@
-; RUN: llc < %s -march=xcore > %t1.s
-; RUN: grep "bl __misaligned_store" %t1.s | count 1
-; RUN: grep st16 %t1.s | count 2
-; RUN: grep shr %t1.s | count 1
+; RUN: llc < %s -march=xcore | FileCheck %s
 
-; Byte aligned store. Expands to call to __misaligned_store.
+; Byte aligned store.
+; CHECK: align1:
+; CHECK: bl __misaligned_store
 define void @align1(i32* %p, i32 %val) nounwind {
 entry:
 	store i32 %val, i32* %p, align 1
 	ret void
 }
 
-; Half word aligned store. Expands to two 16bit stores.
+; Half word aligned store.
+; CHECK: align2
+; CHECK: st16
+; CHECK: st16
 define void @align2(i32* %p, i32 %val) nounwind {
 entry:
 	store i32 %val, i32* %p, align 2
-- 
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