From 989df958a10f0beb90b89ccadd8351cbe51d90b1 Mon Sep 17 00:00:00 2001
From: Roman Divacky <rdivacky@FreeBSD.org>
Date: Sat, 23 Jan 2010 11:09:33 +0000
Subject: Update LLVM to r94309.

---
 test/CodeGen/ARM/ctz.ll                            |  11 +++
 test/CodeGen/ARM/indirectbr.ll                     |   4 +
 test/CodeGen/ARM/vbits.ll                          |  12 +--
 test/CodeGen/CellSPU/call_indirect.ll              |   4 +-
 test/CodeGen/Generic/GC/frame_size.ll              |  14 ---
 test/CodeGen/MSP430/bit.ll                         |   1 -
 test/CodeGen/MSP430/setcc.ll                       |  13 ++-
 test/CodeGen/PIC16/globals.ll                      |   6 +-
 test/CodeGen/PowerPC/2008-12-12-EH.ll              |   1 -
 test/CodeGen/PowerPC/sections.ll                   |   2 +-
 test/CodeGen/PowerPC/stubs.ll                      |  22 +++++
 .../Thumb/2009-12-17-pre-regalloc-taildup.ll       |   2 +-
 .../Thumb/2010-01-15-local-alloc-spill-physical.ll |  20 ++++
 .../Thumb2/2010-01-06-TailDuplicateLabels.ll       |   2 +-
 test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll |  53 +++++++++++
 test/CodeGen/X86/2007-08-13-SpillerReuse.ll        | 102 ---------------------
 test/CodeGen/X86/2008-04-02-unnamedEH.ll           |  20 +---
 test/CodeGen/X86/2008-09-18-inline-asm-2.ll        |   4 +-
 test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll     |   2 +-
 test/CodeGen/X86/2009-02-04-sext-i64-gep.ll        |   2 +-
 test/CodeGen/X86/2009-09-10-SpillComments.ll       |   9 +-
 test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll   |  28 ++++++
 test/CodeGen/X86/2010-01-19-OptExtBug.ll           |  57 ++++++++++++
 test/CodeGen/X86/bigstructret2.ll                  |  12 +++
 test/CodeGen/X86/bss_pagealigned.ll                |   2 +-
 test/CodeGen/X86/full-lsr.ll                       |  12 ++-
 test/CodeGen/X86/global-sections.ll                |  20 +++-
 test/CodeGen/X86/i128-and-beyond.ll                |   2 +-
 test/CodeGen/X86/illegal-asm.ll                    |  34 -------
 test/CodeGen/X86/loop-hoist.ll                     |   2 +-
 test/CodeGen/X86/loop-strength-reduce4.ll          |   2 +-
 test/CodeGen/X86/neg-shl-add.ll                    |  17 ++++
 test/CodeGen/X86/pr3495-2.ll                       |   1 +
 test/CodeGen/X86/pr3495.ll                         |   6 +-
 test/CodeGen/X86/ptrtoint-constexpr.ll             |   2 +-
 test/CodeGen/X86/remat-mov-0.ll                    |  26 +++++-
 test/CodeGen/X86/remat-mov-1.ll                    |  40 --------
 test/CodeGen/X86/remat-scalar-zero.ll              |   2 +-
 test/CodeGen/X86/splat-scalar-load.ll              |  26 ------
 test/CodeGen/X86/stride-reuse.ll                   |   2 +-
 test/CodeGen/X86/subreg-to-reg-5.ll                |  35 -------
 test/CodeGen/X86/tail-opts.ll                      |   6 +-
 test/CodeGen/X86/unaligned-load.ll                 |   4 +-
 test/CodeGen/X86/xor.ll                            |  11 +++
 44 files changed, 336 insertions(+), 319 deletions(-)
 create mode 100644 test/CodeGen/ARM/ctz.ll
 delete mode 100644 test/CodeGen/Generic/GC/frame_size.ll
 create mode 100644 test/CodeGen/PowerPC/stubs.ll
 create mode 100644 test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll
 create mode 100644 test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
 delete mode 100644 test/CodeGen/X86/2007-08-13-SpillerReuse.ll
 create mode 100644 test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
 create mode 100644 test/CodeGen/X86/2010-01-19-OptExtBug.ll
 create mode 100644 test/CodeGen/X86/bigstructret2.ll
 delete mode 100644 test/CodeGen/X86/illegal-asm.ll
 create mode 100644 test/CodeGen/X86/neg-shl-add.ll
 delete mode 100644 test/CodeGen/X86/remat-mov-1.ll
 delete mode 100644 test/CodeGen/X86/subreg-to-reg-5.ll

(limited to 'test/CodeGen')

diff --git a/test/CodeGen/ARM/ctz.ll b/test/CodeGen/ARM/ctz.ll
new file mode 100644
index 0000000000000..1d2ced37b0356
--- /dev/null
+++ b/test/CodeGen/ARM/ctz.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
+
+declare i32 @llvm.cttz.i32(i32)
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: rbit
+; CHECK: clz
+  %tmp = call i32 @llvm.cttz.i32( i32 %a )
+  ret i32 %tmp
+}
diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
index cd16084dbdb3e..5135d036e24b6 100644
--- a/test/CodeGen/ARM/indirectbr.ll
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -12,6 +12,10 @@ define internal arm_apcscc i32 @foo(i32 %i) nounwind {
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
+; indirect branch gets duplicated here
+; ARM: bx
+; THUMB: mov pc, r1
+; THUMB2: mov pc, r1
   br i1 %1, label %bb3, label %bb2
 
 bb2:                                              ; preds = %entry, %bb3
diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll
index e1d23a17b4cbf..293d22938a76c 100644
--- a/test/CodeGen/ARM/vbits.ll
+++ b/test/CodeGen/ARM/vbits.ll
@@ -442,7 +442,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 
 define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vtsti8:
-;CHECK: vtst.i8
+;CHECK: vtst.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
 	%tmp3 = and <8 x i8> %tmp1, %tmp2
@@ -453,7 +453,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 
 define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vtsti16:
-;CHECK: vtst.i16
+;CHECK: vtst.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
 	%tmp3 = and <4 x i16> %tmp1, %tmp2
@@ -464,7 +464,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 
 define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vtsti32:
-;CHECK: vtst.i32
+;CHECK: vtst.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
 	%tmp3 = and <2 x i32> %tmp1, %tmp2
@@ -475,7 +475,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 
 define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vtstQi8:
-;CHECK: vtst.i8
+;CHECK: vtst.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
 	%tmp3 = and <16 x i8> %tmp1, %tmp2
@@ -486,7 +486,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 
 define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vtstQi16:
-;CHECK: vtst.i16
+;CHECK: vtst.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
 	%tmp3 = and <8 x i16> %tmp1, %tmp2
@@ -497,7 +497,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 
 define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: vtstQi32:
-;CHECK: vtst.i32
+;CHECK: vtst.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
 	%tmp3 = and <4 x i32> %tmp1, %tmp2
diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll
index f25d6b5810f5f..08dad74843e46 100644
--- a/test/CodeGen/CellSPU/call_indirect.ll
+++ b/test/CodeGen/CellSPU/call_indirect.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=cellspu > %t1.s
-; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
+; RUN: llc < %s -march=cellspu -asm-verbose=0 > %t1.s
+; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 > %t2.s
 ; RUN: grep bisl    %t1.s | count 7
 ; RUN: grep ila     %t1.s | count 1
 ; RUN: grep rotqby  %t1.s | count 5
diff --git a/test/CodeGen/Generic/GC/frame_size.ll b/test/CodeGen/Generic/GC/frame_size.ll
deleted file mode 100644
index 31783cdb97efd..0000000000000
--- a/test/CodeGen/Generic/GC/frame_size.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llc < %s -asm-verbose | grep {frame size} | grep -v 0x0
-
-declare void @llvm.gcroot(i8** %value, i8* %tag)
-declare void @g() gc "ocaml"
-
-define void @f(i8* %arg.0, void()* %arg.1) gc "ocaml" {
-entry:
-	%gcroot.0 = alloca i8*
-	call void @llvm.gcroot(i8** %gcroot.0, i8* null)
-	store i8* %arg.0, i8** %gcroot.0
-	call void @g()
-	call void %arg.1()
-	ret void
-}
diff --git a/test/CodeGen/MSP430/bit.ll b/test/CodeGen/MSP430/bit.ll
index 0dc21584e8cfd..cd664a17bf62f 100644
--- a/test/CodeGen/MSP430/bit.ll
+++ b/test/CodeGen/MSP430/bit.ll
@@ -1,5 +1,4 @@
 ; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
-; XFAIL: *
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll
index ecf066154fc38..9db51cce73cb0 100644
--- a/test/CodeGen/MSP430/setcc.ll
+++ b/test/CodeGen/MSP430/setcc.ll
@@ -1,5 +1,4 @@
 ; RUN: llc -march=msp430 < %s | FileCheck %s
-; XFAIL: *
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
@@ -32,7 +31,7 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwne:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	rra.w	r15
 ; CHECK-NEXT:	and.w	#1, r15
@@ -43,7 +42,7 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccweq:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	rra.w	r15
 ; CHECK-NEXT:	and.w	#1, r15
@@ -55,7 +54,7 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwugt:
-; CHECK:	cmp.w	r14, r15
+; CHECK:	cmp.w	r15, r14
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 ; CHECK-NEXT:	xor.w	#1, r15
@@ -66,7 +65,7 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwuge:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 
@@ -76,7 +75,7 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwult:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 ; CHECK-NEXT:	xor.w	#1, r15
@@ -87,7 +86,7 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwule:
-; CHECK:	cmp.w	r14, r15
+; CHECK:	cmp.w	r15, r14
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 
diff --git a/test/CodeGen/PIC16/globals.ll b/test/CodeGen/PIC16/globals.ll
index b8c9116777b49..432c291078d31 100644
--- a/test/CodeGen/PIC16/globals.ll
+++ b/test/CodeGen/PIC16/globals.ll
@@ -2,7 +2,8 @@
 
 @G1 = global i32 4712, section "Address=412"
 ; CHECK: @G1.412..user_section.#	IDATA	412
-; CHECK: @G1 dl 4712
+; CHECK: @G1
+; CHECK:     dl 4712
 
 @G2 = global i32 0, section "Address=412"
 ; CHECK: @G2.412..user_section.#	UDATA	412
@@ -10,6 +11,7 @@
 
 @G3 = addrspace(1) constant i32 4712, section "Address=412"
 ; CHECK: @G3.412..user_section.#	ROMDATA	412
-; CHECK: @G3 rom_dl 4712
+; CHECK: @G3
+; CHECK:     rom_dl 4712
 
 
diff --git a/test/CodeGen/PowerPC/2008-12-12-EH.ll b/test/CodeGen/PowerPC/2008-12-12-EH.ll
index b56c22abc6ddd..2315e36ff465c 100644
--- a/test/CodeGen/PowerPC/2008-12-12-EH.ll
+++ b/test/CodeGen/PowerPC/2008-12-12-EH.ll
@@ -1,4 +1,3 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | grep ^.L_Z1fv.eh
 ; RUN: llc < %s  -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh
 
 define void @_Z1fv() {
diff --git a/test/CodeGen/PowerPC/sections.ll b/test/CodeGen/PowerPC/sections.ll
index 1af370935e231..0ff4a89ff3794 100644
--- a/test/CodeGen/PowerPC/sections.ll
+++ b/test/CodeGen/PowerPC/sections.ll
@@ -4,5 +4,5 @@
 @A = global i32 0
 
 ; CHECK:  .section  .bss,"aw",@nobits
-; CHECK:  .global A
+; CHECK:  .globl A
 
diff --git a/test/CodeGen/PowerPC/stubs.ll b/test/CodeGen/PowerPC/stubs.ll
new file mode 100644
index 0000000000000..4889263b4c4e9
--- /dev/null
+++ b/test/CodeGen/PowerPC/stubs.ll
@@ -0,0 +1,22 @@
+; RUN: llc %s -o - -mtriple=powerpc-apple-darwin8 | FileCheck %s
+define ppc_fp128 @test1(i64 %X) nounwind readnone {
+entry:
+  %0 = sitofp i64 %X to ppc_fp128
+  ret ppc_fp128 %0
+}
+
+; CHECK: _test1:
+; CHECK: bl ___floatditf$stub
+; CHECK: 	.section	__TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
+; CHECK: ___floatditf$stub:
+; CHECK: 	.indirect_symbol ___floatditf
+; CHECK: 	lis r11,ha16(___floatditf$lazy_ptr)
+; CHECK: 	lwzu r12,lo16(___floatditf$lazy_ptr)(r11)
+; CHECK: 	mtctr r12
+; CHECK: 	bctr
+; CHECK: 	.section	__DATA,__la_symbol_ptr,lazy_symbol_pointers
+; CHECK: ___floatditf$lazy_ptr:
+; CHECK: 	.indirect_symbol ___floatditf
+; CHECK: 	.long dyld_stub_binding_helper
+
+
diff --git a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
index 3401915eacbbb..2a5d9d6857021 100644
--- a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
+++ b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O3 -pre-regalloc-taildup < %s | FileCheck %s
+; RUN: llc -O3 < %s | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 target triple = "thumbv7-apple-darwin10"
 
diff --git a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll
new file mode 100644
index 0000000000000..d676369020acd
--- /dev/null
+++ b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s
+
+target triple = "thumbv6-apple-darwin10"
+
+@fred = internal global i32 0              ; <i32*> [#uses=1]
+
+define arm_apcscc void @foo() nounwind {
+entry:
+; CHECK: str r0, [sp]
+  %0 = call arm_apcscc  i32 (...)* @bar() nounwind ; <i32> [#uses=1]
+; CHECK: blx _bar
+; CHECK: ldr r1, [sp]
+  store i32 %0, i32* @fred, align 4
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+declare arm_apcscc i32 @bar(...)
diff --git a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
index 6a05df111472f..07a35277b81be 100644
--- a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
+++ b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
@@ -1,4 +1,4 @@
-; RUN: llc -relocation-model=pic -pre-regalloc-taildup < %s | grep {:$} | sort | uniq -d | count 0
+; RUN: llc -relocation-model=pic < %s | grep {:$} | sort | uniq -d | count 0
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 target triple = "thumbv7-apple-darwin10"
 
diff --git a/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
new file mode 100644
index 0000000000000..41682c1054d11
--- /dev/null
+++ b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
@@ -0,0 +1,53 @@
+; RUN: llc -O3 -relocation-model=pic -mcpu=cortex-a8 -mattr=+thumb2 < %s
+;
+; This test creates a predicated t2ADDri instruction that is then turned into a t2MOVgpr2gpr instr.
+; Test that that the predicate operands are removed properly.
+;
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10"
+
+declare arm_apcscc void @etoe53(i16* nocapture, i16* nocapture) nounwind
+
+define arm_apcscc void @earith(double* nocapture %value, i32 %icode, double* nocapture %r1, double* nocapture %r2) nounwind {
+entry:
+  %v = alloca [6 x i16], align 4                  ; <[6 x i16]*> [#uses=1]
+  br i1 undef, label %bb2.i, label %bb5
+
+bb2.i:                                            ; preds = %entry
+  %0 = bitcast double* %value to i16*             ; <i16*> [#uses=1]
+  call arm_apcscc  void @etoe53(i16* null, i16* %0) nounwind
+  ret void
+
+bb5:                                              ; preds = %entry
+  switch i32 %icode, label %bb10 [
+    i32 57, label %bb14
+    i32 58, label %bb18
+    i32 67, label %bb22
+    i32 76, label %bb26
+    i32 77, label %bb35
+  ]
+
+bb10:                                             ; preds = %bb5
+  br label %bb46
+
+bb14:                                             ; preds = %bb5
+  unreachable
+
+bb18:                                             ; preds = %bb5
+  unreachable
+
+bb22:                                             ; preds = %bb5
+  unreachable
+
+bb26:                                             ; preds = %bb5
+  br label %bb46
+
+bb35:                                             ; preds = %bb5
+  unreachable
+
+bb46:                                             ; preds = %bb26, %bb10
+  %1 = bitcast double* %value to i16*             ; <i16*> [#uses=1]
+  %v47 = getelementptr inbounds [6 x i16]* %v, i32 0, i32 0 ; <i16*> [#uses=1]
+  call arm_apcscc  void @etoe53(i16* %v47, i16* %1) nounwind
+  ret void
+}
diff --git a/test/CodeGen/X86/2007-08-13-SpillerReuse.ll b/test/CodeGen/X86/2007-08-13-SpillerReuse.ll
deleted file mode 100644
index d6ea5109d1fb6..0000000000000
--- a/test/CodeGen/X86/2007-08-13-SpillerReuse.ll
+++ /dev/null
@@ -1,102 +0,0 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin | grep "48(%esp)" | count 5
-
-	%struct..0anon = type { i32 }
-	%struct.rtvec_def = type { i32, [1 x %struct..0anon] }
-	%struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
-@rtx_format = external global [116 x i8*]		; <[116 x i8*]*> [#uses=1]
-@rtx_length = external global [117 x i32]		; <[117 x i32]*> [#uses=1]
-
-declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*, i32)
-
-define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) {
-entry:
-	%tmp2 = icmp eq %struct.rtx_def* %x, null		; <i1> [#uses=1]
-	br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next
-
-cond_next:		; preds = %entry
-	%tmp6 = getelementptr %struct.rtx_def* %x, i32 0, i32 0		; <i16*> [#uses=1]
-	%tmp7 = load i16* %tmp6		; <i16> [#uses=2]
-	%tmp78 = zext i16 %tmp7 to i32		; <i32> [#uses=2]
-	%tmp10 = icmp eq i16 %tmp7, 54		; <i1> [#uses=1]
-	br i1 %tmp10, label %cond_true13, label %cond_next32
-
-cond_true13:		; preds = %cond_next
-	%tmp15 = getelementptr %struct.rtx_def* %x, i32 0, i32 3		; <[1 x %struct..0anon]*> [#uses=1]
-	%tmp1718 = bitcast [1 x %struct..0anon]* %tmp15 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp19 = load %struct.rtx_def** %tmp1718		; <%struct.rtx_def*> [#uses=1]
-	%tmp20 = getelementptr %struct.rtx_def* %tmp19, i32 0, i32 0		; <i16*> [#uses=1]
-	%tmp21 = load i16* %tmp20		; <i16> [#uses=1]
-	%tmp22 = icmp eq i16 %tmp21, 57		; <i1> [#uses=1]
-	br i1 %tmp22, label %cond_true25, label %cond_next32
-
-cond_true25:		; preds = %cond_true13
-	%tmp29 = tail call %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 )		; <%struct.rtx_def*> [#uses=1]
-	ret %struct.rtx_def* %tmp29
-
-cond_next32:		; preds = %cond_true13, %cond_next
-	%tmp34 = getelementptr [116 x i8*]* @rtx_format, i32 0, i32 %tmp78		; <i8**> [#uses=1]
-	%tmp35 = load i8** %tmp34, align 4		; <i8*> [#uses=1]
-	%tmp37 = getelementptr [117 x i32]* @rtx_length, i32 0, i32 %tmp78		; <i32*> [#uses=1]
-	%tmp38 = load i32* %tmp37, align 4		; <i32> [#uses=1]
-	%i.011 = add i32 %tmp38, -1		; <i32> [#uses=2]
-	%tmp12513 = icmp sgt i32 %i.011, -1		; <i1> [#uses=1]
-	br i1 %tmp12513, label %bb, label %UnifiedReturnBlock
-
-bb:		; preds = %bb123, %cond_next32
-	%indvar = phi i32 [ %indvar.next26, %bb123 ], [ 0, %cond_next32 ]		; <i32> [#uses=2]
-	%i.01.0 = sub i32 %i.011, %indvar		; <i32> [#uses=5]
-	%tmp42 = getelementptr i8* %tmp35, i32 %i.01.0		; <i8*> [#uses=2]
-	%tmp43 = load i8* %tmp42		; <i8> [#uses=1]
-	switch i8 %tmp43, label %bb123 [
-		 i8 101, label %cond_true47
-		 i8 69, label %bb105.preheader
-	]
-
-cond_true47:		; preds = %bb
-	%tmp52 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
-	%tmp5354 = bitcast %struct..0anon* %tmp52 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp55 = load %struct.rtx_def** %tmp5354		; <%struct.rtx_def*> [#uses=1]
-	%tmp58 = tail call  %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn )		; <%struct.rtx_def*> [#uses=1]
-	%tmp62 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0		; <i32*> [#uses=1]
-	%tmp58.c = ptrtoint %struct.rtx_def* %tmp58 to i32		; <i32> [#uses=1]
-	store i32 %tmp58.c, i32* %tmp62
-	%tmp6816 = load i8* %tmp42		; <i8> [#uses=1]
-	%tmp6917 = icmp eq i8 %tmp6816, 69		; <i1> [#uses=1]
-	br i1 %tmp6917, label %bb105.preheader, label %bb123
-
-bb105.preheader:		; preds = %cond_true47, %bb
-	%tmp11020 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
-	%tmp11111221 = bitcast %struct..0anon* %tmp11020 to %struct.rtvec_def**		; <%struct.rtvec_def**> [#uses=3]
-	%tmp11322 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
-	%tmp11423 = getelementptr %struct.rtvec_def* %tmp11322, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp11524 = load i32* %tmp11423		; <i32> [#uses=1]
-	%tmp11625 = icmp eq i32 %tmp11524, 0		; <i1> [#uses=1]
-	br i1 %tmp11625, label %bb123, label %bb73
-
-bb73:		; preds = %bb73, %bb105.preheader
-	%j.019 = phi i32 [ %tmp104, %bb73 ], [ 0, %bb105.preheader ]		; <i32> [#uses=3]
-	%tmp81 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=2]
-	%tmp92 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019		; <%struct..0anon*> [#uses=1]
-	%tmp9394 = bitcast %struct..0anon* %tmp92 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp95 = load %struct.rtx_def** %tmp9394		; <%struct.rtx_def*> [#uses=1]
-	%tmp98 = tail call  %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn )		; <%struct.rtx_def*> [#uses=1]
-	%tmp101 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0		; <i32*> [#uses=1]
-	%tmp98.c = ptrtoint %struct.rtx_def* %tmp98 to i32		; <i32> [#uses=1]
-	store i32 %tmp98.c, i32* %tmp101
-	%tmp104 = add i32 %j.019, 1		; <i32> [#uses=2]
-	%tmp113 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
-	%tmp114 = getelementptr %struct.rtvec_def* %tmp113, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp115 = load i32* %tmp114		; <i32> [#uses=1]
-	%tmp116 = icmp ult i32 %tmp104, %tmp115		; <i1> [#uses=1]
-	br i1 %tmp116, label %bb73, label %bb123
-
-bb123:		; preds = %bb73, %bb105.preheader, %cond_true47, %bb
-	%i.0 = add i32 %i.01.0, -1		; <i32> [#uses=1]
-	%tmp125 = icmp sgt i32 %i.0, -1		; <i1> [#uses=1]
-	%indvar.next26 = add i32 %indvar, 1		; <i32> [#uses=1]
-	br i1 %tmp125, label %bb, label %UnifiedReturnBlock
-
-UnifiedReturnBlock:		; preds = %bb123, %cond_next32, %entry
-	%UnifiedRetVal = phi %struct.rtx_def* [ null, %entry ], [ %x, %cond_next32 ], [ %x, %bb123 ]		; <%struct.rtx_def*> [#uses=1]
-	ret %struct.rtx_def* %UnifiedRetVal
-}
diff --git a/test/CodeGen/X86/2008-04-02-unnamedEH.ll b/test/CodeGen/X86/2008-04-02-unnamedEH.ll
index a9f368b6eaa5b..27bbbaa2962da 100644
--- a/test/CodeGen/X86/2008-04-02-unnamedEH.ll
+++ b/test/CodeGen/X86/2008-04-02-unnamedEH.ll
@@ -1,26 +1,16 @@
-; RUN: llc < %s | grep unnamed_1.eh
+; RUN: llc < %s | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin8"
 
 define void @_Z3bazv() {
-	call i32 @0( )		; <i32>:1 [#uses=0]
-	br label %2
-; <label>:2		; preds = %0
+	call void @0( )		; <i32>:1 [#uses=0]
 	ret void
 }
 
-define internal i32 @""() {
-	alloca i32		; <i32*>:1 [#uses=2]
-	alloca i32		; <i32*>:2 [#uses=2]
-	bitcast i32 0 to i32		; <i32>:3 [#uses=0]
+define internal void @""() {
 	call i32 @_Z3barv( )		; <i32>:4 [#uses=1]
-	store i32 %4, i32* %2, align 4
-	load i32* %2, align 4		; <i32>:5 [#uses=1]
-	store i32 %5, i32* %1, align 4
-	br label %6
-; <label>:6		; preds = %0
-	load i32* %1		; <i32>:7 [#uses=1]
-	ret i32 %7
+	ret void
 }
+; CHECK: unnamed_1.eh
 
 declare i32 @_Z3barv()
diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
index f5bd307139d60..e3b6fdf5113a2 100644
--- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
+++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86 | grep "#%ebp %edi %esi 8(%edx) %eax (%ebx)"
-; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %edx %ebp 8(%ebx) %eax (%esi)"
+; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)"
+; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
 ; The 1st, 2nd, 3rd and 5th registers above must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
 ; operand.  There are many combinations that work; this is what llc puts out now.
diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
index 13a9080c1401f..a6cabc4fd3318 100644
--- a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
+++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -asm-verbose=0 | FileCheck %s
 ; PR3149
 ; Make sure the copy after inline asm is not coalesced away.
 
diff --git a/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
index 6ba046a80c228..4880f626d5dac 100644
--- a/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
+++ b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | grep { - 92}
+; RUN: llc < %s | grep p-92
 ; PR3481
 ; The offset should print as -92, not +17179869092
 
diff --git a/test/CodeGen/X86/2009-09-10-SpillComments.ll b/test/CodeGen/X86/2009-09-10-SpillComments.ll
index 1dd9990e71a5b..f9ca861c558ac 100644
--- a/test/CodeGen/X86/2009-09-10-SpillComments.ll
+++ b/test/CodeGen/X86/2009-09-10-SpillComments.ll
@@ -1,5 +1,11 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s
 
+; This test shouldn't require spills.
+
+; CHECK: subq  $8, %rsp
+; CHECK-NOT: $rsp
+; CHECK: addq  $8, %rsp
+
 	%struct..0anon = type { i32 }
 	%struct.rtvec_def = type { i32, [1 x %struct..0anon] }
 	%struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
@@ -10,9 +16,6 @@ declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*
 
 define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) {
 entry:
-; CHECK: Spill
-; CHECK: Folded Spill
-; CHECK: Reload
 	%tmp2 = icmp eq %struct.rtx_def* %x, null		; <i1> [#uses=1]
 	br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next
 
diff --git a/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
new file mode 100644
index 0000000000000..5d96e4a192f39
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86-64
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @numvec_(i32* noalias %ncelet, i32* noalias %ncel, i32* noalias %nfac, i32* noalias %nfabor, i32* noalias %lregis, i32* noalias %irveci, i32* noalias %irvecb, [0 x [2 x i32]]* noalias %ifacel, [0 x i32]* noalias %ifabor, [0 x i32]* noalias %inumfi, [0 x i32]* noalias %inumfb, [1 x i32]* noalias %iworkf, [0 x i32]* noalias %ismbs) {
+"file bug754399.f90, line 1, bb1":
+	%r1037 = bitcast <2 x double> zeroinitializer to <4 x i32>		; <<4 x i32>> [#uses=1]
+	br label %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164"
+
+"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164":		; preds = %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164", %"file bug754399.f90, line 1, bb1"
+	%tmp641 = add i64 0, 48		; <i64> [#uses=1]
+	%tmp641642 = inttoptr i64 %tmp641 to <4 x i32>*		; <<4 x i32>*> [#uses=1]
+	%r1258 = load <4 x i32>* %tmp641642, align 4		; <<4 x i32>> [#uses=2]
+	%r1295 = extractelement <4 x i32> %r1258, i32 3		; <i32> [#uses=1]
+	%r1296 = sext i32 %r1295 to i64		; <i64> [#uses=1]
+	%r1297 = add i64 %r1296, -1		; <i64> [#uses=1]
+	%r1298183 = getelementptr [0 x i32]* %ismbs, i64 0, i64 %r1297		; <i32*> [#uses=1]
+	%r1298184 = load i32* %r1298183, align 4		; <i32> [#uses=1]
+	%r1301 = extractelement <4 x i32> %r1037, i32 3		; <i32> [#uses=1]
+	%r1302 = mul i32 %r1298184, %r1301		; <i32> [#uses=1]
+	%r1306 = insertelement <4 x i32> zeroinitializer, i32 %r1302, i32 3		; <<4 x i32>> [#uses=1]
+	%r1321 = add <4 x i32> %r1306, %r1258		; <<4 x i32>> [#uses=1]
+	%tmp643 = add i64 0, 48		; <i64> [#uses=1]
+	%tmp643644 = inttoptr i64 %tmp643 to <4 x i32>*		; <<4 x i32>*> [#uses=1]
+	store <4 x i32> %r1321, <4 x i32>* %tmp643644, align 4
+	br label %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164"
+}
diff --git a/test/CodeGen/X86/2010-01-19-OptExtBug.ll b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
new file mode 100644
index 0000000000000..cd8960b9ed7b4
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -relocation-model=pic -disable-fp-elim -stats |& not grep ext-opt
+
+define fastcc i8* @S_scan_str(i8* %start, i32 %keep_quoted, i32 %keep_delims) nounwind ssp {
+entry:
+  switch i8 undef, label %bb6 [
+    i8 9, label %bb5
+    i8 32, label %bb5
+    i8 10, label %bb5
+    i8 13, label %bb5
+    i8 12, label %bb5
+  ]
+
+bb5:                                              ; preds = %entry, %entry, %entry, %entry, %entry
+  br label %bb6
+
+bb6:                                              ; preds = %bb5, %entry
+  br i1 undef, label %bb7, label %bb9
+
+bb7:                                              ; preds = %bb6
+  unreachable
+
+bb9:                                              ; preds = %bb6
+  %0 = load i8* undef, align 1                    ; <i8> [#uses=3]
+  br i1 undef, label %bb12, label %bb10
+
+bb10:                                             ; preds = %bb9
+  br i1 undef, label %bb12, label %bb11
+
+bb11:                                             ; preds = %bb10
+  unreachable
+
+bb12:                                             ; preds = %bb10, %bb9
+  br i1 undef, label %bb13, label %bb14
+
+bb13:                                             ; preds = %bb12
+  store i8 %0, i8* undef, align 1
+  %1 = zext i8 %0 to i32                          ; <i32> [#uses=1]
+  br label %bb18
+
+bb14:                                             ; preds = %bb12
+  br label %bb18
+
+bb18:                                             ; preds = %bb14, %bb13
+  %termcode.0 = phi i32 [ %1, %bb13 ], [ undef, %bb14 ] ; <i32> [#uses=2]
+  %2 = icmp eq i8 %0, 0                           ; <i1> [#uses=1]
+  br i1 %2, label %bb21, label %bb19
+
+bb19:                                             ; preds = %bb18
+  br i1 undef, label %bb21, label %bb20
+
+bb20:                                             ; preds = %bb19
+  br label %bb21
+
+bb21:                                             ; preds = %bb20, %bb19, %bb18
+  %termcode.1 = phi i32 [ %termcode.0, %bb18 ], [ %termcode.0, %bb19 ], [ undef, %bb20 ] ; <i32> [#uses=0]
+  unreachable
+}
diff --git a/test/CodeGen/X86/bigstructret2.ll b/test/CodeGen/X86/bigstructret2.ll
new file mode 100644
index 0000000000000..46e0fd2176465
--- /dev/null
+++ b/test/CodeGen/X86/bigstructret2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -o %t
+
+%0 = type { i64, i64 }
+
+declare fastcc %0 @ReturnBigStruct() nounwind readnone
+
+define void @test(%0* %p) {
+  %1 = call fastcc %0 @ReturnBigStruct()
+  store %0 %1, %0* %p
+  ret void
+}
+
diff --git a/test/CodeGen/X86/bss_pagealigned.ll b/test/CodeGen/X86/bss_pagealigned.ll
index 27c536144b4b8..da95aca110da2 100644
--- a/test/CodeGen/X86/bss_pagealigned.ll
+++ b/test/CodeGen/X86/bss_pagealigned.ll
@@ -1,4 +1,4 @@
-; RUN: llc --code-model=kernel -march=x86-64 <%s | FileCheck %s
+; RUN: llc --code-model=kernel -march=x86-64 <%s -asm-verbose=0 | FileCheck %s
 ; PR4933
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/test/CodeGen/X86/full-lsr.ll b/test/CodeGen/X86/full-lsr.ll
index 68575bc401d75..3bd58b65be498 100644
--- a/test/CodeGen/X86/full-lsr.ll
+++ b/test/CodeGen/X86/full-lsr.ll
@@ -1,6 +1,12 @@
-; RUN: llc < %s -march=x86 -enable-full-lsr >%t
-; RUN: grep {addl	\\\$4,} %t | count 3
-; RUN: not grep {,%} %t
+; RUN: llc < %s -march=x86 >%t
+
+; TODO: Enhance full lsr mode to get this:
+; RUNX: grep {addl	\\\$4,} %t | count 3
+; RUNX: not grep {,%} %t
+
+; For now, it should find this, which is still pretty good:
+; RUN: not grep {addl	\\\$4,} %t
+; RUN: grep {,%} %t | count 6
 
 define void @foo(float* nocapture %A, float* nocapture %B, float* nocapture %C, i32 %N) nounwind {
 entry:
diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll
index 38948a7dc9124..1a7b5777ae8ac 100644
--- a/test/CodeGen/X86/global-sections.ll
+++ b/test/CodeGen/X86/global-sections.ll
@@ -6,7 +6,6 @@
 @G1 = common global i32 0
 
 ; LINUX: .type   G1,@object
-; LINUX: .section .gnu.linkonce.b.G1,"aw",@nobits
 ; LINUX: .comm  G1,4,4
 
 ; DARWIN: .comm	_G1,4,2
@@ -76,14 +75,14 @@
 ; LINUX:   .section	.gnu.linkonce.r.G6,"a",@progbits
 ; LINUX:   .weak	G6
 ; LINUX: G6:
-; LINUX:   .ascii	"\001"
+; LINUX:   .byte	1
 ; LINUX:   .size	G6, 1
 
 ; DARWIN:  .section __TEXT,__const_coal,coalesced
 ; DARWIN:  .globl _G6
 ; DARWIN:  .weak_definition _G6
 ; DARWIN:_G6:
-; DARWIN:  .ascii "\001"
+; DARWIN:  .byte 1
 
 
 @G7 = constant [10 x i8] c"abcdefghi\00"
@@ -120,4 +119,19 @@
 ; LINUX:G9
 
 
+@G10 = weak global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=0]
+
+
+; DARWIN: 	.section	__DATA,__datacoal_nt,coalesced
+; DARWIN: .globl _G10
+; DARWIN:	.weak_definition _G10
+; DARWIN:	.align	5
+; DARWIN: _G10:
+; DARWIN:	.space	400
+
+; LINUX:	.bss
+; LINUX:	.weak	G10
+; LINUX:	.align	32
+; LINUX: G10:
+; LINUX:	.zero	400
 
diff --git a/test/CodeGen/X86/i128-and-beyond.ll b/test/CodeGen/X86/i128-and-beyond.ll
index 907a6b8de2fe2..b741681ac17e4 100644
--- a/test/CodeGen/X86/i128-and-beyond.ll
+++ b/test/CodeGen/X86/i128-and-beyond.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep 18446744073709551615 | count 14
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep -- -1 | count 14
 
 ; These static initializers are too big to hand off to assemblers
 ; as monolithic blobs.
diff --git a/test/CodeGen/X86/illegal-asm.ll b/test/CodeGen/X86/illegal-asm.ll
deleted file mode 100644
index 43128dcf010b6..0000000000000
--- a/test/CodeGen/X86/illegal-asm.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim
-; RUN: llc < %s -mtriple=i386-linux        -disable-fp-elim
-; XFAIL: *
-; Expected to run out of registers during allocation.
-; PR3864
-; rdar://6251720
-
-	%struct.CABACContext = type { i32, i32, i8* }
-	%struct.H264Context = type { %struct.CABACContext, [460 x i8] }
-@coeff_abs_level_m1_offset = common global [6 x i32] zeroinitializer		; <[6 x i32]*> [#uses=1]
-@coeff_abs_level1_ctx = common global [8 x i8] zeroinitializer		; <[8 x i8]*> [#uses=1]
-
-define i32 @decode_cabac_residual(%struct.H264Context* %h, i32 %cat) nounwind {
-entry:
-	%0 = getelementptr [6 x i32]* @coeff_abs_level_m1_offset, i32 0, i32 %cat		; <i32*> [#uses=1]
-	%1 = load i32* %0, align 4		; <i32> [#uses=1]
-	%2 = load i8* getelementptr ([8 x i8]* @coeff_abs_level1_ctx, i32 0, i32 0), align 1		; <i8> [#uses=1]
-	%3 = zext i8 %2 to i32		; <i32> [#uses=1]
-	%.sum = add i32 %3, %1		; <i32> [#uses=1]
-	%4 = getelementptr %struct.H264Context* %h, i32 0, i32 1, i32 %.sum		; <i8*> [#uses=2]
-	%5 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 0		; <i32*> [#uses=2]
-	%6 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 1		; <i32*> [#uses=2]
-	%7 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 2		; <i8**> [#uses=2]
-	%8 = load i32* %5, align 4		; <i32> [#uses=1]
-	%9 = load i32* %6, align 4		; <i32> [#uses=1]
-	%10 = load i8* %4, align 4		; <i8> [#uses=1]
-	%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&{di},=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %7, i8* %4, i32 %8, i32 %9, i8** %7, i8 %10) nounwind		; <{ i32, i32, i32, i32 }> [#uses=3]
-	%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0		; <i32> [#uses=1]
-	%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1		; <i32> [#uses=1]
-	store i32 %asmresult1, i32* %5
-	%asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2		; <i32> [#uses=1]
-	store i32 %asmresult2, i32* %6
-	ret i32 %asmresult
-}
diff --git a/test/CodeGen/X86/loop-hoist.ll b/test/CodeGen/X86/loop-hoist.ll
index b52066dac62eb..b9008e5e3022d 100644
--- a/test/CodeGen/X86/loop-hoist.ll
+++ b/test/CodeGen/X86/loop-hoist.ll
@@ -4,7 +4,7 @@
 
 ; CHECK: _foo:
 ; CHECK:    L_Arr$non_lazy_ptr
-; CHECK: LBB1_1:	## %cond_true
+; CHECK: LBB1_1:
 
 @Arr = external global [0 x i32]		; <[0 x i32]*> [#uses=1]
 
diff --git a/test/CodeGen/X86/loop-strength-reduce4.ll b/test/CodeGen/X86/loop-strength-reduce4.ll
index 87b606f558a45..07e46eca75e9f 100644
--- a/test/CodeGen/X86/loop-strength-reduce4.ll
+++ b/test/CodeGen/X86/loop-strength-reduce4.ll
@@ -4,7 +4,7 @@
 @state = external global [0 x i32]		; <[0 x i32]*> [#uses=4]
 @S = external global [0 x i32]		; <[0 x i32]*> [#uses=4]
 
-define i32 @foo() {
+define i32 @foo() nounwind {
 entry:
 	br label %bb
 
diff --git a/test/CodeGen/X86/neg-shl-add.ll b/test/CodeGen/X86/neg-shl-add.ll
new file mode 100644
index 0000000000000..7aebc383ddebe
--- /dev/null
+++ b/test/CodeGen/X86/neg-shl-add.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=x86-64 < %s | not grep negq
+
+; These sequences don't need neg instructions; they can be done with
+; a single shift and sub each.
+
+define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind {
+  %a = sub i64 0, %y
+  %b = shl i64 %a, %n
+  %c = add i64 %b, %x
+  ret i64 %c
+}
+define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind {
+  %a = sub i64 0, %y
+  %b = shl i64 %a, %n
+  %c = add i64 %x, %b
+  ret i64 %c
+}
diff --git a/test/CodeGen/X86/pr3495-2.ll b/test/CodeGen/X86/pr3495-2.ll
index 1372a1522bd42..71aa5a04881e8 100644
--- a/test/CodeGen/X86/pr3495-2.ll
+++ b/test/CodeGen/X86/pr3495-2.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited}
 
+target datalayout = "e-p:32:32:32"
 target triple = "i386-apple-darwin9.6"
 	%struct.constraintVCGType = type { i32, i32, i32, i32 }
 	%struct.nodeVCGType = type { %struct.constraintVCGType*, i32, i32, i32, %struct.constraintVCGType*, i32, i32, i32 }
diff --git a/test/CodeGen/X86/pr3495.ll b/test/CodeGen/X86/pr3495.ll
index 4b62bf40da4bf..1795970d353ee 100644
--- a/test/CodeGen/X86/pr3495.ll
+++ b/test/CodeGen/X86/pr3495.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=x86 -stats |& grep {Number of reloads omited} | grep 1
-; RUN: llc < %s -march=x86 -stats |& grep {Number of available reloads turned into copies} | grep 1
-; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 40
+; RUN: llc < %s -march=x86 -stats |& grep {Number of loads added} | grep 2
+; RUN: llc < %s -march=x86 -stats |& grep {Number of register spills} | grep 1
+; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 38
 ; PR3495
 ; The loop reversal kicks in once here, resulting in one fewer instruction.
 
diff --git a/test/CodeGen/X86/ptrtoint-constexpr.ll b/test/CodeGen/X86/ptrtoint-constexpr.ll
index 72a428ea32083..7e33e7916c89c 100644
--- a/test/CodeGen/X86/ptrtoint-constexpr.ll
+++ b/test/CodeGen/X86/ptrtoint-constexpr.ll
@@ -3,6 +3,6 @@
 
 ; CHECK:	.globl r
 ; CHECK: r:
-; CHECK: .quad	((r) & 4294967295)
+; CHECK: .quad	r&4294967295
 
 @r = global %union.x { i64 ptrtoint (%union.x* @r to i64) }, align 4
diff --git a/test/CodeGen/X86/remat-mov-0.ll b/test/CodeGen/X86/remat-mov-0.ll
index c4f768ca529bb..5fb445c9357c8 100644
--- a/test/CodeGen/X86/remat-mov-0.ll
+++ b/test/CodeGen/X86/remat-mov-0.ll
@@ -1,13 +1,33 @@
-; RUN: llc < %s -march=x86-64 | grep {xorl	%edi, %edi} | count 4
+; RUN: llc < %s -march=x86-64 | FileCheck %s
 
 ; CodeGen should remat the zero instead of spilling it.
 
 declare void @foo(i64 %p)
 
+; CHECK: bar:
+; CHECK: xorl %edi, %edi
+; CHECK: xorl %edi, %edi
 define void @bar() nounwind {
   call void @foo(i64 0)
   call void @foo(i64 0)
-  call void @foo(i64 0)
-  call void @foo(i64 0)
   ret void
 }
+
+; CHECK: bat:
+; CHECK: movq $-1, %rdi
+; CHECK: movq $-1, %rdi
+define void @bat() nounwind {
+  call void @foo(i64 -1)
+  call void @foo(i64 -1)
+  ret void
+}
+
+; CHECK: bau:
+; CHECK: movl $1, %edi
+; CHECK: movl $1, %edi
+define void @bau() nounwind {
+  call void @foo(i64 1)
+  call void @foo(i64 1)
+  ret void
+}
+
diff --git a/test/CodeGen/X86/remat-mov-1.ll b/test/CodeGen/X86/remat-mov-1.ll
deleted file mode 100644
index d71b7a5b910a3..0000000000000
--- a/test/CodeGen/X86/remat-mov-1.ll
+++ /dev/null
@@ -1,40 +0,0 @@
-; RUN: llc < %s -march=x86 | grep -- -1 | grep mov | count 2
-
-	%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
-	%struct.ImgT = type { i8, i8*, i8*, %struct.FILE*, i32, i32, i32, i32, i8*, double*, float*, float*, float*, i32*, double, double, i32*, double*, i32*, i32* }
-	%struct._CompT = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, i8, %struct._PixT*, %struct._CompT*, i8, %struct._CompT* }
-	%struct._PixT = type { i32, i32, %struct._PixT* }
-	%struct.__sFILEX = type opaque
-	%struct.__sbuf = type { i8*, i32 }
-
-declare fastcc void @MergeComponents(%struct._CompT*, %struct._CompT*, %struct._CompT*, %struct._CompT**, %struct.ImgT*) nounwind 
-
-define fastcc void @MergeToLeft(%struct._CompT* %comp, %struct._CompT** %head, %struct.ImgT* %img) nounwind  {
-entry:
-	br label %bb208
-
-bb105:		; preds = %bb200
-	br i1 false, label %bb197, label %bb149
-
-bb149:		; preds = %bb105
-	%tmp151 = getelementptr %struct._CompT* %comp, i32 0, i32 0		; <i32*> [#uses=1]
-	br label %bb193
-
-bb193:		; preds = %bb184, %bb149
-	%tmp196 = load i32* %tmp151, align 4		; <i32> [#uses=1]
-	br label %bb197
-
-bb197:		; preds = %bb193, %bb105
-	%last_comp.0 = phi i32 [ %tmp196, %bb193 ], [ 0, %bb105 ]		; <i32> [#uses=0]
-	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
-	br label %bb200
-
-bb200:		; preds = %bb208, %bb197
-	%indvar = phi i32 [ 0, %bb208 ], [ %indvar.next, %bb197 ]		; <i32> [#uses=2]
-	%xm.0 = sub i32 %indvar, 0		; <i32> [#uses=1]
-	%tmp202 = icmp slt i32 %xm.0, 1		; <i1> [#uses=1]
-	br i1 %tmp202, label %bb105, label %bb208
-
-bb208:		; preds = %bb200, %entry
-	br label %bb200
-}
diff --git a/test/CodeGen/X86/remat-scalar-zero.ll b/test/CodeGen/X86/remat-scalar-zero.ll
index 790ae83c2b2bc..2da96aba5531d 100644
--- a/test/CodeGen/X86/remat-scalar-zero.ll
+++ b/test/CodeGen/X86/remat-scalar-zero.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu > %t
 ; RUN: not grep xor %t
 ; RUN: not grep movap %t
-; RUN: grep {\\.zero} %t
+; RUN: grep {\\.quad.*0} %t
 
 ; Remat should be able to fold the zero constant into the div instructions
 ; as a constant-pool load.
diff --git a/test/CodeGen/X86/splat-scalar-load.ll b/test/CodeGen/X86/splat-scalar-load.ll
index 32d3ab661d18e..2b13029896eed 100644
--- a/test/CodeGen/X86/splat-scalar-load.ll
+++ b/test/CodeGen/X86/splat-scalar-load.ll
@@ -1,21 +1,6 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | FileCheck %s
 ; rdar://7434544
 
-define <2 x i64> @t1() nounwind ssp {
-entry:
-; CHECK: t1:
-; CHECK: pshufd	$0, (%esp), %xmm0
-  %array = alloca [8 x float], align 16
-  %arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 0
-  %tmp2 = load float* %arrayidx
-  %vecinit = insertelement <4 x float> undef, float %tmp2, i32 0
-  %vecinit5 = insertelement <4 x float> %vecinit, float %tmp2, i32 1
-  %vecinit7 = insertelement <4 x float> %vecinit5, float %tmp2, i32 2
-  %vecinit9 = insertelement <4 x float> %vecinit7, float %tmp2, i32 3
-  %0 = bitcast <4 x float> %vecinit9 to <2 x i64>
-  ret <2 x i64> %0
-}
-
 define <2 x i64> @t2() nounwind ssp {
 entry:
 ; CHECK: t2:
@@ -30,14 +15,3 @@ entry:
   %0 = bitcast <4 x float> %vecinit9 to <2 x i64>
   ret <2 x i64> %0
 }
-
-define <4 x float> @t3(float %tmp1, float %tmp2, float %tmp3) nounwind readnone ssp {
-entry:
-; CHECK: t3:
-; CHECK: pshufd	$-86, (%esp), %xmm0
-  %0 = insertelement <4 x float> undef, float %tmp3, i32 0
-  %1 = insertelement <4 x float> %0, float %tmp3, i32 1
-  %2 = insertelement <4 x float> %1, float %tmp3, i32 2
-  %3 = insertelement <4 x float> %2, float %tmp3, i32 3
-  ret <4 x float> %3
-}
diff --git a/test/CodeGen/X86/stride-reuse.ll b/test/CodeGen/X86/stride-reuse.ll
index a99a9c95a4cc9..5cbd895250a67 100644
--- a/test/CodeGen/X86/stride-reuse.ll
+++ b/test/CodeGen/X86/stride-reuse.ll
@@ -5,7 +5,7 @@
 @A = external global [1000 x float], align 32
 @P = external global [1000 x i32], align 32
 
-define void @foo(i32 %m) {
+define void @foo(i32 %m) nounwind {
 entry:
 	%tmp1 = icmp sgt i32 %m, 0
 	br i1 %tmp1, label %bb, label %return
diff --git a/test/CodeGen/X86/subreg-to-reg-5.ll b/test/CodeGen/X86/subreg-to-reg-5.ll
deleted file mode 100644
index ba4c307d1090a..0000000000000
--- a/test/CodeGen/X86/subreg-to-reg-5.ll
+++ /dev/null
@@ -1,35 +0,0 @@
-; RUN: llc < %s -march=x86-64 > %t
-; RUN: grep addl %t
-; RUN: not egrep {movl|movq} %t
-
-define float @foo(float* %B) nounwind {
-entry:
-	br label %bb2
-
-bb2:		; preds = %bb3, %entry
-	%B_addr.0.rec = phi i64 [ %indvar.next154, %bb3 ], [ 0, %entry ]		; <i64> [#uses=2]
-        %z = icmp slt i64 %B_addr.0.rec, 20000
-	br i1 %z, label %bb3, label %bb4
-
-bb3:		; preds = %bb2
-	%indvar.next154 = add i64 %B_addr.0.rec, 1		; <i64> [#uses=1]
-	br label %bb2
-
-bb4:		; preds = %bb2
-	%B_addr.0 = getelementptr float* %B, i64 %B_addr.0.rec		; <float*> [#uses=1]
-	%t1 = ptrtoint float* %B_addr.0 to i64		; <i64> [#uses=1]
-	%t2 = and i64 %t1, 4294967295		; <i64> [#uses=1]
-	%t3 = icmp eq i64 %t2, 0		; <i1> [#uses=1]
-	br i1 %t3, label %bb5, label %bb10.preheader
-
-bb10.preheader:		; preds = %bb4
-	br label %bb9
-
-bb5:		; preds = %bb4
-	ret float 7.0
-
-bb9:		; preds = %bb10.preheader
-	%t5 = getelementptr float* %B, i64 0		; <float*> [#uses=1]
-	%t7 = load float* %t5		; <float> [#uses=1]
-	ret float %t7
-}
diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll
index c5dbb04a051b5..7b21e1bd7209c 100644
--- a/test/CodeGen/X86/tail-opts.ll
+++ b/test/CodeGen/X86/tail-opts.ll
@@ -109,15 +109,15 @@ altret:
 
 ; CHECK: dont_merge_oddly:
 ; CHECK-NOT:   ret
-; CHECK:        ucomiss %xmm0, %xmm1
+; CHECK:        ucomiss %xmm1, %xmm2
 ; CHECK-NEXT:   jbe .LBB3_3
-; CHECK-NEXT:   ucomiss %xmm2, %xmm0
+; CHECK-NEXT:   ucomiss %xmm0, %xmm1
 ; CHECK-NEXT:   ja .LBB3_4
 ; CHECK-NEXT: .LBB3_2:
 ; CHECK-NEXT:   movb $1, %al
 ; CHECK-NEXT:   ret
 ; CHECK-NEXT: .LBB3_3:
-; CHECK-NEXT:   ucomiss %xmm2, %xmm1
+; CHECK-NEXT:   ucomiss %xmm0, %xmm2
 ; CHECK-NEXT:   jbe .LBB3_2
 ; CHECK-NEXT: .LBB3_4:
 ; CHECK-NEXT:   xorb %al, %al
diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll
index 7778983e28553..b61803d10ce40 100644
--- a/test/CodeGen/X86/unaligned-load.ll
+++ b/test/CodeGen/X86/unaligned-load.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck %s
 
 @.str1 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 8
 @.str3 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, 2'ND STRING\00", align 8
@@ -23,5 +23,5 @@ declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
 ; CHECK: .align  3
 ; CHECK-NEXT: _.str1:
 ; CHECK-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING"
-; CHECK-NEXT: .align 3
+; CHECK: .align 3
 ; CHECK-NEXT: _.str3:
diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index 7bd06bba4c3e4..9bfff8a06a862 100644
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -131,3 +131,14 @@ bb12:
 ; X32:    andl	{{.*}}[[REG]]
 }
 
+define i32 @test8(i32 %a) nounwind {
+; rdar://7553032
+entry:
+  %t1 = sub i32 0, %a
+  %t2 = add i32 %t1, -1
+  ret i32 %t2
+; X64: test8:
+; X64:   notl %eax
+; X32: test8:
+; X32:   notl %eax
+}
-- 
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