src-test2/sys/dev/ffec, branch release/11.3.0

MFC r338857:

2018-09-28T10:02:47Z

Fix possible NULL pointer dereference in ffec_alloc_mbufcl(). PR: 231514

Revert r330897:

2018-03-29T02:50:57Z

This was intended to be a non-functional change. It wasn't. The commit message was thus wrong. In addition it broke arm, and merged crypto related code. Revert with prejudice. This revert skips files touched in r316370 since that commit was since MFCed. This revert also skips files that require $FreeBSD$ property changes. Thank you to those who helped me get out of this mess including but not limited to gonzo, kevans, rgrimes. Requested by: gjb (re)

Partial merge of the SPDX changes

2018-03-14T03:19:51Z

These changes are incomplete but are making it difficult to determine what other changes can/should be merged. No objections from: pfg

MFC r325045, r325054-r325056, r325061, r325063, r325065

2018-01-06T21:19:52Z

r325045: Actually release resources in detach() rather than just returning EBUSY. This will enable use of 'devctl disable', allow creation of a module, etc. r325054: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325055: Add FECFLAG_AVB variant flag to support new features on imx7. This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB. It indicates an FEC with support for Audio Video Bridging (AVB). This indicator is used for various other parts in the Linux driver (drivers/net/ethernet/freescale/fec_main.c). Use it to customize the receive/transmit buffer alignment. The receive buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX 7Dual. There are no hard alignment restrictions for transmit buffers on these chips. Fix the ffec_softc::fectype type to provide enough storage for the feature flags. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325056: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325061: Support up to 3 IRQs in the ffec driver. Newer hardware splits the interrupts onto 3 different irq lines, but the docs barely mention that there are multiple interrupts, and do not detail how they're split up. The code now supports 1-3 irqs, and uses the same interrupt service routine to handle all of them. I modified the submitted changes to use bus_alloc_resources() instead of using loops to allocate each irq separately. Thus, blame any bugs on me (I can't actually test on imx7 hardware). PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325063: Use the 16-bit receive shift feature in ffec hardware that supports it. When available, enabling this feature causes the hardware to write data to the receive buffer starting at a 16-bit offset from the start address. This eliminates the need to copy the data after receiving to re-align the protocol headers to a 32-bit boundary. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de r325065: Split the hardware type enum and the hw feature flags bits into separate fields in the softc; they're ORed together in the ofw_compat_data. I already caught myself doing 'sc->fectype == ' without masking out the feature bits in one place, and that's sure to happen again. Glomming them together is convenient for storing them in the ofw_compat_data array, but there's no reason to keep them together in the softc.

MFC r319814, r319815, r319818:

2017-09-11T01:59:24Z

Add a set of constants describing the ways a MAC and PHY can be connected. While the initial need for this is to help support phy drivers which are configured with FDT data, there is nothing devicetree-specific about the concept or the names, so they are available for use even on non-FDT systems. Add some utility functions to help a PHY driver on an FDT-configured system retrieve its config data from the fdt data. Convert if_ffec from local code and constants for mac<->phy connection type to new common fdt helper code.

MFC r319811, r319813:

2017-09-11T01:26:26Z

Allow building if_ffec as a module. if_ffec bugfixes related to harvesting of hardware-maintained statistics... After harvesting the hardware statistics counters and summing them into the interface stats, properly clear the hardware counters back to zero. On imx5 and earlier hardware it is necessary to disable collection of stats while writing zeroes to all the registers. On imx6 and newer it turns out it's not even possible to write zeroes, instead you have to toggle a special "zero everything" control bit in a register. Count incoming packets with a bad start frame delim as input errors, and incoming packets dropped due to no fifo space as input drops. Remove all code related to harvesting the hardware stats less often than once per second. It turns out the 32-bit stats registers are backed by 16-bit counters under the hood, and they can easily roll over if you only harvest them once every 3 seconds like the old code was doing. Now we just read all the regs once a second. The combination of not properly zeroing the stats registers and 16-bit counters sometimes wrapping between harvest calls resulted in basically unusable statistics before these changes.

MFC r316664, r316670, r316972, r316996, r317033:

2017-09-11T01:01:00Z

Add imx6ul support (applies to all files). Add code/constants for detecting imx6ul (ultralite) chips, a species of imx6 based on a single cortex-a7 core. Other changes to imx6 drivers and support code are needed to fully support the imx6ul. if_ffec: Add imx6ul SoC support, and get the PHY number from the FDT data. If there is no phy-handle property, fall back to using MII_PHY_ANY. This still doesn't support an mdio bus with multiple PHYs on it, or the possibility that the PHY being used by this instance of ffec is on the mdio bus of some other instance (which is now a possibility with imx6ul). Adding that support will require changes in fdt_get_phyaddr(), which is currently making some assumptions that don't work with modern fdt data.

MFC r313918: Add definitions for the IEEE-1588 registers.

2017-03-01T21:20:28Z

Fix erronious mixed use of tx/rx variables/constants in the same expression.

2016-05-27T22:14:39Z

Pointed out by jmcneill; other instances found by grep -iE 'rx.*tx|tx.*rx'

Add busdma sync ops before reading and after modifying the descriptor rings.

2014-11-24T16:12:11Z

This was previously working by accident because BUSDMA_COHERENT_MEMORY has always been set to strongly-ordered on arm. Now we're moving towards normal-uncacheable (what might be called write-combining on other platforms) and using the proper sync ops will be more important. Of course, that opens the question of just what is the "proper" sync op for shared concurrent dma access as opposed to accesses where the handoff of control of the memory has well-defined sequence points that match the available busdma sync operations.