src-test2/sys/dev/ic, branch release/8.0.0_cvs FreeBSD source tree https://cgit-dev.freebsd.org/src-test2/atom?h=release%2F8.0.0_cvs 2009-11-21T06:13:29Z Create release/8.0.0 for the 8.0-RELEASE. 2009-11-21T06:13:29Z Ken Smith kensmith@FreeBSD.org 2009-11-21T06:13:29Z urn:sha1:a4d3b78df842614c46b116fc5a6f470be637dccd Approved by: re (implicit) This commit was manufactured to restore the state of the 8.0-RELEASE image. add %b formats for various registers 2009-06-21T19:17:22Z Sam Leffler sam@FreeBSD.org 2009-06-21T19:17:22Z urn:sha1:04ddfac3390b5b7fc9d57edf2ad2b7fb5c3e692c - Cleanup i8251 related defines. 2008-09-07T04:35:04Z Yoshihiro Takahashi nyan@FreeBSD.org 2008-09-07T04:35:04Z urn:sha1:ebd2b744768169ad575024ce4c1033833a220c6d - Move i8255 related defines into a separate file. unifdef PC98 2008-08-29T12:25:58Z Yoshihiro Takahashi nyan@FreeBSD.org 2008-08-29T12:25:58Z urn:sha1:5798cf97e910447c5dbee9d70706a276b163b5a4 Support for Freescale QUad Integrated Communications Controller. 2008-03-03T18:20:17Z Rafal Jaworowski raj@FreeBSD.org 2008-03-03T18:20:17Z urn:sha1:e1ef781113fba635a7fa4a979607261385971992 The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500 Fix style nits. No md5 changes in .o's. ;-) 2006-09-08T21:46:01Z Jung-uk Kim jkim@FreeBSD.org 2006-09-08T21:46:01Z urn:sha1:0da90eb878fdcd8c766c609afbf5f53cc56858e7 Enhanced floppy controllers have Data Rate Select Register (DSR) at 0x3f4. 2006-07-06T21:12:18Z Jung-uk Kim jkim@FreeBSD.org 2006-07-06T21:12:18Z urn:sha1:50d99d1a52d3bc87a4897cc87db950960060e35e Use it to reset controller and to select data rate. According to Intel 80277AA datasheet, software reset behaves the same as DOR reset except that it is self clearing. National Semiconductor PC8477B datasheet says the same. As a side effect, we no longer use Configuration Control Register (CCR) at 0x3f7 for these controllers, which is often missing in modern hardware. Allow uart(4)'s ns8250 driver to work with devices whose regshift is > 0. 2006-05-23T00:41:12Z Benno Rice benno@FreeBSD.org 2006-05-23T00:41:12Z urn:sha1:58957d87173648541b214726c95eb4614ba31848 - Rename REG_DL to REG_DLL and REG_DLH. - Always treat DLL and DLH as two separate 8-bit registers instead of one 16-bit register. Additionally, remove the probe for the high 4 bits of IER being 0 and don't assume we can always read/write 0 to/from those bits. These changes allow uart(4) to drive the UARTs on the Intel XScale PXA255. Reviewed by: marcel MFp4: 2006-02-24T02:03:35Z Marcel Moolenaar marcel@FreeBSD.org 2006-02-24T02:03:35Z urn:sha1:1ba1685b25c0189a4a2f2118b7151b96ccfec929 Add CHAN_A & CHAN_B for channel register offsets. While here, fix a comment. Register definitions for the ancient via6522. This 20+ year-old chip 2005-12-02T22:36:14Z Peter Grehan grehan@FreeBSD.org 2005-12-02T22:36:14Z urn:sha1:e2b03d4d48a74dda22342289a7b5ba6be59b192b still exists as a cell in the Macio asic on Apples, and is used to communicate through the shift register with the external PMU microcontroller.