FreeBSD source tree https://cgit-dev.freebsd.org/src-test2/atom?h=release%2F11.3.0 2019-02-28T00:30:34Z 2019-02-28T00:30:34Z Alexander Motin mav@FreeBSD.org 2019-02-28T00:30:34Z urn:sha1:da17b32e671b5aa551c9178ee087ac94394e7a40 Its a hack, we can't know/list all DMA engines, but this covers all I/OAT of Xeon E5/E7 at least from Sandy Bridge till Skylake I saw. 2018-02-09T03:07:12Z Alexander Motin mav@FreeBSD.org 2018-02-09T03:07:12Z urn:sha1:b4b430d085e6da068ab182429273f2674026f25f We may not have enough contiguous memory later, when NTB connection get established. It is quite likely that NTB windows are symmetric and this allocation remain, but even if not, we will just reallocate it later. 2018-02-09T03:06:45Z Alexander Motin mav@FreeBSD.org 2018-02-09T03:06:45Z urn:sha1:f98c6b89ef6a9d5958375d532463fbe0f63ccea1 I suppose it should make this code NUMA-aware with recent NUMA drop-in, trying to allocate shared memory buffers from domain closer to NT-bridge. 2017-10-08T07:19:59Z Alexander Motin mav@FreeBSD.org 2017-10-08T07:19:59Z urn:sha1:919a6299934c51f205f04de52e04e5f7b8a965ad When enabled by EEPROM, use it to relax translation address/size alignment requirements for BAR2 window by 128 or 256 times. 2017-09-21T07:35:22Z Alexander Motin mav@FreeBSD.org 2017-09-21T07:35:22Z urn:sha1:0b8b5b6d3283c8cb9a14fb719bf82d5470facdc7 Each of two entries on a virtual side should have its counterpart on a peer's link side. 2017-09-11T18:51:02Z Alexander Motin mav@FreeBSD.org 2017-09-11T18:51:02Z urn:sha1:fe64a962fcab0d6d0b31797dce2d8a8547a040b9 There is no big need to burn CPU if other side may be not there yet. For example, the PLX hardware by default enables the NTB link up on reset, not dependig on driver to do it. In case of Intel hardware this also reduces race between MSI-X workaround negotiation and upper layers, using the same scratchpad registers in different time. 2017-09-11T18:50:36Z Alexander Motin mav@FreeBSD.org 2017-09-11T18:50:36Z urn:sha1:8829a154a64baa6e0b34b10968afb3dc764d2d77 2017-09-11T18:50:09Z Alexander Motin mav@FreeBSD.org 2017-09-11T18:50:09Z urn:sha1:a3a5b705d8576f7ec40fbdf04e7bd091f9940c0c In theory this allows to avoid one more expensive doorbell register read later in some scenarios. But in practice it also significantly increases packet rate on PLX hardware, that I can't explain yet, possibly work- arounding some interrupt delays. 2017-09-11T18:48:09Z Alexander Motin mav@FreeBSD.org 2017-09-11T18:48:09Z urn:sha1:4791823d15269c5782bc274c483951207ba1f03b Add NTB driver for PLX/Avago/Broadcom PCIe switches. This driver supports both NTB-to-NTB and NTB-to-Root Port modes (though the second with predictable complications on hot-plug and reboot events). I tested it with PEX 8717 and PEX 8733 chips, but expect it should work with many other compatible ones too. It supports up to two NT bridges per chip, each of which can have up to 2 64-bit or 4 32-bit memory windows, 6 or 12 scratchpad registers and 16 doorbells. There are also 4 DMA engines in those chips, but they are not yet supported. While there, rename Intel NTB driver from generic ntb_hw(4) to more specific ntb_hw_intel(4), so now it is on par with this new ntb_hw_plx(4) driver and alike to Linux naming. 2017-09-11T18:31:51Z Alexander Motin mav@FreeBSD.org 2017-09-11T18:31:51Z urn:sha1:3eb8998b7a92aba424ce6e3cd266313c8cc39ebd This fixes interrupt storms on hardware using legacy level-triggered interrupts, since doorbell processing could take time after interrupt handler completion, that triggered extra interrupts in a loop.